1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM625 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 oc_sram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x10000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x0 0x00 0x70000000 0x10000>; 15 }; 16 17 gic500: interrupt-controller@1800000 { 18 compatible = "arm,gic-v3"; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 ranges; 22 #interrupt-cells = <3>; 23 interrupt-controller; 24 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 25 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 26 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 27 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 28 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 29 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 30 /* 31 * vcpumntirq: 32 * virtual CPU interface maintenance interrupt 33 */ 34 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 35 36 gic_its: msi-controller@1820000 { 37 compatible = "arm,gic-v3-its"; 38 reg = <0x00 0x01820000 0x00 0x10000>; 39 socionext,synquacer-pre-its = <0x1000000 0x400000>; 40 msi-controller; 41 #msi-cells = <1>; 42 }; 43 }; 44 45 main_conf: syscon@100000 { 46 compatible = "syscon", "simple-mfd"; 47 reg = <0x00 0x00100000 0x00 0x20000>; 48 #address-cells = <1>; 49 #size-cells = <1>; 50 ranges = <0x0 0x00 0x00100000 0x20000>; 51 52 phy_gmii_sel: phy@4044 { 53 compatible = "ti,am654-phy-gmii-sel"; 54 reg = <0x4044 0x8>; 55 #phy-cells = <1>; 56 }; 57 }; 58 59 dmss: bus@48000000 { 60 compatible = "simple-mfd"; 61 #address-cells = <2>; 62 #size-cells = <2>; 63 dma-ranges; 64 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 65 66 ti,sci-dev-id = <25>; 67 68 secure_proxy_main: mailbox@4d000000 { 69 compatible = "ti,am654-secure-proxy"; 70 #mbox-cells = <1>; 71 reg-names = "target_data", "rt", "scfg"; 72 reg = <0x00 0x4d000000 0x00 0x80000>, 73 <0x00 0x4a600000 0x00 0x80000>, 74 <0x00 0x4a400000 0x00 0x80000>; 75 interrupt-names = "rx_012"; 76 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 77 }; 78 79 inta_main_dmss: interrupt-controller@48000000 { 80 compatible = "ti,sci-inta"; 81 reg = <0x00 0x48000000 0x00 0x100000>; 82 #interrupt-cells = <0>; 83 interrupt-controller; 84 interrupt-parent = <&gic500>; 85 msi-controller; 86 ti,sci = <&dmsc>; 87 ti,sci-dev-id = <28>; 88 ti,interrupt-ranges = <4 68 36>; 89 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 90 }; 91 92 main_bcdma: dma-controller@485c0100 { 93 compatible = "ti,am64-dmss-bcdma"; 94 reg = <0x00 0x485c0100 0x00 0x100>, 95 <0x00 0x4c000000 0x00 0x20000>, 96 <0x00 0x4a820000 0x00 0x20000>, 97 <0x00 0x4aa40000 0x00 0x20000>, 98 <0x00 0x4bc00000 0x00 0x100000>; 99 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; 100 msi-parent = <&inta_main_dmss>; 101 #dma-cells = <3>; 102 103 ti,sci = <&dmsc>; 104 ti,sci-dev-id = <26>; 105 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 106 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 107 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 108 }; 109 110 main_pktdma: dma-controller@485c0000 { 111 compatible = "ti,am64-dmss-pktdma"; 112 reg = <0x00 0x485c0000 0x00 0x100>, 113 <0x00 0x4a800000 0x00 0x20000>, 114 <0x00 0x4aa00000 0x00 0x40000>, 115 <0x00 0x4b800000 0x00 0x400000>; 116 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 117 msi-parent = <&inta_main_dmss>; 118 #dma-cells = <2>; 119 120 ti,sci = <&dmsc>; 121 ti,sci-dev-id = <30>; 122 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 123 <0x24>, /* CPSW_TX_CHAN */ 124 <0x25>, /* SAUL_TX_0_CHAN */ 125 <0x26>; /* SAUL_TX_1_CHAN */ 126 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 127 <0x11>, /* RING_CPSW_TX_CHAN */ 128 <0x12>, /* RING_SAUL_TX_0_CHAN */ 129 <0x13>; /* RING_SAUL_TX_1_CHAN */ 130 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 131 <0x2b>, /* CPSW_RX_CHAN */ 132 <0x2d>, /* SAUL_RX_0_CHAN */ 133 <0x2f>, /* SAUL_RX_1_CHAN */ 134 <0x31>, /* SAUL_RX_2_CHAN */ 135 <0x33>; /* SAUL_RX_3_CHAN */ 136 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 137 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 138 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 139 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ 140 }; 141 }; 142 143 dmsc: system-controller@44043000 { 144 compatible = "ti,k2g-sci"; 145 ti,host-id = <12>; 146 mbox-names = "rx", "tx"; 147 mboxes= <&secure_proxy_main 12>, 148 <&secure_proxy_main 13>; 149 reg-names = "debug_messages"; 150 reg = <0x00 0x44043000 0x00 0xfe0>; 151 152 k3_pds: power-controller { 153 compatible = "ti,sci-pm-domain"; 154 #power-domain-cells = <2>; 155 }; 156 157 k3_clks: clock-controller { 158 compatible = "ti,k2g-sci-clk"; 159 #clock-cells = <2>; 160 }; 161 162 k3_reset: reset-controller { 163 compatible = "ti,sci-reset"; 164 #reset-cells = <2>; 165 }; 166 }; 167 168 main_pmx0: pinctrl@f4000 { 169 compatible = "pinctrl-single"; 170 reg = <0x00 0xf4000 0x00 0x2ac>; 171 #pinctrl-cells = <1>; 172 pinctrl-single,register-width = <32>; 173 pinctrl-single,function-mask = <0xffffffff>; 174 }; 175 176 main_uart0: serial@2800000 { 177 compatible = "ti,am64-uart", "ti,am654-uart"; 178 reg = <0x00 0x02800000 0x00 0x100>; 179 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 180 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 181 clocks = <&k3_clks 146 0>; 182 clock-names = "fclk"; 183 }; 184 185 main_uart1: serial@2810000 { 186 compatible = "ti,am64-uart", "ti,am654-uart"; 187 reg = <0x00 0x02810000 0x00 0x100>; 188 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 189 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 190 clocks = <&k3_clks 152 0>; 191 clock-names = "fclk"; 192 }; 193 194 main_uart2: serial@2820000 { 195 compatible = "ti,am64-uart", "ti,am654-uart"; 196 reg = <0x00 0x02820000 0x00 0x100>; 197 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 198 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 199 clocks = <&k3_clks 153 0>; 200 clock-names = "fclk"; 201 }; 202 203 main_uart3: serial@2830000 { 204 compatible = "ti,am64-uart", "ti,am654-uart"; 205 reg = <0x00 0x02830000 0x00 0x100>; 206 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 207 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 208 clocks = <&k3_clks 154 0>; 209 clock-names = "fclk"; 210 }; 211 212 main_uart4: serial@2840000 { 213 compatible = "ti,am64-uart", "ti,am654-uart"; 214 reg = <0x00 0x02840000 0x00 0x100>; 215 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 216 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 217 clocks = <&k3_clks 155 0>; 218 clock-names = "fclk"; 219 }; 220 221 main_uart5: serial@2850000 { 222 compatible = "ti,am64-uart", "ti,am654-uart"; 223 reg = <0x00 0x02850000 0x00 0x100>; 224 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 225 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 226 clocks = <&k3_clks 156 0>; 227 clock-names = "fclk"; 228 }; 229 230 main_uart6: serial@2860000 { 231 compatible = "ti,am64-uart", "ti,am654-uart"; 232 reg = <0x00 0x02860000 0x00 0x100>; 233 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 234 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 235 clocks = <&k3_clks 158 0>; 236 clock-names = "fclk"; 237 }; 238 239 main_i2c0: i2c@20000000 { 240 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 241 reg = <0x00 0x20000000 0x00 0x100>; 242 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 246 clocks = <&k3_clks 102 2>; 247 clock-names = "fck"; 248 }; 249 250 main_i2c1: i2c@20010000 { 251 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 252 reg = <0x00 0x20010000 0x00 0x100>; 253 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 254 #address-cells = <1>; 255 #size-cells = <0>; 256 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 257 clocks = <&k3_clks 103 2>; 258 clock-names = "fck"; 259 }; 260 261 main_i2c2: i2c@20020000 { 262 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 263 reg = <0x00 0x20020000 0x00 0x100>; 264 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 265 #address-cells = <1>; 266 #size-cells = <0>; 267 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 268 clocks = <&k3_clks 104 2>; 269 clock-names = "fck"; 270 }; 271 272 main_i2c3: i2c@20030000 { 273 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 274 reg = <0x00 0x20030000 0x00 0x100>; 275 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 279 clocks = <&k3_clks 105 2>; 280 clock-names = "fck"; 281 }; 282 283 main_spi0: spi@20100000 { 284 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 285 reg = <0x00 0x20100000 0x00 0x400>; 286 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 287 #address-cells = <1>; 288 #size-cells = <0>; 289 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 290 clocks = <&k3_clks 172 0>; 291 }; 292 293 main_spi1: spi@20110000 { 294 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 295 reg = <0x00 0x20110000 0x00 0x400>; 296 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 300 clocks = <&k3_clks 173 0>; 301 }; 302 303 main_spi2: spi@20120000 { 304 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 305 reg = <0x00 0x20120000 0x00 0x400>; 306 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 307 #address-cells = <1>; 308 #size-cells = <0>; 309 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 310 clocks = <&k3_clks 174 0>; 311 }; 312 313 main_gpio_intr: interrupt-controller@a00000 { 314 compatible = "ti,sci-intr"; 315 reg = <0x00 0x00a00000 0x00 0x800>; 316 ti,intr-trigger-type = <1>; 317 interrupt-controller; 318 interrupt-parent = <&gic500>; 319 #interrupt-cells = <1>; 320 ti,sci = <&dmsc>; 321 ti,sci-dev-id = <3>; 322 ti,interrupt-ranges = <0 32 16>; 323 }; 324 325 main_gpio0: gpio@600000 { 326 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 327 reg = <0x0 0x00600000 0x0 0x100>; 328 gpio-controller; 329 #gpio-cells = <2>; 330 interrupt-parent = <&main_gpio_intr>; 331 interrupts = <190>, <191>, <192>, 332 <193>, <194>, <195>; 333 interrupt-controller; 334 #interrupt-cells = <2>; 335 ti,ngpio = <87>; 336 ti,davinci-gpio-unbanked = <0>; 337 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 338 clocks = <&k3_clks 77 0>; 339 clock-names = "gpio"; 340 }; 341 342 main_gpio1: gpio@601000 { 343 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 344 reg = <0x0 0x00601000 0x0 0x100>; 345 gpio-controller; 346 #gpio-cells = <2>; 347 interrupt-parent = <&main_gpio_intr>; 348 interrupts = <180>, <181>, <182>, 349 <183>, <184>, <185>; 350 interrupt-controller; 351 #interrupt-cells = <2>; 352 ti,ngpio = <88>; 353 ti,davinci-gpio-unbanked = <0>; 354 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 355 clocks = <&k3_clks 78 0>; 356 clock-names = "gpio"; 357 }; 358 359 sdhci0: mmc@fa10000 { 360 compatible = "ti,am62-sdhci"; 361 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>; 362 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 363 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 364 clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; 365 clock-names = "clk_ahb", "clk_xin"; 366 assigned-clocks = <&k3_clks 57 6>; 367 assigned-clock-parents = <&k3_clks 57 8>; 368 mmc-ddr-1_8v; 369 mmc-hs200-1_8v; 370 ti,trm-icp = <0x2>; 371 bus-width = <8>; 372 ti,clkbuf-sel = <0x7>; 373 ti,otap-del-sel-legacy = <0x0>; 374 ti,otap-del-sel-mmc-hs = <0x0>; 375 ti,otap-del-sel-ddr52 = <0x9>; 376 ti,otap-del-sel-hs200 = <0x6>; 377 }; 378 379 sdhci1: mmc@fa00000 { 380 compatible = "ti,am62-sdhci"; 381 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>; 382 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 383 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 384 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; 385 clock-names = "clk_ahb", "clk_xin"; 386 ti,trm-icp = <0x2>; 387 ti,otap-del-sel-legacy = <0x0>; 388 ti,otap-del-sel-sd-hs = <0x0>; 389 ti,otap-del-sel-sdr12 = <0xf>; 390 ti,otap-del-sel-sdr25 = <0xf>; 391 ti,otap-del-sel-sdr50 = <0xc>; 392 ti,otap-del-sel-sdr104 = <0x6>; 393 ti,otap-del-sel-ddr50 = <0x9>; 394 ti,itap-del-sel-legacy = <0x0>; 395 ti,itap-del-sel-sd-hs = <0x0>; 396 ti,itap-del-sel-sdr12 = <0x0>; 397 ti,itap-del-sel-sdr25 = <0x0>; 398 ti,clkbuf-sel = <0x7>; 399 bus-width = <4>; 400 }; 401 402 sdhci2: mmc@fa20000 { 403 compatible = "ti,am62-sdhci"; 404 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>; 405 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 406 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 407 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; 408 clock-names = "clk_ahb", "clk_xin"; 409 ti,trm-icp = <0x2>; 410 ti,otap-del-sel-legacy = <0x0>; 411 ti,otap-del-sel-sd-hs = <0x0>; 412 ti,otap-del-sel-sdr12 = <0xf>; 413 ti,otap-del-sel-sdr25 = <0xf>; 414 ti,otap-del-sel-sdr50 = <0xc>; 415 ti,otap-del-sel-sdr104 = <0x6>; 416 ti,otap-del-sel-ddr50 = <0x9>; 417 ti,itap-del-sel-legacy = <0x0>; 418 ti,itap-del-sel-sd-hs = <0x0>; 419 ti,itap-del-sel-sdr12 = <0x0>; 420 ti,itap-del-sel-sdr25 = <0x0>; 421 ti,clkbuf-sel = <0x7>; 422 }; 423 424 fss: bus@fc00000 { 425 compatible = "simple-bus"; 426 reg = <0x00 0x0fc00000 0x00 0x70000>; 427 #address-cells = <2>; 428 #size-cells = <2>; 429 ranges; 430 431 ospi0: spi@fc40000 { 432 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 433 reg = <0x00 0x0fc40000 0x00 0x100>, 434 <0x05 0x00000000 0x01 0x00000000>; 435 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 436 cdns,fifo-depth = <256>; 437 cdns,fifo-width = <4>; 438 cdns,trigger-address = <0x0>; 439 clocks = <&k3_clks 75 7>; 440 assigned-clocks = <&k3_clks 75 7>; 441 assigned-clock-parents = <&k3_clks 75 8>; 442 assigned-clock-rates = <166666666>; 443 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 }; 447 }; 448 449 cpsw3g: ethernet@8000000 { 450 compatible = "ti,am642-cpsw-nuss"; 451 #address-cells = <2>; 452 #size-cells = <2>; 453 reg = <0x00 0x08000000 0x00 0x200000>; 454 reg-names = "cpsw_nuss"; 455 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>; 456 clocks = <&k3_clks 13 0>; 457 assigned-clocks = <&k3_clks 13 3>; 458 assigned-clock-parents = <&k3_clks 13 11>; 459 clock-names = "fck"; 460 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 461 462 dmas = <&main_pktdma 0xc600 15>, 463 <&main_pktdma 0xc601 15>, 464 <&main_pktdma 0xc602 15>, 465 <&main_pktdma 0xc603 15>, 466 <&main_pktdma 0xc604 15>, 467 <&main_pktdma 0xc605 15>, 468 <&main_pktdma 0xc606 15>, 469 <&main_pktdma 0xc607 15>, 470 <&main_pktdma 0x4600 15>; 471 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 472 "tx7", "rx"; 473 474 ethernet-ports { 475 #address-cells = <1>; 476 #size-cells = <0>; 477 478 cpsw_port1: port@1 { 479 reg = <1>; 480 ti,mac-only; 481 label = "port1"; 482 phys = <&phy_gmii_sel 1>; 483 mac-address = [00 00 00 00 00 00]; 484 ti,syscon-efuse = <&wkup_conf 0x200>; 485 }; 486 487 cpsw_port2: port@2 { 488 reg = <2>; 489 ti,mac-only; 490 label = "port2"; 491 phys = <&phy_gmii_sel 2>; 492 mac-address = [00 00 00 00 00 00]; 493 }; 494 }; 495 496 cpsw3g_mdio: mdio@f00 { 497 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 498 reg = <0x00 0xf00 0x00 0x100>; 499 #address-cells = <1>; 500 #size-cells = <0>; 501 clocks = <&k3_clks 13 0>; 502 clock-names = "fck"; 503 bus_freq = <1000000>; 504 }; 505 506 cpts@3d000 { 507 compatible = "ti,j721e-cpts"; 508 reg = <0x00 0x3d000 0x00 0x400>; 509 clocks = <&k3_clks 13 3>; 510 clock-names = "cpts"; 511 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 512 interrupt-names = "cpts"; 513 ti,cpts-ext-ts-inputs = <4>; 514 ti,cpts-periodic-outputs = <2>; 515 }; 516 }; 517 518 hwspinlock: spinlock@2a000000 { 519 compatible = "ti,am64-hwspinlock"; 520 reg = <0x00 0x2a000000 0x00 0x1000>; 521 #hwlock-cells = <1>; 522 }; 523 524 mailbox0_cluster0: mailbox@29000000 { 525 compatible = "ti,am64-mailbox"; 526 reg = <0x00 0x29000000 0x00 0x200>; 527 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 529 #mbox-cells = <1>; 530 ti,mbox-num-users = <4>; 531 ti,mbox-num-fifos = <16>; 532 }; 533 534 ecap0: pwm@23100000 { 535 compatible = "ti,am3352-ecap"; 536 #pwm-cells = <3>; 537 reg = <0x00 0x23100000 0x00 0x100>; 538 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 539 clocks = <&k3_clks 51 0>; 540 clock-names = "fck"; 541 }; 542 543 ecap1: pwm@23110000 { 544 compatible = "ti,am3352-ecap"; 545 #pwm-cells = <3>; 546 reg = <0x00 0x23110000 0x00 0x100>; 547 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 548 clocks = <&k3_clks 52 0>; 549 clock-names = "fck"; 550 }; 551 552 ecap2: pwm@23120000 { 553 compatible = "ti,am3352-ecap"; 554 #pwm-cells = <3>; 555 reg = <0x00 0x23120000 0x00 0x100>; 556 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 557 clocks = <&k3_clks 53 0>; 558 clock-names = "fck"; 559 }; 560 561 main_mcan0: can@20701000 { 562 compatible = "bosch,m_can"; 563 reg = <0x00 0x20701000 0x00 0x200>, 564 <0x00 0x20708000 0x00 0x8000>; 565 reg-names = "m_can", "message_ram"; 566 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 567 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; 568 clock-names = "hclk", "cclk"; 569 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 571 interrupt-names = "int0", "int1"; 572 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 573 }; 574}; 575