1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM625 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 oc_sram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x10000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x0 0x00 0x70000000 0x10000>; 15 }; 16 17 gic500: interrupt-controller@1800000 { 18 compatible = "arm,gic-v3"; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 ranges; 22 #interrupt-cells = <3>; 23 interrupt-controller; 24 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 25 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 26 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 27 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 28 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 29 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 30 /* 31 * vcpumntirq: 32 * virtual CPU interface maintenance interrupt 33 */ 34 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 35 36 gic_its: msi-controller@1820000 { 37 compatible = "arm,gic-v3-its"; 38 reg = <0x00 0x01820000 0x00 0x10000>; 39 socionext,synquacer-pre-its = <0x1000000 0x400000>; 40 msi-controller; 41 #msi-cells = <1>; 42 }; 43 }; 44 45 main_conf: syscon@100000 { 46 compatible = "syscon", "simple-mfd"; 47 reg = <0x00 0x00100000 0x00 0x20000>; 48 #address-cells = <1>; 49 #size-cells = <1>; 50 ranges = <0x0 0x00 0x00100000 0x20000>; 51 52 phy_gmii_sel: phy@4044 { 53 compatible = "ti,am654-phy-gmii-sel"; 54 reg = <0x4044 0x8>; 55 #phy-cells = <1>; 56 }; 57 58 epwm_tbclk: clock-controller@4130 { 59 compatible = "ti,am62-epwm-tbclk"; 60 reg = <0x4130 0x4>; 61 #clock-cells = <1>; 62 }; 63 64 audio_refclk0: clock-controller@82e0 { 65 compatible = "ti,am62-audio-refclk"; 66 reg = <0x82e0 0x4>; 67 clocks = <&k3_clks 157 0>; 68 assigned-clocks = <&k3_clks 157 0>; 69 assigned-clock-parents = <&k3_clks 157 8>; 70 #clock-cells = <0>; 71 }; 72 73 audio_refclk1: clock-controller@82e4 { 74 compatible = "ti,am62-audio-refclk"; 75 reg = <0x82e4 0x4>; 76 clocks = <&k3_clks 157 10>; 77 assigned-clocks = <&k3_clks 157 10>; 78 assigned-clock-parents = <&k3_clks 157 18>; 79 #clock-cells = <0>; 80 }; 81 }; 82 83 dmss: bus@48000000 { 84 compatible = "simple-mfd"; 85 #address-cells = <2>; 86 #size-cells = <2>; 87 dma-ranges; 88 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 89 90 ti,sci-dev-id = <25>; 91 92 secure_proxy_main: mailbox@4d000000 { 93 compatible = "ti,am654-secure-proxy"; 94 #mbox-cells = <1>; 95 reg-names = "target_data", "rt", "scfg"; 96 reg = <0x00 0x4d000000 0x00 0x80000>, 97 <0x00 0x4a600000 0x00 0x80000>, 98 <0x00 0x4a400000 0x00 0x80000>; 99 interrupt-names = "rx_012"; 100 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 101 }; 102 103 inta_main_dmss: interrupt-controller@48000000 { 104 compatible = "ti,sci-inta"; 105 reg = <0x00 0x48000000 0x00 0x100000>; 106 #interrupt-cells = <0>; 107 interrupt-controller; 108 interrupt-parent = <&gic500>; 109 msi-controller; 110 ti,sci = <&dmsc>; 111 ti,sci-dev-id = <28>; 112 ti,interrupt-ranges = <4 68 36>; 113 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 114 }; 115 116 main_bcdma: dma-controller@485c0100 { 117 compatible = "ti,am64-dmss-bcdma"; 118 reg = <0x00 0x485c0100 0x00 0x100>, 119 <0x00 0x4c000000 0x00 0x20000>, 120 <0x00 0x4a820000 0x00 0x20000>, 121 <0x00 0x4aa40000 0x00 0x20000>, 122 <0x00 0x4bc00000 0x00 0x100000>; 123 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; 124 msi-parent = <&inta_main_dmss>; 125 #dma-cells = <3>; 126 127 ti,sci = <&dmsc>; 128 ti,sci-dev-id = <26>; 129 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 130 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 131 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 132 }; 133 134 main_pktdma: dma-controller@485c0000 { 135 compatible = "ti,am64-dmss-pktdma"; 136 reg = <0x00 0x485c0000 0x00 0x100>, 137 <0x00 0x4a800000 0x00 0x20000>, 138 <0x00 0x4aa00000 0x00 0x40000>, 139 <0x00 0x4b800000 0x00 0x400000>; 140 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 141 msi-parent = <&inta_main_dmss>; 142 #dma-cells = <2>; 143 144 ti,sci = <&dmsc>; 145 ti,sci-dev-id = <30>; 146 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 147 <0x24>, /* CPSW_TX_CHAN */ 148 <0x25>, /* SAUL_TX_0_CHAN */ 149 <0x26>; /* SAUL_TX_1_CHAN */ 150 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 151 <0x11>, /* RING_CPSW_TX_CHAN */ 152 <0x12>, /* RING_SAUL_TX_0_CHAN */ 153 <0x13>; /* RING_SAUL_TX_1_CHAN */ 154 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 155 <0x2b>, /* CPSW_RX_CHAN */ 156 <0x2d>, /* SAUL_RX_0_CHAN */ 157 <0x2f>, /* SAUL_RX_1_CHAN */ 158 <0x31>, /* SAUL_RX_2_CHAN */ 159 <0x33>; /* SAUL_RX_3_CHAN */ 160 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 161 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 162 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 163 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ 164 }; 165 }; 166 167 dmsc: system-controller@44043000 { 168 compatible = "ti,k2g-sci"; 169 ti,host-id = <12>; 170 mbox-names = "rx", "tx"; 171 mboxes = <&secure_proxy_main 12>, 172 <&secure_proxy_main 13>; 173 reg-names = "debug_messages"; 174 reg = <0x00 0x44043000 0x00 0xfe0>; 175 176 k3_pds: power-controller { 177 compatible = "ti,sci-pm-domain"; 178 #power-domain-cells = <2>; 179 }; 180 181 k3_clks: clock-controller { 182 compatible = "ti,k2g-sci-clk"; 183 #clock-cells = <2>; 184 }; 185 186 k3_reset: reset-controller { 187 compatible = "ti,sci-reset"; 188 #reset-cells = <2>; 189 }; 190 }; 191 192 crypto: crypto@40900000 { 193 compatible = "ti,am62-sa3ul"; 194 reg = <0x00 0x40900000 0x00 0x1200>; 195 #address-cells = <2>; 196 #size-cells = <2>; 197 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 198 199 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, 200 <&main_pktdma 0x7507 0>; 201 dma-names = "tx", "rx1", "rx2"; 202 }; 203 204 secure_proxy_sa3: mailbox@43600000 { 205 compatible = "ti,am654-secure-proxy"; 206 #mbox-cells = <1>; 207 reg-names = "target_data", "rt", "scfg"; 208 reg = <0x00 0x43600000 0x00 0x10000>, 209 <0x00 0x44880000 0x00 0x20000>, 210 <0x00 0x44860000 0x00 0x20000>; 211 /* 212 * Marked Disabled: 213 * Node is incomplete as it is meant for bootloaders and 214 * firmware on non-MPU processors 215 */ 216 status = "disabled"; 217 }; 218 219 main_pmx0: pinctrl@f4000 { 220 compatible = "pinctrl-single"; 221 reg = <0x00 0xf4000 0x00 0x2ac>; 222 #pinctrl-cells = <1>; 223 pinctrl-single,register-width = <32>; 224 pinctrl-single,function-mask = <0xffffffff>; 225 }; 226 227 main_esm: esm@420000 { 228 compatible = "ti,j721e-esm"; 229 reg = <0x00 0x420000 0x00 0x1000>; 230 ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>; 231 }; 232 233 main_timer0: timer@2400000 { 234 compatible = "ti,am654-timer"; 235 reg = <0x00 0x2400000 0x00 0x400>; 236 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&k3_clks 36 2>; 238 clock-names = "fck"; 239 assigned-clocks = <&k3_clks 36 2>; 240 assigned-clock-parents = <&k3_clks 36 3>; 241 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 242 ti,timer-pwm; 243 }; 244 245 main_timer1: timer@2410000 { 246 compatible = "ti,am654-timer"; 247 reg = <0x00 0x2410000 0x00 0x400>; 248 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&k3_clks 37 2>; 250 clock-names = "fck"; 251 assigned-clocks = <&k3_clks 37 2>; 252 assigned-clock-parents = <&k3_clks 37 3>; 253 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 254 ti,timer-pwm; 255 }; 256 257 main_timer2: timer@2420000 { 258 compatible = "ti,am654-timer"; 259 reg = <0x00 0x2420000 0x00 0x400>; 260 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&k3_clks 38 2>; 262 clock-names = "fck"; 263 assigned-clocks = <&k3_clks 38 2>; 264 assigned-clock-parents = <&k3_clks 38 3>; 265 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 266 ti,timer-pwm; 267 }; 268 269 main_timer3: timer@2430000 { 270 compatible = "ti,am654-timer"; 271 reg = <0x00 0x2430000 0x00 0x400>; 272 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&k3_clks 39 2>; 274 clock-names = "fck"; 275 assigned-clocks = <&k3_clks 39 2>; 276 assigned-clock-parents = <&k3_clks 39 3>; 277 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 278 ti,timer-pwm; 279 }; 280 281 main_timer4: timer@2440000 { 282 compatible = "ti,am654-timer"; 283 reg = <0x00 0x2440000 0x00 0x400>; 284 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&k3_clks 40 2>; 286 clock-names = "fck"; 287 assigned-clocks = <&k3_clks 40 2>; 288 assigned-clock-parents = <&k3_clks 40 3>; 289 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 290 ti,timer-pwm; 291 }; 292 293 main_timer5: timer@2450000 { 294 compatible = "ti,am654-timer"; 295 reg = <0x00 0x2450000 0x00 0x400>; 296 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&k3_clks 41 2>; 298 clock-names = "fck"; 299 assigned-clocks = <&k3_clks 41 2>; 300 assigned-clock-parents = <&k3_clks 41 3>; 301 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 302 ti,timer-pwm; 303 }; 304 305 main_timer6: timer@2460000 { 306 compatible = "ti,am654-timer"; 307 reg = <0x00 0x2460000 0x00 0x400>; 308 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 309 clocks = <&k3_clks 42 2>; 310 clock-names = "fck"; 311 assigned-clocks = <&k3_clks 42 2>; 312 assigned-clock-parents = <&k3_clks 42 3>; 313 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 314 ti,timer-pwm; 315 }; 316 317 main_timer7: timer@2470000 { 318 compatible = "ti,am654-timer"; 319 reg = <0x00 0x2470000 0x00 0x400>; 320 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&k3_clks 43 2>; 322 clock-names = "fck"; 323 assigned-clocks = <&k3_clks 43 2>; 324 assigned-clock-parents = <&k3_clks 43 3>; 325 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 326 ti,timer-pwm; 327 }; 328 329 main_uart0: serial@2800000 { 330 compatible = "ti,am64-uart", "ti,am654-uart"; 331 reg = <0x00 0x02800000 0x00 0x100>; 332 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 333 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 334 clocks = <&k3_clks 146 0>; 335 clock-names = "fclk"; 336 status = "disabled"; 337 }; 338 339 main_uart1: serial@2810000 { 340 compatible = "ti,am64-uart", "ti,am654-uart"; 341 reg = <0x00 0x02810000 0x00 0x100>; 342 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 343 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 344 clocks = <&k3_clks 152 0>; 345 clock-names = "fclk"; 346 status = "disabled"; 347 }; 348 349 main_uart2: serial@2820000 { 350 compatible = "ti,am64-uart", "ti,am654-uart"; 351 reg = <0x00 0x02820000 0x00 0x100>; 352 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 353 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 354 clocks = <&k3_clks 153 0>; 355 clock-names = "fclk"; 356 status = "disabled"; 357 }; 358 359 main_uart3: serial@2830000 { 360 compatible = "ti,am64-uart", "ti,am654-uart"; 361 reg = <0x00 0x02830000 0x00 0x100>; 362 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 363 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 364 clocks = <&k3_clks 154 0>; 365 clock-names = "fclk"; 366 status = "disabled"; 367 }; 368 369 main_uart4: serial@2840000 { 370 compatible = "ti,am64-uart", "ti,am654-uart"; 371 reg = <0x00 0x02840000 0x00 0x100>; 372 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 373 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 374 clocks = <&k3_clks 155 0>; 375 clock-names = "fclk"; 376 status = "disabled"; 377 }; 378 379 main_uart5: serial@2850000 { 380 compatible = "ti,am64-uart", "ti,am654-uart"; 381 reg = <0x00 0x02850000 0x00 0x100>; 382 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 383 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 384 clocks = <&k3_clks 156 0>; 385 clock-names = "fclk"; 386 status = "disabled"; 387 }; 388 389 main_uart6: serial@2860000 { 390 compatible = "ti,am64-uart", "ti,am654-uart"; 391 reg = <0x00 0x02860000 0x00 0x100>; 392 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 393 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 394 clocks = <&k3_clks 158 0>; 395 clock-names = "fclk"; 396 status = "disabled"; 397 }; 398 399 main_i2c0: i2c@20000000 { 400 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 401 reg = <0x00 0x20000000 0x00 0x100>; 402 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 406 clocks = <&k3_clks 102 2>; 407 clock-names = "fck"; 408 status = "disabled"; 409 }; 410 411 main_i2c1: i2c@20010000 { 412 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 413 reg = <0x00 0x20010000 0x00 0x100>; 414 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 418 clocks = <&k3_clks 103 2>; 419 clock-names = "fck"; 420 status = "disabled"; 421 }; 422 423 main_i2c2: i2c@20020000 { 424 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 425 reg = <0x00 0x20020000 0x00 0x100>; 426 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 430 clocks = <&k3_clks 104 2>; 431 clock-names = "fck"; 432 status = "disabled"; 433 }; 434 435 main_i2c3: i2c@20030000 { 436 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 437 reg = <0x00 0x20030000 0x00 0x100>; 438 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 442 clocks = <&k3_clks 105 2>; 443 clock-names = "fck"; 444 status = "disabled"; 445 }; 446 447 main_spi0: spi@20100000 { 448 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 449 reg = <0x00 0x20100000 0x00 0x400>; 450 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 451 #address-cells = <1>; 452 #size-cells = <0>; 453 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 454 clocks = <&k3_clks 141 0>; 455 status = "disabled"; 456 }; 457 458 main_spi1: spi@20110000 { 459 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 460 reg = <0x00 0x20110000 0x00 0x400>; 461 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 465 clocks = <&k3_clks 142 0>; 466 status = "disabled"; 467 }; 468 469 main_spi2: spi@20120000 { 470 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 471 reg = <0x00 0x20120000 0x00 0x400>; 472 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 476 clocks = <&k3_clks 143 0>; 477 status = "disabled"; 478 }; 479 480 main_gpio_intr: interrupt-controller@a00000 { 481 compatible = "ti,sci-intr"; 482 reg = <0x00 0x00a00000 0x00 0x800>; 483 ti,intr-trigger-type = <1>; 484 interrupt-controller; 485 interrupt-parent = <&gic500>; 486 #interrupt-cells = <1>; 487 ti,sci = <&dmsc>; 488 ti,sci-dev-id = <3>; 489 ti,interrupt-ranges = <0 32 16>; 490 }; 491 492 main_gpio0: gpio@600000 { 493 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 494 reg = <0x0 0x00600000 0x0 0x100>; 495 gpio-controller; 496 #gpio-cells = <2>; 497 interrupt-parent = <&main_gpio_intr>; 498 interrupts = <190>, <191>, <192>, 499 <193>, <194>, <195>; 500 interrupt-controller; 501 #interrupt-cells = <2>; 502 ti,ngpio = <92>; 503 ti,davinci-gpio-unbanked = <0>; 504 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 505 clocks = <&k3_clks 77 0>; 506 clock-names = "gpio"; 507 }; 508 509 main_gpio1: gpio@601000 { 510 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 511 reg = <0x0 0x00601000 0x0 0x100>; 512 gpio-controller; 513 #gpio-cells = <2>; 514 interrupt-parent = <&main_gpio_intr>; 515 interrupts = <180>, <181>, <182>, 516 <183>, <184>, <185>; 517 interrupt-controller; 518 #interrupt-cells = <2>; 519 ti,ngpio = <52>; 520 ti,davinci-gpio-unbanked = <0>; 521 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 522 clocks = <&k3_clks 78 0>; 523 clock-names = "gpio"; 524 }; 525 526 sdhci0: mmc@fa10000 { 527 compatible = "ti,am62-sdhci"; 528 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>; 529 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 530 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 531 clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; 532 clock-names = "clk_ahb", "clk_xin"; 533 assigned-clocks = <&k3_clks 57 6>; 534 assigned-clock-parents = <&k3_clks 57 8>; 535 mmc-ddr-1_8v; 536 mmc-hs200-1_8v; 537 ti,trm-icp = <0x2>; 538 bus-width = <8>; 539 ti,clkbuf-sel = <0x7>; 540 ti,otap-del-sel-legacy = <0x0>; 541 ti,otap-del-sel-mmc-hs = <0x0>; 542 ti,otap-del-sel-ddr52 = <0x5>; 543 ti,otap-del-sel-hs200 = <0x5>; 544 ti,itap-del-sel-legacy = <0xa>; 545 ti,itap-del-sel-mmc-hs = <0x1>; 546 status = "disabled"; 547 }; 548 549 sdhci1: mmc@fa00000 { 550 compatible = "ti,am62-sdhci"; 551 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>; 552 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 553 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 554 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; 555 clock-names = "clk_ahb", "clk_xin"; 556 ti,trm-icp = <0x2>; 557 ti,otap-del-sel-legacy = <0x8>; 558 ti,otap-del-sel-sd-hs = <0x0>; 559 ti,otap-del-sel-sdr12 = <0x0>; 560 ti,otap-del-sel-sdr25 = <0x0>; 561 ti,otap-del-sel-sdr50 = <0x8>; 562 ti,otap-del-sel-sdr104 = <0x7>; 563 ti,otap-del-sel-ddr50 = <0x4>; 564 ti,itap-del-sel-legacy = <0xa>; 565 ti,itap-del-sel-sd-hs = <0x1>; 566 ti,itap-del-sel-sdr12 = <0xa>; 567 ti,itap-del-sel-sdr25 = <0x1>; 568 ti,clkbuf-sel = <0x7>; 569 bus-width = <4>; 570 status = "disabled"; 571 }; 572 573 sdhci2: mmc@fa20000 { 574 compatible = "ti,am62-sdhci"; 575 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>; 576 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 577 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 578 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; 579 clock-names = "clk_ahb", "clk_xin"; 580 ti,trm-icp = <0x2>; 581 ti,otap-del-sel-legacy = <0x8>; 582 ti,otap-del-sel-sd-hs = <0x0>; 583 ti,otap-del-sel-sdr12 = <0x0>; 584 ti,otap-del-sel-sdr25 = <0x0>; 585 ti,otap-del-sel-sdr50 = <0x8>; 586 ti,otap-del-sel-sdr104 = <0x7>; 587 ti,otap-del-sel-ddr50 = <0x8>; 588 ti,itap-del-sel-legacy = <0xa>; 589 ti,itap-del-sel-sd-hs = <0xa>; 590 ti,itap-del-sel-sdr12 = <0xa>; 591 ti,itap-del-sel-sdr25 = <0x1>; 592 ti,clkbuf-sel = <0x7>; 593 status = "disabled"; 594 }; 595 596 usbss0: dwc3-usb@f900000 { 597 compatible = "ti,am62-usb"; 598 reg = <0x00 0x0f900000 0x00 0x800>; 599 clocks = <&k3_clks 161 3>; 600 clock-names = "ref"; 601 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>; 602 #address-cells = <2>; 603 #size-cells = <2>; 604 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 605 ranges; 606 status = "disabled"; 607 608 usb0: usb@31000000 { 609 compatible = "snps,dwc3"; 610 reg = <0x00 0x31000000 0x00 0x50000>; 611 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 612 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 613 interrupt-names = "host", "peripheral"; 614 maximum-speed = "high-speed"; 615 dr_mode = "otg"; 616 }; 617 }; 618 619 usbss1: dwc3-usb@f910000 { 620 compatible = "ti,am62-usb"; 621 reg = <0x00 0x0f910000 0x00 0x800>; 622 clocks = <&k3_clks 162 3>; 623 clock-names = "ref"; 624 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>; 625 #address-cells = <2>; 626 #size-cells = <2>; 627 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 628 ranges; 629 status = "disabled"; 630 631 usb1: usb@31100000 { 632 compatible = "snps,dwc3"; 633 reg = <0x00 0x31100000 0x00 0x50000>; 634 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 635 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 636 interrupt-names = "host", "peripheral"; 637 maximum-speed = "high-speed"; 638 dr_mode = "otg"; 639 }; 640 }; 641 642 fss: bus@fc00000 { 643 compatible = "simple-bus"; 644 reg = <0x00 0x0fc00000 0x00 0x70000>; 645 #address-cells = <2>; 646 #size-cells = <2>; 647 ranges; 648 649 ospi0: spi@fc40000 { 650 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 651 reg = <0x00 0x0fc40000 0x00 0x100>, 652 <0x05 0x00000000 0x01 0x00000000>; 653 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 654 cdns,fifo-depth = <256>; 655 cdns,fifo-width = <4>; 656 cdns,trigger-address = <0x0>; 657 clocks = <&k3_clks 75 7>; 658 assigned-clocks = <&k3_clks 75 7>; 659 assigned-clock-parents = <&k3_clks 75 8>; 660 assigned-clock-rates = <166666666>; 661 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 662 #address-cells = <1>; 663 #size-cells = <0>; 664 status = "disabled"; 665 }; 666 }; 667 668 cpsw3g: ethernet@8000000 { 669 compatible = "ti,am642-cpsw-nuss"; 670 #address-cells = <2>; 671 #size-cells = <2>; 672 reg = <0x00 0x08000000 0x00 0x200000>; 673 reg-names = "cpsw_nuss"; 674 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>; 675 clocks = <&k3_clks 13 0>; 676 assigned-clocks = <&k3_clks 13 3>; 677 assigned-clock-parents = <&k3_clks 13 11>; 678 clock-names = "fck"; 679 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 680 681 dmas = <&main_pktdma 0xc600 15>, 682 <&main_pktdma 0xc601 15>, 683 <&main_pktdma 0xc602 15>, 684 <&main_pktdma 0xc603 15>, 685 <&main_pktdma 0xc604 15>, 686 <&main_pktdma 0xc605 15>, 687 <&main_pktdma 0xc606 15>, 688 <&main_pktdma 0xc607 15>, 689 <&main_pktdma 0x4600 15>; 690 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 691 "tx7", "rx"; 692 693 ethernet-ports { 694 #address-cells = <1>; 695 #size-cells = <0>; 696 697 cpsw_port1: port@1 { 698 reg = <1>; 699 ti,mac-only; 700 label = "port1"; 701 phys = <&phy_gmii_sel 1>; 702 mac-address = [00 00 00 00 00 00]; 703 ti,syscon-efuse = <&wkup_conf 0x200>; 704 }; 705 706 cpsw_port2: port@2 { 707 reg = <2>; 708 ti,mac-only; 709 label = "port2"; 710 phys = <&phy_gmii_sel 2>; 711 mac-address = [00 00 00 00 00 00]; 712 }; 713 }; 714 715 cpsw3g_mdio: mdio@f00 { 716 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 717 reg = <0x00 0xf00 0x00 0x100>; 718 #address-cells = <1>; 719 #size-cells = <0>; 720 clocks = <&k3_clks 13 0>; 721 clock-names = "fck"; 722 bus_freq = <1000000>; 723 status = "disabled"; 724 }; 725 726 cpts@3d000 { 727 compatible = "ti,j721e-cpts"; 728 reg = <0x00 0x3d000 0x00 0x400>; 729 clocks = <&k3_clks 13 3>; 730 clock-names = "cpts"; 731 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 732 interrupt-names = "cpts"; 733 ti,cpts-ext-ts-inputs = <4>; 734 ti,cpts-periodic-outputs = <2>; 735 }; 736 }; 737 738 dss: dss@30200000 { 739 compatible = "ti,am625-dss"; 740 reg = <0x00 0x30200000 0x00 0x1000>, /* common */ 741 <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ 742 <0x00 0x30206000 0x00 0x1000>, /* vid */ 743 <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ 744 <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ 745 <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ 746 <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */ 747 reg-names = "common", "vidl1", "vid", 748 "ovr1", "ovr2", "vp1", "vp2"; 749 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; 750 clocks = <&k3_clks 186 6>, 751 <&dss_vp1_clk>, 752 <&k3_clks 186 2>; 753 clock-names = "fck", "vp1", "vp2"; 754 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 755 status = "disabled"; 756 757 dss_ports: ports { 758 #address-cells = <1>; 759 #size-cells = <0>; 760 }; 761 }; 762 763 hwspinlock: spinlock@2a000000 { 764 compatible = "ti,am64-hwspinlock"; 765 reg = <0x00 0x2a000000 0x00 0x1000>; 766 #hwlock-cells = <1>; 767 }; 768 769 mailbox0_cluster0: mailbox@29000000 { 770 compatible = "ti,am64-mailbox"; 771 reg = <0x00 0x29000000 0x00 0x200>; 772 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 774 #mbox-cells = <1>; 775 ti,mbox-num-users = <4>; 776 ti,mbox-num-fifos = <16>; 777 }; 778 779 ecap0: pwm@23100000 { 780 compatible = "ti,am3352-ecap"; 781 #pwm-cells = <3>; 782 reg = <0x00 0x23100000 0x00 0x100>; 783 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 784 clocks = <&k3_clks 51 0>; 785 clock-names = "fck"; 786 status = "disabled"; 787 }; 788 789 ecap1: pwm@23110000 { 790 compatible = "ti,am3352-ecap"; 791 #pwm-cells = <3>; 792 reg = <0x00 0x23110000 0x00 0x100>; 793 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 794 clocks = <&k3_clks 52 0>; 795 clock-names = "fck"; 796 status = "disabled"; 797 }; 798 799 ecap2: pwm@23120000 { 800 compatible = "ti,am3352-ecap"; 801 #pwm-cells = <3>; 802 reg = <0x00 0x23120000 0x00 0x100>; 803 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 804 clocks = <&k3_clks 53 0>; 805 clock-names = "fck"; 806 status = "disabled"; 807 }; 808 809 main_mcan0: can@20701000 { 810 compatible = "bosch,m_can"; 811 reg = <0x00 0x20701000 0x00 0x200>, 812 <0x00 0x20708000 0x00 0x8000>; 813 reg-names = "m_can", "message_ram"; 814 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 815 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; 816 clock-names = "hclk", "cclk"; 817 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 819 interrupt-names = "int0", "int1"; 820 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 821 status = "disabled"; 822 }; 823 824 main_rti0: watchdog@e000000 { 825 compatible = "ti,j7-rti-wdt"; 826 reg = <0x00 0x0e000000 0x00 0x100>; 827 clocks = <&k3_clks 125 0>; 828 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 829 assigned-clocks = <&k3_clks 125 0>; 830 assigned-clock-parents = <&k3_clks 125 2>; 831 }; 832 833 main_rti1: watchdog@e010000 { 834 compatible = "ti,j7-rti-wdt"; 835 reg = <0x00 0x0e010000 0x00 0x100>; 836 clocks = <&k3_clks 126 0>; 837 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 838 assigned-clocks = <&k3_clks 126 0>; 839 assigned-clock-parents = <&k3_clks 126 2>; 840 }; 841 842 main_rti2: watchdog@e020000 { 843 compatible = "ti,j7-rti-wdt"; 844 reg = <0x00 0x0e020000 0x00 0x100>; 845 clocks = <&k3_clks 127 0>; 846 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; 847 assigned-clocks = <&k3_clks 127 0>; 848 assigned-clock-parents = <&k3_clks 127 2>; 849 }; 850 851 main_rti3: watchdog@e030000 { 852 compatible = "ti,j7-rti-wdt"; 853 reg = <0x00 0x0e030000 0x00 0x100>; 854 clocks = <&k3_clks 128 0>; 855 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; 856 assigned-clocks = <&k3_clks 128 0>; 857 assigned-clock-parents = <&k3_clks 128 2>; 858 }; 859 860 main_rti15: watchdog@e0f0000 { 861 compatible = "ti,j7-rti-wdt"; 862 reg = <0x00 0x0e0f0000 0x00 0x100>; 863 clocks = <&k3_clks 130 0>; 864 power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>; 865 assigned-clocks = <&k3_clks 130 0>; 866 assigned-clock-parents = <&k3_clks 130 2>; 867 }; 868 869 epwm0: pwm@23000000 { 870 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 871 #pwm-cells = <3>; 872 reg = <0x00 0x23000000 0x00 0x100>; 873 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 874 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 875 clock-names = "tbclk", "fck"; 876 status = "disabled"; 877 }; 878 879 epwm1: pwm@23010000 { 880 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 881 #pwm-cells = <3>; 882 reg = <0x00 0x23010000 0x00 0x100>; 883 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 884 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 885 clock-names = "tbclk", "fck"; 886 status = "disabled"; 887 }; 888 889 epwm2: pwm@23020000 { 890 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 891 #pwm-cells = <3>; 892 reg = <0x00 0x23020000 0x00 0x100>; 893 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 894 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 895 clock-names = "tbclk", "fck"; 896 status = "disabled"; 897 }; 898 899 mcasp0: audio-controller@2b00000 { 900 compatible = "ti,am33xx-mcasp-audio"; 901 reg = <0x00 0x02b00000 0x00 0x2000>, 902 <0x00 0x02b08000 0x00 0x400>; 903 reg-names = "mpu", "dat"; 904 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 906 interrupt-names = "tx", "rx"; 907 908 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; 909 dma-names = "tx", "rx"; 910 911 clocks = <&k3_clks 190 0>; 912 clock-names = "fck"; 913 assigned-clocks = <&k3_clks 190 0>; 914 assigned-clock-parents = <&k3_clks 190 2>; 915 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 916 status = "disabled"; 917 }; 918 919 mcasp1: audio-controller@2b10000 { 920 compatible = "ti,am33xx-mcasp-audio"; 921 reg = <0x00 0x02b10000 0x00 0x2000>, 922 <0x00 0x02b18000 0x00 0x400>; 923 reg-names = "mpu", "dat"; 924 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 926 interrupt-names = "tx", "rx"; 927 928 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; 929 dma-names = "tx", "rx"; 930 931 clocks = <&k3_clks 191 0>; 932 clock-names = "fck"; 933 assigned-clocks = <&k3_clks 191 0>; 934 assigned-clock-parents = <&k3_clks 191 2>; 935 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 936 status = "disabled"; 937 }; 938 939 mcasp2: audio-controller@2b20000 { 940 compatible = "ti,am33xx-mcasp-audio"; 941 reg = <0x00 0x02b20000 0x00 0x2000>, 942 <0x00 0x02b28000 0x00 0x400>; 943 reg-names = "mpu", "dat"; 944 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 946 interrupt-names = "tx", "rx"; 947 948 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; 949 dma-names = "tx", "rx"; 950 951 clocks = <&k3_clks 192 0>; 952 clock-names = "fck"; 953 assigned-clocks = <&k3_clks 192 0>; 954 assigned-clock-parents = <&k3_clks 192 2>; 955 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 956 status = "disabled"; 957 }; 958}; 959