1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Tesla Full Self-Driving SoC device tree source 4 * 5 * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd. 6 * https://www.samsung.com 7 * Copyright (c) 2017-2022 Tesla, Inc. 8 * https://www.tesla.com 9 */ 10 11#include <dt-bindings/clock/fsd-clk.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14/ { 15 compatible = "tesla,fsd"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 i2c0 = &hsi2c_0; 22 i2c1 = &hsi2c_1; 23 i2c2 = &hsi2c_2; 24 i2c3 = &hsi2c_3; 25 i2c4 = &hsi2c_4; 26 i2c5 = &hsi2c_5; 27 i2c6 = &hsi2c_6; 28 i2c7 = &hsi2c_7; 29 pinctrl0 = &pinctrl_fsys0; 30 pinctrl1 = &pinctrl_peric; 31 pinctrl2 = &pinctrl_pmu; 32 spi0 = &spi_0; 33 spi1 = &spi_1; 34 spi2 = &spi_2; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 cpu-map { 42 cluster0 { 43 core0 { 44 cpu = <&cpucl0_0>; 45 }; 46 core1 { 47 cpu = <&cpucl0_1>; 48 }; 49 core2 { 50 cpu = <&cpucl0_2>; 51 }; 52 core3 { 53 cpu = <&cpucl0_3>; 54 }; 55 }; 56 57 cluster1 { 58 core0 { 59 cpu = <&cpucl1_0>; 60 }; 61 core1 { 62 cpu = <&cpucl1_1>; 63 }; 64 core2 { 65 cpu = <&cpucl1_2>; 66 }; 67 core3 { 68 cpu = <&cpucl1_3>; 69 }; 70 }; 71 72 cluster2 { 73 core0 { 74 cpu = <&cpucl2_0>; 75 }; 76 core1 { 77 cpu = <&cpucl2_1>; 78 }; 79 core2 { 80 cpu = <&cpucl2_2>; 81 }; 82 core3 { 83 cpu = <&cpucl2_3>; 84 }; 85 }; 86 }; 87 88 /* Cluster 0 */ 89 cpucl0_0: cpu@0 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a72"; 92 reg = <0x0 0x000>; 93 enable-method = "psci"; 94 clock-frequency = <2400000000>; 95 cpu-idle-states = <&CPU_SLEEP>; 96 }; 97 98 cpucl0_1: cpu@1 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a72"; 101 reg = <0x0 0x001>; 102 enable-method = "psci"; 103 clock-frequency = <2400000000>; 104 cpu-idle-states = <&CPU_SLEEP>; 105 }; 106 107 cpucl0_2: cpu@2 { 108 device_type = "cpu"; 109 compatible = "arm,cortex-a72"; 110 reg = <0x0 0x002>; 111 enable-method = "psci"; 112 clock-frequency = <2400000000>; 113 cpu-idle-states = <&CPU_SLEEP>; 114 }; 115 116 cpucl0_3: cpu@3 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a72"; 119 reg = <0x0 0x003>; 120 enable-method = "psci"; 121 cpu-idle-states = <&CPU_SLEEP>; 122 }; 123 124 /* Cluster 1 */ 125 cpucl1_0: cpu@100 { 126 device_type = "cpu"; 127 compatible = "arm,cortex-a72"; 128 reg = <0x0 0x100>; 129 enable-method = "psci"; 130 clock-frequency = <2400000000>; 131 cpu-idle-states = <&CPU_SLEEP>; 132 }; 133 134 cpucl1_1: cpu@101 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a72"; 137 reg = <0x0 0x101>; 138 enable-method = "psci"; 139 clock-frequency = <2400000000>; 140 cpu-idle-states = <&CPU_SLEEP>; 141 }; 142 143 cpucl1_2: cpu@102 { 144 device_type = "cpu"; 145 compatible = "arm,cortex-a72"; 146 reg = <0x0 0x102>; 147 enable-method = "psci"; 148 clock-frequency = <2400000000>; 149 cpu-idle-states = <&CPU_SLEEP>; 150 }; 151 152 cpucl1_3: cpu@103 { 153 device_type = "cpu"; 154 compatible = "arm,cortex-a72"; 155 reg = <0x0 0x103>; 156 enable-method = "psci"; 157 clock-frequency = <2400000000>; 158 cpu-idle-states = <&CPU_SLEEP>; 159 }; 160 161 /* Cluster 2 */ 162 cpucl2_0: cpu@200 { 163 device_type = "cpu"; 164 compatible = "arm,cortex-a72"; 165 reg = <0x0 0x200>; 166 enable-method = "psci"; 167 clock-frequency = <2400000000>; 168 cpu-idle-states = <&CPU_SLEEP>; 169 }; 170 171 cpucl2_1: cpu@201 { 172 device_type = "cpu"; 173 compatible = "arm,cortex-a72"; 174 reg = <0x0 0x201>; 175 enable-method = "psci"; 176 clock-frequency = <2400000000>; 177 cpu-idle-states = <&CPU_SLEEP>; 178 }; 179 180 cpucl2_2: cpu@202 { 181 device_type = "cpu"; 182 compatible = "arm,cortex-a72"; 183 reg = <0x0 0x202>; 184 enable-method = "psci"; 185 clock-frequency = <2400000000>; 186 cpu-idle-states = <&CPU_SLEEP>; 187 }; 188 189 cpucl2_3: cpu@203 { 190 device_type = "cpu"; 191 compatible = "arm,cortex-a72"; 192 reg = <0x0 0x203>; 193 enable-method = "psci"; 194 clock-frequency = <2400000000>; 195 cpu-idle-states = <&CPU_SLEEP>; 196 }; 197 198 idle-states { 199 entry-method = "psci"; 200 201 CPU_SLEEP: cpu-sleep { 202 idle-state-name = "c2"; 203 compatible = "arm,idle-state"; 204 local-timer-stop; 205 arm,psci-suspend-param = <0x0010000>; 206 entry-latency-us = <30>; 207 exit-latency-us = <75>; 208 min-residency-us = <300>; 209 }; 210 }; 211 }; 212 213 arm-pmu { 214 compatible = "arm,armv8-pmuv3"; 215 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>; 227 interrupt-affinity = <&cpucl0_0>, <&cpucl0_1>, <&cpucl0_2>, 228 <&cpucl0_3>, <&cpucl1_0>, <&cpucl1_1>, 229 <&cpucl1_2>, <&cpucl1_3>, <&cpucl2_0>, 230 <&cpucl2_1>, <&cpucl2_2>, <&cpucl2_3>; 231 }; 232 233 psci { 234 compatible = "arm,psci-1.0"; 235 method = "smc"; 236 }; 237 238 timer { 239 compatible = "arm,armv8-timer"; 240 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 241 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 242 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 243 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 244 }; 245 246 fin_pll: clock { 247 compatible = "fixed-clock"; 248 clock-output-names = "fin_pll"; 249 #clock-cells = <0>; 250 }; 251 252 soc: soc@0 { 253 compatible = "simple-bus"; 254 #address-cells = <2>; 255 #size-cells = <2>; 256 ranges = <0x0 0x0 0x0 0x0 0x0 0x18000000>; 257 dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; 258 259 gic: interrupt-controller@10400000 { 260 compatible = "arm,gic-v3"; 261 #interrupt-cells = <3>; 262 interrupt-controller; 263 reg = <0x0 0x10400000 0x0 0x10000>, /* GICD */ 264 <0x0 0x10600000 0x0 0x200000>; /* GICR_RD+GICR_SGI */ 265 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 266 }; 267 268 smmu_imem: iommu@10200000 { 269 compatible = "arm,mmu-500"; 270 reg = <0x0 0x10200000 0x0 0x10000>; 271 #iommu-cells = <2>; 272 #global-interrupts = <7>; 273 interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */ 274 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */ 275 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */ 276 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */ 277 /* Performance counter interrupts */ 278 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS1_0 */ 279 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS1_1 */ 280 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, /* for IMEM_0 */ 281 /* Per context non-secure context interrupts, 0-3 interrupts */ 282 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */ 283 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_1 */ 284 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_2 */ 285 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_3 */ 286 }; 287 288 smmu_isp: iommu@12100000 { 289 compatible = "arm,mmu-500"; 290 reg = <0x0 0x12100000 0x0 0x10000>; 291 #iommu-cells = <2>; 292 #global-interrupts = <11>; 293 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */ 294 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */ 295 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */ 296 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */ 297 /* Performance counter interrupts */ 298 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_CSI */ 299 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_DP_0 */ 300 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_DP_1 */ 301 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_ISP_0 */ 302 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_ISP_1 */ 303 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_MFC_0 */ 304 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_MFC_1 */ 305 /* Per context non-secure context interrupts, 0-7 interrupts */ 306 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */ 307 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_1 */ 308 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_2 */ 309 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_3 */ 310 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_4 */ 311 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_5 */ 312 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_6 */ 313 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_7 */ 314 }; 315 316 smmu_peric: iommu@14900000 { 317 compatible = "arm,mmu-500"; 318 reg = <0x0 0x14900000 0x0 0x10000>; 319 #iommu-cells = <2>; 320 #global-interrupts = <5>; 321 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */ 322 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */ 323 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */ 324 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */ 325 /* Performance counter interrupts */ 326 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, /* for PERIC */ 327 /* Per context non-secure context interrupts, 0-1 interrupts */ 328 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */ 329 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_1 */ 330 }; 331 332 smmu_fsys0: iommu@15450000 { 333 compatible = "arm,mmu-500"; 334 reg = <0x0 0x15450000 0x0 0x10000>; 335 #iommu-cells = <2>; 336 #global-interrupts = <5>; 337 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */ 338 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */ 339 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */ 340 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */ 341 /* Performance counter interrupts */ 342 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS0 */ 343 /* Per context non-secure context interrupts, 0-1 interrupts */ 344 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */ 345 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_1 */ 346 }; 347 348 clock_imem: clock-controller@10010000 { 349 compatible = "tesla,fsd-clock-imem"; 350 reg = <0x0 0x10010000 0x0 0x3000>; 351 #clock-cells = <1>; 352 clocks = <&fin_pll>, 353 <&clock_cmu DOUT_CMU_IMEM_TCUCLK>, 354 <&clock_cmu DOUT_CMU_IMEM_ACLK>, 355 <&clock_cmu DOUT_CMU_IMEM_DMACLK>; 356 clock-names = "fin_pll", 357 "dout_cmu_imem_tcuclk", 358 "dout_cmu_imem_aclk", 359 "dout_cmu_imem_dmaclk"; 360 }; 361 362 clock_cmu: clock-controller@11c10000 { 363 compatible = "tesla,fsd-clock-cmu"; 364 reg = <0x0 0x11c10000 0x0 0x3000>; 365 #clock-cells = <1>; 366 clocks = <&fin_pll>; 367 clock-names = "fin_pll"; 368 }; 369 370 clock_csi: clock-controller@12610000 { 371 compatible = "tesla,fsd-clock-cam_csi"; 372 reg = <0x0 0x12610000 0x0 0x3000>; 373 #clock-cells = <1>; 374 clocks = <&fin_pll>; 375 clock-names = "fin_pll"; 376 }; 377 378 clock_mfc: clock-controller@12810000 { 379 compatible = "tesla,fsd-clock-mfc"; 380 reg = <0x0 0x12810000 0x0 0x3000>; 381 #clock-cells = <1>; 382 clocks = <&fin_pll>; 383 clock-names = "fin_pll"; 384 }; 385 386 clock_peric: clock-controller@14010000 { 387 compatible = "tesla,fsd-clock-peric"; 388 reg = <0x0 0x14010000 0x0 0x3000>; 389 #clock-cells = <1>; 390 clocks = <&fin_pll>, 391 <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV4>, 392 <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV36>, 393 <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK>, 394 <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV20>, 395 <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV4_DMACLK>; 396 clock-names = "fin_pll", 397 "dout_cmu_pll_shared0_div4", 398 "dout_cmu_peric_shared1div36", 399 "dout_cmu_peric_shared0div3_tbuclk", 400 "dout_cmu_peric_shared0div20", 401 "dout_cmu_peric_shared1div4_dmaclk"; 402 }; 403 404 clock_fsys0: clock-controller@15010000 { 405 compatible = "tesla,fsd-clock-fsys0"; 406 reg = <0x0 0x15010000 0x0 0x3000>; 407 #clock-cells = <1>; 408 clocks = <&fin_pll>, 409 <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV6>, 410 <&clock_cmu DOUT_CMU_FSYS0_SHARED1DIV4>, 411 <&clock_cmu DOUT_CMU_FSYS0_SHARED0DIV4>; 412 clock-names = "fin_pll", 413 "dout_cmu_pll_shared0_div6", 414 "dout_cmu_fsys0_shared1div4", 415 "dout_cmu_fsys0_shared0div4"; 416 }; 417 418 clock_fsys1: clock-controller@16810000 { 419 compatible = "tesla,fsd-clock-fsys1"; 420 reg = <0x0 0x16810000 0x0 0x3000>; 421 #clock-cells = <1>; 422 clocks = <&fin_pll>, 423 <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>, 424 <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>; 425 clock-names = "fin_pll", 426 "dout_cmu_fsys1_shared0div8", 427 "dout_cmu_fsys1_shared0div4"; 428 }; 429 430 mdma0: dma-controller@10100000 { 431 compatible = "arm,pl330", "arm,primecell"; 432 reg = <0x0 0x10100000 0x0 0x1000>; 433 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>; 434 #dma-cells = <1>; 435 #dma-channels = <8>; 436 #dma-requests = <32>; 437 clocks = <&clock_imem IMEM_DMA0_IPCLKPORT_ACLK>; 438 clock-names = "apb_pclk"; 439 iommus = <&smmu_imem 0x800 0x0>; 440 }; 441 442 mdma1: dma-controller@10110000 { 443 compatible = "arm,pl330", "arm,primecell"; 444 reg = <0x0 0x10110000 0x0 0x1000>; 445 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 446 #dma-cells = <1>; 447 #dma-channels = <8>; 448 #dma-requests = <32>; 449 clocks = <&clock_imem IMEM_DMA1_IPCLKPORT_ACLK>; 450 clock-names = "apb_pclk"; 451 iommus = <&smmu_imem 0x801 0x0>; 452 }; 453 454 pdma0: dma-controller@14280000 { 455 compatible = "arm,pl330", "arm,primecell"; 456 reg = <0x0 0x14280000 0x0 0x1000>; 457 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 458 #dma-cells = <1>; 459 #dma-channels = <8>; 460 #dma-requests = <32>; 461 clocks = <&clock_peric PERIC_DMA0_IPCLKPORT_ACLK>; 462 clock-names = "apb_pclk"; 463 iommus = <&smmu_peric 0x2 0x0>; 464 }; 465 466 pdma1: dma-controller@14290000 { 467 compatible = "arm,pl330", "arm,primecell"; 468 reg = <0x0 0x14290000 0x0 0x1000>; 469 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 470 #dma-cells = <1>; 471 #dma-channels = <8>; 472 #dma-requests = <32>; 473 clocks = <&clock_peric PERIC_DMA1_IPCLKPORT_ACLK>; 474 clock-names = "apb_pclk"; 475 iommus = <&smmu_peric 0x1 0x0>; 476 }; 477 478 serial_0: serial@14180000 { 479 compatible = "samsung,exynos4210-uart"; 480 reg = <0x0 0x14180000 0x0 0x100>; 481 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 482 dmas = <&pdma1 1>, <&pdma1 0>; 483 dma-names = "rx", "tx"; 484 clocks = <&clock_peric PERIC_PCLK_UART0>, 485 <&clock_peric PERIC_SCLK_UART0>; 486 clock-names = "uart", "clk_uart_baud0"; 487 status = "disabled"; 488 }; 489 490 serial_1: serial@14190000 { 491 compatible = "samsung,exynos4210-uart"; 492 reg = <0x0 0x14190000 0x0 0x100>; 493 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 494 dmas = <&pdma1 3>, <&pdma1 2>; 495 dma-names = "rx", "tx"; 496 clocks = <&clock_peric PERIC_PCLK_UART1>, 497 <&clock_peric PERIC_SCLK_UART1>; 498 clock-names = "uart", "clk_uart_baud0"; 499 status = "disabled"; 500 }; 501 502 pmu_system_controller: system-controller@11400000 { 503 compatible = "samsung,exynos7-pmu", "syscon"; 504 reg = <0x0 0x11400000 0x0 0x5000>; 505 }; 506 507 watchdog_0: watchdog@100a0000 { 508 compatible = "samsung,exynos7-wdt"; 509 reg = <0x0 0x100a0000 0x0 0x100>; 510 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 511 samsung,syscon-phandle = <&pmu_system_controller>; 512 clocks = <&fin_pll>; 513 clock-names = "watchdog"; 514 }; 515 516 watchdog_1: watchdog@100b0000 { 517 compatible = "samsung,exynos7-wdt"; 518 reg = <0x0 0x100b0000 0x0 0x100>; 519 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 520 samsung,syscon-phandle = <&pmu_system_controller>; 521 clocks = <&fin_pll>; 522 clock-names = "watchdog"; 523 }; 524 525 watchdog_2: watchdog@100c0000 { 526 compatible = "samsung,exynos7-wdt"; 527 reg = <0x0 0x100c0000 0x0 0x100>; 528 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 529 samsung,syscon-phandle = <&pmu_system_controller>; 530 clocks = <&fin_pll>; 531 clock-names = "watchdog"; 532 }; 533 534 pwm_0: pwm@14100000 { 535 compatible = "samsung,exynos4210-pwm"; 536 reg = <0x0 0x14100000 0x0 0x100>; 537 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 538 #pwm-cells = <3>; 539 clocks = <&clock_peric PERIC_PWM0_IPCLKPORT_I_PCLK_S0>; 540 clock-names = "timers"; 541 status = "disabled"; 542 }; 543 544 pwm_1: pwm@14110000 { 545 compatible = "samsung,exynos4210-pwm"; 546 reg = <0x0 0x14110000 0x0 0x100>; 547 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 548 #pwm-cells = <3>; 549 clocks = <&clock_peric PERIC_PWM1_IPCLKPORT_I_PCLK_S0>; 550 clock-names = "timers"; 551 status = "disabled"; 552 }; 553 554 hsi2c_0: i2c@14200000 { 555 compatible = "samsung,exynos7-hsi2c"; 556 reg = <0x0 0x14200000 0x0 0x1000>; 557 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 pinctrl-names = "default"; 561 pinctrl-0 = <&hs_i2c0_bus>; 562 clocks = <&clock_peric PERIC_PCLK_HSI2C0>; 563 clock-names = "hsi2c"; 564 status = "disabled"; 565 }; 566 567 hsi2c_1: i2c@14210000 { 568 compatible = "samsung,exynos7-hsi2c"; 569 reg = <0x0 0x14210000 0x0 0x1000>; 570 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 571 #address-cells = <1>; 572 #size-cells = <0>; 573 pinctrl-names = "default"; 574 pinctrl-0 = <&hs_i2c1_bus>; 575 clocks = <&clock_peric PERIC_PCLK_HSI2C1>; 576 clock-names = "hsi2c"; 577 status = "disabled"; 578 }; 579 580 hsi2c_2: i2c@14220000 { 581 compatible = "samsung,exynos7-hsi2c"; 582 reg = <0x0 0x14220000 0x0 0x1000>; 583 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 584 #address-cells = <1>; 585 #size-cells = <0>; 586 pinctrl-names = "default"; 587 pinctrl-0 = <&hs_i2c2_bus>; 588 clocks = <&clock_peric PERIC_PCLK_HSI2C2>; 589 clock-names = "hsi2c"; 590 status = "disabled"; 591 }; 592 593 hsi2c_3: i2c@14230000 { 594 compatible = "samsung,exynos7-hsi2c"; 595 reg = <0x0 0x14230000 0x0 0x1000>; 596 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 pinctrl-names = "default"; 600 pinctrl-0 = <&hs_i2c3_bus>; 601 clocks = <&clock_peric PERIC_PCLK_HSI2C3>; 602 clock-names = "hsi2c"; 603 status = "disabled"; 604 }; 605 606 hsi2c_4: i2c@14240000 { 607 compatible = "samsung,exynos7-hsi2c"; 608 reg = <0x0 0x14240000 0x0 0x1000>; 609 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 610 #address-cells = <1>; 611 #size-cells = <0>; 612 pinctrl-names = "default"; 613 pinctrl-0 = <&hs_i2c4_bus>; 614 clocks = <&clock_peric PERIC_PCLK_HSI2C4>; 615 clock-names = "hsi2c"; 616 status = "disabled"; 617 }; 618 619 hsi2c_5: i2c@14250000 { 620 compatible = "samsung,exynos7-hsi2c"; 621 reg = <0x0 0x14250000 0x0 0x1000>; 622 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 623 #address-cells = <1>; 624 #size-cells = <0>; 625 pinctrl-names = "default"; 626 pinctrl-0 = <&hs_i2c5_bus>; 627 clocks = <&clock_peric PERIC_PCLK_HSI2C5>; 628 clock-names = "hsi2c"; 629 status = "disabled"; 630 }; 631 632 hsi2c_6: i2c@14260000 { 633 compatible = "samsung,exynos7-hsi2c"; 634 reg = <0x0 0x14260000 0x0 0x1000>; 635 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 pinctrl-names = "default"; 639 pinctrl-0 = <&hs_i2c6_bus>; 640 clocks = <&clock_peric PERIC_PCLK_HSI2C6>; 641 clock-names = "hsi2c"; 642 status = "disabled"; 643 }; 644 645 hsi2c_7: i2c@14270000 { 646 compatible = "samsung,exynos7-hsi2c"; 647 reg = <0x0 0x14270000 0x0 0x1000>; 648 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 649 #address-cells = <1>; 650 #size-cells = <0>; 651 pinctrl-names = "default"; 652 pinctrl-0 = <&hs_i2c7_bus>; 653 clocks = <&clock_peric PERIC_PCLK_HSI2C7>; 654 clock-names = "hsi2c"; 655 status = "disabled"; 656 }; 657 658 pinctrl_pmu: pinctrl@114f0000 { 659 compatible = "tesla,fsd-pinctrl"; 660 reg = <0x0 0x114f0000 0x0 0x1000>; 661 }; 662 663 pinctrl_peric: pinctrl@141f0000 { 664 compatible = "tesla,fsd-pinctrl"; 665 reg = <0x0 0x141f0000 0x0 0x1000>; 666 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 667 }; 668 669 pinctrl_fsys0: pinctrl@15020000 { 670 compatible = "tesla,fsd-pinctrl"; 671 reg = <0x0 0x15020000 0x0 0x1000>; 672 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 673 }; 674 675 spi_0: spi@14140000 { 676 compatible = "tesla,fsd-spi"; 677 reg = <0x0 0x14140000 0x0 0x100>; 678 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 679 dmas = <&pdma1 4>, <&pdma1 5>; 680 dma-names = "tx", "rx"; 681 #address-cells = <1>; 682 #size-cells = <0>; 683 clocks = <&clock_peric PERIC_PCLK_SPI0>, 684 <&clock_peric PERIC_SCLK_SPI0>; 685 clock-names = "spi", "spi_busclk0"; 686 samsung,spi-src-clk = <0>; 687 pinctrl-names = "default"; 688 pinctrl-0 = <&spi0_bus>; 689 num-cs = <1>; 690 status = "disabled"; 691 }; 692 693 spi_1: spi@14150000 { 694 compatible = "tesla,fsd-spi"; 695 reg = <0x0 0x14150000 0x0 0x100>; 696 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 697 dmas = <&pdma1 6>, <&pdma1 7>; 698 dma-names = "tx", "rx"; 699 #address-cells = <1>; 700 #size-cells = <0>; 701 clocks = <&clock_peric PERIC_PCLK_SPI1>, 702 <&clock_peric PERIC_SCLK_SPI1>; 703 clock-names = "spi", "spi_busclk0"; 704 samsung,spi-src-clk = <0>; 705 pinctrl-names = "default"; 706 pinctrl-0 = <&spi1_bus>; 707 num-cs = <1>; 708 status = "disabled"; 709 }; 710 711 spi_2: spi@14160000 { 712 compatible = "tesla,fsd-spi"; 713 reg = <0x0 0x14160000 0x0 0x100>; 714 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 715 dmas = <&pdma1 8>, <&pdma1 9>; 716 dma-names = "tx", "rx"; 717 #address-cells = <1>; 718 #size-cells = <0>; 719 clocks = <&clock_peric PERIC_PCLK_SPI2>, 720 <&clock_peric PERIC_SCLK_SPI2>; 721 clock-names = "spi", "spi_busclk0"; 722 samsung,spi-src-clk = <0>; 723 pinctrl-names = "default"; 724 pinctrl-0 = <&spi2_bus>; 725 num-cs = <1>; 726 status = "disabled"; 727 }; 728 729 timer@10040000 { 730 compatible = "samsung,exynos4210-mct"; 731 reg = <0x0 0x10040000 0x0 0x800>; 732 interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 748 clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>; 749 clock-names = "fin_pll", "mct"; 750 }; 751 }; 752}; 753 754#include "fsd-pinctrl.dtsi" 755