1031106ceSJisheng Zhang// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2031106ceSJisheng Zhang/* 3031106ceSJisheng Zhang * Copyright (C) 2015 Marvell Technology Group Ltd. 4031106ceSJisheng Zhang * 5031106ceSJisheng Zhang * Author: Jisheng Zhang <jszhang@marvell.com> 6031106ceSJisheng Zhang */ 7031106ceSJisheng Zhang 8031106ceSJisheng Zhang#include <dt-bindings/interrupt-controller/arm-gic.h> 9031106ceSJisheng Zhang 10031106ceSJisheng Zhang/ { 11031106ceSJisheng Zhang compatible = "marvell,berlin4ct", "marvell,berlin"; 12031106ceSJisheng Zhang interrupt-parent = <&gic>; 13031106ceSJisheng Zhang #address-cells = <2>; 14031106ceSJisheng Zhang #size-cells = <2>; 15031106ceSJisheng Zhang 16031106ceSJisheng Zhang aliases { 17031106ceSJisheng Zhang serial0 = &uart0; 18031106ceSJisheng Zhang }; 19031106ceSJisheng Zhang 20031106ceSJisheng Zhang psci { 21031106ceSJisheng Zhang compatible = "arm,psci-1.0", "arm,psci-0.2"; 22031106ceSJisheng Zhang method = "smc"; 23031106ceSJisheng Zhang }; 24031106ceSJisheng Zhang 25031106ceSJisheng Zhang cpus { 26031106ceSJisheng Zhang #address-cells = <1>; 27031106ceSJisheng Zhang #size-cells = <0>; 28031106ceSJisheng Zhang 29031106ceSJisheng Zhang cpu0: cpu@0 { 3031af04cdSRob Herring compatible = "arm,cortex-a53"; 31031106ceSJisheng Zhang device_type = "cpu"; 32031106ceSJisheng Zhang reg = <0x0>; 33031106ceSJisheng Zhang enable-method = "psci"; 34031106ceSJisheng Zhang next-level-cache = <&l2>; 35031106ceSJisheng Zhang cpu-idle-states = <&CPU_SLEEP_0>; 36031106ceSJisheng Zhang }; 37031106ceSJisheng Zhang 38031106ceSJisheng Zhang cpu1: cpu@1 { 3931af04cdSRob Herring compatible = "arm,cortex-a53"; 40031106ceSJisheng Zhang device_type = "cpu"; 41031106ceSJisheng Zhang reg = <0x1>; 42031106ceSJisheng Zhang enable-method = "psci"; 43031106ceSJisheng Zhang next-level-cache = <&l2>; 44031106ceSJisheng Zhang cpu-idle-states = <&CPU_SLEEP_0>; 45031106ceSJisheng Zhang }; 46031106ceSJisheng Zhang 47031106ceSJisheng Zhang cpu2: cpu@2 { 4831af04cdSRob Herring compatible = "arm,cortex-a53"; 49031106ceSJisheng Zhang device_type = "cpu"; 50031106ceSJisheng Zhang reg = <0x2>; 51031106ceSJisheng Zhang enable-method = "psci"; 52031106ceSJisheng Zhang next-level-cache = <&l2>; 53031106ceSJisheng Zhang cpu-idle-states = <&CPU_SLEEP_0>; 54031106ceSJisheng Zhang }; 55031106ceSJisheng Zhang 56031106ceSJisheng Zhang cpu3: cpu@3 { 5731af04cdSRob Herring compatible = "arm,cortex-a53"; 58031106ceSJisheng Zhang device_type = "cpu"; 59031106ceSJisheng Zhang reg = <0x3>; 60031106ceSJisheng Zhang enable-method = "psci"; 61031106ceSJisheng Zhang next-level-cache = <&l2>; 62031106ceSJisheng Zhang cpu-idle-states = <&CPU_SLEEP_0>; 63031106ceSJisheng Zhang }; 64031106ceSJisheng Zhang 65031106ceSJisheng Zhang l2: cache { 66031106ceSJisheng Zhang compatible = "cache"; 67031106ceSJisheng Zhang }; 68031106ceSJisheng Zhang 69031106ceSJisheng Zhang idle-states { 70031106ceSJisheng Zhang entry-method = "psci"; 71031106ceSJisheng Zhang CPU_SLEEP_0: cpu-sleep-0 { 72031106ceSJisheng Zhang compatible = "arm,idle-state"; 73031106ceSJisheng Zhang local-timer-stop; 74031106ceSJisheng Zhang arm,psci-suspend-param = <0x0010000>; 75031106ceSJisheng Zhang entry-latency-us = <75>; 76031106ceSJisheng Zhang exit-latency-us = <155>; 77031106ceSJisheng Zhang min-residency-us = <1000>; 78031106ceSJisheng Zhang }; 79031106ceSJisheng Zhang }; 80031106ceSJisheng Zhang }; 81031106ceSJisheng Zhang 82031106ceSJisheng Zhang osc: osc { 83031106ceSJisheng Zhang compatible = "fixed-clock"; 84031106ceSJisheng Zhang #clock-cells = <0>; 85031106ceSJisheng Zhang clock-frequency = <25000000>; 86031106ceSJisheng Zhang }; 87031106ceSJisheng Zhang 88031106ceSJisheng Zhang pmu { 89031106ceSJisheng Zhang compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; 90031106ceSJisheng Zhang interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 91031106ceSJisheng Zhang <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 92031106ceSJisheng Zhang <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 93031106ceSJisheng Zhang <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 94031106ceSJisheng Zhang interrupt-affinity = <&cpu0>, 95031106ceSJisheng Zhang <&cpu1>, 96031106ceSJisheng Zhang <&cpu2>, 97031106ceSJisheng Zhang <&cpu3>; 98031106ceSJisheng Zhang }; 99031106ceSJisheng Zhang 100031106ceSJisheng Zhang timer { 101031106ceSJisheng Zhang compatible = "arm,armv8-timer"; 102031106ceSJisheng Zhang interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 103031106ceSJisheng Zhang <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 104031106ceSJisheng Zhang <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 105031106ceSJisheng Zhang <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 106031106ceSJisheng Zhang }; 107031106ceSJisheng Zhang 108031106ceSJisheng Zhang soc@f7000000 { 109031106ceSJisheng Zhang compatible = "simple-bus"; 110031106ceSJisheng Zhang #address-cells = <1>; 111031106ceSJisheng Zhang #size-cells = <1>; 112031106ceSJisheng Zhang ranges = <0 0 0xf7000000 0x1000000>; 113031106ceSJisheng Zhang 114031106ceSJisheng Zhang gic: interrupt-controller@901000 { 115031106ceSJisheng Zhang compatible = "arm,gic-400"; 116031106ceSJisheng Zhang #interrupt-cells = <3>; 117031106ceSJisheng Zhang interrupt-controller; 118031106ceSJisheng Zhang reg = <0x901000 0x1000>, 119031106ceSJisheng Zhang <0x902000 0x2000>, 120031106ceSJisheng Zhang <0x904000 0x2000>, 121031106ceSJisheng Zhang <0x906000 0x2000>; 122031106ceSJisheng Zhang interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 123031106ceSJisheng Zhang }; 124031106ceSJisheng Zhang 125031106ceSJisheng Zhang apb@e80000 { 126031106ceSJisheng Zhang compatible = "simple-bus"; 127031106ceSJisheng Zhang #address-cells = <1>; 128031106ceSJisheng Zhang #size-cells = <1>; 129031106ceSJisheng Zhang 130031106ceSJisheng Zhang ranges = <0 0xe80000 0x10000>; 131031106ceSJisheng Zhang interrupt-parent = <&aic>; 132031106ceSJisheng Zhang 133031106ceSJisheng Zhang gpio0: gpio@400 { 134031106ceSJisheng Zhang compatible = "snps,dw-apb-gpio"; 135031106ceSJisheng Zhang reg = <0x0400 0x400>; 136031106ceSJisheng Zhang #address-cells = <1>; 137031106ceSJisheng Zhang #size-cells = <0>; 138031106ceSJisheng Zhang 139031106ceSJisheng Zhang porta: gpio-port@0 { 140031106ceSJisheng Zhang compatible = "snps,dw-apb-gpio-port"; 141031106ceSJisheng Zhang gpio-controller; 142031106ceSJisheng Zhang #gpio-cells = <2>; 143*ec13e502SJisheng Zhang ngpios = <32>; 144031106ceSJisheng Zhang reg = <0>; 145031106ceSJisheng Zhang interrupt-controller; 146031106ceSJisheng Zhang #interrupt-cells = <2>; 147031106ceSJisheng Zhang interrupts = <0>; 148031106ceSJisheng Zhang }; 149031106ceSJisheng Zhang }; 150031106ceSJisheng Zhang 151031106ceSJisheng Zhang gpio1: gpio@800 { 152031106ceSJisheng Zhang compatible = "snps,dw-apb-gpio"; 153031106ceSJisheng Zhang reg = <0x0800 0x400>; 154031106ceSJisheng Zhang #address-cells = <1>; 155031106ceSJisheng Zhang #size-cells = <0>; 156031106ceSJisheng Zhang 157031106ceSJisheng Zhang portb: gpio-port@1 { 158031106ceSJisheng Zhang compatible = "snps,dw-apb-gpio-port"; 159031106ceSJisheng Zhang gpio-controller; 160031106ceSJisheng Zhang #gpio-cells = <2>; 161*ec13e502SJisheng Zhang ngpios = <32>; 162031106ceSJisheng Zhang reg = <0>; 163031106ceSJisheng Zhang interrupt-controller; 164031106ceSJisheng Zhang #interrupt-cells = <2>; 165031106ceSJisheng Zhang interrupts = <1>; 166031106ceSJisheng Zhang }; 167031106ceSJisheng Zhang }; 168031106ceSJisheng Zhang 169031106ceSJisheng Zhang gpio2: gpio@c00 { 170031106ceSJisheng Zhang compatible = "snps,dw-apb-gpio"; 171031106ceSJisheng Zhang reg = <0x0c00 0x400>; 172031106ceSJisheng Zhang #address-cells = <1>; 173031106ceSJisheng Zhang #size-cells = <0>; 174031106ceSJisheng Zhang 175031106ceSJisheng Zhang portc: gpio-port@2 { 176031106ceSJisheng Zhang compatible = "snps,dw-apb-gpio-port"; 177031106ceSJisheng Zhang gpio-controller; 178031106ceSJisheng Zhang #gpio-cells = <2>; 179*ec13e502SJisheng Zhang ngpios = <32>; 180031106ceSJisheng Zhang reg = <0>; 181031106ceSJisheng Zhang interrupt-controller; 182031106ceSJisheng Zhang #interrupt-cells = <2>; 183031106ceSJisheng Zhang interrupts = <2>; 184031106ceSJisheng Zhang }; 185031106ceSJisheng Zhang }; 186031106ceSJisheng Zhang 187031106ceSJisheng Zhang gpio3: gpio@1000 { 188031106ceSJisheng Zhang compatible = "snps,dw-apb-gpio"; 189031106ceSJisheng Zhang reg = <0x1000 0x400>; 190031106ceSJisheng Zhang #address-cells = <1>; 191031106ceSJisheng Zhang #size-cells = <0>; 192031106ceSJisheng Zhang 193031106ceSJisheng Zhang portd: gpio-port@3 { 194031106ceSJisheng Zhang compatible = "snps,dw-apb-gpio-port"; 195031106ceSJisheng Zhang gpio-controller; 196031106ceSJisheng Zhang #gpio-cells = <2>; 197*ec13e502SJisheng Zhang ngpios = <32>; 198031106ceSJisheng Zhang reg = <0>; 199031106ceSJisheng Zhang interrupt-controller; 200031106ceSJisheng Zhang #interrupt-cells = <2>; 201031106ceSJisheng Zhang interrupts = <3>; 202031106ceSJisheng Zhang }; 203031106ceSJisheng Zhang }; 204031106ceSJisheng Zhang 205031106ceSJisheng Zhang aic: interrupt-controller@3800 { 206031106ceSJisheng Zhang compatible = "snps,dw-apb-ictl"; 207031106ceSJisheng Zhang reg = <0x3800 0x30>; 208031106ceSJisheng Zhang interrupt-controller; 209031106ceSJisheng Zhang #interrupt-cells = <1>; 210031106ceSJisheng Zhang interrupt-parent = <&gic>; 211031106ceSJisheng Zhang interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 212031106ceSJisheng Zhang }; 213031106ceSJisheng Zhang }; 214031106ceSJisheng Zhang 215031106ceSJisheng Zhang soc_pinctrl: pin-controller@ea8000 { 216031106ceSJisheng Zhang compatible = "marvell,berlin4ct-soc-pinctrl"; 217031106ceSJisheng Zhang reg = <0xea8000 0x14>; 218031106ceSJisheng Zhang }; 219031106ceSJisheng Zhang 220031106ceSJisheng Zhang avio_pinctrl: pin-controller@ea8400 { 221031106ceSJisheng Zhang compatible = "marvell,berlin4ct-avio-pinctrl"; 222031106ceSJisheng Zhang reg = <0xea8400 0x8>; 223031106ceSJisheng Zhang }; 224031106ceSJisheng Zhang 225031106ceSJisheng Zhang apb@fc0000 { 226031106ceSJisheng Zhang compatible = "simple-bus"; 227031106ceSJisheng Zhang #address-cells = <1>; 228031106ceSJisheng Zhang #size-cells = <1>; 229031106ceSJisheng Zhang ranges = <0 0xfc0000 0x10000>; 230031106ceSJisheng Zhang interrupt-parent = <&sic>; 231031106ceSJisheng Zhang 232031106ceSJisheng Zhang sic: interrupt-controller@1000 { 233031106ceSJisheng Zhang compatible = "snps,dw-apb-ictl"; 234031106ceSJisheng Zhang reg = <0x1000 0x30>; 235031106ceSJisheng Zhang interrupt-controller; 236031106ceSJisheng Zhang #interrupt-cells = <1>; 237031106ceSJisheng Zhang interrupt-parent = <&gic>; 238031106ceSJisheng Zhang interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 239031106ceSJisheng Zhang }; 240031106ceSJisheng Zhang 241031106ceSJisheng Zhang wdt0: watchdog@3000 { 242031106ceSJisheng Zhang compatible = "snps,dw-wdt"; 243031106ceSJisheng Zhang reg = <0x3000 0x100>; 244031106ceSJisheng Zhang clocks = <&osc>; 245031106ceSJisheng Zhang interrupts = <0>; 246031106ceSJisheng Zhang }; 247031106ceSJisheng Zhang 248031106ceSJisheng Zhang wdt1: watchdog@4000 { 249031106ceSJisheng Zhang compatible = "snps,dw-wdt"; 250031106ceSJisheng Zhang reg = <0x4000 0x100>; 251031106ceSJisheng Zhang clocks = <&osc>; 252031106ceSJisheng Zhang interrupts = <1>; 253031106ceSJisheng Zhang }; 254031106ceSJisheng Zhang 255031106ceSJisheng Zhang wdt2: watchdog@5000 { 256031106ceSJisheng Zhang compatible = "snps,dw-wdt"; 257031106ceSJisheng Zhang reg = <0x5000 0x100>; 258031106ceSJisheng Zhang clocks = <&osc>; 259031106ceSJisheng Zhang interrupts = <2>; 260031106ceSJisheng Zhang }; 261031106ceSJisheng Zhang 262031106ceSJisheng Zhang sm_gpio0: gpio@8000 { 263031106ceSJisheng Zhang compatible = "snps,dw-apb-gpio"; 264031106ceSJisheng Zhang reg = <0x8000 0x400>; 265031106ceSJisheng Zhang #address-cells = <1>; 266031106ceSJisheng Zhang #size-cells = <0>; 267031106ceSJisheng Zhang 268031106ceSJisheng Zhang porte: gpio-port@4 { 269031106ceSJisheng Zhang compatible = "snps,dw-apb-gpio-port"; 270031106ceSJisheng Zhang gpio-controller; 271031106ceSJisheng Zhang #gpio-cells = <2>; 272*ec13e502SJisheng Zhang ngpios = <32>; 273031106ceSJisheng Zhang reg = <0>; 274031106ceSJisheng Zhang }; 275031106ceSJisheng Zhang }; 276031106ceSJisheng Zhang 277031106ceSJisheng Zhang sm_gpio1: gpio@9000 { 278031106ceSJisheng Zhang compatible = "snps,dw-apb-gpio"; 279031106ceSJisheng Zhang reg = <0x9000 0x400>; 280031106ceSJisheng Zhang #address-cells = <1>; 281031106ceSJisheng Zhang #size-cells = <0>; 282031106ceSJisheng Zhang 283031106ceSJisheng Zhang portf: gpio-port@5 { 284031106ceSJisheng Zhang compatible = "snps,dw-apb-gpio-port"; 285031106ceSJisheng Zhang gpio-controller; 286031106ceSJisheng Zhang #gpio-cells = <2>; 287*ec13e502SJisheng Zhang ngpios = <32>; 288031106ceSJisheng Zhang reg = <0>; 289031106ceSJisheng Zhang }; 290031106ceSJisheng Zhang }; 291031106ceSJisheng Zhang 292031106ceSJisheng Zhang uart0: uart@d000 { 293031106ceSJisheng Zhang compatible = "snps,dw-apb-uart"; 294031106ceSJisheng Zhang reg = <0xd000 0x100>; 295031106ceSJisheng Zhang interrupts = <8>; 296031106ceSJisheng Zhang clocks = <&osc>; 297031106ceSJisheng Zhang reg-shift = <2>; 298031106ceSJisheng Zhang status = "disabled"; 299031106ceSJisheng Zhang pinctrl-0 = <&uart0_pmux>; 300031106ceSJisheng Zhang pinctrl-names = "default"; 301031106ceSJisheng Zhang }; 302031106ceSJisheng Zhang }; 303031106ceSJisheng Zhang 304031106ceSJisheng Zhang system_pinctrl: pin-controller@fe2200 { 305031106ceSJisheng Zhang compatible = "marvell,berlin4ct-system-pinctrl"; 306031106ceSJisheng Zhang reg = <0xfe2200 0xc>; 307031106ceSJisheng Zhang 308031106ceSJisheng Zhang uart0_pmux: uart0-pmux { 309031106ceSJisheng Zhang groups = "SM_URT0_TXD", "SM_URT0_RXD"; 310031106ceSJisheng Zhang function = "uart0"; 311031106ceSJisheng Zhang }; 312031106ceSJisheng Zhang }; 313031106ceSJisheng Zhang }; 314031106ceSJisheng Zhang}; 315