1/* 2 * Spreadtrum Whale2 platform peripherals 3 * 4 * Copyright (C) 2016, Spreadtrum Communications Inc. 5 * 6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 */ 8 9#include <dt-bindings/clock/sprd,sc9860-clk.h> 10 11/ { 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 soc: soc { 17 compatible = "simple-bus"; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 ranges; 21 22 ap_ahb_regs: syscon@20210000 { 23 compatible = "syscon"; 24 reg = <0 0x20210000 0 0x10000>; 25 }; 26 27 pmu_regs: syscon@402b0000 { 28 compatible = "syscon"; 29 reg = <0 0x402b0000 0 0x10000>; 30 }; 31 32 aon_regs: syscon@402e0000 { 33 compatible = "syscon"; 34 reg = <0 0x402e0000 0 0x10000>; 35 }; 36 37 ana_regs: syscon@40400000 { 38 compatible = "syscon"; 39 reg = <0 0x40400000 0 0x10000>; 40 }; 41 42 agcp_regs: syscon@415e0000 { 43 compatible = "syscon"; 44 reg = <0 0x415e0000 0 0x1000000>; 45 }; 46 47 vsp_regs: syscon@61100000 { 48 compatible = "syscon"; 49 reg = <0 0x61100000 0 0x10000>; 50 }; 51 52 cam_regs: syscon@62100000 { 53 compatible = "syscon"; 54 reg = <0 0x62100000 0 0x10000>; 55 }; 56 57 disp_regs: syscon@63100000 { 58 compatible = "syscon"; 59 reg = <0 0x63100000 0 0x10000>; 60 }; 61 62 ap_apb_regs: syscon@70b00000 { 63 compatible = "syscon"; 64 reg = <0 0x70b00000 0 0x40000>; 65 }; 66 67 ap-apb { 68 compatible = "simple-bus"; 69 #address-cells = <1>; 70 #size-cells = <1>; 71 ranges = <0 0x0 0x70000000 0x10000000>; 72 73 uart0: serial@0 { 74 compatible = "sprd,sc9860-uart", 75 "sprd,sc9836-uart"; 76 reg = <0x0 0x100>; 77 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 78 clocks = <&ext_26m>; 79 status = "disabled"; 80 }; 81 82 uart1: serial@100000 { 83 compatible = "sprd,sc9860-uart", 84 "sprd,sc9836-uart"; 85 reg = <0x100000 0x100>; 86 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 87 clocks = <&ext_26m>; 88 status = "disabled"; 89 }; 90 91 uart2: serial@200000 { 92 compatible = "sprd,sc9860-uart", 93 "sprd,sc9836-uart"; 94 reg = <0x200000 0x100>; 95 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 96 clocks = <&ext_26m>; 97 status = "disabled"; 98 }; 99 100 uart3: serial@300000 { 101 compatible = "sprd,sc9860-uart", 102 "sprd,sc9836-uart"; 103 reg = <0x300000 0x100>; 104 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 105 clocks = <&ext_26m>; 106 status = "disabled"; 107 }; 108 }; 109 110 ap-ahb { 111 compatible = "simple-bus"; 112 #address-cells = <2>; 113 #size-cells = <2>; 114 ranges; 115 116 ap_dma: dma-controller@20100000 { 117 compatible = "sprd,sc9860-dma"; 118 reg = <0 0x20100000 0 0x4000>; 119 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 120 #dma-cells = <1>; 121 #dma-channels = <32>; 122 clock-names = "enable"; 123 clocks = <&apahb_gate CLK_DMA_EB>; 124 }; 125 }; 126 127 aon { 128 compatible = "simple-bus"; 129 #address-cells = <2>; 130 #size-cells = <2>; 131 ranges; 132 133 adi_bus: spi@40030000 { 134 compatible = "sprd,sc9860-adi"; 135 reg = <0 0x40030000 0 0x10000>; 136 hwlocks = <&hwlock 0>; 137 hwlock-names = "adi"; 138 #address-cells = <1>; 139 #size-cells = <0>; 140 }; 141 142 timer@40050000 { 143 compatible = "sprd,sc9860-timer"; 144 reg = <0 0x40050000 0 0x20>; 145 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 146 clocks = <&ext_32k>; 147 }; 148 149 hwlock: hwspinlock@40500000 { 150 compatible = "sprd,hwspinlock-r3p0"; 151 reg = <0 0x40500000 0 0x1000>; 152 #hwlock-cells = <1>; 153 clock-names = "enable"; 154 clocks = <&aon_gate CLK_SPLK_EB>; 155 }; 156 157 eic_debounce: gpio@40210000 { 158 compatible = "sprd,sc9860-eic-debounce"; 159 reg = <0 0x40210000 0 0x80>; 160 gpio-controller; 161 #gpio-cells = <2>; 162 interrupt-controller; 163 #interrupt-cells = <2>; 164 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 165 }; 166 167 eic_latch: gpio@40210080 { 168 compatible = "sprd,sc9860-eic-latch"; 169 reg = <0 0x40210080 0 0x20>; 170 gpio-controller; 171 #gpio-cells = <2>; 172 interrupt-controller; 173 #interrupt-cells = <2>; 174 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 175 }; 176 177 eic_async: gpio@402100a0 { 178 compatible = "sprd,sc9860-eic-async"; 179 reg = <0 0x402100a0 0 0x20>; 180 gpio-controller; 181 #gpio-cells = <2>; 182 interrupt-controller; 183 #interrupt-cells = <2>; 184 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 185 }; 186 187 eic_sync: gpio@402100c0 { 188 compatible = "sprd,sc9860-eic-sync"; 189 reg = <0 0x402100c0 0 0x20>; 190 gpio-controller; 191 #gpio-cells = <2>; 192 interrupt-controller; 193 #interrupt-cells = <2>; 194 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 195 }; 196 197 ap_gpio: gpio@40280000 { 198 compatible = "sprd,sc9860-gpio"; 199 reg = <0 0x40280000 0 0x1000>; 200 gpio-controller; 201 #gpio-cells = <2>; 202 interrupt-controller; 203 #interrupt-cells = <2>; 204 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 205 }; 206 207 pin_controller: pinctrl@402a0000 { 208 compatible = "sprd,sc9860-pinctrl"; 209 reg = <0 0x402a0000 0 0x10000>; 210 }; 211 212 watchdog@40310000 { 213 compatible = "sprd,sp9860-wdt"; 214 reg = <0 0x40310000 0 0x1000>; 215 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 216 timeout-sec = <12>; 217 clock-names = "enable", "rtc_enable"; 218 clocks = <&aon_gate CLK_APCPU_WDG_EB>, 219 <&aon_gate CLK_AP_WDG_RTC_EB>; 220 }; 221 }; 222 223 agcp { 224 compatible = "simple-bus"; 225 #address-cells = <2>; 226 #size-cells = <2>; 227 ranges; 228 229 agcp_dma: dma-controller@41580000 { 230 compatible = "sprd,sc9860-dma"; 231 reg = <0 0x41580000 0 0x4000>; 232 #dma-cells = <1>; 233 #dma-channels = <32>; 234 clock-names = "enable", "ashb_eb"; 235 clocks = <&agcp_gate CLK_AGCP_DMAAP_EB>, 236 <&agcp_gate CLK_AGCP_AP_ASHB_EB>; 237 }; 238 }; 239 }; 240 241 ext_32k: ext_32k { 242 compatible = "fixed-clock"; 243 #clock-cells = <0>; 244 clock-frequency = <32768>; 245 clock-output-names = "ext-32k"; 246 }; 247 248 ext_26m: ext_26m { 249 compatible = "fixed-clock"; 250 #clock-cells = <0>; 251 clock-frequency = <26000000>; 252 clock-output-names = "ext-26m"; 253 }; 254 255 ext_rco_100m: ext_rco_100m { 256 compatible = "fixed-clock"; 257 #clock-cells = <0>; 258 clock-frequency = <100000000>; 259 clock-output-names = "ext-rco-100m"; 260 }; 261}; 262