1/* 2 * Spreadtrum Whale2 platform peripherals 3 * 4 * Copyright (C) 2016, Spreadtrum Communications Inc. 5 * 6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 */ 8 9#include <dt-bindings/clock/sprd,sc9860-clk.h> 10 11/ { 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 soc: soc { 17 compatible = "simple-bus"; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 ranges; 21 22 ap_ahb_regs: syscon@20210000 { 23 compatible = "syscon"; 24 reg = <0 0x20210000 0 0x10000>; 25 }; 26 27 pmu_regs: syscon@402b0000 { 28 compatible = "syscon"; 29 reg = <0 0x402b0000 0 0x10000>; 30 }; 31 32 aon_regs: syscon@402e0000 { 33 compatible = "syscon"; 34 reg = <0 0x402e0000 0 0x10000>; 35 }; 36 37 ana_regs: syscon@40400000 { 38 compatible = "syscon"; 39 reg = <0 0x40400000 0 0x10000>; 40 }; 41 42 agcp_regs: syscon@415e0000 { 43 compatible = "syscon"; 44 reg = <0 0x415e0000 0 0x1000000>; 45 }; 46 47 vsp_regs: syscon@61100000 { 48 compatible = "syscon"; 49 reg = <0 0x61100000 0 0x10000>; 50 }; 51 52 cam_regs: syscon@62100000 { 53 compatible = "syscon"; 54 reg = <0 0x62100000 0 0x10000>; 55 }; 56 57 disp_regs: syscon@63100000 { 58 compatible = "syscon"; 59 reg = <0 0x63100000 0 0x10000>; 60 }; 61 62 ap_apb_regs: syscon@70b00000 { 63 compatible = "syscon"; 64 reg = <0 0x70b00000 0 0x40000>; 65 }; 66 67 ap-apb { 68 compatible = "simple-bus"; 69 #address-cells = <1>; 70 #size-cells = <1>; 71 ranges = <0 0x0 0x70000000 0x10000000>; 72 73 uart0: serial@0 { 74 compatible = "sprd,sc9860-uart", 75 "sprd,sc9836-uart"; 76 reg = <0x0 0x100>; 77 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 78 clock-names = "enable", "uart", "source"; 79 clocks = <&apapb_gate CLK_UART0_EB>, 80 <&ap_clk CLK_UART0>, <&ext_26m>; 81 status = "disabled"; 82 }; 83 84 uart1: serial@100000 { 85 compatible = "sprd,sc9860-uart", 86 "sprd,sc9836-uart"; 87 reg = <0x100000 0x100>; 88 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 89 clock-names = "enable", "uart", "source"; 90 clocks = <&apapb_gate CLK_UART1_EB>, 91 <&ap_clk CLK_UART1>, <&ext_26m>; 92 status = "disabled"; 93 }; 94 95 uart2: serial@200000 { 96 compatible = "sprd,sc9860-uart", 97 "sprd,sc9836-uart"; 98 reg = <0x200000 0x100>; 99 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 100 clock-names = "enable", "uart", "source"; 101 clocks = <&apapb_gate CLK_UART2_EB>, 102 <&ap_clk CLK_UART2>, <&ext_26m>; 103 status = "disabled"; 104 }; 105 106 uart3: serial@300000 { 107 compatible = "sprd,sc9860-uart", 108 "sprd,sc9836-uart"; 109 reg = <0x300000 0x100>; 110 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 111 clock-names = "enable", "uart", "source"; 112 clocks = <&apapb_gate CLK_UART3_EB>, 113 <&ap_clk CLK_UART3>, <&ext_26m>; 114 status = "disabled"; 115 }; 116 }; 117 118 ap-ahb { 119 compatible = "simple-bus"; 120 #address-cells = <2>; 121 #size-cells = <2>; 122 ranges; 123 124 ap_dma: dma-controller@20100000 { 125 compatible = "sprd,sc9860-dma"; 126 reg = <0 0x20100000 0 0x4000>; 127 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 128 #dma-cells = <1>; 129 #dma-channels = <32>; 130 clock-names = "enable"; 131 clocks = <&apahb_gate CLK_DMA_EB>; 132 }; 133 }; 134 135 aon { 136 compatible = "simple-bus"; 137 #address-cells = <2>; 138 #size-cells = <2>; 139 ranges; 140 141 adi_bus: spi@40030000 { 142 compatible = "sprd,sc9860-adi"; 143 reg = <0 0x40030000 0 0x10000>; 144 hwlocks = <&hwlock 0>; 145 hwlock-names = "adi"; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 }; 149 150 timer@40050000 { 151 compatible = "sprd,sc9860-timer"; 152 reg = <0 0x40050000 0 0x20>; 153 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 154 clocks = <&ext_32k>; 155 }; 156 157 timer@40050020 { 158 compatible = "sprd,sc9860-suspend-timer"; 159 reg = <0 0x40050020 0 0x20>; 160 clocks = <&ext_32k>; 161 }; 162 163 hwlock: hwspinlock@40500000 { 164 compatible = "sprd,hwspinlock-r3p0"; 165 reg = <0 0x40500000 0 0x1000>; 166 #hwlock-cells = <1>; 167 clock-names = "enable"; 168 clocks = <&aon_gate CLK_SPLK_EB>; 169 }; 170 171 eic_debounce: gpio@40210000 { 172 compatible = "sprd,sc9860-eic-debounce"; 173 reg = <0 0x40210000 0 0x80>; 174 gpio-controller; 175 #gpio-cells = <2>; 176 interrupt-controller; 177 #interrupt-cells = <2>; 178 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 179 }; 180 181 eic_latch: gpio@40210080 { 182 compatible = "sprd,sc9860-eic-latch"; 183 reg = <0 0x40210080 0 0x20>; 184 gpio-controller; 185 #gpio-cells = <2>; 186 interrupt-controller; 187 #interrupt-cells = <2>; 188 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 189 }; 190 191 eic_async: gpio@402100a0 { 192 compatible = "sprd,sc9860-eic-async"; 193 reg = <0 0x402100a0 0 0x20>; 194 gpio-controller; 195 #gpio-cells = <2>; 196 interrupt-controller; 197 #interrupt-cells = <2>; 198 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 199 }; 200 201 eic_sync: gpio@402100c0 { 202 compatible = "sprd,sc9860-eic-sync"; 203 reg = <0 0x402100c0 0 0x20>; 204 gpio-controller; 205 #gpio-cells = <2>; 206 interrupt-controller; 207 #interrupt-cells = <2>; 208 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 209 }; 210 211 ap_gpio: gpio@40280000 { 212 compatible = "sprd,sc9860-gpio"; 213 reg = <0 0x40280000 0 0x1000>; 214 gpio-controller; 215 #gpio-cells = <2>; 216 interrupt-controller; 217 #interrupt-cells = <2>; 218 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 219 }; 220 221 pin_controller: pinctrl@402a0000 { 222 compatible = "sprd,sc9860-pinctrl"; 223 reg = <0 0x402a0000 0 0x10000>; 224 }; 225 226 watchdog@40310000 { 227 compatible = "sprd,sp9860-wdt"; 228 reg = <0 0x40310000 0 0x1000>; 229 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 230 timeout-sec = <12>; 231 clock-names = "enable", "rtc_enable"; 232 clocks = <&aon_gate CLK_APCPU_WDG_EB>, 233 <&aon_gate CLK_AP_WDG_RTC_EB>; 234 }; 235 }; 236 237 agcp { 238 compatible = "simple-bus"; 239 #address-cells = <2>; 240 #size-cells = <2>; 241 ranges; 242 243 agcp_dma: dma-controller@41580000 { 244 compatible = "sprd,sc9860-dma"; 245 reg = <0 0x41580000 0 0x4000>; 246 #dma-cells = <1>; 247 #dma-channels = <32>; 248 clock-names = "enable", "ashb_eb"; 249 clocks = <&agcp_gate CLK_AGCP_DMAAP_EB>, 250 <&agcp_gate CLK_AGCP_AP_ASHB_EB>; 251 }; 252 }; 253 }; 254 255 ext_32k: ext_32k { 256 compatible = "fixed-clock"; 257 #clock-cells = <0>; 258 clock-frequency = <32768>; 259 clock-output-names = "ext-32k"; 260 }; 261 262 ext_26m: ext_26m { 263 compatible = "fixed-clock"; 264 #clock-cells = <0>; 265 clock-frequency = <26000000>; 266 clock-output-names = "ext-26m"; 267 }; 268 269 ext_rco_100m: ext_rco_100m { 270 compatible = "fixed-clock"; 271 #clock-cells = <0>; 272 clock-frequency = <100000000>; 273 clock-output-names = "ext-rco-100m"; 274 }; 275}; 276