1c46388a5SZhizhou Zhang/* 2c46388a5SZhizhou Zhang * Spreadtrum Sharkl64 platform DTS file 3c46388a5SZhizhou Zhang * 4c46388a5SZhizhou Zhang * Copyright (C) 2014, Spreadtrum Communications Inc. 5c46388a5SZhizhou Zhang * 6c46388a5SZhizhou Zhang * This file is licensed under a dual GPLv2 or X11 license. 7c46388a5SZhizhou Zhang */ 8c46388a5SZhizhou Zhang 9c46388a5SZhizhou Zhang/ { 10c46388a5SZhizhou Zhang interrupt-parent = <&gic>; 11c46388a5SZhizhou Zhang #address-cells = <2>; 12c46388a5SZhizhou Zhang #size-cells = <2>; 13c46388a5SZhizhou Zhang 14c46388a5SZhizhou Zhang soc { 15c46388a5SZhizhou Zhang compatible = "simple-bus"; 16c46388a5SZhizhou Zhang #address-cells = <2>; 17c46388a5SZhizhou Zhang #size-cells = <2>; 18c46388a5SZhizhou Zhang ranges; 19c46388a5SZhizhou Zhang 20c46388a5SZhizhou Zhang ap-apb { 21c46388a5SZhizhou Zhang compatible = "simple-bus"; 22c46388a5SZhizhou Zhang #address-cells = <2>; 23c46388a5SZhizhou Zhang #size-cells = <2>; 24c46388a5SZhizhou Zhang ranges; 25c46388a5SZhizhou Zhang 26c46388a5SZhizhou Zhang uart0: serial@70000000 { 27c46388a5SZhizhou Zhang compatible = "sprd,sc9836-uart"; 28c46388a5SZhizhou Zhang reg = <0 0x70000000 0 0x100>; 29c46388a5SZhizhou Zhang interrupts = <0 2 0xf04>; 30c46388a5SZhizhou Zhang clocks = <&clk26mhz>; 31c46388a5SZhizhou Zhang status = "disabled"; 32c46388a5SZhizhou Zhang }; 33c46388a5SZhizhou Zhang 34c46388a5SZhizhou Zhang uart1: serial@70100000 { 35c46388a5SZhizhou Zhang compatible = "sprd,sc9836-uart"; 36c46388a5SZhizhou Zhang reg = <0 0x70100000 0 0x100>; 37c46388a5SZhizhou Zhang interrupts = <0 3 0xf04>; 38c46388a5SZhizhou Zhang clocks = <&clk26mhz>; 39c46388a5SZhizhou Zhang status = "disabled"; 40c46388a5SZhizhou Zhang }; 41c46388a5SZhizhou Zhang 42c46388a5SZhizhou Zhang uart2: serial@70200000 { 43c46388a5SZhizhou Zhang compatible = "sprd,sc9836-uart"; 44c46388a5SZhizhou Zhang reg = <0 0x70200000 0 0x100>; 45c46388a5SZhizhou Zhang interrupts = <0 4 0xf04>; 46c46388a5SZhizhou Zhang clocks = <&clk26mhz>; 47c46388a5SZhizhou Zhang status = "disabled"; 48c46388a5SZhizhou Zhang }; 49c46388a5SZhizhou Zhang 50c46388a5SZhizhou Zhang uart3: serial@70300000 { 51c46388a5SZhizhou Zhang compatible = "sprd,sc9836-uart"; 52c46388a5SZhizhou Zhang reg = <0 0x70300000 0 0x100>; 53c46388a5SZhizhou Zhang interrupts = <0 5 0xf04>; 54c46388a5SZhizhou Zhang clocks = <&clk26mhz>; 55c46388a5SZhizhou Zhang status = "disabled"; 56c46388a5SZhizhou Zhang }; 57c46388a5SZhizhou Zhang }; 58c46388a5SZhizhou Zhang }; 59c46388a5SZhizhou Zhang 60c46388a5SZhizhou Zhang clk26mhz: clk26mhz { 61c46388a5SZhizhou Zhang compatible = "fixed-clock"; 62c46388a5SZhizhou Zhang #clock-cells = <0>; 63c46388a5SZhizhou Zhang clock-frequency = <26000000>; 64c46388a5SZhizhou Zhang }; 65c46388a5SZhizhou Zhang}; 66