1/* 2 * Spreadtrum SC9860 SoC 3 * 4 * Copyright (C) 2016, Spreadtrum Communications Inc. 5 * 6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 */ 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include "whale2.dtsi" 11 12/ { 13 cpus { 14 #address-cells = <2>; 15 #size-cells = <0>; 16 17 cpu-map { 18 cluster0 { 19 core0 { 20 cpu = <&CPU0>; 21 }; 22 core1 { 23 cpu = <&CPU1>; 24 }; 25 core2 { 26 cpu = <&CPU2>; 27 }; 28 core3 { 29 cpu = <&CPU3>; 30 }; 31 }; 32 33 cluster1 { 34 core0 { 35 cpu = <&CPU4>; 36 }; 37 core1 { 38 cpu = <&CPU5>; 39 }; 40 core2 { 41 cpu = <&CPU6>; 42 }; 43 core3 { 44 cpu = <&CPU7>; 45 }; 46 }; 47 }; 48 49 CPU0: cpu@530000 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53", "arm,armv8"; 52 reg = <0x0 0x530000>; 53 enable-method = "psci"; 54 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 55 }; 56 57 CPU1: cpu@530001 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a53", "arm,armv8"; 60 reg = <0x0 0x530001>; 61 enable-method = "psci"; 62 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 63 }; 64 65 CPU2: cpu@530002 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a53", "arm,armv8"; 68 reg = <0x0 0x530002>; 69 enable-method = "psci"; 70 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 71 }; 72 73 CPU3: cpu@530003 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a53", "arm,armv8"; 76 reg = <0x0 0x530003>; 77 enable-method = "psci"; 78 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 79 }; 80 81 CPU4: cpu@530100 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53", "arm,armv8"; 84 reg = <0x0 0x530100>; 85 enable-method = "psci"; 86 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 87 }; 88 89 CPU5: cpu@530101 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a53", "arm,armv8"; 92 reg = <0x0 0x530101>; 93 enable-method = "psci"; 94 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 95 }; 96 97 CPU6: cpu@530102 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a53", "arm,armv8"; 100 reg = <0x0 0x530102>; 101 enable-method = "psci"; 102 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 103 }; 104 105 CPU7: cpu@530103 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53", "arm,armv8"; 108 reg = <0x0 0x530103>; 109 enable-method = "psci"; 110 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 111 }; 112 }; 113 114 idle-states{ 115 entry-method = "arm,psci"; 116 117 CORE_PD: core_pd { 118 compatible = "arm,idle-state"; 119 entry-latency-us = <1000>; 120 exit-latency-us = <700>; 121 min-residency-us = <2500>; 122 local-timer-stop; 123 arm,psci-suspend-param = <0x00010002>; 124 }; 125 126 CLUSTER_PD: cluster_pd { 127 compatible = "arm,idle-state"; 128 entry-latency-us = <1000>; 129 exit-latency-us = <1000>; 130 min-residency-us = <3000>; 131 local-timer-stop; 132 arm,psci-suspend-param = <0x01010003>; 133 }; 134 }; 135 136 gic: interrupt-controller@12001000 { 137 compatible = "arm,gic-400"; 138 reg = <0 0x12001000 0 0x1000>, 139 <0 0x12002000 0 0x2000>, 140 <0 0x12004000 0 0x2000>, 141 <0 0x12006000 0 0x2000>; 142 #interrupt-cells = <3>; 143 interrupt-controller; 144 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) 145 | IRQ_TYPE_LEVEL_HIGH)>; 146 }; 147 148 psci { 149 compatible = "arm,psci-0.2"; 150 method = "smc"; 151 }; 152 153 timer { 154 compatible = "arm,armv8-timer"; 155 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) 156 | IRQ_TYPE_LEVEL_LOW)>, 157 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) 158 | IRQ_TYPE_LEVEL_LOW)>, 159 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) 160 | IRQ_TYPE_LEVEL_LOW)>, 161 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) 162 | IRQ_TYPE_LEVEL_LOW)>; 163 }; 164 165 pmu { 166 compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; 167 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 175 interrupt-affinity = <&CPU0>, 176 <&CPU1>, 177 <&CPU2>, 178 <&CPU3>, 179 <&CPU4>, 180 <&CPU5>, 181 <&CPU6>, 182 <&CPU7>; 183 }; 184 185 soc { 186 pmu_gate: pmu-gate { 187 compatible = "sprd,sc9860-pmu-gate"; 188 sprd,syscon = <&pmu_regs>; /* 0x402b0000 */ 189 clocks = <&ext_26m>; 190 #clock-cells = <1>; 191 }; 192 193 pll: pll { 194 compatible = "sprd,sc9860-pll"; 195 sprd,syscon = <&ana_regs>; /* 0x40400000 */ 196 clocks = <&pmu_gate 0>; 197 #clock-cells = <1>; 198 }; 199 200 ap_clk: clock-controller@20000000 { 201 compatible = "sprd,sc9860-ap-clk"; 202 reg = <0 0x20000000 0 0x400>; 203 clocks = <&ext_26m>, <&pll 0>, 204 <&pmu_gate 0>; 205 #clock-cells = <1>; 206 }; 207 208 aon_prediv: aon-prediv { 209 compatible = "sprd,sc9860-aon-prediv"; 210 reg = <0 0x402d0000 0 0x400>; 211 clocks = <&ext_26m>, <&pll 0>, 212 <&pmu_gate 0>; 213 #clock-cells = <1>; 214 }; 215 216 apahb_gate: apahb-gate { 217 compatible = "sprd,sc9860-apahb-gate"; 218 sprd,syscon = <&ap_ahb_regs>; /* 0x20210000 */ 219 clocks = <&aon_prediv 0>; 220 #clock-cells = <1>; 221 }; 222 223 aon_gate: aon-gate { 224 compatible = "sprd,sc9860-aon-gate"; 225 sprd,syscon = <&aon_regs>; /* 0x402e0000 */ 226 clocks = <&aon_prediv 0>; 227 #clock-cells = <1>; 228 }; 229 230 aonsecure_clk: clock-controller@40880000 { 231 compatible = "sprd,sc9860-aonsecure-clk"; 232 reg = <0 0x40880000 0 0x400>; 233 clocks = <&ext_26m>, <&pll 0>; 234 #clock-cells = <1>; 235 }; 236 237 agcp_gate: agcp-gate { 238 compatible = "sprd,sc9860-agcp-gate"; 239 sprd,syscon = <&agcp_regs>; /* 0x415e0000 */ 240 clocks = <&aon_prediv 0>; 241 #clock-cells = <1>; 242 }; 243 244 gpu_clk: clock-controller@60200000 { 245 compatible = "sprd,sc9860-gpu-clk"; 246 reg = <0 0x60200000 0 0x400>; 247 clocks = <&pll 0>; 248 #clock-cells = <1>; 249 }; 250 251 vsp_clk: clock-controller@61000000 { 252 compatible = "sprd,sc9860-vsp-clk"; 253 reg = <0 0x61000000 0 0x400>; 254 clocks = <&ext_26m>, <&pll 0>; 255 #clock-cells = <1>; 256 }; 257 258 vsp_gate: vsp-gate { 259 compatible = "sprd,sc9860-vsp-gate"; 260 sprd,syscon = <&vsp_regs>; /* 0x61100000 */ 261 clocks = <&vsp_clk 0>; 262 #clock-cells = <1>; 263 }; 264 265 cam_clk: clock-controller@62000000 { 266 compatible = "sprd,sc9860-cam-clk"; 267 reg = <0 0x62000000 0 0x4000>; 268 clocks = <&ext_26m>, <&pll 0>; 269 #clock-cells = <1>; 270 }; 271 272 cam_gate: cam-gate { 273 compatible = "sprd,sc9860-cam-gate"; 274 sprd,syscon = <&cam_regs>; /* 0x62100000 */ 275 clocks = <&cam_clk 0>; 276 #clock-cells = <1>; 277 }; 278 279 disp_clk: clock-controller@63000000 { 280 compatible = "sprd,sc9860-disp-clk"; 281 reg = <0 0x63000000 0 0x400>; 282 clocks = <&ext_26m>, <&pll 0>; 283 #clock-cells = <1>; 284 }; 285 286 disp_gate: disp-gate { 287 compatible = "sprd,sc9860-disp-gate"; 288 sprd,syscon = <&disp_regs>; /* 0x63100000 */ 289 clocks = <&disp_clk 0>; 290 #clock-cells = <1>; 291 }; 292 293 apapb_gate: apapb-gate { 294 compatible = "sprd,sc9860-apapb-gate"; 295 sprd,syscon = <&ap_apb_regs>; /* 0x70b00000 */ 296 clocks = <&ap_clk 0>; 297 #clock-cells = <1>; 298 }; 299 300 funnel@10001000 { /* SoC Funnel */ 301 compatible = "arm,coresight-funnel", "arm,primecell"; 302 reg = <0 0x10001000 0 0x1000>; 303 clocks = <&ext_26m>; 304 clock-names = "apb_pclk"; 305 ports { 306 #address-cells = <1>; 307 #size-cells = <0>; 308 309 port@0 { 310 reg = <0>; 311 soc_funnel_out_port: endpoint { 312 remote-endpoint = <&etb_in>; 313 }; 314 }; 315 316 port@1 { 317 reg = <0>; 318 soc_funnel_in_port0: endpoint { 319 slave-mode; 320 remote-endpoint = 321 <&main_funnel_out_port>; 322 }; 323 }; 324 325 port@2 { 326 reg = <4>; 327 soc_funnel_in_port1: endpoint { 328 slave-mode; 329 remote-endpioint = 330 <&stm_out_port>; 331 }; 332 }; 333 }; 334 }; 335 336 etb@10003000 { 337 compatible = "arm,coresight-tmc", "arm,primecell"; 338 reg = <0 0x10003000 0 0x1000>; 339 clocks = <&ext_26m>; 340 clock-names = "apb_pclk"; 341 port { 342 etb_in: endpoint { 343 slave-mode; 344 remote-endpoint = 345 <&soc_funnel_out_port>; 346 }; 347 }; 348 }; 349 350 stm@10006000 { 351 compatible = "arm,coresight-stm", "arm,primecell"; 352 reg = <0 0x10006000 0 0x1000>, 353 <0 0x01000000 0 0x180000>; 354 reg-names = "stm-base", "stm-stimulus-base"; 355 clocks = <&ext_26m>; 356 clock-names = "apb_pclk"; 357 port { 358 stm_out_port: endpoint { 359 remote-endpoint = 360 <&soc_funnel_in_port1>; 361 }; 362 }; 363 }; 364 365 funnel@11001000 { /* Cluster0 Funnel */ 366 compatible = "arm,coresight-funnel", "arm,primecell"; 367 reg = <0 0x11001000 0 0x1000>; 368 clocks = <&ext_26m>; 369 clock-names = "apb_pclk"; 370 ports { 371 #address-cells = <1>; 372 #size-cells = <0>; 373 374 port@0 { 375 reg = <0>; 376 cluster0_funnel_out_port: endpoint { 377 remote-endpoint = 378 <&cluster0_etf_in>; 379 }; 380 }; 381 382 port@1 { 383 reg = <0>; 384 cluster0_funnel_in_port0: endpoint { 385 slave-mode; 386 remote-endpoint = <&etm0_out>; 387 }; 388 }; 389 390 port@2 { 391 reg = <1>; 392 cluster0_funnel_in_port1: endpoint { 393 slave-mode; 394 remote-endpoint = <&etm1_out>; 395 }; 396 }; 397 398 port@3 { 399 reg = <2>; 400 cluster0_funnel_in_port2: endpoint { 401 slave-mode; 402 remote-endpoint = <&etm2_out>; 403 }; 404 }; 405 406 port@4 { 407 reg = <4>; 408 cluster0_funnel_in_port3: endpoint { 409 slave-mode; 410 remote-endpoint = <&etm3_out>; 411 }; 412 }; 413 }; 414 }; 415 416 funnel@11002000 { /* Cluster1 Funnel */ 417 compatible = "arm,coresight-funnel", "arm,primecell"; 418 reg = <0 0x11002000 0 0x1000>; 419 clocks = <&ext_26m>; 420 clock-names = "apb_pclk"; 421 ports { 422 #address-cells = <1>; 423 #size-cells = <0>; 424 425 port@0 { 426 reg = <0>; 427 cluster1_funnel_out_port: endpoint { 428 remote-endpoint = 429 <&cluster1_etf_in>; 430 }; 431 }; 432 433 port@1 { 434 reg = <0>; 435 cluster1_funnel_in_port0: endpoint { 436 slave-mode; 437 remote-endpoint = <&etm4_out>; 438 }; 439 }; 440 441 port@2 { 442 reg = <1>; 443 cluster1_funnel_in_port1: endpoint { 444 slave-mode; 445 remote-endpoint = <&etm5_out>; 446 }; 447 }; 448 449 port@3 { 450 reg = <2>; 451 cluster1_funnel_in_port2: endpoint { 452 slave-mode; 453 remote-endpoint = <&etm6_out>; 454 }; 455 }; 456 457 port@4 { 458 reg = <3>; 459 cluster1_funnel_in_port3: endpoint { 460 slave-mode; 461 remote-endpoint = <&etm7_out>; 462 }; 463 }; 464 }; 465 }; 466 467 etf@11003000 { /* ETF on Cluster0 */ 468 compatible = "arm,coresight-tmc", "arm,primecell"; 469 reg = <0 0x11003000 0 0x1000>; 470 clocks = <&ext_26m>; 471 clock-names = "apb_pclk"; 472 473 ports { 474 #address-cells = <1>; 475 #size-cells = <0>; 476 477 port@0 { 478 reg = <0>; 479 cluster0_etf_out: endpoint { 480 remote-endpoint = 481 <&main_funnel_in_port0>; 482 }; 483 }; 484 485 port@1 { 486 reg = <0>; 487 cluster0_etf_in: endpoint { 488 slave-mode; 489 remote-endpoint = 490 <&cluster0_funnel_out_port>; 491 }; 492 }; 493 }; 494 }; 495 496 etf@11004000 { /* ETF on Cluster1 */ 497 compatible = "arm,coresight-tmc", "arm,primecell"; 498 reg = <0 0x11004000 0 0x1000>; 499 clocks = <&ext_26m>; 500 clock-names = "apb_pclk"; 501 502 ports { 503 #address-cells = <1>; 504 #size-cells = <0>; 505 506 port@0 { 507 reg = <0>; 508 cluster1_etf_out: endpoint { 509 remote-endpoint = 510 <&main_funnel_in_port1>; 511 }; 512 }; 513 514 port@1 { 515 reg = <0>; 516 cluster1_etf_in: endpoint { 517 slave-mode; 518 remote-endpoint = 519 <&cluster1_funnel_out_port>; 520 }; 521 }; 522 }; 523 }; 524 525 funnel@11005000 { /* Main Funnel */ 526 compatible = "arm,coresight-funnel", "arm,primecell"; 527 reg = <0 0x11005000 0 0x1000>; 528 clocks = <&ext_26m>; 529 clock-names = "apb_pclk"; 530 531 ports { 532 #address-cells = <1>; 533 #size-cells = <0>; 534 535 port@0 { 536 reg = <0>; 537 main_funnel_out_port: endpoint { 538 remote-endpoint = 539 <&soc_funnel_in_port0>; 540 }; 541 }; 542 543 port@1 { 544 reg = <0>; 545 main_funnel_in_port0: endpoint { 546 slave-mode; 547 remote-endpoint = 548 <&cluster0_etf_out>; 549 }; 550 }; 551 552 port@2 { 553 reg = <1>; 554 main_funnel_in_port1: endpoint { 555 slave-mode; 556 remote-endpoint = 557 <&cluster1_etf_out>; 558 }; 559 }; 560 }; 561 }; 562 563 etm@11440000 { 564 compatible = "arm,coresight-etm4x", "arm,primecell"; 565 reg = <0 0x11440000 0 0x1000>; 566 cpu = <&CPU0>; 567 clocks = <&ext_26m>; 568 clock-names = "apb_pclk"; 569 570 port { 571 etm0_out: endpoint { 572 remote-endpoint = 573 <&cluster0_funnel_in_port0>; 574 }; 575 }; 576 }; 577 578 etm@11540000 { 579 compatible = "arm,coresight-etm4x", "arm,primecell"; 580 reg = <0 0x11540000 0 0x1000>; 581 cpu = <&CPU1>; 582 clocks = <&ext_26m>; 583 clock-names = "apb_pclk"; 584 585 port { 586 etm1_out: endpoint { 587 remote-endpoint = 588 <&cluster0_funnel_in_port1>; 589 }; 590 }; 591 }; 592 593 etm@11640000 { 594 compatible = "arm,coresight-etm4x", "arm,primecell"; 595 reg = <0 0x11640000 0 0x1000>; 596 cpu = <&CPU2>; 597 clocks = <&ext_26m>; 598 clock-names = "apb_pclk"; 599 600 port { 601 etm2_out: endpoint { 602 remote-endpoint = 603 <&cluster0_funnel_in_port2>; 604 }; 605 }; 606 }; 607 608 etm@11740000 { 609 compatible = "arm,coresight-etm4x", "arm,primecell"; 610 reg = <0 0x11740000 0 0x1000>; 611 cpu = <&CPU3>; 612 clocks = <&ext_26m>; 613 clock-names = "apb_pclk"; 614 615 port { 616 etm3_out: endpoint { 617 remote-endpoint = 618 <&cluster0_funnel_in_port3>; 619 }; 620 }; 621 }; 622 623 etm@11840000 { 624 compatible = "arm,coresight-etm4x", "arm,primecell"; 625 reg = <0 0x11840000 0 0x1000>; 626 cpu = <&CPU4>; 627 clocks = <&ext_26m>; 628 clock-names = "apb_pclk"; 629 630 port { 631 etm4_out: endpoint { 632 remote-endpoint = 633 <&cluster1_funnel_in_port0>; 634 }; 635 }; 636 }; 637 638 etm@11940000 { 639 compatible = "arm,coresight-etm4x", "arm,primecell"; 640 reg = <0 0x11940000 0 0x1000>; 641 cpu = <&CPU5>; 642 clocks = <&ext_26m>; 643 clock-names = "apb_pclk"; 644 645 port { 646 etm5_out: endpoint { 647 remote-endpoint = 648 <&cluster1_funnel_in_port1>; 649 }; 650 }; 651 }; 652 653 etm@11a40000 { 654 compatible = "arm,coresight-etm4x", "arm,primecell"; 655 reg = <0 0x11a40000 0 0x1000>; 656 cpu = <&CPU6>; 657 clocks = <&ext_26m>; 658 clock-names = "apb_pclk"; 659 660 port { 661 etm6_out: endpoint { 662 remote-endpoint = 663 <&cluster1_funnel_in_port2>; 664 }; 665 }; 666 }; 667 668 etm@11b40000 { 669 compatible = "arm,coresight-etm4x", "arm,primecell"; 670 reg = <0 0x11b40000 0 0x1000>; 671 cpu = <&CPU7>; 672 clocks = <&ext_26m>; 673 clock-names = "apb_pclk"; 674 675 port { 676 etm7_out: endpoint { 677 remote-endpoint = 678 <&cluster1_funnel_in_port3>; 679 }; 680 }; 681 }; 682 }; 683}; 684