1/* 2 * Spreadtrum SC9860 SoC 3 * 4 * Copyright (C) 2016, Spreadtrum Communications Inc. 5 * 6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 */ 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/gpio/gpio.h> 12#include "whale2.dtsi" 13 14/ { 15 cpus { 16 #address-cells = <2>; 17 #size-cells = <0>; 18 19 cpu-map { 20 cluster0 { 21 core0 { 22 cpu = <&CPU0>; 23 }; 24 core1 { 25 cpu = <&CPU1>; 26 }; 27 core2 { 28 cpu = <&CPU2>; 29 }; 30 core3 { 31 cpu = <&CPU3>; 32 }; 33 }; 34 35 cluster1 { 36 core0 { 37 cpu = <&CPU4>; 38 }; 39 core1 { 40 cpu = <&CPU5>; 41 }; 42 core2 { 43 cpu = <&CPU6>; 44 }; 45 core3 { 46 cpu = <&CPU7>; 47 }; 48 }; 49 }; 50 51 CPU0: cpu@530000 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53", "arm,armv8"; 54 reg = <0x0 0x530000>; 55 enable-method = "psci"; 56 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 57 }; 58 59 CPU1: cpu@530001 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53", "arm,armv8"; 62 reg = <0x0 0x530001>; 63 enable-method = "psci"; 64 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 65 }; 66 67 CPU2: cpu@530002 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a53", "arm,armv8"; 70 reg = <0x0 0x530002>; 71 enable-method = "psci"; 72 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 73 }; 74 75 CPU3: cpu@530003 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a53", "arm,armv8"; 78 reg = <0x0 0x530003>; 79 enable-method = "psci"; 80 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 81 }; 82 83 CPU4: cpu@530100 { 84 device_type = "cpu"; 85 compatible = "arm,cortex-a53", "arm,armv8"; 86 reg = <0x0 0x530100>; 87 enable-method = "psci"; 88 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 89 }; 90 91 CPU5: cpu@530101 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a53", "arm,armv8"; 94 reg = <0x0 0x530101>; 95 enable-method = "psci"; 96 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 97 }; 98 99 CPU6: cpu@530102 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a53", "arm,armv8"; 102 reg = <0x0 0x530102>; 103 enable-method = "psci"; 104 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 105 }; 106 107 CPU7: cpu@530103 { 108 device_type = "cpu"; 109 compatible = "arm,cortex-a53", "arm,armv8"; 110 reg = <0x0 0x530103>; 111 enable-method = "psci"; 112 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 113 }; 114 }; 115 116 idle-states{ 117 entry-method = "psci"; 118 119 CORE_PD: core_pd { 120 compatible = "arm,idle-state"; 121 entry-latency-us = <1000>; 122 exit-latency-us = <700>; 123 min-residency-us = <2500>; 124 local-timer-stop; 125 arm,psci-suspend-param = <0x00010002>; 126 }; 127 128 CLUSTER_PD: cluster_pd { 129 compatible = "arm,idle-state"; 130 entry-latency-us = <1000>; 131 exit-latency-us = <1000>; 132 min-residency-us = <3000>; 133 local-timer-stop; 134 arm,psci-suspend-param = <0x01010003>; 135 }; 136 }; 137 138 gic: interrupt-controller@12001000 { 139 compatible = "arm,gic-400"; 140 reg = <0 0x12001000 0 0x1000>, 141 <0 0x12002000 0 0x2000>, 142 <0 0x12004000 0 0x2000>, 143 <0 0x12006000 0 0x2000>; 144 #interrupt-cells = <3>; 145 interrupt-controller; 146 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) 147 | IRQ_TYPE_LEVEL_HIGH)>; 148 }; 149 150 psci { 151 compatible = "arm,psci-0.2"; 152 method = "smc"; 153 }; 154 155 timer { 156 compatible = "arm,armv8-timer"; 157 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) 158 | IRQ_TYPE_LEVEL_LOW)>, 159 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) 160 | IRQ_TYPE_LEVEL_LOW)>, 161 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) 162 | IRQ_TYPE_LEVEL_LOW)>, 163 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) 164 | IRQ_TYPE_LEVEL_LOW)>; 165 }; 166 167 pmu { 168 compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; 169 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 177 interrupt-affinity = <&CPU0>, 178 <&CPU1>, 179 <&CPU2>, 180 <&CPU3>, 181 <&CPU4>, 182 <&CPU5>, 183 <&CPU6>, 184 <&CPU7>; 185 }; 186 187 soc { 188 pmu_gate: pmu-gate { 189 compatible = "sprd,sc9860-pmu-gate"; 190 sprd,syscon = <&pmu_regs>; /* 0x402b0000 */ 191 clocks = <&ext_26m>; 192 #clock-cells = <1>; 193 }; 194 195 pll: pll { 196 compatible = "sprd,sc9860-pll"; 197 sprd,syscon = <&ana_regs>; /* 0x40400000 */ 198 clocks = <&pmu_gate 0>; 199 #clock-cells = <1>; 200 }; 201 202 ap_clk: clock-controller@20000000 { 203 compatible = "sprd,sc9860-ap-clk"; 204 reg = <0 0x20000000 0 0x400>; 205 clocks = <&ext_26m>, <&pll 0>, 206 <&pmu_gate 0>; 207 #clock-cells = <1>; 208 }; 209 210 aon_prediv: aon-prediv { 211 compatible = "sprd,sc9860-aon-prediv"; 212 reg = <0 0x402d0000 0 0x400>; 213 clocks = <&ext_26m>, <&pll 0>, 214 <&pmu_gate 0>; 215 #clock-cells = <1>; 216 }; 217 218 apahb_gate: apahb-gate { 219 compatible = "sprd,sc9860-apahb-gate"; 220 sprd,syscon = <&ap_ahb_regs>; /* 0x20210000 */ 221 clocks = <&aon_prediv 0>; 222 #clock-cells = <1>; 223 }; 224 225 aon_gate: aon-gate { 226 compatible = "sprd,sc9860-aon-gate"; 227 sprd,syscon = <&aon_regs>; /* 0x402e0000 */ 228 clocks = <&aon_prediv 0>; 229 #clock-cells = <1>; 230 }; 231 232 aonsecure_clk: clock-controller@40880000 { 233 compatible = "sprd,sc9860-aonsecure-clk"; 234 reg = <0 0x40880000 0 0x400>; 235 clocks = <&ext_26m>, <&pll 0>; 236 #clock-cells = <1>; 237 }; 238 239 agcp_gate: agcp-gate { 240 compatible = "sprd,sc9860-agcp-gate"; 241 sprd,syscon = <&agcp_regs>; /* 0x415e0000 */ 242 clocks = <&aon_prediv 0>; 243 #clock-cells = <1>; 244 }; 245 246 gpu_clk: clock-controller@60200000 { 247 compatible = "sprd,sc9860-gpu-clk"; 248 reg = <0 0x60200000 0 0x400>; 249 clocks = <&pll 0>; 250 #clock-cells = <1>; 251 }; 252 253 vsp_clk: clock-controller@61000000 { 254 compatible = "sprd,sc9860-vsp-clk"; 255 reg = <0 0x61000000 0 0x400>; 256 clocks = <&ext_26m>, <&pll 0>; 257 #clock-cells = <1>; 258 }; 259 260 vsp_gate: vsp-gate { 261 compatible = "sprd,sc9860-vsp-gate"; 262 sprd,syscon = <&vsp_regs>; /* 0x61100000 */ 263 clocks = <&vsp_clk 0>; 264 #clock-cells = <1>; 265 }; 266 267 cam_clk: clock-controller@62000000 { 268 compatible = "sprd,sc9860-cam-clk"; 269 reg = <0 0x62000000 0 0x4000>; 270 clocks = <&ext_26m>, <&pll 0>; 271 #clock-cells = <1>; 272 }; 273 274 cam_gate: cam-gate { 275 compatible = "sprd,sc9860-cam-gate"; 276 sprd,syscon = <&cam_regs>; /* 0x62100000 */ 277 clocks = <&cam_clk 0>; 278 #clock-cells = <1>; 279 }; 280 281 disp_clk: clock-controller@63000000 { 282 compatible = "sprd,sc9860-disp-clk"; 283 reg = <0 0x63000000 0 0x400>; 284 clocks = <&ext_26m>, <&pll 0>; 285 #clock-cells = <1>; 286 }; 287 288 disp_gate: disp-gate { 289 compatible = "sprd,sc9860-disp-gate"; 290 sprd,syscon = <&disp_regs>; /* 0x63100000 */ 291 clocks = <&disp_clk 0>; 292 #clock-cells = <1>; 293 }; 294 295 apapb_gate: apapb-gate { 296 compatible = "sprd,sc9860-apapb-gate"; 297 sprd,syscon = <&ap_apb_regs>; /* 0x70b00000 */ 298 clocks = <&ap_clk 0>; 299 #clock-cells = <1>; 300 }; 301 302 funnel@10001000 { /* SoC Funnel */ 303 compatible = "arm,coresight-funnel", "arm,primecell"; 304 reg = <0 0x10001000 0 0x1000>; 305 clocks = <&ext_26m>; 306 clock-names = "apb_pclk"; 307 ports { 308 #address-cells = <1>; 309 #size-cells = <0>; 310 311 port@0 { 312 reg = <0>; 313 soc_funnel_out_port: endpoint { 314 remote-endpoint = <&etb_in>; 315 }; 316 }; 317 318 port@1 { 319 reg = <0>; 320 soc_funnel_in_port0: endpoint { 321 slave-mode; 322 remote-endpoint = 323 <&main_funnel_out_port>; 324 }; 325 }; 326 327 port@2 { 328 reg = <4>; 329 soc_funnel_in_port1: endpoint { 330 slave-mode; 331 remote-endpoint = 332 <&stm_out_port>; 333 }; 334 }; 335 }; 336 }; 337 338 etb@10003000 { 339 compatible = "arm,coresight-tmc", "arm,primecell"; 340 reg = <0 0x10003000 0 0x1000>; 341 clocks = <&ext_26m>; 342 clock-names = "apb_pclk"; 343 port { 344 etb_in: endpoint { 345 slave-mode; 346 remote-endpoint = 347 <&soc_funnel_out_port>; 348 }; 349 }; 350 }; 351 352 stm@10006000 { 353 compatible = "arm,coresight-stm", "arm,primecell"; 354 reg = <0 0x10006000 0 0x1000>, 355 <0 0x01000000 0 0x180000>; 356 reg-names = "stm-base", "stm-stimulus-base"; 357 clocks = <&ext_26m>; 358 clock-names = "apb_pclk"; 359 port { 360 stm_out_port: endpoint { 361 remote-endpoint = 362 <&soc_funnel_in_port1>; 363 }; 364 }; 365 }; 366 367 funnel@11001000 { /* Cluster0 Funnel */ 368 compatible = "arm,coresight-funnel", "arm,primecell"; 369 reg = <0 0x11001000 0 0x1000>; 370 clocks = <&ext_26m>; 371 clock-names = "apb_pclk"; 372 ports { 373 #address-cells = <1>; 374 #size-cells = <0>; 375 376 port@0 { 377 reg = <0>; 378 cluster0_funnel_out_port: endpoint { 379 remote-endpoint = 380 <&cluster0_etf_in>; 381 }; 382 }; 383 384 port@1 { 385 reg = <0>; 386 cluster0_funnel_in_port0: endpoint { 387 slave-mode; 388 remote-endpoint = <&etm0_out>; 389 }; 390 }; 391 392 port@2 { 393 reg = <1>; 394 cluster0_funnel_in_port1: endpoint { 395 slave-mode; 396 remote-endpoint = <&etm1_out>; 397 }; 398 }; 399 400 port@3 { 401 reg = <2>; 402 cluster0_funnel_in_port2: endpoint { 403 slave-mode; 404 remote-endpoint = <&etm2_out>; 405 }; 406 }; 407 408 port@4 { 409 reg = <4>; 410 cluster0_funnel_in_port3: endpoint { 411 slave-mode; 412 remote-endpoint = <&etm3_out>; 413 }; 414 }; 415 }; 416 }; 417 418 funnel@11002000 { /* Cluster1 Funnel */ 419 compatible = "arm,coresight-funnel", "arm,primecell"; 420 reg = <0 0x11002000 0 0x1000>; 421 clocks = <&ext_26m>; 422 clock-names = "apb_pclk"; 423 ports { 424 #address-cells = <1>; 425 #size-cells = <0>; 426 427 port@0 { 428 reg = <0>; 429 cluster1_funnel_out_port: endpoint { 430 remote-endpoint = 431 <&cluster1_etf_in>; 432 }; 433 }; 434 435 port@1 { 436 reg = <0>; 437 cluster1_funnel_in_port0: endpoint { 438 slave-mode; 439 remote-endpoint = <&etm4_out>; 440 }; 441 }; 442 443 port@2 { 444 reg = <1>; 445 cluster1_funnel_in_port1: endpoint { 446 slave-mode; 447 remote-endpoint = <&etm5_out>; 448 }; 449 }; 450 451 port@3 { 452 reg = <2>; 453 cluster1_funnel_in_port2: endpoint { 454 slave-mode; 455 remote-endpoint = <&etm6_out>; 456 }; 457 }; 458 459 port@4 { 460 reg = <3>; 461 cluster1_funnel_in_port3: endpoint { 462 slave-mode; 463 remote-endpoint = <&etm7_out>; 464 }; 465 }; 466 }; 467 }; 468 469 etf@11003000 { /* ETF on Cluster0 */ 470 compatible = "arm,coresight-tmc", "arm,primecell"; 471 reg = <0 0x11003000 0 0x1000>; 472 clocks = <&ext_26m>; 473 clock-names = "apb_pclk"; 474 475 ports { 476 #address-cells = <1>; 477 #size-cells = <0>; 478 479 port@0 { 480 reg = <0>; 481 cluster0_etf_out: endpoint { 482 remote-endpoint = 483 <&main_funnel_in_port0>; 484 }; 485 }; 486 487 port@1 { 488 reg = <0>; 489 cluster0_etf_in: endpoint { 490 slave-mode; 491 remote-endpoint = 492 <&cluster0_funnel_out_port>; 493 }; 494 }; 495 }; 496 }; 497 498 etf@11004000 { /* ETF on Cluster1 */ 499 compatible = "arm,coresight-tmc", "arm,primecell"; 500 reg = <0 0x11004000 0 0x1000>; 501 clocks = <&ext_26m>; 502 clock-names = "apb_pclk"; 503 504 ports { 505 #address-cells = <1>; 506 #size-cells = <0>; 507 508 port@0 { 509 reg = <0>; 510 cluster1_etf_out: endpoint { 511 remote-endpoint = 512 <&main_funnel_in_port1>; 513 }; 514 }; 515 516 port@1 { 517 reg = <0>; 518 cluster1_etf_in: endpoint { 519 slave-mode; 520 remote-endpoint = 521 <&cluster1_funnel_out_port>; 522 }; 523 }; 524 }; 525 }; 526 527 funnel@11005000 { /* Main Funnel */ 528 compatible = "arm,coresight-funnel", "arm,primecell"; 529 reg = <0 0x11005000 0 0x1000>; 530 clocks = <&ext_26m>; 531 clock-names = "apb_pclk"; 532 533 ports { 534 #address-cells = <1>; 535 #size-cells = <0>; 536 537 port@0 { 538 reg = <0>; 539 main_funnel_out_port: endpoint { 540 remote-endpoint = 541 <&soc_funnel_in_port0>; 542 }; 543 }; 544 545 port@1 { 546 reg = <0>; 547 main_funnel_in_port0: endpoint { 548 slave-mode; 549 remote-endpoint = 550 <&cluster0_etf_out>; 551 }; 552 }; 553 554 port@2 { 555 reg = <1>; 556 main_funnel_in_port1: endpoint { 557 slave-mode; 558 remote-endpoint = 559 <&cluster1_etf_out>; 560 }; 561 }; 562 }; 563 }; 564 565 etm@11440000 { 566 compatible = "arm,coresight-etm4x", "arm,primecell"; 567 reg = <0 0x11440000 0 0x1000>; 568 cpu = <&CPU0>; 569 clocks = <&ext_26m>; 570 clock-names = "apb_pclk"; 571 572 port { 573 etm0_out: endpoint { 574 remote-endpoint = 575 <&cluster0_funnel_in_port0>; 576 }; 577 }; 578 }; 579 580 etm@11540000 { 581 compatible = "arm,coresight-etm4x", "arm,primecell"; 582 reg = <0 0x11540000 0 0x1000>; 583 cpu = <&CPU1>; 584 clocks = <&ext_26m>; 585 clock-names = "apb_pclk"; 586 587 port { 588 etm1_out: endpoint { 589 remote-endpoint = 590 <&cluster0_funnel_in_port1>; 591 }; 592 }; 593 }; 594 595 etm@11640000 { 596 compatible = "arm,coresight-etm4x", "arm,primecell"; 597 reg = <0 0x11640000 0 0x1000>; 598 cpu = <&CPU2>; 599 clocks = <&ext_26m>; 600 clock-names = "apb_pclk"; 601 602 port { 603 etm2_out: endpoint { 604 remote-endpoint = 605 <&cluster0_funnel_in_port2>; 606 }; 607 }; 608 }; 609 610 etm@11740000 { 611 compatible = "arm,coresight-etm4x", "arm,primecell"; 612 reg = <0 0x11740000 0 0x1000>; 613 cpu = <&CPU3>; 614 clocks = <&ext_26m>; 615 clock-names = "apb_pclk"; 616 617 port { 618 etm3_out: endpoint { 619 remote-endpoint = 620 <&cluster0_funnel_in_port3>; 621 }; 622 }; 623 }; 624 625 etm@11840000 { 626 compatible = "arm,coresight-etm4x", "arm,primecell"; 627 reg = <0 0x11840000 0 0x1000>; 628 cpu = <&CPU4>; 629 clocks = <&ext_26m>; 630 clock-names = "apb_pclk"; 631 632 port { 633 etm4_out: endpoint { 634 remote-endpoint = 635 <&cluster1_funnel_in_port0>; 636 }; 637 }; 638 }; 639 640 etm@11940000 { 641 compatible = "arm,coresight-etm4x", "arm,primecell"; 642 reg = <0 0x11940000 0 0x1000>; 643 cpu = <&CPU5>; 644 clocks = <&ext_26m>; 645 clock-names = "apb_pclk"; 646 647 port { 648 etm5_out: endpoint { 649 remote-endpoint = 650 <&cluster1_funnel_in_port1>; 651 }; 652 }; 653 }; 654 655 etm@11a40000 { 656 compatible = "arm,coresight-etm4x", "arm,primecell"; 657 reg = <0 0x11a40000 0 0x1000>; 658 cpu = <&CPU6>; 659 clocks = <&ext_26m>; 660 clock-names = "apb_pclk"; 661 662 port { 663 etm6_out: endpoint { 664 remote-endpoint = 665 <&cluster1_funnel_in_port2>; 666 }; 667 }; 668 }; 669 670 etm@11b40000 { 671 compatible = "arm,coresight-etm4x", "arm,primecell"; 672 reg = <0 0x11b40000 0 0x1000>; 673 cpu = <&CPU7>; 674 clocks = <&ext_26m>; 675 clock-names = "apb_pclk"; 676 677 port { 678 etm7_out: endpoint { 679 remote-endpoint = 680 <&cluster1_funnel_in_port3>; 681 }; 682 }; 683 }; 684 685 gpio-keys { 686 compatible = "gpio-keys"; 687 688 key-volumedown { 689 label = "Volume Down Key"; 690 linux,code = <KEY_VOLUMEDOWN>; 691 gpios = <&eic_debounce 2 GPIO_ACTIVE_LOW>; 692 debounce-interval = <2>; 693 wakeup-source; 694 }; 695 696 key-volumeup { 697 label = "Volume Up Key"; 698 linux,code = <KEY_VOLUMEUP>; 699 gpios = <&pmic_eic 10 GPIO_ACTIVE_HIGH>; 700 debounce-interval = <2>; 701 wakeup-source; 702 }; 703 704 key-power { 705 label = "Power Key"; 706 linux,code = <KEY_POWER>; 707 gpios = <&pmic_eic 1 GPIO_ACTIVE_HIGH>; 708 debounce-interval = <2>; 709 wakeup-source; 710 }; 711 }; 712 }; 713}; 714