1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Device Tree Source for UniPhier PXs3 SoC 4// 5// Copyright (C) 2017 Socionext Inc. 6// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/gpio/uniphier-gpio.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/thermal/thermal.h> 12 13/ { 14 compatible = "socionext,uniphier-pxs3"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 interrupt-parent = <&gic>; 18 19 cpus { 20 #address-cells = <2>; 21 #size-cells = <0>; 22 23 cpu-map { 24 cluster0 { 25 core0 { 26 cpu = <&cpu0>; 27 }; 28 core1 { 29 cpu = <&cpu1>; 30 }; 31 core2 { 32 cpu = <&cpu2>; 33 }; 34 core3 { 35 cpu = <&cpu3>; 36 }; 37 }; 38 }; 39 40 cpu0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53"; 43 reg = <0 0x000>; 44 clocks = <&sys_clk 33>; 45 enable-method = "psci"; 46 next-level-cache = <&l2>; 47 operating-points-v2 = <&cluster0_opp>; 48 #cooling-cells = <2>; 49 }; 50 51 cpu1: cpu@1 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 reg = <0 0x001>; 55 clocks = <&sys_clk 33>; 56 enable-method = "psci"; 57 next-level-cache = <&l2>; 58 operating-points-v2 = <&cluster0_opp>; 59 #cooling-cells = <2>; 60 }; 61 62 cpu2: cpu@2 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a53"; 65 reg = <0 0x002>; 66 clocks = <&sys_clk 33>; 67 enable-method = "psci"; 68 next-level-cache = <&l2>; 69 operating-points-v2 = <&cluster0_opp>; 70 #cooling-cells = <2>; 71 }; 72 73 cpu3: cpu@3 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a53"; 76 reg = <0 0x003>; 77 clocks = <&sys_clk 33>; 78 enable-method = "psci"; 79 next-level-cache = <&l2>; 80 operating-points-v2 = <&cluster0_opp>; 81 #cooling-cells = <2>; 82 }; 83 84 l2: l2-cache { 85 compatible = "cache"; 86 }; 87 }; 88 89 cluster0_opp: opp-table { 90 compatible = "operating-points-v2"; 91 opp-shared; 92 93 opp-250000000 { 94 opp-hz = /bits/ 64 <250000000>; 95 clock-latency-ns = <300>; 96 }; 97 opp-325000000 { 98 opp-hz = /bits/ 64 <325000000>; 99 clock-latency-ns = <300>; 100 }; 101 opp-500000000 { 102 opp-hz = /bits/ 64 <500000000>; 103 clock-latency-ns = <300>; 104 }; 105 opp-650000000 { 106 opp-hz = /bits/ 64 <650000000>; 107 clock-latency-ns = <300>; 108 }; 109 opp-666667000 { 110 opp-hz = /bits/ 64 <666667000>; 111 clock-latency-ns = <300>; 112 }; 113 opp-866667000 { 114 opp-hz = /bits/ 64 <866667000>; 115 clock-latency-ns = <300>; 116 }; 117 opp-1000000000 { 118 opp-hz = /bits/ 64 <1000000000>; 119 clock-latency-ns = <300>; 120 }; 121 opp-1300000000 { 122 opp-hz = /bits/ 64 <1300000000>; 123 clock-latency-ns = <300>; 124 }; 125 }; 126 127 psci { 128 compatible = "arm,psci-1.0"; 129 method = "smc"; 130 }; 131 132 clocks { 133 refclk: ref { 134 compatible = "fixed-clock"; 135 #clock-cells = <0>; 136 clock-frequency = <25000000>; 137 }; 138 }; 139 140 emmc_pwrseq: emmc-pwrseq { 141 compatible = "mmc-pwrseq-emmc"; 142 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>; 143 }; 144 145 timer { 146 compatible = "arm,armv8-timer"; 147 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 151 }; 152 153 thermal-zones { 154 cpu-thermal { 155 polling-delay-passive = <250>; /* 250ms */ 156 polling-delay = <1000>; /* 1000ms */ 157 thermal-sensors = <&pvtctl>; 158 159 trips { 160 cpu_crit: cpu-crit { 161 temperature = <110000>; /* 110C */ 162 hysteresis = <2000>; 163 type = "critical"; 164 }; 165 cpu_alert: cpu-alert { 166 temperature = <100000>; /* 100C */ 167 hysteresis = <2000>; 168 type = "passive"; 169 }; 170 }; 171 172 cooling-maps { 173 map0 { 174 trip = <&cpu_alert>; 175 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 176 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 177 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 178 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 179 }; 180 }; 181 }; 182 }; 183 184 reserved-memory { 185 #address-cells = <2>; 186 #size-cells = <2>; 187 ranges; 188 189 secure-memory@81000000 { 190 reg = <0x0 0x81000000 0x0 0x01000000>; 191 no-map; 192 }; 193 }; 194 195 soc@0 { 196 compatible = "simple-bus"; 197 #address-cells = <1>; 198 #size-cells = <1>; 199 ranges = <0 0 0 0xffffffff>; 200 201 spi0: spi@54006000 { 202 compatible = "socionext,uniphier-scssi"; 203 status = "disabled"; 204 reg = <0x54006000 0x100>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 208 pinctrl-names = "default"; 209 pinctrl-0 = <&pinctrl_spi0>; 210 clocks = <&peri_clk 11>; 211 resets = <&peri_rst 11>; 212 }; 213 214 spi1: spi@54006100 { 215 compatible = "socionext,uniphier-scssi"; 216 status = "disabled"; 217 reg = <0x54006100 0x100>; 218 #address-cells = <1>; 219 #size-cells = <0>; 220 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 221 pinctrl-names = "default"; 222 pinctrl-0 = <&pinctrl_spi1>; 223 clocks = <&peri_clk 12>; 224 resets = <&peri_rst 12>; 225 }; 226 227 serial0: serial@54006800 { 228 compatible = "socionext,uniphier-uart"; 229 status = "disabled"; 230 reg = <0x54006800 0x40>; 231 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 232 pinctrl-names = "default"; 233 pinctrl-0 = <&pinctrl_uart0>; 234 clocks = <&peri_clk 0>; 235 resets = <&peri_rst 0>; 236 }; 237 238 serial1: serial@54006900 { 239 compatible = "socionext,uniphier-uart"; 240 status = "disabled"; 241 reg = <0x54006900 0x40>; 242 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&pinctrl_uart1>; 245 clocks = <&peri_clk 1>; 246 resets = <&peri_rst 1>; 247 }; 248 249 serial2: serial@54006a00 { 250 compatible = "socionext,uniphier-uart"; 251 status = "disabled"; 252 reg = <0x54006a00 0x40>; 253 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 254 pinctrl-names = "default"; 255 pinctrl-0 = <&pinctrl_uart2>; 256 clocks = <&peri_clk 2>; 257 resets = <&peri_rst 2>; 258 }; 259 260 serial3: serial@54006b00 { 261 compatible = "socionext,uniphier-uart"; 262 status = "disabled"; 263 reg = <0x54006b00 0x40>; 264 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 265 pinctrl-names = "default"; 266 pinctrl-0 = <&pinctrl_uart3>; 267 clocks = <&peri_clk 3>; 268 resets = <&peri_rst 3>; 269 }; 270 271 gpio: gpio@55000000 { 272 compatible = "socionext,uniphier-gpio"; 273 reg = <0x55000000 0x200>; 274 interrupt-parent = <&aidet>; 275 interrupt-controller; 276 #interrupt-cells = <2>; 277 gpio-controller; 278 #gpio-cells = <2>; 279 gpio-ranges = <&pinctrl 0 0 0>, 280 <&pinctrl 104 0 0>, 281 <&pinctrl 168 0 0>; 282 gpio-ranges-group-names = "gpio_range0", 283 "gpio_range1", 284 "gpio_range2"; 285 ngpios = <286>; 286 socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 287 <21 217 3>; 288 }; 289 290 i2c0: i2c@58780000 { 291 compatible = "socionext,uniphier-fi2c"; 292 status = "disabled"; 293 reg = <0x58780000 0x80>; 294 #address-cells = <1>; 295 #size-cells = <0>; 296 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 297 pinctrl-names = "default"; 298 pinctrl-0 = <&pinctrl_i2c0>; 299 clocks = <&peri_clk 4>; 300 resets = <&peri_rst 4>; 301 clock-frequency = <100000>; 302 }; 303 304 i2c1: i2c@58781000 { 305 compatible = "socionext,uniphier-fi2c"; 306 status = "disabled"; 307 reg = <0x58781000 0x80>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 311 pinctrl-names = "default"; 312 pinctrl-0 = <&pinctrl_i2c1>; 313 clocks = <&peri_clk 5>; 314 resets = <&peri_rst 5>; 315 clock-frequency = <100000>; 316 }; 317 318 i2c2: i2c@58782000 { 319 compatible = "socionext,uniphier-fi2c"; 320 status = "disabled"; 321 reg = <0x58782000 0x80>; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 325 pinctrl-names = "default"; 326 pinctrl-0 = <&pinctrl_i2c2>; 327 clocks = <&peri_clk 6>; 328 resets = <&peri_rst 6>; 329 clock-frequency = <100000>; 330 }; 331 332 i2c3: i2c@58783000 { 333 compatible = "socionext,uniphier-fi2c"; 334 status = "disabled"; 335 reg = <0x58783000 0x80>; 336 #address-cells = <1>; 337 #size-cells = <0>; 338 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 339 pinctrl-names = "default"; 340 pinctrl-0 = <&pinctrl_i2c3>; 341 clocks = <&peri_clk 7>; 342 resets = <&peri_rst 7>; 343 clock-frequency = <100000>; 344 }; 345 346 /* chip-internal connection for HDMI */ 347 i2c6: i2c@58786000 { 348 compatible = "socionext,uniphier-fi2c"; 349 reg = <0x58786000 0x80>; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 353 clocks = <&peri_clk 10>; 354 resets = <&peri_rst 10>; 355 clock-frequency = <400000>; 356 }; 357 358 system_bus: system-bus@58c00000 { 359 compatible = "socionext,uniphier-system-bus"; 360 status = "disabled"; 361 reg = <0x58c00000 0x400>; 362 #address-cells = <2>; 363 #size-cells = <1>; 364 pinctrl-names = "default"; 365 pinctrl-0 = <&pinctrl_system_bus>; 366 }; 367 368 smpctrl@59801000 { 369 compatible = "socionext,uniphier-smpctrl"; 370 reg = <0x59801000 0x400>; 371 }; 372 373 syscon@59810000 { 374 compatible = "socionext,uniphier-pxs3-sdctrl", 375 "simple-mfd", "syscon"; 376 reg = <0x59810000 0x400>; 377 378 sd_clk: clock-controller { 379 compatible = "socionext,uniphier-pxs3-sd-clock"; 380 #clock-cells = <1>; 381 }; 382 383 sd_rst: reset-controller { 384 compatible = "socionext,uniphier-pxs3-sd-reset"; 385 #reset-cells = <1>; 386 }; 387 }; 388 389 syscon@59820000 { 390 compatible = "socionext,uniphier-pxs3-perictrl", 391 "simple-mfd", "syscon"; 392 reg = <0x59820000 0x200>; 393 394 peri_clk: clock-controller { 395 compatible = "socionext,uniphier-pxs3-peri-clock"; 396 #clock-cells = <1>; 397 }; 398 399 peri_rst: reset-controller { 400 compatible = "socionext,uniphier-pxs3-peri-reset"; 401 #reset-cells = <1>; 402 }; 403 }; 404 405 emmc: mmc@5a000000 { 406 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 407 reg = <0x5a000000 0x400>; 408 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 409 pinctrl-names = "default"; 410 pinctrl-0 = <&pinctrl_emmc>; 411 clocks = <&sys_clk 4>; 412 resets = <&sys_rst 4>; 413 bus-width = <8>; 414 mmc-ddr-1_8v; 415 mmc-hs200-1_8v; 416 mmc-pwrseq = <&emmc_pwrseq>; 417 cdns,phy-input-delay-legacy = <9>; 418 cdns,phy-input-delay-mmc-highspeed = <2>; 419 cdns,phy-input-delay-mmc-ddr = <3>; 420 cdns,phy-dll-delay-sdclk = <21>; 421 cdns,phy-dll-delay-sdclk-hsmmc = <21>; 422 }; 423 424 sd: mmc@5a400000 { 425 compatible = "socionext,uniphier-sd-v3.1.1"; 426 status = "disabled"; 427 reg = <0x5a400000 0x800>; 428 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 429 pinctrl-names = "default", "uhs"; 430 pinctrl-0 = <&pinctrl_sd>; 431 pinctrl-1 = <&pinctrl_sd_uhs>; 432 clocks = <&sd_clk 0>; 433 reset-names = "host"; 434 resets = <&sd_rst 0>; 435 bus-width = <4>; 436 cap-sd-highspeed; 437 sd-uhs-sdr12; 438 sd-uhs-sdr25; 439 sd-uhs-sdr50; 440 }; 441 442 soc_glue: syscon@5f800000 { 443 compatible = "socionext,uniphier-pxs3-soc-glue", 444 "simple-mfd", "syscon"; 445 reg = <0x5f800000 0x2000>; 446 447 pinctrl: pinctrl { 448 compatible = "socionext,uniphier-pxs3-pinctrl"; 449 }; 450 }; 451 452 syscon@5f900000 { 453 compatible = "socionext,uniphier-pxs3-soc-glue-debug", 454 "simple-mfd"; 455 reg = <0x5f900000 0x2000>; 456 #address-cells = <1>; 457 #size-cells = <1>; 458 ranges = <0 0x5f900000 0x2000>; 459 460 efuse@100 { 461 compatible = "socionext,uniphier-efuse"; 462 reg = <0x100 0x28>; 463 }; 464 465 efuse@200 { 466 compatible = "socionext,uniphier-efuse"; 467 reg = <0x200 0x68>; 468 #address-cells = <1>; 469 #size-cells = <1>; 470 471 /* USB cells */ 472 usb_rterm0: trim@54,4 { 473 reg = <0x54 1>; 474 bits = <4 2>; 475 }; 476 usb_rterm1: trim@55,4 { 477 reg = <0x55 1>; 478 bits = <4 2>; 479 }; 480 usb_rterm2: trim@58,4 { 481 reg = <0x58 1>; 482 bits = <4 2>; 483 }; 484 usb_rterm3: trim@59,4 { 485 reg = <0x59 1>; 486 bits = <4 2>; 487 }; 488 usb_sel_t0: trim@54,0 { 489 reg = <0x54 1>; 490 bits = <0 4>; 491 }; 492 usb_sel_t1: trim@55,0 { 493 reg = <0x55 1>; 494 bits = <0 4>; 495 }; 496 usb_sel_t2: trim@58,0 { 497 reg = <0x58 1>; 498 bits = <0 4>; 499 }; 500 usb_sel_t3: trim@59,0 { 501 reg = <0x59 1>; 502 bits = <0 4>; 503 }; 504 usb_hs_i0: trim@56,0 { 505 reg = <0x56 1>; 506 bits = <0 4>; 507 }; 508 usb_hs_i2: trim@5a,0 { 509 reg = <0x5a 1>; 510 bits = <0 4>; 511 }; 512 }; 513 }; 514 515 xdmac: dma-controller@5fc10000 { 516 compatible = "socionext,uniphier-xdmac"; 517 reg = <0x5fc10000 0x5300>; 518 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 519 dma-channels = <16>; 520 #dma-cells = <2>; 521 }; 522 523 aidet: interrupt-controller@5fc20000 { 524 compatible = "socionext,uniphier-pxs3-aidet"; 525 reg = <0x5fc20000 0x200>; 526 interrupt-controller; 527 #interrupt-cells = <2>; 528 }; 529 530 gic: interrupt-controller@5fe00000 { 531 compatible = "arm,gic-v3"; 532 reg = <0x5fe00000 0x10000>, /* GICD */ 533 <0x5fe80000 0x80000>; /* GICR */ 534 interrupt-controller; 535 #interrupt-cells = <3>; 536 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 537 }; 538 539 syscon@61840000 { 540 compatible = "socionext,uniphier-pxs3-sysctrl", 541 "simple-mfd", "syscon"; 542 reg = <0x61840000 0x10000>; 543 544 sys_clk: clock-controller { 545 compatible = "socionext,uniphier-pxs3-clock"; 546 #clock-cells = <1>; 547 }; 548 549 sys_rst: reset-controller { 550 compatible = "socionext,uniphier-pxs3-reset"; 551 #reset-cells = <1>; 552 }; 553 554 watchdog { 555 compatible = "socionext,uniphier-wdt"; 556 }; 557 558 pvtctl: thermal-sensor { 559 compatible = "socionext,uniphier-pxs3-thermal"; 560 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 561 #thermal-sensor-cells = <0>; 562 socionext,tmod-calibration = <0x0f22 0x68ee>; 563 }; 564 }; 565 566 eth0: ethernet@65000000 { 567 compatible = "socionext,uniphier-pxs3-ave4"; 568 status = "disabled"; 569 reg = <0x65000000 0x8500>; 570 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 571 pinctrl-names = "default"; 572 pinctrl-0 = <&pinctrl_ether_rgmii>; 573 clock-names = "ether"; 574 clocks = <&sys_clk 6>; 575 reset-names = "ether"; 576 resets = <&sys_rst 6>; 577 phy-mode = "rgmii-id"; 578 local-mac-address = [00 00 00 00 00 00]; 579 socionext,syscon-phy-mode = <&soc_glue 0>; 580 581 mdio0: mdio { 582 #address-cells = <1>; 583 #size-cells = <0>; 584 }; 585 }; 586 587 eth1: ethernet@65200000 { 588 compatible = "socionext,uniphier-pxs3-ave4"; 589 status = "disabled"; 590 reg = <0x65200000 0x8500>; 591 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 592 pinctrl-names = "default"; 593 pinctrl-0 = <&pinctrl_ether1_rgmii>; 594 clock-names = "ether"; 595 clocks = <&sys_clk 7>; 596 reset-names = "ether"; 597 resets = <&sys_rst 7>; 598 phy-mode = "rgmii-id"; 599 local-mac-address = [00 00 00 00 00 00]; 600 socionext,syscon-phy-mode = <&soc_glue 1>; 601 602 mdio1: mdio { 603 #address-cells = <1>; 604 #size-cells = <0>; 605 }; 606 }; 607 608 ahci0: sata@65600000 { 609 compatible = "socionext,uniphier-pxs3-ahci", 610 "generic-ahci"; 611 status = "disabled"; 612 reg = <0x65600000 0x10000>; 613 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 614 clocks = <&sys_clk 28>; 615 resets = <&sys_rst 28>, <&ahci0_rst 0>; 616 ports-implemented = <1>; 617 phys = <&ahci0_phy>; 618 }; 619 620 sata-controller@65700000 { 621 compatible = "socionext,uniphier-pxs3-ahci-glue", 622 "simple-mfd"; 623 reg = <0x65700000 0x100>; 624 #address-cells = <1>; 625 #size-cells = <1>; 626 ranges = <0 0x65700000 0x100>; 627 628 ahci0_rst: reset-controller@0 { 629 compatible = "socionext,uniphier-pxs3-ahci-reset"; 630 reg = <0x0 0x4>; 631 clock-names = "link"; 632 clocks = <&sys_clk 28>; 633 reset-names = "link"; 634 resets = <&sys_rst 28>; 635 #reset-cells = <1>; 636 }; 637 638 ahci0_phy: sata-phy@10 { 639 compatible = "socionext,uniphier-pxs3-ahci-phy"; 640 reg = <0x10 0x10>; 641 clock-names = "link", "phy"; 642 clocks = <&sys_clk 28>, <&sys_clk 30>; 643 reset-names = "link", "phy"; 644 resets = <&sys_rst 28>, <&sys_rst 30>; 645 #phy-cells = <0>; 646 }; 647 }; 648 649 ahci1: sata@65800000 { 650 compatible = "socionext,uniphier-pxs3-ahci", 651 "generic-ahci"; 652 status = "disabled"; 653 reg = <0x65800000 0x10000>; 654 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 655 clocks = <&sys_clk 29>; 656 resets = <&sys_rst 29>, <&ahci1_rst 0>; 657 ports-implemented = <1>; 658 phys = <&ahci1_phy>; 659 }; 660 661 sata-controller@65900000 { 662 compatible = "socionext,uniphier-pxs3-ahci-glue", 663 "simple-mfd"; 664 reg = <0x65900000 0x100>; 665 #address-cells = <1>; 666 #size-cells = <1>; 667 ranges = <0 0x65900000 0x100>; 668 669 ahci1_rst: reset-controller@0 { 670 compatible = "socionext,uniphier-pxs3-ahci-reset"; 671 reg = <0x0 0x4>; 672 clock-names = "link"; 673 clocks = <&sys_clk 29>; 674 reset-names = "link"; 675 resets = <&sys_rst 29>; 676 #reset-cells = <1>; 677 }; 678 679 ahci1_phy: sata-phy@10 { 680 compatible = "socionext,uniphier-pxs3-ahci-phy"; 681 reg = <0x10 0x10>; 682 clock-names = "link", "phy"; 683 clocks = <&sys_clk 29>, <&sys_clk 30>; 684 reset-names = "link", "phy"; 685 resets = <&sys_rst 29>, <&sys_rst 30>; 686 #phy-cells = <0>; 687 }; 688 }; 689 690 usb0: usb@65a00000 { 691 compatible = "socionext,uniphier-dwc3", "snps,dwc3"; 692 status = "disabled"; 693 reg = <0x65a00000 0xcd00>; 694 interrupt-names = "dwc_usb3"; 695 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 696 pinctrl-names = "default"; 697 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; 698 clock-names = "ref", "bus_early", "suspend"; 699 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; 700 resets = <&usb0_rst 15>; 701 phys = <&usb0_hsphy0>, <&usb0_hsphy1>, 702 <&usb0_ssphy0>, <&usb0_ssphy1>; 703 dr_mode = "host"; 704 }; 705 706 usb-controller@65b00000 { 707 compatible = "socionext,uniphier-pxs3-dwc3-glue", 708 "simple-mfd"; 709 reg = <0x65b00000 0x400>; 710 #address-cells = <1>; 711 #size-cells = <1>; 712 ranges = <0 0x65b00000 0x400>; 713 714 usb0_rst: reset-controller@0 { 715 compatible = "socionext,uniphier-pxs3-usb3-reset"; 716 reg = <0x0 0x4>; 717 #reset-cells = <1>; 718 clock-names = "link"; 719 clocks = <&sys_clk 12>; 720 reset-names = "link"; 721 resets = <&sys_rst 12>; 722 }; 723 724 usb0_vbus0: regulator@100 { 725 compatible = "socionext,uniphier-pxs3-usb3-regulator"; 726 reg = <0x100 0x10>; 727 clock-names = "link"; 728 clocks = <&sys_clk 12>; 729 reset-names = "link"; 730 resets = <&sys_rst 12>; 731 }; 732 733 usb0_vbus1: regulator@110 { 734 compatible = "socionext,uniphier-pxs3-usb3-regulator"; 735 reg = <0x110 0x10>; 736 clock-names = "link"; 737 clocks = <&sys_clk 12>; 738 reset-names = "link"; 739 resets = <&sys_rst 12>; 740 }; 741 742 usb0_hsphy0: phy@200 { 743 compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 744 reg = <0x200 0x10>; 745 #phy-cells = <0>; 746 clock-names = "link", "phy"; 747 clocks = <&sys_clk 12>, <&sys_clk 16>; 748 reset-names = "link", "phy"; 749 resets = <&sys_rst 12>, <&sys_rst 16>; 750 vbus-supply = <&usb0_vbus0>; 751 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 752 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, 753 <&usb_hs_i0>; 754 }; 755 756 usb0_hsphy1: phy@210 { 757 compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 758 reg = <0x210 0x10>; 759 #phy-cells = <0>; 760 clock-names = "link", "phy"; 761 clocks = <&sys_clk 12>, <&sys_clk 16>; 762 reset-names = "link", "phy"; 763 resets = <&sys_rst 12>, <&sys_rst 16>; 764 vbus-supply = <&usb0_vbus1>; 765 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 766 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>, 767 <&usb_hs_i0>; 768 }; 769 770 usb0_ssphy0: phy@300 { 771 compatible = "socionext,uniphier-pxs3-usb3-ssphy"; 772 reg = <0x300 0x10>; 773 #phy-cells = <0>; 774 clock-names = "link", "phy"; 775 clocks = <&sys_clk 12>, <&sys_clk 17>; 776 reset-names = "link", "phy"; 777 resets = <&sys_rst 12>, <&sys_rst 17>; 778 vbus-supply = <&usb0_vbus0>; 779 }; 780 781 usb0_ssphy1: phy@310 { 782 compatible = "socionext,uniphier-pxs3-usb3-ssphy"; 783 reg = <0x310 0x10>; 784 #phy-cells = <0>; 785 clock-names = "link", "phy"; 786 clocks = <&sys_clk 12>, <&sys_clk 18>; 787 reset-names = "link", "phy"; 788 resets = <&sys_rst 12>, <&sys_rst 18>; 789 vbus-supply = <&usb0_vbus1>; 790 }; 791 }; 792 793 usb1: usb@65c00000 { 794 compatible = "socionext,uniphier-dwc3", "snps,dwc3"; 795 status = "disabled"; 796 reg = <0x65c00000 0xcd00>; 797 interrupt-names = "dwc_usb3"; 798 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 799 pinctrl-names = "default"; 800 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; 801 clock-names = "ref", "bus_early", "suspend"; 802 clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>; 803 resets = <&usb1_rst 15>; 804 phys = <&usb1_hsphy0>, <&usb1_hsphy1>, 805 <&usb1_ssphy0>; 806 dr_mode = "host"; 807 }; 808 809 usb-controller@65d00000 { 810 compatible = "socionext,uniphier-pxs3-dwc3-glue", 811 "simple-mfd"; 812 reg = <0x65d00000 0x400>; 813 #address-cells = <1>; 814 #size-cells = <1>; 815 ranges = <0 0x65d00000 0x400>; 816 817 usb1_rst: reset-controller@0 { 818 compatible = "socionext,uniphier-pxs3-usb3-reset"; 819 reg = <0x0 0x4>; 820 #reset-cells = <1>; 821 clock-names = "link"; 822 clocks = <&sys_clk 13>; 823 reset-names = "link"; 824 resets = <&sys_rst 13>; 825 }; 826 827 usb1_vbus0: regulator@100 { 828 compatible = "socionext,uniphier-pxs3-usb3-regulator"; 829 reg = <0x100 0x10>; 830 clock-names = "link"; 831 clocks = <&sys_clk 13>; 832 reset-names = "link"; 833 resets = <&sys_rst 13>; 834 }; 835 836 usb1_vbus1: regulator@110 { 837 compatible = "socionext,uniphier-pxs3-usb3-regulator"; 838 reg = <0x110 0x10>; 839 clock-names = "link"; 840 clocks = <&sys_clk 13>; 841 reset-names = "link"; 842 resets = <&sys_rst 13>; 843 }; 844 845 usb1_hsphy0: phy@200 { 846 compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 847 reg = <0x200 0x10>; 848 #phy-cells = <0>; 849 clock-names = "link", "phy", "phy-ext"; 850 clocks = <&sys_clk 13>, <&sys_clk 20>, 851 <&sys_clk 14>; 852 reset-names = "link", "phy"; 853 resets = <&sys_rst 13>, <&sys_rst 20>; 854 vbus-supply = <&usb1_vbus0>; 855 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 856 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>, 857 <&usb_hs_i2>; 858 }; 859 860 usb1_hsphy1: phy@210 { 861 compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 862 reg = <0x210 0x10>; 863 #phy-cells = <0>; 864 clock-names = "link", "phy", "phy-ext"; 865 clocks = <&sys_clk 13>, <&sys_clk 20>, 866 <&sys_clk 14>; 867 reset-names = "link", "phy"; 868 resets = <&sys_rst 13>, <&sys_rst 20>; 869 vbus-supply = <&usb1_vbus1>; 870 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 871 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>, 872 <&usb_hs_i2>; 873 }; 874 875 usb1_ssphy0: phy@300 { 876 compatible = "socionext,uniphier-pxs3-usb3-ssphy"; 877 reg = <0x300 0x10>; 878 #phy-cells = <0>; 879 clock-names = "link", "phy", "phy-ext"; 880 clocks = <&sys_clk 13>, <&sys_clk 21>, 881 <&sys_clk 14>; 882 reset-names = "link", "phy"; 883 resets = <&sys_rst 13>, <&sys_rst 21>; 884 vbus-supply = <&usb1_vbus0>; 885 }; 886 }; 887 888 pcie: pcie@66000000 { 889 compatible = "socionext,uniphier-pcie"; 890 status = "disabled"; 891 reg-names = "dbi", "link", "config"; 892 reg = <0x66000000 0x1000>, <0x66010000 0x10000>, 893 <0x2fff0000 0x10000>; 894 #address-cells = <3>; 895 #size-cells = <2>; 896 clocks = <&sys_clk 24>; 897 resets = <&sys_rst 24>; 898 num-lanes = <1>; 899 num-viewport = <1>; 900 bus-range = <0x0 0xff>; 901 device_type = "pci"; 902 ranges = 903 /* downstream I/O */ 904 <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>, 905 /* non-prefetchable memory */ 906 <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>; 907 #interrupt-cells = <1>; 908 interrupt-names = "dma", "msi"; 909 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 911 interrupt-map-mask = <0 0 0 7>; 912 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */ 913 <0 0 0 2 &pcie_intc 1>, /* INTB */ 914 <0 0 0 3 &pcie_intc 2>, /* INTC */ 915 <0 0 0 4 &pcie_intc 3>; /* INTD */ 916 phy-names = "pcie-phy"; 917 phys = <&pcie_phy>; 918 919 pcie_intc: legacy-interrupt-controller { 920 interrupt-controller; 921 #interrupt-cells = <1>; 922 interrupt-parent = <&gic>; 923 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 924 }; 925 }; 926 927 pcie_phy: phy@66038000 { 928 compatible = "socionext,uniphier-pxs3-pcie-phy"; 929 reg = <0x66038000 0x4000>; 930 #phy-cells = <0>; 931 clock-names = "link"; 932 clocks = <&sys_clk 24>; 933 reset-names = "link"; 934 resets = <&sys_rst 24>; 935 socionext,syscon = <&soc_glue>; 936 }; 937 938 nand: nand-controller@68000000 { 939 compatible = "socionext,uniphier-denali-nand-v5b"; 940 status = "disabled"; 941 reg-names = "nand_data", "denali_reg"; 942 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 943 #address-cells = <1>; 944 #size-cells = <0>; 945 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 946 pinctrl-names = "default"; 947 pinctrl-0 = <&pinctrl_nand>; 948 clock-names = "nand", "nand_x", "ecc"; 949 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; 950 reset-names = "nand", "reg"; 951 resets = <&sys_rst 2>, <&sys_rst 2>; 952 }; 953 }; 954}; 955 956#include "uniphier-pinctrl.dtsi" 957