1/*
2 * Device Tree Source for UniPhier PXs3 SoC
3 *
4 * Copyright (C) 2017 Socionext Inc.
5 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 *
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 */
9
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/gpio/uniphier-gpio.h>
12
13/memreserve/ 0x80000000 0x02000000;
14
15/ {
16	compatible = "socionext,uniphier-pxs3";
17	#address-cells = <2>;
18	#size-cells = <2>;
19	interrupt-parent = <&gic>;
20
21	cpus {
22		#address-cells = <2>;
23		#size-cells = <0>;
24
25		cpu-map {
26			cluster0 {
27				core0 {
28					cpu = <&cpu0>;
29				};
30				core1 {
31					cpu = <&cpu1>;
32				};
33				core2 {
34					cpu = <&cpu2>;
35				};
36				core3 {
37					cpu = <&cpu3>;
38				};
39			};
40		};
41
42		cpu0: cpu@0 {
43			device_type = "cpu";
44			compatible = "arm,cortex-a53", "arm,armv8";
45			reg = <0 0x000>;
46			clocks = <&sys_clk 33>;
47			enable-method = "psci";
48			operating-points-v2 = <&cluster0_opp>;
49		};
50
51		cpu1: cpu@1 {
52			device_type = "cpu";
53			compatible = "arm,cortex-a53", "arm,armv8";
54			reg = <0 0x001>;
55			clocks = <&sys_clk 33>;
56			enable-method = "psci";
57			operating-points-v2 = <&cluster0_opp>;
58		};
59
60		cpu2: cpu@2 {
61			device_type = "cpu";
62			compatible = "arm,cortex-a53", "arm,armv8";
63			reg = <0 0x002>;
64			clocks = <&sys_clk 33>;
65			enable-method = "psci";
66			operating-points-v2 = <&cluster0_opp>;
67		};
68
69		cpu3: cpu@3 {
70			device_type = "cpu";
71			compatible = "arm,cortex-a53", "arm,armv8";
72			reg = <0 0x003>;
73			clocks = <&sys_clk 33>;
74			enable-method = "psci";
75			operating-points-v2 = <&cluster0_opp>;
76		};
77	};
78
79	cluster0_opp: opp-table {
80		compatible = "operating-points-v2";
81		opp-shared;
82
83		opp-250000000 {
84			opp-hz = /bits/ 64 <250000000>;
85			clock-latency-ns = <300>;
86		};
87		opp-325000000 {
88			opp-hz = /bits/ 64 <325000000>;
89			clock-latency-ns = <300>;
90		};
91		opp-500000000 {
92			opp-hz = /bits/ 64 <500000000>;
93			clock-latency-ns = <300>;
94		};
95		opp-650000000 {
96			opp-hz = /bits/ 64 <650000000>;
97			clock-latency-ns = <300>;
98		};
99		opp-666667000 {
100			opp-hz = /bits/ 64 <666667000>;
101			clock-latency-ns = <300>;
102		};
103		opp-866667000 {
104			opp-hz = /bits/ 64 <866667000>;
105			clock-latency-ns = <300>;
106		};
107		opp-1000000000 {
108			opp-hz = /bits/ 64 <1000000000>;
109			clock-latency-ns = <300>;
110		};
111		opp-1300000000 {
112			opp-hz = /bits/ 64 <1300000000>;
113			clock-latency-ns = <300>;
114		};
115	};
116
117	psci {
118		compatible = "arm,psci-1.0";
119		method = "smc";
120	};
121
122	clocks {
123		refclk: ref {
124			compatible = "fixed-clock";
125			#clock-cells = <0>;
126			clock-frequency = <25000000>;
127		};
128	};
129
130	emmc_pwrseq: emmc-pwrseq {
131		compatible = "mmc-pwrseq-emmc";
132		reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>;
133	};
134
135	timer {
136		compatible = "arm,armv8-timer";
137		interrupts = <1 13 4>,
138			     <1 14 4>,
139			     <1 11 4>,
140			     <1 10 4>;
141	};
142
143	soc@0 {
144		compatible = "simple-bus";
145		#address-cells = <1>;
146		#size-cells = <1>;
147		ranges = <0 0 0 0xffffffff>;
148
149		serial0: serial@54006800 {
150			compatible = "socionext,uniphier-uart";
151			status = "disabled";
152			reg = <0x54006800 0x40>;
153			interrupts = <0 33 4>;
154			pinctrl-names = "default";
155			pinctrl-0 = <&pinctrl_uart0>;
156			clocks = <&peri_clk 0>;
157			resets = <&peri_rst 0>;
158		};
159
160		serial1: serial@54006900 {
161			compatible = "socionext,uniphier-uart";
162			status = "disabled";
163			reg = <0x54006900 0x40>;
164			interrupts = <0 35 4>;
165			pinctrl-names = "default";
166			pinctrl-0 = <&pinctrl_uart1>;
167			clocks = <&peri_clk 1>;
168			resets = <&peri_rst 1>;
169		};
170
171		serial2: serial@54006a00 {
172			compatible = "socionext,uniphier-uart";
173			status = "disabled";
174			reg = <0x54006a00 0x40>;
175			interrupts = <0 37 4>;
176			pinctrl-names = "default";
177			pinctrl-0 = <&pinctrl_uart2>;
178			clocks = <&peri_clk 2>;
179			resets = <&peri_rst 2>;
180		};
181
182		serial3: serial@54006b00 {
183			compatible = "socionext,uniphier-uart";
184			status = "disabled";
185			reg = <0x54006b00 0x40>;
186			interrupts = <0 177 4>;
187			pinctrl-names = "default";
188			pinctrl-0 = <&pinctrl_uart3>;
189			clocks = <&peri_clk 3>;
190			resets = <&peri_rst 3>;
191		};
192
193		gpio: gpio@55000000 {
194			compatible = "socionext,uniphier-gpio";
195			reg = <0x55000000 0x200>;
196			interrupt-parent = <&aidet>;
197			interrupt-controller;
198			#interrupt-cells = <2>;
199			gpio-controller;
200			#gpio-cells = <2>;
201			gpio-ranges = <&pinctrl 0 0 0>,
202				      <&pinctrl 104 0 0>,
203				      <&pinctrl 168 0 0>;
204			gpio-ranges-group-names = "gpio_range0",
205						  "gpio_range1",
206						  "gpio_range2";
207			ngpios = <286>;
208			socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
209						     <21 217 3>;
210		};
211
212		i2c0: i2c@58780000 {
213			compatible = "socionext,uniphier-fi2c";
214			status = "disabled";
215			reg = <0x58780000 0x80>;
216			#address-cells = <1>;
217			#size-cells = <0>;
218			interrupts = <0 41 4>;
219			pinctrl-names = "default";
220			pinctrl-0 = <&pinctrl_i2c0>;
221			clocks = <&peri_clk 4>;
222			resets = <&peri_rst 4>;
223			clock-frequency = <100000>;
224		};
225
226		i2c1: i2c@58781000 {
227			compatible = "socionext,uniphier-fi2c";
228			status = "disabled";
229			reg = <0x58781000 0x80>;
230			#address-cells = <1>;
231			#size-cells = <0>;
232			interrupts = <0 42 4>;
233			pinctrl-names = "default";
234			pinctrl-0 = <&pinctrl_i2c1>;
235			clocks = <&peri_clk 5>;
236			resets = <&peri_rst 5>;
237			clock-frequency = <100000>;
238		};
239
240		i2c2: i2c@58782000 {
241			compatible = "socionext,uniphier-fi2c";
242			status = "disabled";
243			reg = <0x58782000 0x80>;
244			#address-cells = <1>;
245			#size-cells = <0>;
246			interrupts = <0 43 4>;
247			pinctrl-names = "default";
248			pinctrl-0 = <&pinctrl_i2c2>;
249			clocks = <&peri_clk 6>;
250			resets = <&peri_rst 6>;
251			clock-frequency = <100000>;
252		};
253
254		i2c3: i2c@58783000 {
255			compatible = "socionext,uniphier-fi2c";
256			status = "disabled";
257			reg = <0x58783000 0x80>;
258			#address-cells = <1>;
259			#size-cells = <0>;
260			interrupts = <0 44 4>;
261			pinctrl-names = "default";
262			pinctrl-0 = <&pinctrl_i2c3>;
263			clocks = <&peri_clk 7>;
264			resets = <&peri_rst 7>;
265			clock-frequency = <100000>;
266		};
267
268		/* chip-internal connection for HDMI */
269		i2c6: i2c@58786000 {
270			compatible = "socionext,uniphier-fi2c";
271			reg = <0x58786000 0x80>;
272			#address-cells = <1>;
273			#size-cells = <0>;
274			interrupts = <0 26 4>;
275			clocks = <&peri_clk 10>;
276			resets = <&peri_rst 10>;
277			clock-frequency = <400000>;
278		};
279
280		system_bus: system-bus@58c00000 {
281			compatible = "socionext,uniphier-system-bus";
282			status = "disabled";
283			reg = <0x58c00000 0x400>;
284			#address-cells = <2>;
285			#size-cells = <1>;
286			pinctrl-names = "default";
287			pinctrl-0 = <&pinctrl_system_bus>;
288		};
289
290		smpctrl@59801000 {
291			compatible = "socionext,uniphier-smpctrl";
292			reg = <0x59801000 0x400>;
293		};
294
295		sdctrl@59810000 {
296			compatible = "socionext,uniphier-pxs3-sdctrl",
297				     "simple-mfd", "syscon";
298			reg = <0x59810000 0x400>;
299
300			sd_clk: clock {
301				compatible = "socionext,uniphier-pxs3-sd-clock";
302				#clock-cells = <1>;
303			};
304
305			sd_rst: reset {
306				compatible = "socionext,uniphier-pxs3-sd-reset";
307				#reset-cells = <1>;
308			};
309		};
310
311		perictrl@59820000 {
312			compatible = "socionext,uniphier-pxs3-perictrl",
313				     "simple-mfd", "syscon";
314			reg = <0x59820000 0x200>;
315
316			peri_clk: clock {
317				compatible = "socionext,uniphier-pxs3-peri-clock";
318				#clock-cells = <1>;
319			};
320
321			peri_rst: reset {
322				compatible = "socionext,uniphier-pxs3-peri-reset";
323				#reset-cells = <1>;
324			};
325		};
326
327		emmc: sdhc@5a000000 {
328			compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
329			reg = <0x5a000000 0x400>;
330			interrupts = <0 78 4>;
331			pinctrl-names = "default";
332			pinctrl-0 = <&pinctrl_emmc>;
333			clocks = <&sys_clk 4>;
334			resets = <&sys_rst 4>;
335			bus-width = <8>;
336			mmc-ddr-1_8v;
337			mmc-hs200-1_8v;
338			mmc-pwrseq = <&emmc_pwrseq>;
339			cdns,phy-input-delay-legacy = <4>;
340			cdns,phy-input-delay-mmc-highspeed = <2>;
341			cdns,phy-input-delay-mmc-ddr = <3>;
342			cdns,phy-dll-delay-sdclk = <21>;
343			cdns,phy-dll-delay-sdclk-hsmmc = <21>;
344		};
345
346		soc-glue@5f800000 {
347			compatible = "socionext,uniphier-pxs3-soc-glue",
348				     "simple-mfd", "syscon";
349			reg = <0x5f800000 0x2000>;
350
351			pinctrl: pinctrl {
352				compatible = "socionext,uniphier-pxs3-pinctrl";
353			};
354		};
355
356		soc-glue@5f900000 {
357			compatible = "socionext,uniphier-pxs3-soc-glue-debug",
358				     "simple-mfd";
359			#address-cells = <1>;
360			#size-cells = <1>;
361			ranges = <0 0x5f900000 0x2000>;
362
363			efuse@100 {
364				compatible = "socionext,uniphier-efuse";
365				reg = <0x100 0x28>;
366			};
367
368			efuse@200 {
369				compatible = "socionext,uniphier-efuse";
370				reg = <0x200 0x68>;
371			};
372		};
373
374		aidet: aidet@5fc20000 {
375			compatible = "socionext,uniphier-pxs3-aidet";
376			reg = <0x5fc20000 0x200>;
377			interrupt-controller;
378			#interrupt-cells = <2>;
379		};
380
381		gic: interrupt-controller@5fe00000 {
382			compatible = "arm,gic-v3";
383			reg = <0x5fe00000 0x10000>,	/* GICD */
384			      <0x5fe80000 0x80000>;	/* GICR */
385			interrupt-controller;
386			#interrupt-cells = <3>;
387			interrupts = <1 9 4>;
388		};
389
390		sysctrl@61840000 {
391			compatible = "socionext,uniphier-pxs3-sysctrl",
392				     "simple-mfd", "syscon";
393			reg = <0x61840000 0x10000>;
394
395			sys_clk: clock {
396				compatible = "socionext,uniphier-pxs3-clock";
397				#clock-cells = <1>;
398			};
399
400			sys_rst: reset {
401				compatible = "socionext,uniphier-pxs3-reset";
402				#reset-cells = <1>;
403			};
404
405			watchdog {
406				compatible = "socionext,uniphier-wdt";
407			};
408		};
409
410		nand: nand@68000000 {
411			compatible = "socionext,uniphier-denali-nand-v5b";
412			status = "disabled";
413			reg-names = "nand_data", "denali_reg";
414			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
415			interrupts = <0 65 4>;
416			pinctrl-names = "default";
417			pinctrl-0 = <&pinctrl_nand>;
418			clocks = <&sys_clk 2>;
419			resets = <&sys_rst 2>;
420		};
421	};
422};
423
424#include "uniphier-pinctrl.dtsi"
425