1/*
2 * Device Tree Source for UniPhier PXs3 SoC
3 *
4 * Copyright (C) 2017 Socionext Inc.
5 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 *
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 */
9
10#include <dt-bindings/gpio/gpio.h>
11
12/memreserve/ 0x80000000 0x02000000;
13
14/ {
15	compatible = "socionext,uniphier-pxs3";
16	#address-cells = <2>;
17	#size-cells = <2>;
18	interrupt-parent = <&gic>;
19
20	cpus {
21		#address-cells = <2>;
22		#size-cells = <0>;
23
24		cpu-map {
25			cluster0 {
26				core0 {
27					cpu = <&cpu0>;
28				};
29				core1 {
30					cpu = <&cpu1>;
31				};
32				core2 {
33					cpu = <&cpu2>;
34				};
35				core3 {
36					cpu = <&cpu3>;
37				};
38			};
39		};
40
41		cpu0: cpu@0 {
42			device_type = "cpu";
43			compatible = "arm,cortex-a53", "arm,armv8";
44			reg = <0 0x000>;
45			clocks = <&sys_clk 33>;
46			enable-method = "psci";
47			operating-points-v2 = <&cluster0_opp>;
48		};
49
50		cpu1: cpu@1 {
51			device_type = "cpu";
52			compatible = "arm,cortex-a53", "arm,armv8";
53			reg = <0 0x001>;
54			clocks = <&sys_clk 33>;
55			enable-method = "psci";
56			operating-points-v2 = <&cluster0_opp>;
57		};
58
59		cpu2: cpu@2 {
60			device_type = "cpu";
61			compatible = "arm,cortex-a53", "arm,armv8";
62			reg = <0 0x002>;
63			clocks = <&sys_clk 33>;
64			enable-method = "psci";
65			operating-points-v2 = <&cluster0_opp>;
66		};
67
68		cpu3: cpu@3 {
69			device_type = "cpu";
70			compatible = "arm,cortex-a53", "arm,armv8";
71			reg = <0 0x003>;
72			clocks = <&sys_clk 33>;
73			enable-method = "psci";
74			operating-points-v2 = <&cluster0_opp>;
75		};
76	};
77
78	cluster0_opp: opp-table {
79		compatible = "operating-points-v2";
80		opp-shared;
81
82		opp-250000000 {
83			opp-hz = /bits/ 64 <250000000>;
84			clock-latency-ns = <300>;
85		};
86		opp-325000000 {
87			opp-hz = /bits/ 64 <325000000>;
88			clock-latency-ns = <300>;
89		};
90		opp-500000000 {
91			opp-hz = /bits/ 64 <500000000>;
92			clock-latency-ns = <300>;
93		};
94		opp-650000000 {
95			opp-hz = /bits/ 64 <650000000>;
96			clock-latency-ns = <300>;
97		};
98		opp-666667000 {
99			opp-hz = /bits/ 64 <666667000>;
100			clock-latency-ns = <300>;
101		};
102		opp-866667000 {
103			opp-hz = /bits/ 64 <866667000>;
104			clock-latency-ns = <300>;
105		};
106		opp-1000000000 {
107			opp-hz = /bits/ 64 <1000000000>;
108			clock-latency-ns = <300>;
109		};
110		opp-1300000000 {
111			opp-hz = /bits/ 64 <1300000000>;
112			clock-latency-ns = <300>;
113		};
114	};
115
116	psci {
117		compatible = "arm,psci-1.0";
118		method = "smc";
119	};
120
121	clocks {
122		refclk: ref {
123			compatible = "fixed-clock";
124			#clock-cells = <0>;
125			clock-frequency = <25000000>;
126		};
127	};
128
129	emmc_pwrseq: emmc-pwrseq {
130		compatible = "mmc-pwrseq-emmc";
131		reset-gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
132	};
133
134	timer {
135		compatible = "arm,armv8-timer";
136		interrupts = <1 13 4>,
137			     <1 14 4>,
138			     <1 11 4>,
139			     <1 10 4>;
140	};
141
142	soc@0 {
143		compatible = "simple-bus";
144		#address-cells = <1>;
145		#size-cells = <1>;
146		ranges = <0 0 0 0xffffffff>;
147
148		serial0: serial@54006800 {
149			compatible = "socionext,uniphier-uart";
150			status = "disabled";
151			reg = <0x54006800 0x40>;
152			interrupts = <0 33 4>;
153			pinctrl-names = "default";
154			pinctrl-0 = <&pinctrl_uart0>;
155			clocks = <&peri_clk 0>;
156			resets = <&peri_rst 0>;
157		};
158
159		serial1: serial@54006900 {
160			compatible = "socionext,uniphier-uart";
161			status = "disabled";
162			reg = <0x54006900 0x40>;
163			interrupts = <0 35 4>;
164			pinctrl-names = "default";
165			pinctrl-0 = <&pinctrl_uart1>;
166			clocks = <&peri_clk 1>;
167			resets = <&peri_rst 1>;
168		};
169
170		serial2: serial@54006a00 {
171			compatible = "socionext,uniphier-uart";
172			status = "disabled";
173			reg = <0x54006a00 0x40>;
174			interrupts = <0 37 4>;
175			pinctrl-names = "default";
176			pinctrl-0 = <&pinctrl_uart2>;
177			clocks = <&peri_clk 2>;
178			resets = <&peri_rst 2>;
179		};
180
181		serial3: serial@54006b00 {
182			compatible = "socionext,uniphier-uart";
183			status = "disabled";
184			reg = <0x54006b00 0x40>;
185			interrupts = <0 177 4>;
186			pinctrl-names = "default";
187			pinctrl-0 = <&pinctrl_uart3>;
188			clocks = <&peri_clk 3>;
189			resets = <&peri_rst 3>;
190		};
191
192		gpio: gpio@55000000 {
193			compatible = "socionext,uniphier-gpio";
194			reg = <0x55000000 0x200>;
195			interrupt-parent = <&aidet>;
196			interrupt-controller;
197			#interrupt-cells = <2>;
198			gpio-controller;
199			#gpio-cells = <2>;
200			gpio-ranges = <&pinctrl 0 0 0>,
201				      <&pinctrl 96 0 0>,
202				      <&pinctrl 160 0 0>;
203			gpio-ranges-group-names = "gpio_range0",
204						  "gpio_range1",
205						  "gpio_range2";
206			ngpios = <286>;
207			socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
208						     <21 217 3>;
209		};
210
211		i2c0: i2c@58780000 {
212			compatible = "socionext,uniphier-fi2c";
213			status = "disabled";
214			reg = <0x58780000 0x80>;
215			#address-cells = <1>;
216			#size-cells = <0>;
217			interrupts = <0 41 4>;
218			pinctrl-names = "default";
219			pinctrl-0 = <&pinctrl_i2c0>;
220			clocks = <&peri_clk 4>;
221			resets = <&peri_rst 4>;
222			clock-frequency = <100000>;
223		};
224
225		i2c1: i2c@58781000 {
226			compatible = "socionext,uniphier-fi2c";
227			status = "disabled";
228			reg = <0x58781000 0x80>;
229			#address-cells = <1>;
230			#size-cells = <0>;
231			interrupts = <0 42 4>;
232			pinctrl-names = "default";
233			pinctrl-0 = <&pinctrl_i2c1>;
234			clocks = <&peri_clk 5>;
235			resets = <&peri_rst 5>;
236			clock-frequency = <100000>;
237		};
238
239		i2c2: i2c@58782000 {
240			compatible = "socionext,uniphier-fi2c";
241			status = "disabled";
242			reg = <0x58782000 0x80>;
243			#address-cells = <1>;
244			#size-cells = <0>;
245			interrupts = <0 43 4>;
246			pinctrl-names = "default";
247			pinctrl-0 = <&pinctrl_i2c2>;
248			clocks = <&peri_clk 6>;
249			resets = <&peri_rst 6>;
250			clock-frequency = <100000>;
251		};
252
253		i2c3: i2c@58783000 {
254			compatible = "socionext,uniphier-fi2c";
255			status = "disabled";
256			reg = <0x58783000 0x80>;
257			#address-cells = <1>;
258			#size-cells = <0>;
259			interrupts = <0 44 4>;
260			pinctrl-names = "default";
261			pinctrl-0 = <&pinctrl_i2c3>;
262			clocks = <&peri_clk 7>;
263			resets = <&peri_rst 7>;
264			clock-frequency = <100000>;
265		};
266
267		/* chip-internal connection for HDMI */
268		i2c6: i2c@58786000 {
269			compatible = "socionext,uniphier-fi2c";
270			reg = <0x58786000 0x80>;
271			#address-cells = <1>;
272			#size-cells = <0>;
273			interrupts = <0 26 4>;
274			clocks = <&peri_clk 10>;
275			resets = <&peri_rst 10>;
276			clock-frequency = <400000>;
277		};
278
279		system_bus: system-bus@58c00000 {
280			compatible = "socionext,uniphier-system-bus";
281			status = "disabled";
282			reg = <0x58c00000 0x400>;
283			#address-cells = <2>;
284			#size-cells = <1>;
285			pinctrl-names = "default";
286			pinctrl-0 = <&pinctrl_system_bus>;
287		};
288
289		smpctrl@59801000 {
290			compatible = "socionext,uniphier-smpctrl";
291			reg = <0x59801000 0x400>;
292		};
293
294		sdctrl@59810000 {
295			compatible = "socionext,uniphier-pxs3-sdctrl",
296				     "simple-mfd", "syscon";
297			reg = <0x59810000 0x400>;
298
299			sd_clk: clock {
300				compatible = "socionext,uniphier-pxs3-sd-clock";
301				#clock-cells = <1>;
302			};
303
304			sd_rst: reset {
305				compatible = "socionext,uniphier-pxs3-sd-reset";
306				#reset-cells = <1>;
307			};
308		};
309
310		perictrl@59820000 {
311			compatible = "socionext,uniphier-pxs3-perictrl",
312				     "simple-mfd", "syscon";
313			reg = <0x59820000 0x200>;
314
315			peri_clk: clock {
316				compatible = "socionext,uniphier-pxs3-peri-clock";
317				#clock-cells = <1>;
318			};
319
320			peri_rst: reset {
321				compatible = "socionext,uniphier-pxs3-peri-reset";
322				#reset-cells = <1>;
323			};
324		};
325
326		emmc: sdhc@5a000000 {
327			compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
328			reg = <0x5a000000 0x400>;
329			interrupts = <0 78 4>;
330			pinctrl-names = "default";
331			pinctrl-0 = <&pinctrl_emmc>;
332			clocks = <&sys_clk 4>;
333			resets = <&sys_rst 4>;
334			bus-width = <8>;
335			mmc-ddr-1_8v;
336			mmc-hs200-1_8v;
337			mmc-pwrseq = <&emmc_pwrseq>;
338			cdns,phy-input-delay-legacy = <4>;
339			cdns,phy-input-delay-mmc-highspeed = <2>;
340			cdns,phy-input-delay-mmc-ddr = <3>;
341			cdns,phy-dll-delay-sdclk = <21>;
342			cdns,phy-dll-delay-sdclk-hsmmc = <21>;
343		};
344
345		soc-glue@5f800000 {
346			compatible = "socionext,uniphier-pxs3-soc-glue",
347				     "simple-mfd", "syscon";
348			reg = <0x5f800000 0x2000>;
349
350			pinctrl: pinctrl {
351				compatible = "socionext,uniphier-pxs3-pinctrl";
352			};
353		};
354
355		soc-glue@5f900000 {
356			compatible = "socionext,uniphier-pxs3-soc-glue-debug",
357				     "simple-mfd";
358			#address-cells = <1>;
359			#size-cells = <1>;
360			ranges = <0 0x5f900000 0x2000>;
361
362			efuse@100 {
363				compatible = "socionext,uniphier-efuse";
364				reg = <0x100 0x28>;
365			};
366
367			efuse@200 {
368				compatible = "socionext,uniphier-efuse";
369				reg = <0x200 0x68>;
370			};
371		};
372
373		aidet: aidet@5fc20000 {
374			compatible = "socionext,uniphier-pxs3-aidet";
375			reg = <0x5fc20000 0x200>;
376			interrupt-controller;
377			#interrupt-cells = <2>;
378		};
379
380		gic: interrupt-controller@5fe00000 {
381			compatible = "arm,gic-v3";
382			reg = <0x5fe00000 0x10000>,	/* GICD */
383			      <0x5fe80000 0x80000>;	/* GICR */
384			interrupt-controller;
385			#interrupt-cells = <3>;
386			interrupts = <1 9 4>;
387		};
388
389		sysctrl@61840000 {
390			compatible = "socionext,uniphier-pxs3-sysctrl",
391				     "simple-mfd", "syscon";
392			reg = <0x61840000 0x10000>;
393
394			sys_clk: clock {
395				compatible = "socionext,uniphier-pxs3-clock";
396				#clock-cells = <1>;
397			};
398
399			sys_rst: reset {
400				compatible = "socionext,uniphier-pxs3-reset";
401				#reset-cells = <1>;
402			};
403
404			watchdog {
405				compatible = "socionext,uniphier-wdt";
406			};
407		};
408
409		nand: nand@68000000 {
410			compatible = "socionext,uniphier-denali-nand-v5b";
411			status = "disabled";
412			reg-names = "nand_data", "denali_reg";
413			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
414			interrupts = <0 65 4>;
415			pinctrl-names = "default";
416			pinctrl-0 = <&pinctrl_nand>;
417			clocks = <&sys_clk 2>;
418			resets = <&sys_rst 2>;
419		};
420	};
421};
422
423#include "uniphier-pinctrl.dtsi"
424