1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Device Tree Source for UniPhier PXs3 SoC 4// 5// Copyright (C) 2017 Socionext Inc. 6// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/gpio/uniphier-gpio.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/thermal/thermal.h> 12 13/ { 14 compatible = "socionext,uniphier-pxs3"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 interrupt-parent = <&gic>; 18 19 cpus { 20 #address-cells = <2>; 21 #size-cells = <0>; 22 23 cpu-map { 24 cluster0 { 25 core0 { 26 cpu = <&cpu0>; 27 }; 28 core1 { 29 cpu = <&cpu1>; 30 }; 31 core2 { 32 cpu = <&cpu2>; 33 }; 34 core3 { 35 cpu = <&cpu3>; 36 }; 37 }; 38 }; 39 40 cpu0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53"; 43 reg = <0 0x000>; 44 clocks = <&sys_clk 33>; 45 enable-method = "psci"; 46 operating-points-v2 = <&cluster0_opp>; 47 #cooling-cells = <2>; 48 }; 49 50 cpu1: cpu@1 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0 0x001>; 54 clocks = <&sys_clk 33>; 55 enable-method = "psci"; 56 operating-points-v2 = <&cluster0_opp>; 57 #cooling-cells = <2>; 58 }; 59 60 cpu2: cpu@2 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 reg = <0 0x002>; 64 clocks = <&sys_clk 33>; 65 enable-method = "psci"; 66 operating-points-v2 = <&cluster0_opp>; 67 #cooling-cells = <2>; 68 }; 69 70 cpu3: cpu@3 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 reg = <0 0x003>; 74 clocks = <&sys_clk 33>; 75 enable-method = "psci"; 76 operating-points-v2 = <&cluster0_opp>; 77 #cooling-cells = <2>; 78 }; 79 }; 80 81 cluster0_opp: opp-table { 82 compatible = "operating-points-v2"; 83 opp-shared; 84 85 opp-250000000 { 86 opp-hz = /bits/ 64 <250000000>; 87 clock-latency-ns = <300>; 88 }; 89 opp-325000000 { 90 opp-hz = /bits/ 64 <325000000>; 91 clock-latency-ns = <300>; 92 }; 93 opp-500000000 { 94 opp-hz = /bits/ 64 <500000000>; 95 clock-latency-ns = <300>; 96 }; 97 opp-650000000 { 98 opp-hz = /bits/ 64 <650000000>; 99 clock-latency-ns = <300>; 100 }; 101 opp-666667000 { 102 opp-hz = /bits/ 64 <666667000>; 103 clock-latency-ns = <300>; 104 }; 105 opp-866667000 { 106 opp-hz = /bits/ 64 <866667000>; 107 clock-latency-ns = <300>; 108 }; 109 opp-1000000000 { 110 opp-hz = /bits/ 64 <1000000000>; 111 clock-latency-ns = <300>; 112 }; 113 opp-1300000000 { 114 opp-hz = /bits/ 64 <1300000000>; 115 clock-latency-ns = <300>; 116 }; 117 }; 118 119 psci { 120 compatible = "arm,psci-1.0"; 121 method = "smc"; 122 }; 123 124 clocks { 125 refclk: ref { 126 compatible = "fixed-clock"; 127 #clock-cells = <0>; 128 clock-frequency = <25000000>; 129 }; 130 }; 131 132 emmc_pwrseq: emmc-pwrseq { 133 compatible = "mmc-pwrseq-emmc"; 134 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>; 135 }; 136 137 timer { 138 compatible = "arm,armv8-timer"; 139 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 143 }; 144 145 thermal-zones { 146 cpu-thermal { 147 polling-delay-passive = <250>; /* 250ms */ 148 polling-delay = <1000>; /* 1000ms */ 149 thermal-sensors = <&pvtctl>; 150 151 trips { 152 cpu_crit: cpu-crit { 153 temperature = <110000>; /* 110C */ 154 hysteresis = <2000>; 155 type = "critical"; 156 }; 157 cpu_alert: cpu-alert { 158 temperature = <100000>; /* 100C */ 159 hysteresis = <2000>; 160 type = "passive"; 161 }; 162 }; 163 164 cooling-maps { 165 map0 { 166 trip = <&cpu_alert>; 167 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 168 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 169 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 170 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 171 }; 172 }; 173 }; 174 }; 175 176 reserved-memory { 177 #address-cells = <2>; 178 #size-cells = <2>; 179 ranges; 180 181 secure-memory@81000000 { 182 reg = <0x0 0x81000000 0x0 0x01000000>; 183 no-map; 184 }; 185 }; 186 187 soc@0 { 188 compatible = "simple-bus"; 189 #address-cells = <1>; 190 #size-cells = <1>; 191 ranges = <0 0 0 0xffffffff>; 192 193 spi0: spi@54006000 { 194 compatible = "socionext,uniphier-scssi"; 195 status = "disabled"; 196 reg = <0x54006000 0x100>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 200 pinctrl-names = "default"; 201 pinctrl-0 = <&pinctrl_spi0>; 202 clocks = <&peri_clk 11>; 203 resets = <&peri_rst 11>; 204 }; 205 206 spi1: spi@54006100 { 207 compatible = "socionext,uniphier-scssi"; 208 status = "disabled"; 209 reg = <0x54006100 0x100>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 213 pinctrl-names = "default"; 214 pinctrl-0 = <&pinctrl_spi1>; 215 clocks = <&peri_clk 12>; 216 resets = <&peri_rst 12>; 217 }; 218 219 serial0: serial@54006800 { 220 compatible = "socionext,uniphier-uart"; 221 status = "disabled"; 222 reg = <0x54006800 0x40>; 223 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 224 pinctrl-names = "default"; 225 pinctrl-0 = <&pinctrl_uart0>; 226 clocks = <&peri_clk 0>; 227 resets = <&peri_rst 0>; 228 }; 229 230 serial1: serial@54006900 { 231 compatible = "socionext,uniphier-uart"; 232 status = "disabled"; 233 reg = <0x54006900 0x40>; 234 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 235 pinctrl-names = "default"; 236 pinctrl-0 = <&pinctrl_uart1>; 237 clocks = <&peri_clk 1>; 238 resets = <&peri_rst 1>; 239 }; 240 241 serial2: serial@54006a00 { 242 compatible = "socionext,uniphier-uart"; 243 status = "disabled"; 244 reg = <0x54006a00 0x40>; 245 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 246 pinctrl-names = "default"; 247 pinctrl-0 = <&pinctrl_uart2>; 248 clocks = <&peri_clk 2>; 249 resets = <&peri_rst 2>; 250 }; 251 252 serial3: serial@54006b00 { 253 compatible = "socionext,uniphier-uart"; 254 status = "disabled"; 255 reg = <0x54006b00 0x40>; 256 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 257 pinctrl-names = "default"; 258 pinctrl-0 = <&pinctrl_uart3>; 259 clocks = <&peri_clk 3>; 260 resets = <&peri_rst 3>; 261 }; 262 263 gpio: gpio@55000000 { 264 compatible = "socionext,uniphier-gpio"; 265 reg = <0x55000000 0x200>; 266 interrupt-parent = <&aidet>; 267 interrupt-controller; 268 #interrupt-cells = <2>; 269 gpio-controller; 270 #gpio-cells = <2>; 271 gpio-ranges = <&pinctrl 0 0 0>, 272 <&pinctrl 104 0 0>, 273 <&pinctrl 168 0 0>; 274 gpio-ranges-group-names = "gpio_range0", 275 "gpio_range1", 276 "gpio_range2"; 277 ngpios = <286>; 278 socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 279 <21 217 3>; 280 }; 281 282 i2c0: i2c@58780000 { 283 compatible = "socionext,uniphier-fi2c"; 284 status = "disabled"; 285 reg = <0x58780000 0x80>; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 289 pinctrl-names = "default"; 290 pinctrl-0 = <&pinctrl_i2c0>; 291 clocks = <&peri_clk 4>; 292 resets = <&peri_rst 4>; 293 clock-frequency = <100000>; 294 }; 295 296 i2c1: i2c@58781000 { 297 compatible = "socionext,uniphier-fi2c"; 298 status = "disabled"; 299 reg = <0x58781000 0x80>; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 303 pinctrl-names = "default"; 304 pinctrl-0 = <&pinctrl_i2c1>; 305 clocks = <&peri_clk 5>; 306 resets = <&peri_rst 5>; 307 clock-frequency = <100000>; 308 }; 309 310 i2c2: i2c@58782000 { 311 compatible = "socionext,uniphier-fi2c"; 312 status = "disabled"; 313 reg = <0x58782000 0x80>; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 317 pinctrl-names = "default"; 318 pinctrl-0 = <&pinctrl_i2c2>; 319 clocks = <&peri_clk 6>; 320 resets = <&peri_rst 6>; 321 clock-frequency = <100000>; 322 }; 323 324 i2c3: i2c@58783000 { 325 compatible = "socionext,uniphier-fi2c"; 326 status = "disabled"; 327 reg = <0x58783000 0x80>; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 331 pinctrl-names = "default"; 332 pinctrl-0 = <&pinctrl_i2c3>; 333 clocks = <&peri_clk 7>; 334 resets = <&peri_rst 7>; 335 clock-frequency = <100000>; 336 }; 337 338 /* chip-internal connection for HDMI */ 339 i2c6: i2c@58786000 { 340 compatible = "socionext,uniphier-fi2c"; 341 reg = <0x58786000 0x80>; 342 #address-cells = <1>; 343 #size-cells = <0>; 344 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&peri_clk 10>; 346 resets = <&peri_rst 10>; 347 clock-frequency = <400000>; 348 }; 349 350 system_bus: system-bus@58c00000 { 351 compatible = "socionext,uniphier-system-bus"; 352 status = "disabled"; 353 reg = <0x58c00000 0x400>; 354 #address-cells = <2>; 355 #size-cells = <1>; 356 pinctrl-names = "default"; 357 pinctrl-0 = <&pinctrl_system_bus>; 358 }; 359 360 smpctrl@59801000 { 361 compatible = "socionext,uniphier-smpctrl"; 362 reg = <0x59801000 0x400>; 363 }; 364 365 sdctrl@59810000 { 366 compatible = "socionext,uniphier-pxs3-sdctrl", 367 "simple-mfd", "syscon"; 368 reg = <0x59810000 0x400>; 369 370 sd_clk: clock { 371 compatible = "socionext,uniphier-pxs3-sd-clock"; 372 #clock-cells = <1>; 373 }; 374 375 sd_rst: reset { 376 compatible = "socionext,uniphier-pxs3-sd-reset"; 377 #reset-cells = <1>; 378 }; 379 }; 380 381 perictrl@59820000 { 382 compatible = "socionext,uniphier-pxs3-perictrl", 383 "simple-mfd", "syscon"; 384 reg = <0x59820000 0x200>; 385 386 peri_clk: clock { 387 compatible = "socionext,uniphier-pxs3-peri-clock"; 388 #clock-cells = <1>; 389 }; 390 391 peri_rst: reset { 392 compatible = "socionext,uniphier-pxs3-peri-reset"; 393 #reset-cells = <1>; 394 }; 395 }; 396 397 emmc: mmc@5a000000 { 398 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 399 reg = <0x5a000000 0x400>; 400 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 401 pinctrl-names = "default"; 402 pinctrl-0 = <&pinctrl_emmc>; 403 clocks = <&sys_clk 4>; 404 resets = <&sys_rst 4>; 405 bus-width = <8>; 406 mmc-ddr-1_8v; 407 mmc-hs200-1_8v; 408 mmc-pwrseq = <&emmc_pwrseq>; 409 cdns,phy-input-delay-legacy = <9>; 410 cdns,phy-input-delay-mmc-highspeed = <2>; 411 cdns,phy-input-delay-mmc-ddr = <3>; 412 cdns,phy-dll-delay-sdclk = <21>; 413 cdns,phy-dll-delay-sdclk-hsmmc = <21>; 414 }; 415 416 sd: mmc@5a400000 { 417 compatible = "socionext,uniphier-sd-v3.1.1"; 418 status = "disabled"; 419 reg = <0x5a400000 0x800>; 420 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 421 pinctrl-names = "default", "uhs"; 422 pinctrl-0 = <&pinctrl_sd>; 423 pinctrl-1 = <&pinctrl_sd_uhs>; 424 clocks = <&sd_clk 0>; 425 reset-names = "host"; 426 resets = <&sd_rst 0>; 427 bus-width = <4>; 428 cap-sd-highspeed; 429 sd-uhs-sdr12; 430 sd-uhs-sdr25; 431 sd-uhs-sdr50; 432 }; 433 434 soc_glue: soc-glue@5f800000 { 435 compatible = "socionext,uniphier-pxs3-soc-glue", 436 "simple-mfd", "syscon"; 437 reg = <0x5f800000 0x2000>; 438 439 pinctrl: pinctrl { 440 compatible = "socionext,uniphier-pxs3-pinctrl"; 441 }; 442 }; 443 444 soc-glue@5f900000 { 445 compatible = "socionext,uniphier-pxs3-soc-glue-debug", 446 "simple-mfd"; 447 #address-cells = <1>; 448 #size-cells = <1>; 449 ranges = <0 0x5f900000 0x2000>; 450 451 efuse@100 { 452 compatible = "socionext,uniphier-efuse"; 453 reg = <0x100 0x28>; 454 }; 455 456 efuse@200 { 457 compatible = "socionext,uniphier-efuse"; 458 reg = <0x200 0x68>; 459 #address-cells = <1>; 460 #size-cells = <1>; 461 462 /* USB cells */ 463 usb_rterm0: trim@54,4 { 464 reg = <0x54 1>; 465 bits = <4 2>; 466 }; 467 usb_rterm1: trim@55,4 { 468 reg = <0x55 1>; 469 bits = <4 2>; 470 }; 471 usb_rterm2: trim@58,4 { 472 reg = <0x58 1>; 473 bits = <4 2>; 474 }; 475 usb_rterm3: trim@59,4 { 476 reg = <0x59 1>; 477 bits = <4 2>; 478 }; 479 usb_sel_t0: trim@54,0 { 480 reg = <0x54 1>; 481 bits = <0 4>; 482 }; 483 usb_sel_t1: trim@55,0 { 484 reg = <0x55 1>; 485 bits = <0 4>; 486 }; 487 usb_sel_t2: trim@58,0 { 488 reg = <0x58 1>; 489 bits = <0 4>; 490 }; 491 usb_sel_t3: trim@59,0 { 492 reg = <0x59 1>; 493 bits = <0 4>; 494 }; 495 usb_hs_i0: trim@56,0 { 496 reg = <0x56 1>; 497 bits = <0 4>; 498 }; 499 usb_hs_i2: trim@5a,0 { 500 reg = <0x5a 1>; 501 bits = <0 4>; 502 }; 503 }; 504 }; 505 506 xdmac: dma-controller@5fc10000 { 507 compatible = "socionext,uniphier-xdmac"; 508 reg = <0x5fc10000 0x5300>; 509 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 510 dma-channels = <16>; 511 #dma-cells = <2>; 512 }; 513 514 aidet: interrupt-controller@5fc20000 { 515 compatible = "socionext,uniphier-pxs3-aidet"; 516 reg = <0x5fc20000 0x200>; 517 interrupt-controller; 518 #interrupt-cells = <2>; 519 }; 520 521 gic: interrupt-controller@5fe00000 { 522 compatible = "arm,gic-v3"; 523 reg = <0x5fe00000 0x10000>, /* GICD */ 524 <0x5fe80000 0x80000>; /* GICR */ 525 interrupt-controller; 526 #interrupt-cells = <3>; 527 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 528 }; 529 530 sysctrl@61840000 { 531 compatible = "socionext,uniphier-pxs3-sysctrl", 532 "simple-mfd", "syscon"; 533 reg = <0x61840000 0x10000>; 534 535 sys_clk: clock { 536 compatible = "socionext,uniphier-pxs3-clock"; 537 #clock-cells = <1>; 538 }; 539 540 sys_rst: reset { 541 compatible = "socionext,uniphier-pxs3-reset"; 542 #reset-cells = <1>; 543 }; 544 545 watchdog { 546 compatible = "socionext,uniphier-wdt"; 547 }; 548 549 pvtctl: thermal-sensor { 550 compatible = "socionext,uniphier-pxs3-thermal"; 551 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 552 #thermal-sensor-cells = <0>; 553 socionext,tmod-calibration = <0x0f22 0x68ee>; 554 }; 555 }; 556 557 eth0: ethernet@65000000 { 558 compatible = "socionext,uniphier-pxs3-ave4"; 559 status = "disabled"; 560 reg = <0x65000000 0x8500>; 561 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 562 pinctrl-names = "default"; 563 pinctrl-0 = <&pinctrl_ether_rgmii>; 564 clock-names = "ether"; 565 clocks = <&sys_clk 6>; 566 reset-names = "ether"; 567 resets = <&sys_rst 6>; 568 phy-mode = "rgmii-id"; 569 local-mac-address = [00 00 00 00 00 00]; 570 socionext,syscon-phy-mode = <&soc_glue 0>; 571 572 mdio0: mdio { 573 #address-cells = <1>; 574 #size-cells = <0>; 575 }; 576 }; 577 578 eth1: ethernet@65200000 { 579 compatible = "socionext,uniphier-pxs3-ave4"; 580 status = "disabled"; 581 reg = <0x65200000 0x8500>; 582 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 583 pinctrl-names = "default"; 584 pinctrl-0 = <&pinctrl_ether1_rgmii>; 585 clock-names = "ether"; 586 clocks = <&sys_clk 7>; 587 reset-names = "ether"; 588 resets = <&sys_rst 7>; 589 phy-mode = "rgmii-id"; 590 local-mac-address = [00 00 00 00 00 00]; 591 socionext,syscon-phy-mode = <&soc_glue 1>; 592 593 mdio1: mdio { 594 #address-cells = <1>; 595 #size-cells = <0>; 596 }; 597 }; 598 599 ahci0: sata@65600000 { 600 compatible = "socionext,uniphier-pxs3-ahci", 601 "generic-ahci"; 602 status = "disabled"; 603 reg = <0x65600000 0x10000>; 604 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 605 clocks = <&sys_clk 28>; 606 resets = <&sys_rst 28>, <&ahci0_rst 0>; 607 ports-implemented = <1>; 608 phys = <&ahci0_phy>; 609 }; 610 611 sata-controller@65700000 { 612 compatible = "socionext,uniphier-pxs3-ahci-glue", 613 "simple-mfd"; 614 #address-cells = <1>; 615 #size-cells = <1>; 616 ranges = <0 0x65700000 0x100>; 617 618 ahci0_rst: reset-controller@0 { 619 compatible = "socionext,uniphier-pxs3-ahci-reset"; 620 reg = <0x0 0x4>; 621 clock-names = "link"; 622 clocks = <&sys_clk 28>; 623 reset-names = "link"; 624 resets = <&sys_rst 28>; 625 #reset-cells = <1>; 626 }; 627 628 ahci0_phy: sata-phy@10 { 629 compatible = "socionext,uniphier-pxs3-ahci-phy"; 630 reg = <0x10 0x10>; 631 clock-names = "link", "phy"; 632 clocks = <&sys_clk 28>, <&sys_clk 30>; 633 reset-names = "link", "phy"; 634 resets = <&sys_rst 28>, <&sys_rst 30>; 635 #phy-cells = <0>; 636 }; 637 }; 638 639 ahci1: sata@65800000 { 640 compatible = "socionext,uniphier-pxs3-ahci", 641 "generic-ahci"; 642 status = "disabled"; 643 reg = <0x65800000 0x10000>; 644 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 645 clocks = <&sys_clk 29>; 646 resets = <&sys_rst 29>, <&ahci1_rst 0>; 647 ports-implemented = <1>; 648 phys = <&ahci1_phy>; 649 }; 650 651 sata-controller@65900000 { 652 compatible = "socionext,uniphier-pxs3-ahci-glue", 653 "simple-mfd"; 654 #address-cells = <1>; 655 #size-cells = <1>; 656 ranges = <0 0x65900000 0x100>; 657 658 ahci1_rst: reset-controller@0 { 659 compatible = "socionext,uniphier-pxs3-ahci-reset"; 660 reg = <0x0 0x4>; 661 clock-names = "link"; 662 clocks = <&sys_clk 29>; 663 reset-names = "link"; 664 resets = <&sys_rst 29>; 665 #reset-cells = <1>; 666 }; 667 668 ahci1_phy: sata-phy@10 { 669 compatible = "socionext,uniphier-pxs3-ahci-phy"; 670 reg = <0x10 0x10>; 671 clock-names = "link", "phy"; 672 clocks = <&sys_clk 29>, <&sys_clk 30>; 673 reset-names = "link", "phy"; 674 resets = <&sys_rst 29>, <&sys_rst 30>; 675 #phy-cells = <0>; 676 }; 677 }; 678 679 usb0: usb@65a00000 { 680 compatible = "socionext,uniphier-dwc3", "snps,dwc3"; 681 status = "disabled"; 682 reg = <0x65a00000 0xcd00>; 683 interrupt-names = "dwc_usb3"; 684 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 685 pinctrl-names = "default"; 686 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; 687 clock-names = "ref", "bus_early", "suspend"; 688 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; 689 resets = <&usb0_rst 15>; 690 phys = <&usb0_hsphy0>, <&usb0_hsphy1>, 691 <&usb0_ssphy0>, <&usb0_ssphy1>; 692 dr_mode = "host"; 693 }; 694 695 usb-controller@65b00000 { 696 compatible = "socionext,uniphier-pxs3-dwc3-glue", 697 "simple-mfd"; 698 #address-cells = <1>; 699 #size-cells = <1>; 700 ranges = <0 0x65b00000 0x400>; 701 702 usb0_rst: reset@0 { 703 compatible = "socionext,uniphier-pxs3-usb3-reset"; 704 reg = <0x0 0x4>; 705 #reset-cells = <1>; 706 clock-names = "link"; 707 clocks = <&sys_clk 12>; 708 reset-names = "link"; 709 resets = <&sys_rst 12>; 710 }; 711 712 usb0_vbus0: regulator@100 { 713 compatible = "socionext,uniphier-pxs3-usb3-regulator"; 714 reg = <0x100 0x10>; 715 clock-names = "link"; 716 clocks = <&sys_clk 12>; 717 reset-names = "link"; 718 resets = <&sys_rst 12>; 719 }; 720 721 usb0_vbus1: regulator@110 { 722 compatible = "socionext,uniphier-pxs3-usb3-regulator"; 723 reg = <0x110 0x10>; 724 clock-names = "link"; 725 clocks = <&sys_clk 12>; 726 reset-names = "link"; 727 resets = <&sys_rst 12>; 728 }; 729 730 usb0_hsphy0: hs-phy@200 { 731 compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 732 reg = <0x200 0x10>; 733 #phy-cells = <0>; 734 clock-names = "link", "phy"; 735 clocks = <&sys_clk 12>, <&sys_clk 16>; 736 reset-names = "link", "phy"; 737 resets = <&sys_rst 12>, <&sys_rst 16>; 738 vbus-supply = <&usb0_vbus0>; 739 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 740 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, 741 <&usb_hs_i0>; 742 }; 743 744 usb0_hsphy1: hs-phy@210 { 745 compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 746 reg = <0x210 0x10>; 747 #phy-cells = <0>; 748 clock-names = "link", "phy"; 749 clocks = <&sys_clk 12>, <&sys_clk 16>; 750 reset-names = "link", "phy"; 751 resets = <&sys_rst 12>, <&sys_rst 16>; 752 vbus-supply = <&usb0_vbus1>; 753 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 754 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>, 755 <&usb_hs_i0>; 756 }; 757 758 usb0_ssphy0: ss-phy@300 { 759 compatible = "socionext,uniphier-pxs3-usb3-ssphy"; 760 reg = <0x300 0x10>; 761 #phy-cells = <0>; 762 clock-names = "link", "phy"; 763 clocks = <&sys_clk 12>, <&sys_clk 17>; 764 reset-names = "link", "phy"; 765 resets = <&sys_rst 12>, <&sys_rst 17>; 766 vbus-supply = <&usb0_vbus0>; 767 }; 768 769 usb0_ssphy1: ss-phy@310 { 770 compatible = "socionext,uniphier-pxs3-usb3-ssphy"; 771 reg = <0x310 0x10>; 772 #phy-cells = <0>; 773 clock-names = "link", "phy"; 774 clocks = <&sys_clk 12>, <&sys_clk 18>; 775 reset-names = "link", "phy"; 776 resets = <&sys_rst 12>, <&sys_rst 18>; 777 vbus-supply = <&usb0_vbus1>; 778 }; 779 }; 780 781 usb1: usb@65c00000 { 782 compatible = "socionext,uniphier-dwc3", "snps,dwc3"; 783 status = "disabled"; 784 reg = <0x65c00000 0xcd00>; 785 interrupt-names = "dwc_usb3"; 786 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 787 pinctrl-names = "default"; 788 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; 789 clock-names = "ref", "bus_early", "suspend"; 790 clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>; 791 resets = <&usb1_rst 15>; 792 phys = <&usb1_hsphy0>, <&usb1_hsphy1>, 793 <&usb1_ssphy0>; 794 dr_mode = "host"; 795 }; 796 797 usb-controller@65d00000 { 798 compatible = "socionext,uniphier-pxs3-dwc3-glue", 799 "simple-mfd"; 800 #address-cells = <1>; 801 #size-cells = <1>; 802 ranges = <0 0x65d00000 0x400>; 803 804 usb1_rst: reset@0 { 805 compatible = "socionext,uniphier-pxs3-usb3-reset"; 806 reg = <0x0 0x4>; 807 #reset-cells = <1>; 808 clock-names = "link"; 809 clocks = <&sys_clk 13>; 810 reset-names = "link"; 811 resets = <&sys_rst 13>; 812 }; 813 814 usb1_vbus0: regulator@100 { 815 compatible = "socionext,uniphier-pxs3-usb3-regulator"; 816 reg = <0x100 0x10>; 817 clock-names = "link"; 818 clocks = <&sys_clk 13>; 819 reset-names = "link"; 820 resets = <&sys_rst 13>; 821 }; 822 823 usb1_vbus1: regulator@110 { 824 compatible = "socionext,uniphier-pxs3-usb3-regulator"; 825 reg = <0x110 0x10>; 826 clock-names = "link"; 827 clocks = <&sys_clk 13>; 828 reset-names = "link"; 829 resets = <&sys_rst 13>; 830 }; 831 832 usb1_hsphy0: hs-phy@200 { 833 compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 834 reg = <0x200 0x10>; 835 #phy-cells = <0>; 836 clock-names = "link", "phy", "phy-ext"; 837 clocks = <&sys_clk 13>, <&sys_clk 20>, 838 <&sys_clk 14>; 839 reset-names = "link", "phy"; 840 resets = <&sys_rst 13>, <&sys_rst 20>; 841 vbus-supply = <&usb1_vbus0>; 842 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 843 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>, 844 <&usb_hs_i2>; 845 }; 846 847 usb1_hsphy1: hs-phy@210 { 848 compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 849 reg = <0x210 0x10>; 850 #phy-cells = <0>; 851 clock-names = "link", "phy", "phy-ext"; 852 clocks = <&sys_clk 13>, <&sys_clk 20>, 853 <&sys_clk 14>; 854 reset-names = "link", "phy"; 855 resets = <&sys_rst 13>, <&sys_rst 20>; 856 vbus-supply = <&usb1_vbus1>; 857 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 858 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>, 859 <&usb_hs_i2>; 860 }; 861 862 usb1_ssphy0: ss-phy@300 { 863 compatible = "socionext,uniphier-pxs3-usb3-ssphy"; 864 reg = <0x300 0x10>; 865 #phy-cells = <0>; 866 clock-names = "link", "phy", "phy-ext"; 867 clocks = <&sys_clk 13>, <&sys_clk 21>, 868 <&sys_clk 14>; 869 reset-names = "link", "phy"; 870 resets = <&sys_rst 13>, <&sys_rst 21>; 871 vbus-supply = <&usb1_vbus0>; 872 }; 873 }; 874 875 pcie: pcie@66000000 { 876 compatible = "socionext,uniphier-pcie", "snps,dw-pcie"; 877 status = "disabled"; 878 reg-names = "dbi", "link", "config"; 879 reg = <0x66000000 0x1000>, <0x66010000 0x10000>, 880 <0x2fff0000 0x10000>; 881 #address-cells = <3>; 882 #size-cells = <2>; 883 clocks = <&sys_clk 24>; 884 resets = <&sys_rst 24>; 885 num-lanes = <1>; 886 num-viewport = <1>; 887 bus-range = <0x0 0xff>; 888 device_type = "pci"; 889 ranges = 890 /* downstream I/O */ 891 <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>, 892 /* non-prefetchable memory */ 893 <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>; 894 #interrupt-cells = <1>; 895 interrupt-names = "dma", "msi"; 896 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 898 interrupt-map-mask = <0 0 0 7>; 899 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */ 900 <0 0 0 2 &pcie_intc 1>, /* INTB */ 901 <0 0 0 3 &pcie_intc 2>, /* INTC */ 902 <0 0 0 4 &pcie_intc 3>; /* INTD */ 903 phy-names = "pcie-phy"; 904 phys = <&pcie_phy>; 905 906 pcie_intc: legacy-interrupt-controller { 907 interrupt-controller; 908 #interrupt-cells = <1>; 909 interrupt-parent = <&gic>; 910 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 911 }; 912 }; 913 914 pcie_phy: phy@66038000 { 915 compatible = "socionext,uniphier-pxs3-pcie-phy"; 916 reg = <0x66038000 0x4000>; 917 #phy-cells = <0>; 918 clock-names = "link"; 919 clocks = <&sys_clk 24>; 920 reset-names = "link"; 921 resets = <&sys_rst 24>; 922 socionext,syscon = <&soc_glue>; 923 }; 924 925 nand: nand-controller@68000000 { 926 compatible = "socionext,uniphier-denali-nand-v5b"; 927 status = "disabled"; 928 reg-names = "nand_data", "denali_reg"; 929 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 930 #address-cells = <1>; 931 #size-cells = <0>; 932 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 933 pinctrl-names = "default"; 934 pinctrl-0 = <&pinctrl_nand>; 935 clock-names = "nand", "nand_x", "ecc"; 936 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; 937 reset-names = "nand", "reg"; 938 resets = <&sys_rst 2>, <&sys_rst 2>; 939 }; 940 }; 941}; 942 943#include "uniphier-pinctrl.dtsi" 944