1/*
2 * Device Tree Source for UniPhier LD20 SoC
3 *
4 * Copyright (C) 2015-2016 Socionext Inc.
5 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 *
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 */
9
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/thermal/thermal.h>
12
13/memreserve/ 0x80000000 0x02000000;
14
15/ {
16	compatible = "socionext,uniphier-ld20";
17	#address-cells = <2>;
18	#size-cells = <2>;
19	interrupt-parent = <&gic>;
20
21	cpus {
22		#address-cells = <2>;
23		#size-cells = <0>;
24
25		cpu-map {
26			cluster0 {
27				core0 {
28					cpu = <&cpu0>;
29				};
30				core1 {
31					cpu = <&cpu1>;
32				};
33			};
34
35			cluster1 {
36				core0 {
37					cpu = <&cpu2>;
38				};
39				core1 {
40					cpu = <&cpu3>;
41				};
42			};
43		};
44
45		cpu0: cpu@0 {
46			device_type = "cpu";
47			compatible = "arm,cortex-a72", "arm,armv8";
48			reg = <0 0x000>;
49			clocks = <&sys_clk 32>;
50			enable-method = "psci";
51			operating-points-v2 = <&cluster0_opp>;
52			#cooling-cells = <2>;
53		};
54
55		cpu1: cpu@1 {
56			device_type = "cpu";
57			compatible = "arm,cortex-a72", "arm,armv8";
58			reg = <0 0x001>;
59			clocks = <&sys_clk 32>;
60			enable-method = "psci";
61			operating-points-v2 = <&cluster0_opp>;
62		};
63
64		cpu2: cpu@100 {
65			device_type = "cpu";
66			compatible = "arm,cortex-a53", "arm,armv8";
67			reg = <0 0x100>;
68			clocks = <&sys_clk 33>;
69			enable-method = "psci";
70			operating-points-v2 = <&cluster1_opp>;
71			#cooling-cells = <2>;
72		};
73
74		cpu3: cpu@101 {
75			device_type = "cpu";
76			compatible = "arm,cortex-a53", "arm,armv8";
77			reg = <0 0x101>;
78			clocks = <&sys_clk 33>;
79			enable-method = "psci";
80			operating-points-v2 = <&cluster1_opp>;
81		};
82	};
83
84	cluster0_opp: opp-table0 {
85		compatible = "operating-points-v2";
86		opp-shared;
87
88		opp-250000000 {
89			opp-hz = /bits/ 64 <250000000>;
90			clock-latency-ns = <300>;
91		};
92		opp-275000000 {
93			opp-hz = /bits/ 64 <275000000>;
94			clock-latency-ns = <300>;
95		};
96		opp-500000000 {
97			opp-hz = /bits/ 64 <500000000>;
98			clock-latency-ns = <300>;
99		};
100		opp-550000000 {
101			opp-hz = /bits/ 64 <550000000>;
102			clock-latency-ns = <300>;
103		};
104		opp-666667000 {
105			opp-hz = /bits/ 64 <666667000>;
106			clock-latency-ns = <300>;
107		};
108		opp-733334000 {
109			opp-hz = /bits/ 64 <733334000>;
110			clock-latency-ns = <300>;
111		};
112		opp-1000000000 {
113			opp-hz = /bits/ 64 <1000000000>;
114			clock-latency-ns = <300>;
115		};
116		opp-1100000000 {
117			opp-hz = /bits/ 64 <1100000000>;
118			clock-latency-ns = <300>;
119		};
120	};
121
122	cluster1_opp: opp-table1 {
123		compatible = "operating-points-v2";
124		opp-shared;
125
126		opp-250000000 {
127			opp-hz = /bits/ 64 <250000000>;
128			clock-latency-ns = <300>;
129		};
130		opp-275000000 {
131			opp-hz = /bits/ 64 <275000000>;
132			clock-latency-ns = <300>;
133		};
134		opp-500000000 {
135			opp-hz = /bits/ 64 <500000000>;
136			clock-latency-ns = <300>;
137		};
138		opp-550000000 {
139			opp-hz = /bits/ 64 <550000000>;
140			clock-latency-ns = <300>;
141		};
142		opp-666667000 {
143			opp-hz = /bits/ 64 <666667000>;
144			clock-latency-ns = <300>;
145		};
146		opp-733334000 {
147			opp-hz = /bits/ 64 <733334000>;
148			clock-latency-ns = <300>;
149		};
150		opp-1000000000 {
151			opp-hz = /bits/ 64 <1000000000>;
152			clock-latency-ns = <300>;
153		};
154		opp-1100000000 {
155			opp-hz = /bits/ 64 <1100000000>;
156			clock-latency-ns = <300>;
157		};
158	};
159
160	psci {
161		compatible = "arm,psci-1.0";
162		method = "smc";
163	};
164
165	clocks {
166		refclk: ref {
167			compatible = "fixed-clock";
168			#clock-cells = <0>;
169			clock-frequency = <25000000>;
170		};
171	};
172
173	emmc_pwrseq: emmc-pwrseq {
174		compatible = "mmc-pwrseq-emmc";
175		reset-gpios = <&gpio 26 GPIO_ACTIVE_LOW>;
176	};
177
178	timer {
179		compatible = "arm,armv8-timer";
180		interrupts = <1 13 4>,
181			     <1 14 4>,
182			     <1 11 4>,
183			     <1 10 4>;
184	};
185
186	thermal-zones {
187		cpu-thermal {
188			polling-delay-passive = <250>;	/* 250ms */
189			polling-delay = <1000>;		/* 1000ms */
190			thermal-sensors = <&pvtctl>;
191
192			trips {
193				cpu_crit: cpu-crit {
194					temperature = <110000>;	/* 110C */
195					hysteresis = <2000>;
196					type = "critical";
197				};
198				cpu_alert: cpu-alert {
199					temperature = <100000>;	/* 100C */
200					hysteresis = <2000>;
201					type = "passive";
202				};
203			};
204
205			cooling-maps {
206				map0 {
207					trip = <&cpu_alert>;
208					cooling-device = <&cpu0
209					    THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
210				};
211				map1 {
212					trip = <&cpu_alert>;
213					cooling-device = <&cpu2
214					    THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
215				};
216			};
217		};
218	};
219
220	soc@0 {
221		compatible = "simple-bus";
222		#address-cells = <1>;
223		#size-cells = <1>;
224		ranges = <0 0 0 0xffffffff>;
225
226		serial0: serial@54006800 {
227			compatible = "socionext,uniphier-uart";
228			status = "disabled";
229			reg = <0x54006800 0x40>;
230			interrupts = <0 33 4>;
231			pinctrl-names = "default";
232			pinctrl-0 = <&pinctrl_uart0>;
233			clocks = <&peri_clk 0>;
234			resets = <&peri_rst 0>;
235		};
236
237		serial1: serial@54006900 {
238			compatible = "socionext,uniphier-uart";
239			status = "disabled";
240			reg = <0x54006900 0x40>;
241			interrupts = <0 35 4>;
242			pinctrl-names = "default";
243			pinctrl-0 = <&pinctrl_uart1>;
244			clocks = <&peri_clk 1>;
245			resets = <&peri_rst 1>;
246		};
247
248		serial2: serial@54006a00 {
249			compatible = "socionext,uniphier-uart";
250			status = "disabled";
251			reg = <0x54006a00 0x40>;
252			interrupts = <0 37 4>;
253			pinctrl-names = "default";
254			pinctrl-0 = <&pinctrl_uart2>;
255			clocks = <&peri_clk 2>;
256			resets = <&peri_rst 2>;
257		};
258
259		serial3: serial@54006b00 {
260			compatible = "socionext,uniphier-uart";
261			status = "disabled";
262			reg = <0x54006b00 0x40>;
263			interrupts = <0 177 4>;
264			pinctrl-names = "default";
265			pinctrl-0 = <&pinctrl_uart3>;
266			clocks = <&peri_clk 3>;
267			resets = <&peri_rst 3>;
268		};
269
270		gpio: gpio@55000000 {
271			compatible = "socionext,uniphier-gpio";
272			reg = <0x55000000 0x200>;
273			interrupt-parent = <&aidet>;
274			interrupt-controller;
275			#interrupt-cells = <2>;
276			gpio-controller;
277			#gpio-cells = <2>;
278			gpio-ranges = <&pinctrl 0 0 0>,
279				      <&pinctrl 96 0 0>,
280				      <&pinctrl 160 0 0>;
281			gpio-ranges-group-names = "gpio_range0",
282						  "gpio_range1",
283						  "gpio_range2";
284			ngpios = <205>;
285			socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
286						     <21 217 3>;
287		};
288
289		adamv@57920000 {
290			compatible = "socionext,uniphier-ld20-adamv",
291				     "simple-mfd", "syscon";
292			reg = <0x57920000 0x1000>;
293
294			adamv_rst: reset {
295				compatible = "socionext,uniphier-ld20-adamv-reset";
296				#reset-cells = <1>;
297			};
298		};
299
300		i2c0: i2c@58780000 {
301			compatible = "socionext,uniphier-fi2c";
302			status = "disabled";
303			reg = <0x58780000 0x80>;
304			#address-cells = <1>;
305			#size-cells = <0>;
306			interrupts = <0 41 4>;
307			pinctrl-names = "default";
308			pinctrl-0 = <&pinctrl_i2c0>;
309			clocks = <&peri_clk 4>;
310			resets = <&peri_rst 4>;
311			clock-frequency = <100000>;
312		};
313
314		i2c1: i2c@58781000 {
315			compatible = "socionext,uniphier-fi2c";
316			status = "disabled";
317			reg = <0x58781000 0x80>;
318			#address-cells = <1>;
319			#size-cells = <0>;
320			interrupts = <0 42 4>;
321			pinctrl-names = "default";
322			pinctrl-0 = <&pinctrl_i2c1>;
323			clocks = <&peri_clk 5>;
324			resets = <&peri_rst 5>;
325			clock-frequency = <100000>;
326		};
327
328		i2c2: i2c@58782000 {
329			compatible = "socionext,uniphier-fi2c";
330			reg = <0x58782000 0x80>;
331			#address-cells = <1>;
332			#size-cells = <0>;
333			interrupts = <0 43 4>;
334			clocks = <&peri_clk 6>;
335			resets = <&peri_rst 6>;
336			clock-frequency = <400000>;
337		};
338
339		i2c3: i2c@58783000 {
340			compatible = "socionext,uniphier-fi2c";
341			status = "disabled";
342			reg = <0x58783000 0x80>;
343			#address-cells = <1>;
344			#size-cells = <0>;
345			interrupts = <0 44 4>;
346			pinctrl-names = "default";
347			pinctrl-0 = <&pinctrl_i2c3>;
348			clocks = <&peri_clk 7>;
349			resets = <&peri_rst 7>;
350			clock-frequency = <100000>;
351		};
352
353		i2c4: i2c@58784000 {
354			compatible = "socionext,uniphier-fi2c";
355			status = "disabled";
356			reg = <0x58784000 0x80>;
357			#address-cells = <1>;
358			#size-cells = <0>;
359			interrupts = <0 45 4>;
360			pinctrl-names = "default";
361			pinctrl-0 = <&pinctrl_i2c4>;
362			clocks = <&peri_clk 8>;
363			resets = <&peri_rst 8>;
364			clock-frequency = <100000>;
365		};
366
367		i2c5: i2c@58785000 {
368			compatible = "socionext,uniphier-fi2c";
369			reg = <0x58785000 0x80>;
370			#address-cells = <1>;
371			#size-cells = <0>;
372			interrupts = <0 25 4>;
373			clocks = <&peri_clk 9>;
374			resets = <&peri_rst 9>;
375			clock-frequency = <400000>;
376		};
377
378		system_bus: system-bus@58c00000 {
379			compatible = "socionext,uniphier-system-bus";
380			status = "disabled";
381			reg = <0x58c00000 0x400>;
382			#address-cells = <2>;
383			#size-cells = <1>;
384			pinctrl-names = "default";
385			pinctrl-0 = <&pinctrl_system_bus>;
386		};
387
388		smpctrl@59801000 {
389			compatible = "socionext,uniphier-smpctrl";
390			reg = <0x59801000 0x400>;
391		};
392
393		sdctrl@59810000 {
394			compatible = "socionext,uniphier-ld20-sdctrl",
395				     "simple-mfd", "syscon";
396			reg = <0x59810000 0x400>;
397
398			sd_clk: clock {
399				compatible = "socionext,uniphier-ld20-sd-clock";
400				#clock-cells = <1>;
401			};
402
403			sd_rst: reset {
404				compatible = "socionext,uniphier-ld20-sd-reset";
405				#reset-cells = <1>;
406			};
407		};
408
409		perictrl@59820000 {
410			compatible = "socionext,uniphier-ld20-perictrl",
411				     "simple-mfd", "syscon";
412			reg = <0x59820000 0x200>;
413
414			peri_clk: clock {
415				compatible = "socionext,uniphier-ld20-peri-clock";
416				#clock-cells = <1>;
417			};
418
419			peri_rst: reset {
420				compatible = "socionext,uniphier-ld20-peri-reset";
421				#reset-cells = <1>;
422			};
423		};
424
425		emmc: sdhc@5a000000 {
426			compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
427			reg = <0x5a000000 0x400>;
428			interrupts = <0 78 4>;
429			pinctrl-names = "default";
430			pinctrl-0 = <&pinctrl_emmc>;
431			clocks = <&sys_clk 4>;
432			resets = <&sys_rst 4>;
433			bus-width = <8>;
434			mmc-ddr-1_8v;
435			mmc-hs200-1_8v;
436			mmc-pwrseq = <&emmc_pwrseq>;
437			cdns,phy-input-delay-legacy = <4>;
438			cdns,phy-input-delay-mmc-highspeed = <2>;
439			cdns,phy-input-delay-mmc-ddr = <3>;
440			cdns,phy-dll-delay-sdclk = <21>;
441			cdns,phy-dll-delay-sdclk-hsmmc = <21>;
442		};
443
444		soc-glue@5f800000 {
445			compatible = "socionext,uniphier-ld20-soc-glue",
446				     "simple-mfd", "syscon";
447			reg = <0x5f800000 0x2000>;
448
449			pinctrl: pinctrl {
450				compatible = "socionext,uniphier-ld20-pinctrl";
451			};
452		};
453
454		soc-glue@5f900000 {
455			compatible = "socionext,uniphier-ld20-soc-glue-debug",
456				     "simple-mfd";
457			#address-cells = <1>;
458			#size-cells = <1>;
459			ranges = <0 0x5f900000 0x2000>;
460
461			efuse@100 {
462				compatible = "socionext,uniphier-efuse";
463				reg = <0x100 0x28>;
464			};
465
466			efuse@200 {
467				compatible = "socionext,uniphier-efuse";
468				reg = <0x200 0x68>;
469			};
470		};
471
472		aidet: aidet@5fc20000 {
473			compatible = "socionext,uniphier-ld20-aidet";
474			reg = <0x5fc20000 0x200>;
475			interrupt-controller;
476			#interrupt-cells = <2>;
477		};
478
479		gic: interrupt-controller@5fe00000 {
480			compatible = "arm,gic-v3";
481			reg = <0x5fe00000 0x10000>,	/* GICD */
482			      <0x5fe80000 0x80000>;	/* GICR */
483			interrupt-controller;
484			#interrupt-cells = <3>;
485			interrupts = <1 9 4>;
486		};
487
488		sysctrl@61840000 {
489			compatible = "socionext,uniphier-ld20-sysctrl",
490				     "simple-mfd", "syscon";
491			reg = <0x61840000 0x10000>;
492
493			sys_clk: clock {
494				compatible = "socionext,uniphier-ld20-clock";
495				#clock-cells = <1>;
496			};
497
498			sys_rst: reset {
499				compatible = "socionext,uniphier-ld20-reset";
500				#reset-cells = <1>;
501			};
502
503			watchdog {
504				compatible = "socionext,uniphier-wdt";
505			};
506
507			pvtctl: pvtctl {
508				compatible = "socionext,uniphier-ld20-thermal";
509				interrupts = <0 3 4>;
510				#thermal-sensor-cells = <0>;
511				socionext,tmod-calibration = <0x0f22 0x68ee>;
512			};
513		};
514
515		nand: nand@68000000 {
516			compatible = "socionext,uniphier-denali-nand-v5b";
517			status = "disabled";
518			reg-names = "nand_data", "denali_reg";
519			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
520			interrupts = <0 65 4>;
521			pinctrl-names = "default";
522			pinctrl-0 = <&pinctrl_nand>;
523			clocks = <&sys_clk 2>;
524			resets = <&sys_rst 2>;
525		};
526	};
527};
528
529#include "uniphier-pinctrl.dtsi"
530