1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rk3588-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/power/rk3588-power.h> 10#include <dt-bindings/reset/rockchip,rk3588-cru.h> 11 12/ { 13 compatible = "rockchip,rk3588"; 14 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu-map { 24 cluster0 { 25 core0 { 26 cpu = <&cpu_l0>; 27 }; 28 core1 { 29 cpu = <&cpu_l1>; 30 }; 31 core2 { 32 cpu = <&cpu_l2>; 33 }; 34 core3 { 35 cpu = <&cpu_l3>; 36 }; 37 }; 38 cluster1 { 39 core0 { 40 cpu = <&cpu_b0>; 41 }; 42 core1 { 43 cpu = <&cpu_b1>; 44 }; 45 }; 46 cluster2 { 47 core0 { 48 cpu = <&cpu_b2>; 49 }; 50 core1 { 51 cpu = <&cpu_b3>; 52 }; 53 }; 54 }; 55 56 cpu_l0: cpu@0 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a55"; 59 reg = <0x0>; 60 enable-method = "psci"; 61 capacity-dmips-mhz = <530>; 62 clocks = <&scmi_clk SCMI_CLK_CPUL>; 63 assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; 64 assigned-clock-rates = <816000000>; 65 cpu-idle-states = <&CPU_SLEEP>; 66 i-cache-size = <32768>; 67 i-cache-line-size = <64>; 68 i-cache-sets = <128>; 69 d-cache-size = <32768>; 70 d-cache-line-size = <64>; 71 d-cache-sets = <128>; 72 next-level-cache = <&l2_cache_l0>; 73 dynamic-power-coefficient = <228>; 74 #cooling-cells = <2>; 75 }; 76 77 cpu_l1: cpu@100 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a55"; 80 reg = <0x100>; 81 enable-method = "psci"; 82 capacity-dmips-mhz = <530>; 83 clocks = <&scmi_clk SCMI_CLK_CPUL>; 84 cpu-idle-states = <&CPU_SLEEP>; 85 i-cache-size = <32768>; 86 i-cache-line-size = <64>; 87 i-cache-sets = <128>; 88 d-cache-size = <32768>; 89 d-cache-line-size = <64>; 90 d-cache-sets = <128>; 91 next-level-cache = <&l2_cache_l1>; 92 dynamic-power-coefficient = <228>; 93 #cooling-cells = <2>; 94 }; 95 96 cpu_l2: cpu@200 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a55"; 99 reg = <0x200>; 100 enable-method = "psci"; 101 capacity-dmips-mhz = <530>; 102 clocks = <&scmi_clk SCMI_CLK_CPUL>; 103 cpu-idle-states = <&CPU_SLEEP>; 104 i-cache-size = <32768>; 105 i-cache-line-size = <64>; 106 i-cache-sets = <128>; 107 d-cache-size = <32768>; 108 d-cache-line-size = <64>; 109 d-cache-sets = <128>; 110 next-level-cache = <&l2_cache_l2>; 111 dynamic-power-coefficient = <228>; 112 #cooling-cells = <2>; 113 }; 114 115 cpu_l3: cpu@300 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a55"; 118 reg = <0x300>; 119 enable-method = "psci"; 120 capacity-dmips-mhz = <530>; 121 clocks = <&scmi_clk SCMI_CLK_CPUL>; 122 cpu-idle-states = <&CPU_SLEEP>; 123 i-cache-size = <32768>; 124 i-cache-line-size = <64>; 125 i-cache-sets = <128>; 126 d-cache-size = <32768>; 127 d-cache-line-size = <64>; 128 d-cache-sets = <128>; 129 next-level-cache = <&l2_cache_l3>; 130 dynamic-power-coefficient = <228>; 131 #cooling-cells = <2>; 132 }; 133 134 cpu_b0: cpu@400 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a76"; 137 reg = <0x400>; 138 enable-method = "psci"; 139 capacity-dmips-mhz = <1024>; 140 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 141 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; 142 assigned-clock-rates = <816000000>; 143 cpu-idle-states = <&CPU_SLEEP>; 144 i-cache-size = <65536>; 145 i-cache-line-size = <64>; 146 i-cache-sets = <256>; 147 d-cache-size = <65536>; 148 d-cache-line-size = <64>; 149 d-cache-sets = <256>; 150 next-level-cache = <&l2_cache_b0>; 151 dynamic-power-coefficient = <416>; 152 #cooling-cells = <2>; 153 }; 154 155 cpu_b1: cpu@500 { 156 device_type = "cpu"; 157 compatible = "arm,cortex-a76"; 158 reg = <0x500>; 159 enable-method = "psci"; 160 capacity-dmips-mhz = <1024>; 161 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 162 cpu-idle-states = <&CPU_SLEEP>; 163 i-cache-size = <65536>; 164 i-cache-line-size = <64>; 165 i-cache-sets = <256>; 166 d-cache-size = <65536>; 167 d-cache-line-size = <64>; 168 d-cache-sets = <256>; 169 next-level-cache = <&l2_cache_b1>; 170 dynamic-power-coefficient = <416>; 171 #cooling-cells = <2>; 172 }; 173 174 cpu_b2: cpu@600 { 175 device_type = "cpu"; 176 compatible = "arm,cortex-a76"; 177 reg = <0x600>; 178 enable-method = "psci"; 179 capacity-dmips-mhz = <1024>; 180 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 181 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; 182 assigned-clock-rates = <816000000>; 183 cpu-idle-states = <&CPU_SLEEP>; 184 i-cache-size = <65536>; 185 i-cache-line-size = <64>; 186 i-cache-sets = <256>; 187 d-cache-size = <65536>; 188 d-cache-line-size = <64>; 189 d-cache-sets = <256>; 190 next-level-cache = <&l2_cache_b2>; 191 dynamic-power-coefficient = <416>; 192 #cooling-cells = <2>; 193 }; 194 195 cpu_b3: cpu@700 { 196 device_type = "cpu"; 197 compatible = "arm,cortex-a76"; 198 reg = <0x700>; 199 enable-method = "psci"; 200 capacity-dmips-mhz = <1024>; 201 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 202 cpu-idle-states = <&CPU_SLEEP>; 203 i-cache-size = <65536>; 204 i-cache-line-size = <64>; 205 i-cache-sets = <256>; 206 d-cache-size = <65536>; 207 d-cache-line-size = <64>; 208 d-cache-sets = <256>; 209 next-level-cache = <&l2_cache_b3>; 210 dynamic-power-coefficient = <416>; 211 #cooling-cells = <2>; 212 }; 213 214 idle-states { 215 entry-method = "psci"; 216 CPU_SLEEP: cpu-sleep { 217 compatible = "arm,idle-state"; 218 local-timer-stop; 219 arm,psci-suspend-param = <0x0010000>; 220 entry-latency-us = <100>; 221 exit-latency-us = <120>; 222 min-residency-us = <1000>; 223 }; 224 }; 225 226 l2_cache_l0: l2-cache-l0 { 227 compatible = "cache"; 228 cache-size = <131072>; 229 cache-line-size = <64>; 230 cache-sets = <512>; 231 cache-level = <2>; 232 next-level-cache = <&l3_cache>; 233 }; 234 235 l2_cache_l1: l2-cache-l1 { 236 compatible = "cache"; 237 cache-size = <131072>; 238 cache-line-size = <64>; 239 cache-sets = <512>; 240 cache-level = <2>; 241 next-level-cache = <&l3_cache>; 242 }; 243 244 l2_cache_l2: l2-cache-l2 { 245 compatible = "cache"; 246 cache-size = <131072>; 247 cache-line-size = <64>; 248 cache-sets = <512>; 249 cache-level = <2>; 250 next-level-cache = <&l3_cache>; 251 }; 252 253 l2_cache_l3: l2-cache-l3 { 254 compatible = "cache"; 255 cache-size = <131072>; 256 cache-line-size = <64>; 257 cache-sets = <512>; 258 cache-level = <2>; 259 next-level-cache = <&l3_cache>; 260 }; 261 262 l2_cache_b0: l2-cache-b0 { 263 compatible = "cache"; 264 cache-size = <524288>; 265 cache-line-size = <64>; 266 cache-sets = <1024>; 267 cache-level = <2>; 268 next-level-cache = <&l3_cache>; 269 }; 270 271 l2_cache_b1: l2-cache-b1 { 272 compatible = "cache"; 273 cache-size = <524288>; 274 cache-line-size = <64>; 275 cache-sets = <1024>; 276 cache-level = <2>; 277 next-level-cache = <&l3_cache>; 278 }; 279 280 l2_cache_b2: l2-cache-b2 { 281 compatible = "cache"; 282 cache-size = <524288>; 283 cache-line-size = <64>; 284 cache-sets = <1024>; 285 cache-level = <2>; 286 next-level-cache = <&l3_cache>; 287 }; 288 289 l2_cache_b3: l2-cache-b3 { 290 compatible = "cache"; 291 cache-size = <524288>; 292 cache-line-size = <64>; 293 cache-sets = <1024>; 294 cache-level = <2>; 295 next-level-cache = <&l3_cache>; 296 }; 297 298 l3_cache: l3-cache { 299 compatible = "cache"; 300 cache-size = <3145728>; 301 cache-line-size = <64>; 302 cache-sets = <4096>; 303 cache-level = <3>; 304 }; 305 }; 306 307 firmware { 308 optee: optee { 309 compatible = "linaro,optee-tz"; 310 method = "smc"; 311 }; 312 313 scmi: scmi { 314 compatible = "arm,scmi-smc"; 315 arm,smc-id = <0x82000010>; 316 shmem = <&scmi_shmem>; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 320 scmi_clk: protocol@14 { 321 reg = <0x14>; 322 #clock-cells = <1>; 323 }; 324 325 scmi_reset: protocol@16 { 326 reg = <0x16>; 327 #reset-cells = <1>; 328 }; 329 }; 330 }; 331 332 pmu-a55 { 333 compatible = "arm,cortex-a55-pmu"; 334 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>; 335 }; 336 337 pmu-a76 { 338 compatible = "arm,cortex-a76-pmu"; 339 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>; 340 }; 341 342 psci { 343 compatible = "arm,psci-1.0"; 344 method = "smc"; 345 }; 346 347 spll: clock-0 { 348 compatible = "fixed-clock"; 349 clock-frequency = <702000000>; 350 clock-output-names = "spll"; 351 #clock-cells = <0>; 352 }; 353 354 timer { 355 compatible = "arm,armv8-timer"; 356 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 357 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 358 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 359 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>, 360 <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 361 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 362 }; 363 364 xin24m: clock-1 { 365 compatible = "fixed-clock"; 366 clock-frequency = <24000000>; 367 clock-output-names = "xin24m"; 368 #clock-cells = <0>; 369 }; 370 371 xin32k: clock-2 { 372 compatible = "fixed-clock"; 373 clock-frequency = <32768>; 374 clock-output-names = "xin32k"; 375 #clock-cells = <0>; 376 }; 377 378 pmu_sram: sram@10f000 { 379 compatible = "mmio-sram"; 380 reg = <0x0 0x0010f000 0x0 0x100>; 381 ranges = <0 0x0 0x0010f000 0x100>; 382 #address-cells = <1>; 383 #size-cells = <1>; 384 385 scmi_shmem: sram@0 { 386 compatible = "arm,scmi-shmem"; 387 reg = <0x0 0x100>; 388 }; 389 }; 390 391 sys_grf: syscon@fd58c000 { 392 compatible = "rockchip,rk3588-sys-grf", "syscon"; 393 reg = <0x0 0xfd58c000 0x0 0x1000>; 394 }; 395 396 php_grf: syscon@fd5b0000 { 397 compatible = "rockchip,rk3588-php-grf", "syscon"; 398 reg = <0x0 0xfd5b0000 0x0 0x1000>; 399 }; 400 401 ioc: syscon@fd5f0000 { 402 compatible = "rockchip,rk3588-ioc", "syscon"; 403 reg = <0x0 0xfd5f0000 0x0 0x10000>; 404 }; 405 406 system_sram1: sram@fd600000 { 407 compatible = "mmio-sram"; 408 reg = <0x0 0xfd600000 0x0 0x100000>; 409 ranges = <0x0 0x0 0xfd600000 0x100000>; 410 #address-cells = <1>; 411 #size-cells = <1>; 412 }; 413 414 cru: clock-controller@fd7c0000 { 415 compatible = "rockchip,rk3588-cru"; 416 reg = <0x0 0xfd7c0000 0x0 0x5c000>; 417 assigned-clocks = 418 <&cru PLL_PPLL>, <&cru PLL_AUPLL>, 419 <&cru PLL_NPLL>, <&cru PLL_GPLL>, 420 <&cru ACLK_CENTER_ROOT>, 421 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, 422 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, 423 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, 424 <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, 425 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, 426 <&cru CLK_GPU>; 427 assigned-clock-rates = 428 <1100000000>, <786432000>, 429 <850000000>, <1188000000>, 430 <702000000>, 431 <400000000>, <500000000>, 432 <800000000>, <100000000>, 433 <400000000>, <100000000>, 434 <200000000>, <500000000>, 435 <375000000>, <150000000>, 436 <200000000>; 437 rockchip,grf = <&php_grf>; 438 #clock-cells = <1>; 439 #reset-cells = <1>; 440 }; 441 442 i2c0: i2c@fd880000 { 443 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 444 reg = <0x0 0xfd880000 0x0 0x1000>; 445 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>; 446 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 447 clock-names = "i2c", "pclk"; 448 pinctrl-0 = <&i2c0m0_xfer>; 449 pinctrl-names = "default"; 450 #address-cells = <1>; 451 #size-cells = <0>; 452 status = "disabled"; 453 }; 454 455 uart0: serial@fd890000 { 456 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 457 reg = <0x0 0xfd890000 0x0 0x100>; 458 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; 459 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 460 clock-names = "baudclk", "apb_pclk"; 461 dmas = <&dmac0 6>, <&dmac0 7>; 462 dma-names = "tx", "rx"; 463 pinctrl-0 = <&uart0m1_xfer>; 464 pinctrl-names = "default"; 465 reg-shift = <2>; 466 reg-io-width = <4>; 467 status = "disabled"; 468 }; 469 470 pwm0: pwm@fd8b0000 { 471 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 472 reg = <0x0 0xfd8b0000 0x0 0x10>; 473 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 474 clock-names = "pwm", "pclk"; 475 pinctrl-0 = <&pwm0m0_pins>; 476 pinctrl-names = "default"; 477 #pwm-cells = <3>; 478 status = "disabled"; 479 }; 480 481 pwm1: pwm@fd8b0010 { 482 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 483 reg = <0x0 0xfd8b0010 0x0 0x10>; 484 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 485 clock-names = "pwm", "pclk"; 486 pinctrl-0 = <&pwm1m0_pins>; 487 pinctrl-names = "default"; 488 #pwm-cells = <3>; 489 status = "disabled"; 490 }; 491 492 pwm2: pwm@fd8b0020 { 493 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 494 reg = <0x0 0xfd8b0020 0x0 0x10>; 495 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 496 clock-names = "pwm", "pclk"; 497 pinctrl-0 = <&pwm2m0_pins>; 498 pinctrl-names = "default"; 499 #pwm-cells = <3>; 500 status = "disabled"; 501 }; 502 503 pwm3: pwm@fd8b0030 { 504 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 505 reg = <0x0 0xfd8b0030 0x0 0x10>; 506 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 507 clock-names = "pwm", "pclk"; 508 pinctrl-0 = <&pwm3m0_pins>; 509 pinctrl-names = "default"; 510 #pwm-cells = <3>; 511 status = "disabled"; 512 }; 513 514 pmu: power-management@fd8d8000 { 515 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; 516 reg = <0x0 0xfd8d8000 0x0 0x400>; 517 518 power: power-controller { 519 compatible = "rockchip,rk3588-power-controller"; 520 #address-cells = <1>; 521 #power-domain-cells = <1>; 522 #size-cells = <0>; 523 status = "okay"; 524 525 /* These power domains are grouped by VD_NPU */ 526 power-domain@RK3588_PD_NPU { 527 reg = <RK3588_PD_NPU>; 528 #power-domain-cells = <0>; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 532 power-domain@RK3588_PD_NPUTOP { 533 reg = <RK3588_PD_NPUTOP>; 534 clocks = <&cru HCLK_NPU_ROOT>, 535 <&cru PCLK_NPU_ROOT>, 536 <&cru CLK_NPU_DSU0>, 537 <&cru HCLK_NPU_CM0_ROOT>; 538 pm_qos = <&qos_npu0_mwr>, 539 <&qos_npu0_mro>, 540 <&qos_mcu_npu>; 541 #power-domain-cells = <0>; 542 #address-cells = <1>; 543 #size-cells = <0>; 544 545 power-domain@RK3588_PD_NPU1 { 546 reg = <RK3588_PD_NPU1>; 547 clocks = <&cru HCLK_NPU_ROOT>, 548 <&cru PCLK_NPU_ROOT>, 549 <&cru CLK_NPU_DSU0>; 550 pm_qos = <&qos_npu1>; 551 #power-domain-cells = <0>; 552 }; 553 power-domain@RK3588_PD_NPU2 { 554 reg = <RK3588_PD_NPU2>; 555 clocks = <&cru HCLK_NPU_ROOT>, 556 <&cru PCLK_NPU_ROOT>, 557 <&cru CLK_NPU_DSU0>; 558 pm_qos = <&qos_npu2>; 559 #power-domain-cells = <0>; 560 }; 561 }; 562 }; 563 /* These power domains are grouped by VD_GPU */ 564 power-domain@RK3588_PD_GPU { 565 reg = <RK3588_PD_GPU>; 566 clocks = <&cru CLK_GPU>, 567 <&cru CLK_GPU_COREGROUP>, 568 <&cru CLK_GPU_STACKS>; 569 pm_qos = <&qos_gpu_m0>, 570 <&qos_gpu_m1>, 571 <&qos_gpu_m2>, 572 <&qos_gpu_m3>; 573 #power-domain-cells = <0>; 574 }; 575 /* These power domains are grouped by VD_VCODEC */ 576 power-domain@RK3588_PD_VCODEC { 577 reg = <RK3588_PD_VCODEC>; 578 #address-cells = <1>; 579 #size-cells = <0>; 580 #power-domain-cells = <0>; 581 582 power-domain@RK3588_PD_RKVDEC0 { 583 reg = <RK3588_PD_RKVDEC0>; 584 clocks = <&cru HCLK_RKVDEC0>, 585 <&cru HCLK_VDPU_ROOT>, 586 <&cru ACLK_VDPU_ROOT>, 587 <&cru ACLK_RKVDEC0>, 588 <&cru ACLK_RKVDEC_CCU>; 589 pm_qos = <&qos_rkvdec0>; 590 #power-domain-cells = <0>; 591 }; 592 power-domain@RK3588_PD_RKVDEC1 { 593 reg = <RK3588_PD_RKVDEC1>; 594 clocks = <&cru HCLK_RKVDEC1>, 595 <&cru HCLK_VDPU_ROOT>, 596 <&cru ACLK_VDPU_ROOT>, 597 <&cru ACLK_RKVDEC1>; 598 pm_qos = <&qos_rkvdec1>; 599 #power-domain-cells = <0>; 600 }; 601 power-domain@RK3588_PD_VENC0 { 602 reg = <RK3588_PD_VENC0>; 603 clocks = <&cru HCLK_RKVENC0>, 604 <&cru ACLK_RKVENC0>; 605 pm_qos = <&qos_rkvenc0_m0ro>, 606 <&qos_rkvenc0_m1ro>, 607 <&qos_rkvenc0_m2wo>; 608 #address-cells = <1>; 609 #size-cells = <0>; 610 #power-domain-cells = <0>; 611 612 power-domain@RK3588_PD_VENC1 { 613 reg = <RK3588_PD_VENC1>; 614 clocks = <&cru HCLK_RKVENC1>, 615 <&cru HCLK_RKVENC0>, 616 <&cru ACLK_RKVENC0>, 617 <&cru ACLK_RKVENC1>; 618 pm_qos = <&qos_rkvenc1_m0ro>, 619 <&qos_rkvenc1_m1ro>, 620 <&qos_rkvenc1_m2wo>; 621 #power-domain-cells = <0>; 622 }; 623 }; 624 }; 625 /* These power domains are grouped by VD_LOGIC */ 626 power-domain@RK3588_PD_VDPU { 627 reg = <RK3588_PD_VDPU>; 628 clocks = <&cru HCLK_VDPU_ROOT>, 629 <&cru ACLK_VDPU_LOW_ROOT>, 630 <&cru ACLK_VDPU_ROOT>, 631 <&cru ACLK_JPEG_DECODER_ROOT>, 632 <&cru ACLK_IEP2P0>, 633 <&cru HCLK_IEP2P0>, 634 <&cru ACLK_JPEG_ENCODER0>, 635 <&cru HCLK_JPEG_ENCODER0>, 636 <&cru ACLK_JPEG_ENCODER1>, 637 <&cru HCLK_JPEG_ENCODER1>, 638 <&cru ACLK_JPEG_ENCODER2>, 639 <&cru HCLK_JPEG_ENCODER2>, 640 <&cru ACLK_JPEG_ENCODER3>, 641 <&cru HCLK_JPEG_ENCODER3>, 642 <&cru ACLK_JPEG_DECODER>, 643 <&cru HCLK_JPEG_DECODER>, 644 <&cru ACLK_RGA2>, 645 <&cru HCLK_RGA2>; 646 pm_qos = <&qos_iep>, 647 <&qos_jpeg_dec>, 648 <&qos_jpeg_enc0>, 649 <&qos_jpeg_enc1>, 650 <&qos_jpeg_enc2>, 651 <&qos_jpeg_enc3>, 652 <&qos_rga2_mro>, 653 <&qos_rga2_mwo>; 654 #address-cells = <1>; 655 #size-cells = <0>; 656 #power-domain-cells = <0>; 657 658 659 power-domain@RK3588_PD_AV1 { 660 reg = <RK3588_PD_AV1>; 661 clocks = <&cru PCLK_AV1>, 662 <&cru ACLK_AV1>, 663 <&cru HCLK_VDPU_ROOT>; 664 pm_qos = <&qos_av1>; 665 #power-domain-cells = <0>; 666 }; 667 power-domain@RK3588_PD_RKVDEC0 { 668 reg = <RK3588_PD_RKVDEC0>; 669 clocks = <&cru HCLK_RKVDEC0>, 670 <&cru HCLK_VDPU_ROOT>, 671 <&cru ACLK_VDPU_ROOT>, 672 <&cru ACLK_RKVDEC0>; 673 pm_qos = <&qos_rkvdec0>; 674 #power-domain-cells = <0>; 675 }; 676 power-domain@RK3588_PD_RKVDEC1 { 677 reg = <RK3588_PD_RKVDEC1>; 678 clocks = <&cru HCLK_RKVDEC1>, 679 <&cru HCLK_VDPU_ROOT>, 680 <&cru ACLK_VDPU_ROOT>; 681 pm_qos = <&qos_rkvdec1>; 682 #power-domain-cells = <0>; 683 }; 684 power-domain@RK3588_PD_RGA30 { 685 reg = <RK3588_PD_RGA30>; 686 clocks = <&cru ACLK_RGA3_0>, 687 <&cru HCLK_RGA3_0>; 688 pm_qos = <&qos_rga3_0>; 689 #power-domain-cells = <0>; 690 }; 691 }; 692 power-domain@RK3588_PD_VOP { 693 reg = <RK3588_PD_VOP>; 694 clocks = <&cru PCLK_VOP_ROOT>, 695 <&cru HCLK_VOP_ROOT>, 696 <&cru ACLK_VOP>; 697 pm_qos = <&qos_vop_m0>, 698 <&qos_vop_m1>; 699 #address-cells = <1>; 700 #size-cells = <0>; 701 #power-domain-cells = <0>; 702 703 power-domain@RK3588_PD_VO0 { 704 reg = <RK3588_PD_VO0>; 705 clocks = <&cru PCLK_VO0_ROOT>, 706 <&cru PCLK_VO0_S_ROOT>, 707 <&cru HCLK_VO0_S_ROOT>, 708 <&cru ACLK_VO0_ROOT>, 709 <&cru HCLK_HDCP0>, 710 <&cru ACLK_HDCP0>, 711 <&cru HCLK_VOP_ROOT>; 712 pm_qos = <&qos_hdcp0>; 713 #power-domain-cells = <0>; 714 }; 715 }; 716 power-domain@RK3588_PD_VO1 { 717 reg = <RK3588_PD_VO1>; 718 clocks = <&cru PCLK_VO1_ROOT>, 719 <&cru PCLK_VO1_S_ROOT>, 720 <&cru HCLK_VO1_S_ROOT>, 721 <&cru HCLK_HDCP1>, 722 <&cru ACLK_HDCP1>, 723 <&cru ACLK_HDMIRX_ROOT>, 724 <&cru HCLK_VO1USB_TOP_ROOT>; 725 pm_qos = <&qos_hdcp1>, 726 <&qos_hdmirx>; 727 #power-domain-cells = <0>; 728 }; 729 power-domain@RK3588_PD_VI { 730 reg = <RK3588_PD_VI>; 731 clocks = <&cru HCLK_VI_ROOT>, 732 <&cru PCLK_VI_ROOT>, 733 <&cru HCLK_ISP0>, 734 <&cru ACLK_ISP0>, 735 <&cru HCLK_VICAP>, 736 <&cru ACLK_VICAP>; 737 pm_qos = <&qos_isp0_mro>, 738 <&qos_isp0_mwo>, 739 <&qos_vicap_m0>, 740 <&qos_vicap_m1>; 741 #address-cells = <1>; 742 #size-cells = <0>; 743 #power-domain-cells = <0>; 744 745 power-domain@RK3588_PD_ISP1 { 746 reg = <RK3588_PD_ISP1>; 747 clocks = <&cru HCLK_ISP1>, 748 <&cru ACLK_ISP1>, 749 <&cru HCLK_VI_ROOT>, 750 <&cru PCLK_VI_ROOT>; 751 pm_qos = <&qos_isp1_mwo>, 752 <&qos_isp1_mro>; 753 #power-domain-cells = <0>; 754 }; 755 power-domain@RK3588_PD_FEC { 756 reg = <RK3588_PD_FEC>; 757 clocks = <&cru HCLK_FISHEYE0>, 758 <&cru ACLK_FISHEYE0>, 759 <&cru HCLK_FISHEYE1>, 760 <&cru ACLK_FISHEYE1>, 761 <&cru PCLK_VI_ROOT>; 762 pm_qos = <&qos_fisheye0>, 763 <&qos_fisheye1>; 764 #power-domain-cells = <0>; 765 }; 766 }; 767 power-domain@RK3588_PD_RGA31 { 768 reg = <RK3588_PD_RGA31>; 769 clocks = <&cru HCLK_RGA3_1>, 770 <&cru ACLK_RGA3_1>; 771 pm_qos = <&qos_rga3_1>; 772 #power-domain-cells = <0>; 773 }; 774 power-domain@RK3588_PD_USB { 775 reg = <RK3588_PD_USB>; 776 clocks = <&cru PCLK_PHP_ROOT>, 777 <&cru ACLK_USB_ROOT>, 778 <&cru HCLK_USB_ROOT>, 779 <&cru HCLK_HOST0>, 780 <&cru HCLK_HOST_ARB0>, 781 <&cru HCLK_HOST1>, 782 <&cru HCLK_HOST_ARB1>; 783 pm_qos = <&qos_usb3_0>, 784 <&qos_usb3_1>, 785 <&qos_usb2host_0>, 786 <&qos_usb2host_1>; 787 #power-domain-cells = <0>; 788 }; 789 power-domain@RK3588_PD_GMAC { 790 reg = <RK3588_PD_GMAC>; 791 clocks = <&cru PCLK_PHP_ROOT>, 792 <&cru ACLK_PCIE_ROOT>, 793 <&cru ACLK_PHP_ROOT>; 794 #power-domain-cells = <0>; 795 }; 796 power-domain@RK3588_PD_PCIE { 797 reg = <RK3588_PD_PCIE>; 798 clocks = <&cru PCLK_PHP_ROOT>, 799 <&cru ACLK_PCIE_ROOT>, 800 <&cru ACLK_PHP_ROOT>; 801 #power-domain-cells = <0>; 802 }; 803 power-domain@RK3588_PD_SDIO { 804 reg = <RK3588_PD_SDIO>; 805 clocks = <&cru HCLK_SDIO>, 806 <&cru HCLK_NVM_ROOT>; 807 pm_qos = <&qos_sdio>; 808 #power-domain-cells = <0>; 809 }; 810 power-domain@RK3588_PD_AUDIO { 811 reg = <RK3588_PD_AUDIO>; 812 clocks = <&cru HCLK_AUDIO_ROOT>, 813 <&cru PCLK_AUDIO_ROOT>; 814 #power-domain-cells = <0>; 815 }; 816 power-domain@RK3588_PD_SDMMC { 817 reg = <RK3588_PD_SDMMC>; 818 pm_qos = <&qos_sdmmc>; 819 #power-domain-cells = <0>; 820 }; 821 }; 822 }; 823 824 i2s4_8ch: i2s@fddc0000 { 825 compatible = "rockchip,rk3588-i2s-tdm"; 826 reg = <0x0 0xfddc0000 0x0 0x1000>; 827 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>; 828 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; 829 clock-names = "mclk_tx", "mclk_rx", "hclk"; 830 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; 831 assigned-clock-parents = <&cru PLL_AUPLL>; 832 dmas = <&dmac2 0>; 833 dma-names = "tx"; 834 power-domains = <&power RK3588_PD_VO0>; 835 resets = <&cru SRST_M_I2S4_8CH_TX>; 836 reset-names = "tx-m"; 837 #sound-dai-cells = <0>; 838 status = "disabled"; 839 }; 840 841 i2s5_8ch: i2s@fddf0000 { 842 compatible = "rockchip,rk3588-i2s-tdm"; 843 reg = <0x0 0xfddf0000 0x0 0x1000>; 844 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>; 845 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; 846 clock-names = "mclk_tx", "mclk_rx", "hclk"; 847 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; 848 assigned-clock-parents = <&cru PLL_AUPLL>; 849 dmas = <&dmac2 2>; 850 dma-names = "tx"; 851 power-domains = <&power RK3588_PD_VO1>; 852 resets = <&cru SRST_M_I2S5_8CH_TX>; 853 reset-names = "tx-m"; 854 #sound-dai-cells = <0>; 855 status = "disabled"; 856 }; 857 858 i2s9_8ch: i2s@fddfc000 { 859 compatible = "rockchip,rk3588-i2s-tdm"; 860 reg = <0x0 0xfddfc000 0x0 0x1000>; 861 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>; 862 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; 863 clock-names = "mclk_tx", "mclk_rx", "hclk"; 864 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; 865 assigned-clock-parents = <&cru PLL_AUPLL>; 866 dmas = <&dmac2 23>; 867 dma-names = "rx"; 868 power-domains = <&power RK3588_PD_VO1>; 869 resets = <&cru SRST_M_I2S9_8CH_RX>; 870 reset-names = "rx-m"; 871 #sound-dai-cells = <0>; 872 status = "disabled"; 873 }; 874 875 qos_gpu_m0: qos@fdf35000 { 876 compatible = "rockchip,rk3588-qos", "syscon"; 877 reg = <0x0 0xfdf35000 0x0 0x20>; 878 }; 879 880 qos_gpu_m1: qos@fdf35200 { 881 compatible = "rockchip,rk3588-qos", "syscon"; 882 reg = <0x0 0xfdf35200 0x0 0x20>; 883 }; 884 885 qos_gpu_m2: qos@fdf35400 { 886 compatible = "rockchip,rk3588-qos", "syscon"; 887 reg = <0x0 0xfdf35400 0x0 0x20>; 888 }; 889 890 qos_gpu_m3: qos@fdf35600 { 891 compatible = "rockchip,rk3588-qos", "syscon"; 892 reg = <0x0 0xfdf35600 0x0 0x20>; 893 }; 894 895 qos_rga3_1: qos@fdf36000 { 896 compatible = "rockchip,rk3588-qos", "syscon"; 897 reg = <0x0 0xfdf36000 0x0 0x20>; 898 }; 899 900 qos_sdio: qos@fdf39000 { 901 compatible = "rockchip,rk3588-qos", "syscon"; 902 reg = <0x0 0xfdf39000 0x0 0x20>; 903 }; 904 905 qos_sdmmc: qos@fdf3d800 { 906 compatible = "rockchip,rk3588-qos", "syscon"; 907 reg = <0x0 0xfdf3d800 0x0 0x20>; 908 }; 909 910 qos_usb3_1: qos@fdf3e000 { 911 compatible = "rockchip,rk3588-qos", "syscon"; 912 reg = <0x0 0xfdf3e000 0x0 0x20>; 913 }; 914 915 qos_usb3_0: qos@fdf3e200 { 916 compatible = "rockchip,rk3588-qos", "syscon"; 917 reg = <0x0 0xfdf3e200 0x0 0x20>; 918 }; 919 920 qos_usb2host_0: qos@fdf3e400 { 921 compatible = "rockchip,rk3588-qos", "syscon"; 922 reg = <0x0 0xfdf3e400 0x0 0x20>; 923 }; 924 925 qos_usb2host_1: qos@fdf3e600 { 926 compatible = "rockchip,rk3588-qos", "syscon"; 927 reg = <0x0 0xfdf3e600 0x0 0x20>; 928 }; 929 930 qos_fisheye0: qos@fdf40000 { 931 compatible = "rockchip,rk3588-qos", "syscon"; 932 reg = <0x0 0xfdf40000 0x0 0x20>; 933 }; 934 935 qos_fisheye1: qos@fdf40200 { 936 compatible = "rockchip,rk3588-qos", "syscon"; 937 reg = <0x0 0xfdf40200 0x0 0x20>; 938 }; 939 940 qos_isp0_mro: qos@fdf40400 { 941 compatible = "rockchip,rk3588-qos", "syscon"; 942 reg = <0x0 0xfdf40400 0x0 0x20>; 943 }; 944 945 qos_isp0_mwo: qos@fdf40500 { 946 compatible = "rockchip,rk3588-qos", "syscon"; 947 reg = <0x0 0xfdf40500 0x0 0x20>; 948 }; 949 950 qos_vicap_m0: qos@fdf40600 { 951 compatible = "rockchip,rk3588-qos", "syscon"; 952 reg = <0x0 0xfdf40600 0x0 0x20>; 953 }; 954 955 qos_vicap_m1: qos@fdf40800 { 956 compatible = "rockchip,rk3588-qos", "syscon"; 957 reg = <0x0 0xfdf40800 0x0 0x20>; 958 }; 959 960 qos_isp1_mwo: qos@fdf41000 { 961 compatible = "rockchip,rk3588-qos", "syscon"; 962 reg = <0x0 0xfdf41000 0x0 0x20>; 963 }; 964 965 qos_isp1_mro: qos@fdf41100 { 966 compatible = "rockchip,rk3588-qos", "syscon"; 967 reg = <0x0 0xfdf41100 0x0 0x20>; 968 }; 969 970 qos_rkvenc0_m0ro: qos@fdf60000 { 971 compatible = "rockchip,rk3588-qos", "syscon"; 972 reg = <0x0 0xfdf60000 0x0 0x20>; 973 }; 974 975 qos_rkvenc0_m1ro: qos@fdf60200 { 976 compatible = "rockchip,rk3588-qos", "syscon"; 977 reg = <0x0 0xfdf60200 0x0 0x20>; 978 }; 979 980 qos_rkvenc0_m2wo: qos@fdf60400 { 981 compatible = "rockchip,rk3588-qos", "syscon"; 982 reg = <0x0 0xfdf60400 0x0 0x20>; 983 }; 984 985 qos_rkvenc1_m0ro: qos@fdf61000 { 986 compatible = "rockchip,rk3588-qos", "syscon"; 987 reg = <0x0 0xfdf61000 0x0 0x20>; 988 }; 989 990 qos_rkvenc1_m1ro: qos@fdf61200 { 991 compatible = "rockchip,rk3588-qos", "syscon"; 992 reg = <0x0 0xfdf61200 0x0 0x20>; 993 }; 994 995 qos_rkvenc1_m2wo: qos@fdf61400 { 996 compatible = "rockchip,rk3588-qos", "syscon"; 997 reg = <0x0 0xfdf61400 0x0 0x20>; 998 }; 999 1000 qos_rkvdec0: qos@fdf62000 { 1001 compatible = "rockchip,rk3588-qos", "syscon"; 1002 reg = <0x0 0xfdf62000 0x0 0x20>; 1003 }; 1004 1005 qos_rkvdec1: qos@fdf63000 { 1006 compatible = "rockchip,rk3588-qos", "syscon"; 1007 reg = <0x0 0xfdf63000 0x0 0x20>; 1008 }; 1009 1010 qos_av1: qos@fdf64000 { 1011 compatible = "rockchip,rk3588-qos", "syscon"; 1012 reg = <0x0 0xfdf64000 0x0 0x20>; 1013 }; 1014 1015 qos_iep: qos@fdf66000 { 1016 compatible = "rockchip,rk3588-qos", "syscon"; 1017 reg = <0x0 0xfdf66000 0x0 0x20>; 1018 }; 1019 1020 qos_jpeg_dec: qos@fdf66200 { 1021 compatible = "rockchip,rk3588-qos", "syscon"; 1022 reg = <0x0 0xfdf66200 0x0 0x20>; 1023 }; 1024 1025 qos_jpeg_enc0: qos@fdf66400 { 1026 compatible = "rockchip,rk3588-qos", "syscon"; 1027 reg = <0x0 0xfdf66400 0x0 0x20>; 1028 }; 1029 1030 qos_jpeg_enc1: qos@fdf66600 { 1031 compatible = "rockchip,rk3588-qos", "syscon"; 1032 reg = <0x0 0xfdf66600 0x0 0x20>; 1033 }; 1034 1035 qos_jpeg_enc2: qos@fdf66800 { 1036 compatible = "rockchip,rk3588-qos", "syscon"; 1037 reg = <0x0 0xfdf66800 0x0 0x20>; 1038 }; 1039 1040 qos_jpeg_enc3: qos@fdf66a00 { 1041 compatible = "rockchip,rk3588-qos", "syscon"; 1042 reg = <0x0 0xfdf66a00 0x0 0x20>; 1043 }; 1044 1045 qos_rga2_mro: qos@fdf66c00 { 1046 compatible = "rockchip,rk3588-qos", "syscon"; 1047 reg = <0x0 0xfdf66c00 0x0 0x20>; 1048 }; 1049 1050 qos_rga2_mwo: qos@fdf66e00 { 1051 compatible = "rockchip,rk3588-qos", "syscon"; 1052 reg = <0x0 0xfdf66e00 0x0 0x20>; 1053 }; 1054 1055 qos_rga3_0: qos@fdf67000 { 1056 compatible = "rockchip,rk3588-qos", "syscon"; 1057 reg = <0x0 0xfdf67000 0x0 0x20>; 1058 }; 1059 1060 qos_vdpu: qos@fdf67200 { 1061 compatible = "rockchip,rk3588-qos", "syscon"; 1062 reg = <0x0 0xfdf67200 0x0 0x20>; 1063 }; 1064 1065 qos_npu1: qos@fdf70000 { 1066 compatible = "rockchip,rk3588-qos", "syscon"; 1067 reg = <0x0 0xfdf70000 0x0 0x20>; 1068 }; 1069 1070 qos_npu2: qos@fdf71000 { 1071 compatible = "rockchip,rk3588-qos", "syscon"; 1072 reg = <0x0 0xfdf71000 0x0 0x20>; 1073 }; 1074 1075 qos_npu0_mwr: qos@fdf72000 { 1076 compatible = "rockchip,rk3588-qos", "syscon"; 1077 reg = <0x0 0xfdf72000 0x0 0x20>; 1078 }; 1079 1080 qos_npu0_mro: qos@fdf72200 { 1081 compatible = "rockchip,rk3588-qos", "syscon"; 1082 reg = <0x0 0xfdf72200 0x0 0x20>; 1083 }; 1084 1085 qos_mcu_npu: qos@fdf72400 { 1086 compatible = "rockchip,rk3588-qos", "syscon"; 1087 reg = <0x0 0xfdf72400 0x0 0x20>; 1088 }; 1089 1090 qos_hdcp0: qos@fdf80000 { 1091 compatible = "rockchip,rk3588-qos", "syscon"; 1092 reg = <0x0 0xfdf80000 0x0 0x20>; 1093 }; 1094 1095 qos_hdcp1: qos@fdf81000 { 1096 compatible = "rockchip,rk3588-qos", "syscon"; 1097 reg = <0x0 0xfdf81000 0x0 0x20>; 1098 }; 1099 1100 qos_hdmirx: qos@fdf81200 { 1101 compatible = "rockchip,rk3588-qos", "syscon"; 1102 reg = <0x0 0xfdf81200 0x0 0x20>; 1103 }; 1104 1105 qos_vop_m0: qos@fdf82000 { 1106 compatible = "rockchip,rk3588-qos", "syscon"; 1107 reg = <0x0 0xfdf82000 0x0 0x20>; 1108 }; 1109 1110 qos_vop_m1: qos@fdf82200 { 1111 compatible = "rockchip,rk3588-qos", "syscon"; 1112 reg = <0x0 0xfdf82200 0x0 0x20>; 1113 }; 1114 1115 gmac1: ethernet@fe1c0000 { 1116 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 1117 reg = <0x0 0xfe1c0000 0x0 0x10000>; 1118 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>, 1119 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 1120 interrupt-names = "macirq", "eth_wake_irq"; 1121 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, 1122 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, 1123 <&cru CLK_GMAC1_PTP_REF>; 1124 clock-names = "stmmaceth", "clk_mac_ref", 1125 "pclk_mac", "aclk_mac", 1126 "ptp_ref"; 1127 power-domains = <&power RK3588_PD_GMAC>; 1128 resets = <&cru SRST_A_GMAC1>; 1129 reset-names = "stmmaceth"; 1130 rockchip,grf = <&sys_grf>; 1131 rockchip,php-grf = <&php_grf>; 1132 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1133 snps,mixed-burst; 1134 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1135 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1136 snps,tso; 1137 status = "disabled"; 1138 1139 mdio1: mdio { 1140 compatible = "snps,dwmac-mdio"; 1141 #address-cells = <0x1>; 1142 #size-cells = <0x0>; 1143 }; 1144 1145 gmac1_stmmac_axi_setup: stmmac-axi-config { 1146 snps,blen = <0 0 0 0 16 8 4>; 1147 snps,wr_osr_lmt = <4>; 1148 snps,rd_osr_lmt = <8>; 1149 }; 1150 1151 gmac1_mtl_rx_setup: rx-queues-config { 1152 snps,rx-queues-to-use = <2>; 1153 queue0 {}; 1154 queue1 {}; 1155 }; 1156 1157 gmac1_mtl_tx_setup: tx-queues-config { 1158 snps,tx-queues-to-use = <2>; 1159 queue0 {}; 1160 queue1 {}; 1161 }; 1162 }; 1163 1164 sdmmc: mmc@fe2c0000 { 1165 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1166 reg = <0x0 0xfe2c0000 0x0 0x4000>; 1167 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 1168 clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, 1169 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 1170 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1171 fifo-depth = <0x100>; 1172 max-frequency = <200000000>; 1173 pinctrl-names = "default"; 1174 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 1175 power-domains = <&power RK3588_PD_SDMMC>; 1176 status = "disabled"; 1177 }; 1178 1179 sdio: mmc@fe2d0000 { 1180 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1181 reg = <0x00 0xfe2d0000 0x00 0x4000>; 1182 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>; 1183 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, 1184 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 1185 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1186 fifo-depth = <0x100>; 1187 max-frequency = <200000000>; 1188 pinctrl-names = "default"; 1189 pinctrl-0 = <&sdiom1_pins>; 1190 power-domains = <&power RK3588_PD_SDIO>; 1191 status = "disabled"; 1192 }; 1193 1194 sdhci: mmc@fe2e0000 { 1195 compatible = "rockchip,rk3588-dwcmshc"; 1196 reg = <0x0 0xfe2e0000 0x0 0x10000>; 1197 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 1198 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; 1199 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 1200 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1201 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1202 <&cru TMCLK_EMMC>; 1203 clock-names = "core", "bus", "axi", "block", "timer"; 1204 max-frequency = <200000000>; 1205 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, 1206 <&emmc_cmd>, <&emmc_data_strobe>; 1207 pinctrl-names = "default"; 1208 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 1209 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 1210 <&cru SRST_T_EMMC>; 1211 reset-names = "core", "bus", "axi", "block", "timer"; 1212 status = "disabled"; 1213 }; 1214 1215 i2s0_8ch: i2s@fe470000 { 1216 compatible = "rockchip,rk3588-i2s-tdm"; 1217 reg = <0x0 0xfe470000 0x0 0x1000>; 1218 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>; 1219 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1220 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1221 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; 1222 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; 1223 dmas = <&dmac0 0>, <&dmac0 1>; 1224 dma-names = "tx", "rx"; 1225 power-domains = <&power RK3588_PD_AUDIO>; 1226 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1227 reset-names = "tx-m", "rx-m"; 1228 rockchip,trcm-sync-tx-only; 1229 pinctrl-names = "default"; 1230 pinctrl-0 = <&i2s0_lrck 1231 &i2s0_sclk 1232 &i2s0_sdi0 1233 &i2s0_sdi1 1234 &i2s0_sdi2 1235 &i2s0_sdi3 1236 &i2s0_sdo0 1237 &i2s0_sdo1 1238 &i2s0_sdo2 1239 &i2s0_sdo3>; 1240 #sound-dai-cells = <0>; 1241 status = "disabled"; 1242 }; 1243 1244 i2s1_8ch: i2s@fe480000 { 1245 compatible = "rockchip,rk3588-i2s-tdm"; 1246 reg = <0x0 0xfe480000 0x0 0x1000>; 1247 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>; 1248 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; 1249 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1250 dmas = <&dmac0 2>, <&dmac0 3>; 1251 dma-names = "tx", "rx"; 1252 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 1253 reset-names = "tx-m", "rx-m"; 1254 rockchip,trcm-sync-tx-only; 1255 pinctrl-names = "default"; 1256 pinctrl-0 = <&i2s1m0_lrck 1257 &i2s1m0_sclk 1258 &i2s1m0_sdi0 1259 &i2s1m0_sdi1 1260 &i2s1m0_sdi2 1261 &i2s1m0_sdi3 1262 &i2s1m0_sdo0 1263 &i2s1m0_sdo1 1264 &i2s1m0_sdo2 1265 &i2s1m0_sdo3>; 1266 #sound-dai-cells = <0>; 1267 status = "disabled"; 1268 }; 1269 1270 i2s2_2ch: i2s@fe490000 { 1271 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1272 reg = <0x0 0xfe490000 0x0 0x1000>; 1273 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>; 1274 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 1275 clock-names = "i2s_clk", "i2s_hclk"; 1276 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; 1277 assigned-clock-parents = <&cru PLL_AUPLL>; 1278 dmas = <&dmac1 0>, <&dmac1 1>; 1279 dma-names = "tx", "rx"; 1280 power-domains = <&power RK3588_PD_AUDIO>; 1281 rockchip,trcm-sync-tx-only; 1282 pinctrl-names = "default"; 1283 pinctrl-0 = <&i2s2m1_lrck 1284 &i2s2m1_sclk 1285 &i2s2m1_sdi 1286 &i2s2m1_sdo>; 1287 #sound-dai-cells = <0>; 1288 status = "disabled"; 1289 }; 1290 1291 i2s3_2ch: i2s@fe4a0000 { 1292 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1293 reg = <0x0 0xfe4a0000 0x0 0x1000>; 1294 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>; 1295 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; 1296 clock-names = "i2s_clk", "i2s_hclk"; 1297 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; 1298 assigned-clock-parents = <&cru PLL_AUPLL>; 1299 dmas = <&dmac1 2>, <&dmac1 3>; 1300 dma-names = "tx", "rx"; 1301 power-domains = <&power RK3588_PD_AUDIO>; 1302 rockchip,trcm-sync-tx-only; 1303 pinctrl-names = "default"; 1304 pinctrl-0 = <&i2s3_lrck 1305 &i2s3_sclk 1306 &i2s3_sdi 1307 &i2s3_sdo>; 1308 #sound-dai-cells = <0>; 1309 status = "disabled"; 1310 }; 1311 1312 gic: interrupt-controller@fe600000 { 1313 compatible = "arm,gic-v3"; 1314 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ 1315 <0x0 0xfe680000 0 0x100000>; /* GICR */ 1316 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 1317 interrupt-controller; 1318 mbi-alias = <0x0 0xfe610000>; 1319 mbi-ranges = <424 56>; 1320 msi-controller; 1321 ranges; 1322 #address-cells = <2>; 1323 #interrupt-cells = <4>; 1324 #size-cells = <2>; 1325 1326 its0: msi-controller@fe640000 { 1327 compatible = "arm,gic-v3-its"; 1328 reg = <0x0 0xfe640000 0x0 0x20000>; 1329 msi-controller; 1330 #msi-cells = <1>; 1331 }; 1332 1333 its1: msi-controller@fe660000 { 1334 compatible = "arm,gic-v3-its"; 1335 reg = <0x0 0xfe660000 0x0 0x20000>; 1336 msi-controller; 1337 #msi-cells = <1>; 1338 }; 1339 1340 ppi-partitions { 1341 ppi_partition0: interrupt-partition-0 { 1342 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 1343 }; 1344 1345 ppi_partition1: interrupt-partition-1 { 1346 affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; 1347 }; 1348 }; 1349 }; 1350 1351 dmac0: dma-controller@fea10000 { 1352 compatible = "arm,pl330", "arm,primecell"; 1353 reg = <0x0 0xfea10000 0x0 0x4000>; 1354 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>, 1355 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>; 1356 arm,pl330-periph-burst; 1357 clocks = <&cru ACLK_DMAC0>; 1358 clock-names = "apb_pclk"; 1359 #dma-cells = <1>; 1360 }; 1361 1362 dmac1: dma-controller@fea30000 { 1363 compatible = "arm,pl330", "arm,primecell"; 1364 reg = <0x0 0xfea30000 0x0 0x4000>; 1365 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>, 1366 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>; 1367 arm,pl330-periph-burst; 1368 clocks = <&cru ACLK_DMAC1>; 1369 clock-names = "apb_pclk"; 1370 #dma-cells = <1>; 1371 }; 1372 1373 i2c1: i2c@fea90000 { 1374 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1375 reg = <0x0 0xfea90000 0x0 0x1000>; 1376 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1377 clock-names = "i2c", "pclk"; 1378 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>; 1379 pinctrl-0 = <&i2c1m0_xfer>; 1380 pinctrl-names = "default"; 1381 #address-cells = <1>; 1382 #size-cells = <0>; 1383 status = "disabled"; 1384 }; 1385 1386 i2c2: i2c@feaa0000 { 1387 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1388 reg = <0x0 0xfeaa0000 0x0 0x1000>; 1389 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1390 clock-names = "i2c", "pclk"; 1391 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>; 1392 pinctrl-0 = <&i2c2m0_xfer>; 1393 pinctrl-names = "default"; 1394 #address-cells = <1>; 1395 #size-cells = <0>; 1396 status = "disabled"; 1397 }; 1398 1399 i2c3: i2c@feab0000 { 1400 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1401 reg = <0x0 0xfeab0000 0x0 0x1000>; 1402 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1403 clock-names = "i2c", "pclk"; 1404 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>; 1405 pinctrl-0 = <&i2c3m0_xfer>; 1406 pinctrl-names = "default"; 1407 #address-cells = <1>; 1408 #size-cells = <0>; 1409 status = "disabled"; 1410 }; 1411 1412 i2c4: i2c@feac0000 { 1413 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1414 reg = <0x0 0xfeac0000 0x0 0x1000>; 1415 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1416 clock-names = "i2c", "pclk"; 1417 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>; 1418 pinctrl-0 = <&i2c4m0_xfer>; 1419 pinctrl-names = "default"; 1420 #address-cells = <1>; 1421 #size-cells = <0>; 1422 status = "disabled"; 1423 }; 1424 1425 i2c5: i2c@fead0000 { 1426 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1427 reg = <0x0 0xfead0000 0x0 0x1000>; 1428 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1429 clock-names = "i2c", "pclk"; 1430 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>; 1431 pinctrl-0 = <&i2c5m0_xfer>; 1432 pinctrl-names = "default"; 1433 #address-cells = <1>; 1434 #size-cells = <0>; 1435 status = "disabled"; 1436 }; 1437 1438 timer0: timer@feae0000 { 1439 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; 1440 reg = <0x0 0xfeae0000 0x0 0x20>; 1441 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>; 1442 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; 1443 clock-names = "pclk", "timer"; 1444 }; 1445 1446 wdt: watchdog@feaf0000 { 1447 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; 1448 reg = <0x0 0xfeaf0000 0x0 0x100>; 1449 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 1450 clock-names = "tclk", "pclk"; 1451 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>; 1452 }; 1453 1454 spi0: spi@feb00000 { 1455 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1456 reg = <0x0 0xfeb00000 0x0 0x1000>; 1457 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>; 1458 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 1459 clock-names = "spiclk", "apb_pclk"; 1460 dmas = <&dmac0 14>, <&dmac0 15>; 1461 dma-names = "tx", "rx"; 1462 num-cs = <2>; 1463 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 1464 pinctrl-names = "default"; 1465 #address-cells = <1>; 1466 #size-cells = <0>; 1467 status = "disabled"; 1468 }; 1469 1470 spi1: spi@feb10000 { 1471 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1472 reg = <0x0 0xfeb10000 0x0 0x1000>; 1473 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>; 1474 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1475 clock-names = "spiclk", "apb_pclk"; 1476 dmas = <&dmac0 16>, <&dmac0 17>; 1477 dma-names = "tx", "rx"; 1478 num-cs = <2>; 1479 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; 1480 pinctrl-names = "default"; 1481 #address-cells = <1>; 1482 #size-cells = <0>; 1483 status = "disabled"; 1484 }; 1485 1486 spi2: spi@feb20000 { 1487 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1488 reg = <0x0 0xfeb20000 0x0 0x1000>; 1489 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>; 1490 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 1491 clock-names = "spiclk", "apb_pclk"; 1492 dmas = <&dmac1 15>, <&dmac1 16>; 1493 dma-names = "tx", "rx"; 1494 num-cs = <2>; 1495 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; 1496 pinctrl-names = "default"; 1497 #address-cells = <1>; 1498 #size-cells = <0>; 1499 status = "disabled"; 1500 }; 1501 1502 spi3: spi@feb30000 { 1503 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1504 reg = <0x0 0xfeb30000 0x0 0x1000>; 1505 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>; 1506 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 1507 clock-names = "spiclk", "apb_pclk"; 1508 dmas = <&dmac1 17>, <&dmac1 18>; 1509 dma-names = "tx", "rx"; 1510 num-cs = <2>; 1511 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; 1512 pinctrl-names = "default"; 1513 #address-cells = <1>; 1514 #size-cells = <0>; 1515 status = "disabled"; 1516 }; 1517 1518 uart1: serial@feb40000 { 1519 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1520 reg = <0x0 0xfeb40000 0x0 0x100>; 1521 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>; 1522 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1523 clock-names = "baudclk", "apb_pclk"; 1524 dmas = <&dmac0 8>, <&dmac0 9>; 1525 dma-names = "tx", "rx"; 1526 pinctrl-0 = <&uart1m1_xfer>; 1527 pinctrl-names = "default"; 1528 reg-io-width = <4>; 1529 reg-shift = <2>; 1530 status = "disabled"; 1531 }; 1532 1533 uart2: serial@feb50000 { 1534 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1535 reg = <0x0 0xfeb50000 0x0 0x100>; 1536 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>; 1537 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1538 clock-names = "baudclk", "apb_pclk"; 1539 dmas = <&dmac0 10>, <&dmac0 11>; 1540 dma-names = "tx", "rx"; 1541 pinctrl-0 = <&uart2m1_xfer>; 1542 pinctrl-names = "default"; 1543 reg-io-width = <4>; 1544 reg-shift = <2>; 1545 status = "disabled"; 1546 }; 1547 1548 uart3: serial@feb60000 { 1549 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1550 reg = <0x0 0xfeb60000 0x0 0x100>; 1551 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>; 1552 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1553 clock-names = "baudclk", "apb_pclk"; 1554 dmas = <&dmac0 12>, <&dmac0 13>; 1555 dma-names = "tx", "rx"; 1556 pinctrl-0 = <&uart3m1_xfer>; 1557 pinctrl-names = "default"; 1558 reg-io-width = <4>; 1559 reg-shift = <2>; 1560 status = "disabled"; 1561 }; 1562 1563 uart4: serial@feb70000 { 1564 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1565 reg = <0x0 0xfeb70000 0x0 0x100>; 1566 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>; 1567 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1568 clock-names = "baudclk", "apb_pclk"; 1569 dmas = <&dmac1 9>, <&dmac1 10>; 1570 dma-names = "tx", "rx"; 1571 pinctrl-0 = <&uart4m1_xfer>; 1572 pinctrl-names = "default"; 1573 reg-io-width = <4>; 1574 reg-shift = <2>; 1575 status = "disabled"; 1576 }; 1577 1578 uart5: serial@feb80000 { 1579 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1580 reg = <0x0 0xfeb80000 0x0 0x100>; 1581 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>; 1582 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1583 clock-names = "baudclk", "apb_pclk"; 1584 dmas = <&dmac1 11>, <&dmac1 12>; 1585 dma-names = "tx", "rx"; 1586 pinctrl-0 = <&uart5m1_xfer>; 1587 pinctrl-names = "default"; 1588 reg-io-width = <4>; 1589 reg-shift = <2>; 1590 status = "disabled"; 1591 }; 1592 1593 uart6: serial@feb90000 { 1594 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1595 reg = <0x0 0xfeb90000 0x0 0x100>; 1596 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>; 1597 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1598 clock-names = "baudclk", "apb_pclk"; 1599 dmas = <&dmac1 13>, <&dmac1 14>; 1600 dma-names = "tx", "rx"; 1601 pinctrl-0 = <&uart6m1_xfer>; 1602 pinctrl-names = "default"; 1603 reg-io-width = <4>; 1604 reg-shift = <2>; 1605 status = "disabled"; 1606 }; 1607 1608 uart7: serial@feba0000 { 1609 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1610 reg = <0x0 0xfeba0000 0x0 0x100>; 1611 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>; 1612 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1613 clock-names = "baudclk", "apb_pclk"; 1614 dmas = <&dmac2 7>, <&dmac2 8>; 1615 dma-names = "tx", "rx"; 1616 pinctrl-0 = <&uart7m1_xfer>; 1617 pinctrl-names = "default"; 1618 reg-io-width = <4>; 1619 reg-shift = <2>; 1620 status = "disabled"; 1621 }; 1622 1623 uart8: serial@febb0000 { 1624 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1625 reg = <0x0 0xfebb0000 0x0 0x100>; 1626 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>; 1627 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 1628 clock-names = "baudclk", "apb_pclk"; 1629 dmas = <&dmac2 9>, <&dmac2 10>; 1630 dma-names = "tx", "rx"; 1631 pinctrl-0 = <&uart8m1_xfer>; 1632 pinctrl-names = "default"; 1633 reg-io-width = <4>; 1634 reg-shift = <2>; 1635 status = "disabled"; 1636 }; 1637 1638 uart9: serial@febc0000 { 1639 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1640 reg = <0x0 0xfebc0000 0x0 0x100>; 1641 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>; 1642 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 1643 clock-names = "baudclk", "apb_pclk"; 1644 dmas = <&dmac2 11>, <&dmac2 12>; 1645 dma-names = "tx", "rx"; 1646 pinctrl-0 = <&uart9m1_xfer>; 1647 pinctrl-names = "default"; 1648 reg-io-width = <4>; 1649 reg-shift = <2>; 1650 status = "disabled"; 1651 }; 1652 1653 pwm4: pwm@febd0000 { 1654 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1655 reg = <0x0 0xfebd0000 0x0 0x10>; 1656 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1657 clock-names = "pwm", "pclk"; 1658 pinctrl-0 = <&pwm4m0_pins>; 1659 pinctrl-names = "default"; 1660 #pwm-cells = <3>; 1661 status = "disabled"; 1662 }; 1663 1664 pwm5: pwm@febd0010 { 1665 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1666 reg = <0x0 0xfebd0010 0x0 0x10>; 1667 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1668 clock-names = "pwm", "pclk"; 1669 pinctrl-0 = <&pwm5m0_pins>; 1670 pinctrl-names = "default"; 1671 #pwm-cells = <3>; 1672 status = "disabled"; 1673 }; 1674 1675 pwm6: pwm@febd0020 { 1676 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1677 reg = <0x0 0xfebd0020 0x0 0x10>; 1678 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1679 clock-names = "pwm", "pclk"; 1680 pinctrl-0 = <&pwm6m0_pins>; 1681 pinctrl-names = "default"; 1682 #pwm-cells = <3>; 1683 status = "disabled"; 1684 }; 1685 1686 pwm7: pwm@febd0030 { 1687 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1688 reg = <0x0 0xfebd0030 0x0 0x10>; 1689 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1690 clock-names = "pwm", "pclk"; 1691 pinctrl-0 = <&pwm7m0_pins>; 1692 pinctrl-names = "default"; 1693 #pwm-cells = <3>; 1694 status = "disabled"; 1695 }; 1696 1697 pwm8: pwm@febe0000 { 1698 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1699 reg = <0x0 0xfebe0000 0x0 0x10>; 1700 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1701 clock-names = "pwm", "pclk"; 1702 pinctrl-0 = <&pwm8m0_pins>; 1703 pinctrl-names = "default"; 1704 #pwm-cells = <3>; 1705 status = "disabled"; 1706 }; 1707 1708 pwm9: pwm@febe0010 { 1709 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1710 reg = <0x0 0xfebe0010 0x0 0x10>; 1711 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1712 clock-names = "pwm", "pclk"; 1713 pinctrl-0 = <&pwm9m0_pins>; 1714 pinctrl-names = "default"; 1715 #pwm-cells = <3>; 1716 status = "disabled"; 1717 }; 1718 1719 pwm10: pwm@febe0020 { 1720 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1721 reg = <0x0 0xfebe0020 0x0 0x10>; 1722 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1723 clock-names = "pwm", "pclk"; 1724 pinctrl-0 = <&pwm10m0_pins>; 1725 pinctrl-names = "default"; 1726 #pwm-cells = <3>; 1727 status = "disabled"; 1728 }; 1729 1730 pwm11: pwm@febe0030 { 1731 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1732 reg = <0x0 0xfebe0030 0x0 0x10>; 1733 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1734 clock-names = "pwm", "pclk"; 1735 pinctrl-0 = <&pwm11m0_pins>; 1736 pinctrl-names = "default"; 1737 #pwm-cells = <3>; 1738 status = "disabled"; 1739 }; 1740 1741 pwm12: pwm@febf0000 { 1742 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1743 reg = <0x0 0xfebf0000 0x0 0x10>; 1744 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1745 clock-names = "pwm", "pclk"; 1746 pinctrl-0 = <&pwm12m0_pins>; 1747 pinctrl-names = "default"; 1748 #pwm-cells = <3>; 1749 status = "disabled"; 1750 }; 1751 1752 pwm13: pwm@febf0010 { 1753 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1754 reg = <0x0 0xfebf0010 0x0 0x10>; 1755 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1756 clock-names = "pwm", "pclk"; 1757 pinctrl-0 = <&pwm13m0_pins>; 1758 pinctrl-names = "default"; 1759 #pwm-cells = <3>; 1760 status = "disabled"; 1761 }; 1762 1763 pwm14: pwm@febf0020 { 1764 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1765 reg = <0x0 0xfebf0020 0x0 0x10>; 1766 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1767 clock-names = "pwm", "pclk"; 1768 pinctrl-0 = <&pwm14m0_pins>; 1769 pinctrl-names = "default"; 1770 #pwm-cells = <3>; 1771 status = "disabled"; 1772 }; 1773 1774 pwm15: pwm@febf0030 { 1775 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1776 reg = <0x0 0xfebf0030 0x0 0x10>; 1777 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1778 clock-names = "pwm", "pclk"; 1779 pinctrl-0 = <&pwm15m0_pins>; 1780 pinctrl-names = "default"; 1781 #pwm-cells = <3>; 1782 status = "disabled"; 1783 }; 1784 1785 tsadc: tsadc@fec00000 { 1786 compatible = "rockchip,rk3588-tsadc"; 1787 reg = <0x0 0xfec00000 0x0 0x400>; 1788 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>; 1789 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 1790 clock-names = "tsadc", "apb_pclk"; 1791 assigned-clocks = <&cru CLK_TSADC>; 1792 assigned-clock-rates = <2000000>; 1793 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; 1794 reset-names = "tsadc-apb", "tsadc"; 1795 rockchip,hw-tshut-temp = <120000>; 1796 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 1797 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 1798 pinctrl-0 = <&tsadc_gpio_func>; 1799 pinctrl-1 = <&tsadc_shut>; 1800 pinctrl-names = "gpio", "otpout"; 1801 #thermal-sensor-cells = <1>; 1802 status = "disabled"; 1803 }; 1804 1805 saradc: adc@fec10000 { 1806 compatible = "rockchip,rk3588-saradc"; 1807 reg = <0x0 0xfec10000 0x0 0x10000>; 1808 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>; 1809 #io-channel-cells = <1>; 1810 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1811 clock-names = "saradc", "apb_pclk"; 1812 resets = <&cru SRST_P_SARADC>; 1813 reset-names = "saradc-apb"; 1814 status = "disabled"; 1815 }; 1816 1817 i2c6: i2c@fec80000 { 1818 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1819 reg = <0x0 0xfec80000 0x0 0x1000>; 1820 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 1821 clock-names = "i2c", "pclk"; 1822 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>; 1823 pinctrl-0 = <&i2c6m0_xfer>; 1824 pinctrl-names = "default"; 1825 #address-cells = <1>; 1826 #size-cells = <0>; 1827 status = "disabled"; 1828 }; 1829 1830 i2c7: i2c@fec90000 { 1831 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1832 reg = <0x0 0xfec90000 0x0 0x1000>; 1833 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 1834 clock-names = "i2c", "pclk"; 1835 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; 1836 pinctrl-0 = <&i2c7m0_xfer>; 1837 pinctrl-names = "default"; 1838 #address-cells = <1>; 1839 #size-cells = <0>; 1840 status = "disabled"; 1841 }; 1842 1843 i2c8: i2c@feca0000 { 1844 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1845 reg = <0x0 0xfeca0000 0x0 0x1000>; 1846 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 1847 clock-names = "i2c", "pclk"; 1848 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>; 1849 pinctrl-0 = <&i2c8m0_xfer>; 1850 pinctrl-names = "default"; 1851 #address-cells = <1>; 1852 #size-cells = <0>; 1853 status = "disabled"; 1854 }; 1855 1856 spi4: spi@fecb0000 { 1857 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1858 reg = <0x0 0xfecb0000 0x0 0x1000>; 1859 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>; 1860 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 1861 clock-names = "spiclk", "apb_pclk"; 1862 dmas = <&dmac2 13>, <&dmac2 14>; 1863 dma-names = "tx", "rx"; 1864 num-cs = <2>; 1865 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; 1866 pinctrl-names = "default"; 1867 #address-cells = <1>; 1868 #size-cells = <0>; 1869 status = "disabled"; 1870 }; 1871 1872 otp: efuse@fecc0000 { 1873 compatible = "rockchip,rk3588-otp"; 1874 reg = <0x0 0xfecc0000 0x0 0x400>; 1875 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, 1876 <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; 1877 clock-names = "otp", "apb_pclk", "phy", "arb"; 1878 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, 1879 <&cru SRST_OTPC_ARB>; 1880 reset-names = "otp", "apb", "arb"; 1881 #address-cells = <1>; 1882 #size-cells = <1>; 1883 1884 cpu_code: cpu-code@2 { 1885 reg = <0x02 0x2>; 1886 }; 1887 1888 otp_id: id@7 { 1889 reg = <0x07 0x10>; 1890 }; 1891 1892 cpub0_leakage: cpu-leakage@17 { 1893 reg = <0x17 0x1>; 1894 }; 1895 1896 cpub1_leakage: cpu-leakage@18 { 1897 reg = <0x18 0x1>; 1898 }; 1899 1900 cpul_leakage: cpu-leakage@19 { 1901 reg = <0x19 0x1>; 1902 }; 1903 1904 log_leakage: log-leakage@1a { 1905 reg = <0x1a 0x1>; 1906 }; 1907 1908 gpu_leakage: gpu-leakage@1b { 1909 reg = <0x1b 0x1>; 1910 }; 1911 1912 otp_cpu_version: cpu-version@1c { 1913 reg = <0x1c 0x1>; 1914 bits = <3 3>; 1915 }; 1916 1917 npu_leakage: npu-leakage@28 { 1918 reg = <0x28 0x1>; 1919 }; 1920 1921 codec_leakage: codec-leakage@29 { 1922 reg = <0x29 0x1>; 1923 }; 1924 }; 1925 1926 dmac2: dma-controller@fed10000 { 1927 compatible = "arm,pl330", "arm,primecell"; 1928 reg = <0x0 0xfed10000 0x0 0x4000>; 1929 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>, 1930 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>; 1931 arm,pl330-periph-burst; 1932 clocks = <&cru ACLK_DMAC2>; 1933 clock-names = "apb_pclk"; 1934 #dma-cells = <1>; 1935 }; 1936 1937 system_sram2: sram@ff001000 { 1938 compatible = "mmio-sram"; 1939 reg = <0x0 0xff001000 0x0 0xef000>; 1940 ranges = <0x0 0x0 0xff001000 0xef000>; 1941 #address-cells = <1>; 1942 #size-cells = <1>; 1943 }; 1944 1945 pinctrl: pinctrl { 1946 compatible = "rockchip,rk3588-pinctrl"; 1947 ranges; 1948 rockchip,grf = <&ioc>; 1949 #address-cells = <2>; 1950 #size-cells = <2>; 1951 1952 gpio0: gpio@fd8a0000 { 1953 compatible = "rockchip,gpio-bank"; 1954 reg = <0x0 0xfd8a0000 0x0 0x100>; 1955 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 1956 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 1957 gpio-controller; 1958 gpio-ranges = <&pinctrl 0 0 32>; 1959 interrupt-controller; 1960 #gpio-cells = <2>; 1961 #interrupt-cells = <2>; 1962 }; 1963 1964 gpio1: gpio@fec20000 { 1965 compatible = "rockchip,gpio-bank"; 1966 reg = <0x0 0xfec20000 0x0 0x100>; 1967 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>; 1968 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1969 gpio-controller; 1970 gpio-ranges = <&pinctrl 0 32 32>; 1971 interrupt-controller; 1972 #gpio-cells = <2>; 1973 #interrupt-cells = <2>; 1974 }; 1975 1976 gpio2: gpio@fec30000 { 1977 compatible = "rockchip,gpio-bank"; 1978 reg = <0x0 0xfec30000 0x0 0x100>; 1979 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>; 1980 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1981 gpio-controller; 1982 gpio-ranges = <&pinctrl 0 64 32>; 1983 interrupt-controller; 1984 #gpio-cells = <2>; 1985 #interrupt-cells = <2>; 1986 }; 1987 1988 gpio3: gpio@fec40000 { 1989 compatible = "rockchip,gpio-bank"; 1990 reg = <0x0 0xfec40000 0x0 0x100>; 1991 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>; 1992 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1993 gpio-controller; 1994 gpio-ranges = <&pinctrl 0 96 32>; 1995 interrupt-controller; 1996 #gpio-cells = <2>; 1997 #interrupt-cells = <2>; 1998 }; 1999 2000 gpio4: gpio@fec50000 { 2001 compatible = "rockchip,gpio-bank"; 2002 reg = <0x0 0xfec50000 0x0 0x100>; 2003 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>; 2004 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 2005 gpio-controller; 2006 gpio-ranges = <&pinctrl 0 128 32>; 2007 interrupt-controller; 2008 #gpio-cells = <2>; 2009 #interrupt-cells = <2>; 2010 }; 2011 }; 2012}; 2013 2014#include "rk3588s-pinctrl.dtsi" 2015