1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rk3588-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/power/rk3588-power.h> 10#include <dt-bindings/reset/rockchip,rk3588-cru.h> 11 12/ { 13 compatible = "rockchip,rk3588"; 14 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu-map { 24 cluster0 { 25 core0 { 26 cpu = <&cpu_l0>; 27 }; 28 core1 { 29 cpu = <&cpu_l1>; 30 }; 31 core2 { 32 cpu = <&cpu_l2>; 33 }; 34 core3 { 35 cpu = <&cpu_l3>; 36 }; 37 }; 38 cluster1 { 39 core0 { 40 cpu = <&cpu_b0>; 41 }; 42 core1 { 43 cpu = <&cpu_b1>; 44 }; 45 }; 46 cluster2 { 47 core0 { 48 cpu = <&cpu_b2>; 49 }; 50 core1 { 51 cpu = <&cpu_b3>; 52 }; 53 }; 54 }; 55 56 cpu_l0: cpu@0 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a55"; 59 reg = <0x0>; 60 enable-method = "psci"; 61 capacity-dmips-mhz = <530>; 62 clocks = <&scmi_clk SCMI_CLK_CPUL>; 63 cpu-idle-states = <&CPU_SLEEP>; 64 i-cache-size = <32768>; 65 i-cache-line-size = <64>; 66 i-cache-sets = <128>; 67 d-cache-size = <32768>; 68 d-cache-line-size = <64>; 69 d-cache-sets = <128>; 70 next-level-cache = <&l2_cache_l0>; 71 dynamic-power-coefficient = <228>; 72 #cooling-cells = <2>; 73 }; 74 75 cpu_l1: cpu@100 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a55"; 78 reg = <0x100>; 79 enable-method = "psci"; 80 capacity-dmips-mhz = <530>; 81 clocks = <&scmi_clk SCMI_CLK_CPUL>; 82 cpu-idle-states = <&CPU_SLEEP>; 83 i-cache-size = <32768>; 84 i-cache-line-size = <64>; 85 i-cache-sets = <128>; 86 d-cache-size = <32768>; 87 d-cache-line-size = <64>; 88 d-cache-sets = <128>; 89 next-level-cache = <&l2_cache_l1>; 90 dynamic-power-coefficient = <228>; 91 #cooling-cells = <2>; 92 }; 93 94 cpu_l2: cpu@200 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a55"; 97 reg = <0x200>; 98 enable-method = "psci"; 99 capacity-dmips-mhz = <530>; 100 clocks = <&scmi_clk SCMI_CLK_CPUL>; 101 cpu-idle-states = <&CPU_SLEEP>; 102 i-cache-size = <32768>; 103 i-cache-line-size = <64>; 104 i-cache-sets = <128>; 105 d-cache-size = <32768>; 106 d-cache-line-size = <64>; 107 d-cache-sets = <128>; 108 next-level-cache = <&l2_cache_l2>; 109 dynamic-power-coefficient = <228>; 110 #cooling-cells = <2>; 111 }; 112 113 cpu_l3: cpu@300 { 114 device_type = "cpu"; 115 compatible = "arm,cortex-a55"; 116 reg = <0x300>; 117 enable-method = "psci"; 118 capacity-dmips-mhz = <530>; 119 clocks = <&scmi_clk SCMI_CLK_CPUL>; 120 cpu-idle-states = <&CPU_SLEEP>; 121 i-cache-size = <32768>; 122 i-cache-line-size = <64>; 123 i-cache-sets = <128>; 124 d-cache-size = <32768>; 125 d-cache-line-size = <64>; 126 d-cache-sets = <128>; 127 next-level-cache = <&l2_cache_l3>; 128 dynamic-power-coefficient = <228>; 129 #cooling-cells = <2>; 130 }; 131 132 cpu_b0: cpu@400 { 133 device_type = "cpu"; 134 compatible = "arm,cortex-a76"; 135 reg = <0x400>; 136 enable-method = "psci"; 137 capacity-dmips-mhz = <1024>; 138 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 139 cpu-idle-states = <&CPU_SLEEP>; 140 i-cache-size = <65536>; 141 i-cache-line-size = <64>; 142 i-cache-sets = <256>; 143 d-cache-size = <65536>; 144 d-cache-line-size = <64>; 145 d-cache-sets = <256>; 146 next-level-cache = <&l2_cache_b0>; 147 dynamic-power-coefficient = <416>; 148 #cooling-cells = <2>; 149 }; 150 151 cpu_b1: cpu@500 { 152 device_type = "cpu"; 153 compatible = "arm,cortex-a76"; 154 reg = <0x500>; 155 enable-method = "psci"; 156 capacity-dmips-mhz = <1024>; 157 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 158 cpu-idle-states = <&CPU_SLEEP>; 159 i-cache-size = <65536>; 160 i-cache-line-size = <64>; 161 i-cache-sets = <256>; 162 d-cache-size = <65536>; 163 d-cache-line-size = <64>; 164 d-cache-sets = <256>; 165 next-level-cache = <&l2_cache_b1>; 166 dynamic-power-coefficient = <416>; 167 #cooling-cells = <2>; 168 }; 169 170 cpu_b2: cpu@600 { 171 device_type = "cpu"; 172 compatible = "arm,cortex-a76"; 173 reg = <0x600>; 174 enable-method = "psci"; 175 capacity-dmips-mhz = <1024>; 176 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 177 cpu-idle-states = <&CPU_SLEEP>; 178 i-cache-size = <65536>; 179 i-cache-line-size = <64>; 180 i-cache-sets = <256>; 181 d-cache-size = <65536>; 182 d-cache-line-size = <64>; 183 d-cache-sets = <256>; 184 next-level-cache = <&l2_cache_b2>; 185 dynamic-power-coefficient = <416>; 186 #cooling-cells = <2>; 187 }; 188 189 cpu_b3: cpu@700 { 190 device_type = "cpu"; 191 compatible = "arm,cortex-a76"; 192 reg = <0x700>; 193 enable-method = "psci"; 194 capacity-dmips-mhz = <1024>; 195 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 196 cpu-idle-states = <&CPU_SLEEP>; 197 i-cache-size = <65536>; 198 i-cache-line-size = <64>; 199 i-cache-sets = <256>; 200 d-cache-size = <65536>; 201 d-cache-line-size = <64>; 202 d-cache-sets = <256>; 203 next-level-cache = <&l2_cache_b3>; 204 dynamic-power-coefficient = <416>; 205 #cooling-cells = <2>; 206 }; 207 208 idle-states { 209 entry-method = "psci"; 210 CPU_SLEEP: cpu-sleep { 211 compatible = "arm,idle-state"; 212 local-timer-stop; 213 arm,psci-suspend-param = <0x0010000>; 214 entry-latency-us = <100>; 215 exit-latency-us = <120>; 216 min-residency-us = <1000>; 217 }; 218 }; 219 220 l2_cache_l0: l2-cache-l0 { 221 compatible = "cache"; 222 cache-size = <131072>; 223 cache-line-size = <64>; 224 cache-sets = <512>; 225 cache-level = <2>; 226 next-level-cache = <&l3_cache>; 227 }; 228 229 l2_cache_l1: l2-cache-l1 { 230 compatible = "cache"; 231 cache-size = <131072>; 232 cache-line-size = <64>; 233 cache-sets = <512>; 234 cache-level = <2>; 235 next-level-cache = <&l3_cache>; 236 }; 237 238 l2_cache_l2: l2-cache-l2 { 239 compatible = "cache"; 240 cache-size = <131072>; 241 cache-line-size = <64>; 242 cache-sets = <512>; 243 cache-level = <2>; 244 next-level-cache = <&l3_cache>; 245 }; 246 247 l2_cache_l3: l2-cache-l3 { 248 compatible = "cache"; 249 cache-size = <131072>; 250 cache-line-size = <64>; 251 cache-sets = <512>; 252 cache-level = <2>; 253 next-level-cache = <&l3_cache>; 254 }; 255 256 l2_cache_b0: l2-cache-b0 { 257 compatible = "cache"; 258 cache-size = <524288>; 259 cache-line-size = <64>; 260 cache-sets = <1024>; 261 cache-level = <2>; 262 next-level-cache = <&l3_cache>; 263 }; 264 265 l2_cache_b1: l2-cache-b1 { 266 compatible = "cache"; 267 cache-size = <524288>; 268 cache-line-size = <64>; 269 cache-sets = <1024>; 270 cache-level = <2>; 271 next-level-cache = <&l3_cache>; 272 }; 273 274 l2_cache_b2: l2-cache-b2 { 275 compatible = "cache"; 276 cache-size = <524288>; 277 cache-line-size = <64>; 278 cache-sets = <1024>; 279 cache-level = <2>; 280 next-level-cache = <&l3_cache>; 281 }; 282 283 l2_cache_b3: l2-cache-b3 { 284 compatible = "cache"; 285 cache-size = <524288>; 286 cache-line-size = <64>; 287 cache-sets = <1024>; 288 cache-level = <2>; 289 next-level-cache = <&l3_cache>; 290 }; 291 292 l3_cache: l3-cache { 293 compatible = "cache"; 294 cache-size = <3145728>; 295 cache-line-size = <64>; 296 cache-sets = <4096>; 297 cache-level = <3>; 298 }; 299 }; 300 301 firmware { 302 optee: optee { 303 compatible = "linaro,optee-tz"; 304 method = "smc"; 305 }; 306 307 scmi: scmi { 308 compatible = "arm,scmi-smc"; 309 arm,smc-id = <0x82000010>; 310 shmem = <&scmi_shmem>; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 314 scmi_clk: protocol@14 { 315 reg = <0x14>; 316 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>, 317 <&scmi_clk SCMI_CLK_CPUB23>; 318 assigned-clock-rates = <1200000000>, 319 <1200000000>; 320 #clock-cells = <1>; 321 }; 322 323 scmi_reset: protocol@16 { 324 reg = <0x16>; 325 #reset-cells = <1>; 326 }; 327 }; 328 }; 329 330 pmu-a55 { 331 compatible = "arm,cortex-a55-pmu"; 332 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>; 333 }; 334 335 pmu-a76 { 336 compatible = "arm,cortex-a76-pmu"; 337 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>; 338 }; 339 340 psci { 341 compatible = "arm,psci-1.0"; 342 method = "smc"; 343 }; 344 345 spll: clock-0 { 346 compatible = "fixed-clock"; 347 clock-frequency = <702000000>; 348 clock-output-names = "spll"; 349 #clock-cells = <0>; 350 }; 351 352 timer { 353 compatible = "arm,armv8-timer"; 354 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 355 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 356 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 357 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>, 358 <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 359 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 360 }; 361 362 xin24m: clock-1 { 363 compatible = "fixed-clock"; 364 clock-frequency = <24000000>; 365 clock-output-names = "xin24m"; 366 #clock-cells = <0>; 367 }; 368 369 xin32k: clock-2 { 370 compatible = "fixed-clock"; 371 clock-frequency = <32768>; 372 clock-output-names = "xin32k"; 373 #clock-cells = <0>; 374 }; 375 376 pmu_sram: sram@10f000 { 377 compatible = "mmio-sram"; 378 reg = <0x0 0x0010f000 0x0 0x100>; 379 ranges = <0 0x0 0x0010f000 0x100>; 380 #address-cells = <1>; 381 #size-cells = <1>; 382 383 scmi_shmem: sram@0 { 384 compatible = "arm,scmi-shmem"; 385 reg = <0x0 0x100>; 386 }; 387 }; 388 389 sys_grf: syscon@fd58c000 { 390 compatible = "rockchip,rk3588-sys-grf", "syscon"; 391 reg = <0x0 0xfd58c000 0x0 0x1000>; 392 }; 393 394 php_grf: syscon@fd5b0000 { 395 compatible = "rockchip,rk3588-php-grf", "syscon"; 396 reg = <0x0 0xfd5b0000 0x0 0x1000>; 397 }; 398 399 ioc: syscon@fd5f0000 { 400 compatible = "rockchip,rk3588-ioc", "syscon"; 401 reg = <0x0 0xfd5f0000 0x0 0x10000>; 402 }; 403 404 system_sram1: sram@fd600000 { 405 compatible = "mmio-sram"; 406 reg = <0x0 0xfd600000 0x0 0x100000>; 407 ranges = <0x0 0x0 0xfd600000 0x100000>; 408 #address-cells = <1>; 409 #size-cells = <1>; 410 }; 411 412 cru: clock-controller@fd7c0000 { 413 compatible = "rockchip,rk3588-cru"; 414 reg = <0x0 0xfd7c0000 0x0 0x5c000>; 415 assigned-clocks = 416 <&cru PLL_PPLL>, <&cru PLL_AUPLL>, 417 <&cru PLL_NPLL>, <&cru PLL_GPLL>, 418 <&cru ACLK_CENTER_ROOT>, 419 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, 420 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, 421 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, 422 <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, 423 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, 424 <&cru CLK_GPU>; 425 assigned-clock-rates = 426 <100000000>, <786432000>, 427 <850000000>, <1188000000>, 428 <702000000>, 429 <400000000>, <500000000>, 430 <800000000>, <100000000>, 431 <400000000>, <100000000>, 432 <200000000>, <500000000>, 433 <375000000>, <150000000>, 434 <200000000>; 435 rockchip,grf = <&php_grf>; 436 #clock-cells = <1>; 437 #reset-cells = <1>; 438 }; 439 440 i2c0: i2c@fd880000 { 441 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 442 reg = <0x0 0xfd880000 0x0 0x1000>; 443 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>; 444 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 445 clock-names = "i2c", "pclk"; 446 pinctrl-0 = <&i2c0m0_xfer>; 447 pinctrl-names = "default"; 448 #address-cells = <1>; 449 #size-cells = <0>; 450 status = "disabled"; 451 }; 452 453 uart0: serial@fd890000 { 454 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 455 reg = <0x0 0xfd890000 0x0 0x100>; 456 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; 457 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 458 clock-names = "baudclk", "apb_pclk"; 459 dmas = <&dmac0 6>, <&dmac0 7>; 460 dma-names = "tx", "rx"; 461 pinctrl-0 = <&uart0m1_xfer>; 462 pinctrl-names = "default"; 463 reg-shift = <2>; 464 reg-io-width = <4>; 465 status = "disabled"; 466 }; 467 468 pwm0: pwm@fd8b0000 { 469 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 470 reg = <0x0 0xfd8b0000 0x0 0x10>; 471 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 472 clock-names = "pwm", "pclk"; 473 pinctrl-0 = <&pwm0m0_pins>; 474 pinctrl-names = "default"; 475 #pwm-cells = <3>; 476 status = "disabled"; 477 }; 478 479 pwm1: pwm@fd8b0010 { 480 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 481 reg = <0x0 0xfd8b0010 0x0 0x10>; 482 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 483 clock-names = "pwm", "pclk"; 484 pinctrl-0 = <&pwm1m0_pins>; 485 pinctrl-names = "default"; 486 #pwm-cells = <3>; 487 status = "disabled"; 488 }; 489 490 pwm2: pwm@fd8b0020 { 491 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 492 reg = <0x0 0xfd8b0020 0x0 0x10>; 493 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 494 clock-names = "pwm", "pclk"; 495 pinctrl-0 = <&pwm2m0_pins>; 496 pinctrl-names = "default"; 497 #pwm-cells = <3>; 498 status = "disabled"; 499 }; 500 501 pwm3: pwm@fd8b0030 { 502 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 503 reg = <0x0 0xfd8b0030 0x0 0x10>; 504 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 505 clock-names = "pwm", "pclk"; 506 pinctrl-0 = <&pwm3m0_pins>; 507 pinctrl-names = "default"; 508 #pwm-cells = <3>; 509 status = "disabled"; 510 }; 511 512 pmu: power-management@fd8d8000 { 513 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; 514 reg = <0x0 0xfd8d8000 0x0 0x400>; 515 516 power: power-controller { 517 compatible = "rockchip,rk3588-power-controller"; 518 #address-cells = <1>; 519 #power-domain-cells = <1>; 520 #size-cells = <0>; 521 status = "okay"; 522 523 /* These power domains are grouped by VD_NPU */ 524 power-domain@RK3588_PD_NPU { 525 reg = <RK3588_PD_NPU>; 526 #power-domain-cells = <0>; 527 #address-cells = <1>; 528 #size-cells = <0>; 529 530 power-domain@RK3588_PD_NPUTOP { 531 reg = <RK3588_PD_NPUTOP>; 532 clocks = <&cru HCLK_NPU_ROOT>, 533 <&cru PCLK_NPU_ROOT>, 534 <&cru CLK_NPU_DSU0>, 535 <&cru HCLK_NPU_CM0_ROOT>; 536 pm_qos = <&qos_npu0_mwr>, 537 <&qos_npu0_mro>, 538 <&qos_mcu_npu>; 539 #power-domain-cells = <0>; 540 #address-cells = <1>; 541 #size-cells = <0>; 542 543 power-domain@RK3588_PD_NPU1 { 544 reg = <RK3588_PD_NPU1>; 545 clocks = <&cru HCLK_NPU_ROOT>, 546 <&cru PCLK_NPU_ROOT>, 547 <&cru CLK_NPU_DSU0>; 548 pm_qos = <&qos_npu1>; 549 #power-domain-cells = <0>; 550 }; 551 power-domain@RK3588_PD_NPU2 { 552 reg = <RK3588_PD_NPU2>; 553 clocks = <&cru HCLK_NPU_ROOT>, 554 <&cru PCLK_NPU_ROOT>, 555 <&cru CLK_NPU_DSU0>; 556 pm_qos = <&qos_npu2>; 557 #power-domain-cells = <0>; 558 }; 559 }; 560 }; 561 /* These power domains are grouped by VD_GPU */ 562 power-domain@RK3588_PD_GPU { 563 reg = <RK3588_PD_GPU>; 564 clocks = <&cru CLK_GPU>, 565 <&cru CLK_GPU_COREGROUP>, 566 <&cru CLK_GPU_STACKS>; 567 pm_qos = <&qos_gpu_m0>, 568 <&qos_gpu_m1>, 569 <&qos_gpu_m2>, 570 <&qos_gpu_m3>; 571 #power-domain-cells = <0>; 572 }; 573 /* These power domains are grouped by VD_VCODEC */ 574 power-domain@RK3588_PD_VCODEC { 575 reg = <RK3588_PD_VCODEC>; 576 #address-cells = <1>; 577 #size-cells = <0>; 578 #power-domain-cells = <0>; 579 580 power-domain@RK3588_PD_RKVDEC0 { 581 reg = <RK3588_PD_RKVDEC0>; 582 clocks = <&cru HCLK_RKVDEC0>, 583 <&cru HCLK_VDPU_ROOT>, 584 <&cru ACLK_VDPU_ROOT>, 585 <&cru ACLK_RKVDEC0>, 586 <&cru ACLK_RKVDEC_CCU>; 587 pm_qos = <&qos_rkvdec0>; 588 #power-domain-cells = <0>; 589 }; 590 power-domain@RK3588_PD_RKVDEC1 { 591 reg = <RK3588_PD_RKVDEC1>; 592 clocks = <&cru HCLK_RKVDEC1>, 593 <&cru HCLK_VDPU_ROOT>, 594 <&cru ACLK_VDPU_ROOT>, 595 <&cru ACLK_RKVDEC1>; 596 pm_qos = <&qos_rkvdec1>; 597 #power-domain-cells = <0>; 598 }; 599 power-domain@RK3588_PD_VENC0 { 600 reg = <RK3588_PD_VENC0>; 601 clocks = <&cru HCLK_RKVENC0>, 602 <&cru ACLK_RKVENC0>; 603 pm_qos = <&qos_rkvenc0_m0ro>, 604 <&qos_rkvenc0_m1ro>, 605 <&qos_rkvenc0_m2wo>; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 #power-domain-cells = <0>; 609 610 power-domain@RK3588_PD_VENC1 { 611 reg = <RK3588_PD_VENC1>; 612 clocks = <&cru HCLK_RKVENC1>, 613 <&cru HCLK_RKVENC0>, 614 <&cru ACLK_RKVENC0>, 615 <&cru ACLK_RKVENC1>; 616 pm_qos = <&qos_rkvenc1_m0ro>, 617 <&qos_rkvenc1_m1ro>, 618 <&qos_rkvenc1_m2wo>; 619 #power-domain-cells = <0>; 620 }; 621 }; 622 }; 623 /* These power domains are grouped by VD_LOGIC */ 624 power-domain@RK3588_PD_VDPU { 625 reg = <RK3588_PD_VDPU>; 626 clocks = <&cru HCLK_VDPU_ROOT>, 627 <&cru ACLK_VDPU_LOW_ROOT>, 628 <&cru ACLK_VDPU_ROOT>, 629 <&cru ACLK_JPEG_DECODER_ROOT>, 630 <&cru ACLK_IEP2P0>, 631 <&cru HCLK_IEP2P0>, 632 <&cru ACLK_JPEG_ENCODER0>, 633 <&cru HCLK_JPEG_ENCODER0>, 634 <&cru ACLK_JPEG_ENCODER1>, 635 <&cru HCLK_JPEG_ENCODER1>, 636 <&cru ACLK_JPEG_ENCODER2>, 637 <&cru HCLK_JPEG_ENCODER2>, 638 <&cru ACLK_JPEG_ENCODER3>, 639 <&cru HCLK_JPEG_ENCODER3>, 640 <&cru ACLK_JPEG_DECODER>, 641 <&cru HCLK_JPEG_DECODER>, 642 <&cru ACLK_RGA2>, 643 <&cru HCLK_RGA2>; 644 pm_qos = <&qos_iep>, 645 <&qos_jpeg_dec>, 646 <&qos_jpeg_enc0>, 647 <&qos_jpeg_enc1>, 648 <&qos_jpeg_enc2>, 649 <&qos_jpeg_enc3>, 650 <&qos_rga2_mro>, 651 <&qos_rga2_mwo>; 652 #address-cells = <1>; 653 #size-cells = <0>; 654 #power-domain-cells = <0>; 655 656 657 power-domain@RK3588_PD_AV1 { 658 reg = <RK3588_PD_AV1>; 659 clocks = <&cru PCLK_AV1>, 660 <&cru ACLK_AV1>, 661 <&cru HCLK_VDPU_ROOT>; 662 pm_qos = <&qos_av1>; 663 #power-domain-cells = <0>; 664 }; 665 power-domain@RK3588_PD_RKVDEC0 { 666 reg = <RK3588_PD_RKVDEC0>; 667 clocks = <&cru HCLK_RKVDEC0>, 668 <&cru HCLK_VDPU_ROOT>, 669 <&cru ACLK_VDPU_ROOT>, 670 <&cru ACLK_RKVDEC0>; 671 pm_qos = <&qos_rkvdec0>; 672 #power-domain-cells = <0>; 673 }; 674 power-domain@RK3588_PD_RKVDEC1 { 675 reg = <RK3588_PD_RKVDEC1>; 676 clocks = <&cru HCLK_RKVDEC1>, 677 <&cru HCLK_VDPU_ROOT>, 678 <&cru ACLK_VDPU_ROOT>; 679 pm_qos = <&qos_rkvdec1>; 680 #power-domain-cells = <0>; 681 }; 682 power-domain@RK3588_PD_RGA30 { 683 reg = <RK3588_PD_RGA30>; 684 clocks = <&cru ACLK_RGA3_0>, 685 <&cru HCLK_RGA3_0>; 686 pm_qos = <&qos_rga3_0>; 687 #power-domain-cells = <0>; 688 }; 689 }; 690 power-domain@RK3588_PD_VOP { 691 reg = <RK3588_PD_VOP>; 692 clocks = <&cru PCLK_VOP_ROOT>, 693 <&cru HCLK_VOP_ROOT>, 694 <&cru ACLK_VOP>; 695 pm_qos = <&qos_vop_m0>, 696 <&qos_vop_m1>; 697 #address-cells = <1>; 698 #size-cells = <0>; 699 #power-domain-cells = <0>; 700 701 power-domain@RK3588_PD_VO0 { 702 reg = <RK3588_PD_VO0>; 703 clocks = <&cru PCLK_VO0_ROOT>, 704 <&cru PCLK_VO0_S_ROOT>, 705 <&cru HCLK_VO0_S_ROOT>, 706 <&cru ACLK_VO0_ROOT>, 707 <&cru HCLK_HDCP0>, 708 <&cru ACLK_HDCP0>, 709 <&cru HCLK_VOP_ROOT>; 710 pm_qos = <&qos_hdcp0>; 711 #power-domain-cells = <0>; 712 }; 713 }; 714 power-domain@RK3588_PD_VO1 { 715 reg = <RK3588_PD_VO1>; 716 clocks = <&cru PCLK_VO1_ROOT>, 717 <&cru PCLK_VO1_S_ROOT>, 718 <&cru HCLK_VO1_S_ROOT>, 719 <&cru HCLK_HDCP1>, 720 <&cru ACLK_HDCP1>, 721 <&cru ACLK_HDMIRX_ROOT>, 722 <&cru HCLK_VO1USB_TOP_ROOT>; 723 pm_qos = <&qos_hdcp1>, 724 <&qos_hdmirx>; 725 #power-domain-cells = <0>; 726 }; 727 power-domain@RK3588_PD_VI { 728 reg = <RK3588_PD_VI>; 729 clocks = <&cru HCLK_VI_ROOT>, 730 <&cru PCLK_VI_ROOT>, 731 <&cru HCLK_ISP0>, 732 <&cru ACLK_ISP0>, 733 <&cru HCLK_VICAP>, 734 <&cru ACLK_VICAP>; 735 pm_qos = <&qos_isp0_mro>, 736 <&qos_isp0_mwo>, 737 <&qos_vicap_m0>, 738 <&qos_vicap_m1>; 739 #address-cells = <1>; 740 #size-cells = <0>; 741 #power-domain-cells = <0>; 742 743 power-domain@RK3588_PD_ISP1 { 744 reg = <RK3588_PD_ISP1>; 745 clocks = <&cru HCLK_ISP1>, 746 <&cru ACLK_ISP1>, 747 <&cru HCLK_VI_ROOT>, 748 <&cru PCLK_VI_ROOT>; 749 pm_qos = <&qos_isp1_mwo>, 750 <&qos_isp1_mro>; 751 #power-domain-cells = <0>; 752 }; 753 power-domain@RK3588_PD_FEC { 754 reg = <RK3588_PD_FEC>; 755 clocks = <&cru HCLK_FISHEYE0>, 756 <&cru ACLK_FISHEYE0>, 757 <&cru HCLK_FISHEYE1>, 758 <&cru ACLK_FISHEYE1>, 759 <&cru PCLK_VI_ROOT>; 760 pm_qos = <&qos_fisheye0>, 761 <&qos_fisheye1>; 762 #power-domain-cells = <0>; 763 }; 764 }; 765 power-domain@RK3588_PD_RGA31 { 766 reg = <RK3588_PD_RGA31>; 767 clocks = <&cru HCLK_RGA3_1>, 768 <&cru ACLK_RGA3_1>; 769 pm_qos = <&qos_rga3_1>; 770 #power-domain-cells = <0>; 771 }; 772 power-domain@RK3588_PD_USB { 773 reg = <RK3588_PD_USB>; 774 clocks = <&cru PCLK_PHP_ROOT>, 775 <&cru ACLK_USB_ROOT>, 776 <&cru HCLK_USB_ROOT>, 777 <&cru HCLK_HOST0>, 778 <&cru HCLK_HOST_ARB0>, 779 <&cru HCLK_HOST1>, 780 <&cru HCLK_HOST_ARB1>; 781 pm_qos = <&qos_usb3_0>, 782 <&qos_usb3_1>, 783 <&qos_usb2host_0>, 784 <&qos_usb2host_1>; 785 #power-domain-cells = <0>; 786 }; 787 power-domain@RK3588_PD_GMAC { 788 reg = <RK3588_PD_GMAC>; 789 clocks = <&cru PCLK_PHP_ROOT>, 790 <&cru ACLK_PCIE_ROOT>, 791 <&cru ACLK_PHP_ROOT>; 792 #power-domain-cells = <0>; 793 }; 794 power-domain@RK3588_PD_PCIE { 795 reg = <RK3588_PD_PCIE>; 796 clocks = <&cru PCLK_PHP_ROOT>, 797 <&cru ACLK_PCIE_ROOT>, 798 <&cru ACLK_PHP_ROOT>; 799 #power-domain-cells = <0>; 800 }; 801 power-domain@RK3588_PD_SDIO { 802 reg = <RK3588_PD_SDIO>; 803 clocks = <&cru HCLK_SDIO>, 804 <&cru HCLK_NVM_ROOT>; 805 pm_qos = <&qos_sdio>; 806 #power-domain-cells = <0>; 807 }; 808 power-domain@RK3588_PD_AUDIO { 809 reg = <RK3588_PD_AUDIO>; 810 clocks = <&cru HCLK_AUDIO_ROOT>, 811 <&cru PCLK_AUDIO_ROOT>; 812 #power-domain-cells = <0>; 813 }; 814 power-domain@RK3588_PD_SDMMC { 815 reg = <RK3588_PD_SDMMC>; 816 pm_qos = <&qos_sdmmc>; 817 #power-domain-cells = <0>; 818 }; 819 }; 820 }; 821 822 qos_gpu_m0: qos@fdf35000 { 823 compatible = "rockchip,rk3588-qos", "syscon"; 824 reg = <0x0 0xfdf35000 0x0 0x20>; 825 }; 826 827 qos_gpu_m1: qos@fdf35200 { 828 compatible = "rockchip,rk3588-qos", "syscon"; 829 reg = <0x0 0xfdf35200 0x0 0x20>; 830 }; 831 832 qos_gpu_m2: qos@fdf35400 { 833 compatible = "rockchip,rk3588-qos", "syscon"; 834 reg = <0x0 0xfdf35400 0x0 0x20>; 835 }; 836 837 qos_gpu_m3: qos@fdf35600 { 838 compatible = "rockchip,rk3588-qos", "syscon"; 839 reg = <0x0 0xfdf35600 0x0 0x20>; 840 }; 841 842 qos_rga3_1: qos@fdf36000 { 843 compatible = "rockchip,rk3588-qos", "syscon"; 844 reg = <0x0 0xfdf36000 0x0 0x20>; 845 }; 846 847 qos_sdio: qos@fdf39000 { 848 compatible = "rockchip,rk3588-qos", "syscon"; 849 reg = <0x0 0xfdf39000 0x0 0x20>; 850 }; 851 852 qos_sdmmc: qos@fdf3d800 { 853 compatible = "rockchip,rk3588-qos", "syscon"; 854 reg = <0x0 0xfdf3d800 0x0 0x20>; 855 }; 856 857 qos_usb3_1: qos@fdf3e000 { 858 compatible = "rockchip,rk3588-qos", "syscon"; 859 reg = <0x0 0xfdf3e000 0x0 0x20>; 860 }; 861 862 qos_usb3_0: qos@fdf3e200 { 863 compatible = "rockchip,rk3588-qos", "syscon"; 864 reg = <0x0 0xfdf3e200 0x0 0x20>; 865 }; 866 867 qos_usb2host_0: qos@fdf3e400 { 868 compatible = "rockchip,rk3588-qos", "syscon"; 869 reg = <0x0 0xfdf3e400 0x0 0x20>; 870 }; 871 872 qos_usb2host_1: qos@fdf3e600 { 873 compatible = "rockchip,rk3588-qos", "syscon"; 874 reg = <0x0 0xfdf3e600 0x0 0x20>; 875 }; 876 877 qos_fisheye0: qos@fdf40000 { 878 compatible = "rockchip,rk3588-qos", "syscon"; 879 reg = <0x0 0xfdf40000 0x0 0x20>; 880 }; 881 882 qos_fisheye1: qos@fdf40200 { 883 compatible = "rockchip,rk3588-qos", "syscon"; 884 reg = <0x0 0xfdf40200 0x0 0x20>; 885 }; 886 887 qos_isp0_mro: qos@fdf40400 { 888 compatible = "rockchip,rk3588-qos", "syscon"; 889 reg = <0x0 0xfdf40400 0x0 0x20>; 890 }; 891 892 qos_isp0_mwo: qos@fdf40500 { 893 compatible = "rockchip,rk3588-qos", "syscon"; 894 reg = <0x0 0xfdf40500 0x0 0x20>; 895 }; 896 897 qos_vicap_m0: qos@fdf40600 { 898 compatible = "rockchip,rk3588-qos", "syscon"; 899 reg = <0x0 0xfdf40600 0x0 0x20>; 900 }; 901 902 qos_vicap_m1: qos@fdf40800 { 903 compatible = "rockchip,rk3588-qos", "syscon"; 904 reg = <0x0 0xfdf40800 0x0 0x20>; 905 }; 906 907 qos_isp1_mwo: qos@fdf41000 { 908 compatible = "rockchip,rk3588-qos", "syscon"; 909 reg = <0x0 0xfdf41000 0x0 0x20>; 910 }; 911 912 qos_isp1_mro: qos@fdf41100 { 913 compatible = "rockchip,rk3588-qos", "syscon"; 914 reg = <0x0 0xfdf41100 0x0 0x20>; 915 }; 916 917 qos_rkvenc0_m0ro: qos@fdf60000 { 918 compatible = "rockchip,rk3588-qos", "syscon"; 919 reg = <0x0 0xfdf60000 0x0 0x20>; 920 }; 921 922 qos_rkvenc0_m1ro: qos@fdf60200 { 923 compatible = "rockchip,rk3588-qos", "syscon"; 924 reg = <0x0 0xfdf60200 0x0 0x20>; 925 }; 926 927 qos_rkvenc0_m2wo: qos@fdf60400 { 928 compatible = "rockchip,rk3588-qos", "syscon"; 929 reg = <0x0 0xfdf60400 0x0 0x20>; 930 }; 931 932 qos_rkvenc1_m0ro: qos@fdf61000 { 933 compatible = "rockchip,rk3588-qos", "syscon"; 934 reg = <0x0 0xfdf61000 0x0 0x20>; 935 }; 936 937 qos_rkvenc1_m1ro: qos@fdf61200 { 938 compatible = "rockchip,rk3588-qos", "syscon"; 939 reg = <0x0 0xfdf61200 0x0 0x20>; 940 }; 941 942 qos_rkvenc1_m2wo: qos@fdf61400 { 943 compatible = "rockchip,rk3588-qos", "syscon"; 944 reg = <0x0 0xfdf61400 0x0 0x20>; 945 }; 946 947 qos_rkvdec0: qos@fdf62000 { 948 compatible = "rockchip,rk3588-qos", "syscon"; 949 reg = <0x0 0xfdf62000 0x0 0x20>; 950 }; 951 952 qos_rkvdec1: qos@fdf63000 { 953 compatible = "rockchip,rk3588-qos", "syscon"; 954 reg = <0x0 0xfdf63000 0x0 0x20>; 955 }; 956 957 qos_av1: qos@fdf64000 { 958 compatible = "rockchip,rk3588-qos", "syscon"; 959 reg = <0x0 0xfdf64000 0x0 0x20>; 960 }; 961 962 qos_iep: qos@fdf66000 { 963 compatible = "rockchip,rk3588-qos", "syscon"; 964 reg = <0x0 0xfdf66000 0x0 0x20>; 965 }; 966 967 qos_jpeg_dec: qos@fdf66200 { 968 compatible = "rockchip,rk3588-qos", "syscon"; 969 reg = <0x0 0xfdf66200 0x0 0x20>; 970 }; 971 972 qos_jpeg_enc0: qos@fdf66400 { 973 compatible = "rockchip,rk3588-qos", "syscon"; 974 reg = <0x0 0xfdf66400 0x0 0x20>; 975 }; 976 977 qos_jpeg_enc1: qos@fdf66600 { 978 compatible = "rockchip,rk3588-qos", "syscon"; 979 reg = <0x0 0xfdf66600 0x0 0x20>; 980 }; 981 982 qos_jpeg_enc2: qos@fdf66800 { 983 compatible = "rockchip,rk3588-qos", "syscon"; 984 reg = <0x0 0xfdf66800 0x0 0x20>; 985 }; 986 987 qos_jpeg_enc3: qos@fdf66a00 { 988 compatible = "rockchip,rk3588-qos", "syscon"; 989 reg = <0x0 0xfdf66a00 0x0 0x20>; 990 }; 991 992 qos_rga2_mro: qos@fdf66c00 { 993 compatible = "rockchip,rk3588-qos", "syscon"; 994 reg = <0x0 0xfdf66c00 0x0 0x20>; 995 }; 996 997 qos_rga2_mwo: qos@fdf66e00 { 998 compatible = "rockchip,rk3588-qos", "syscon"; 999 reg = <0x0 0xfdf66e00 0x0 0x20>; 1000 }; 1001 1002 qos_rga3_0: qos@fdf67000 { 1003 compatible = "rockchip,rk3588-qos", "syscon"; 1004 reg = <0x0 0xfdf67000 0x0 0x20>; 1005 }; 1006 1007 qos_vdpu: qos@fdf67200 { 1008 compatible = "rockchip,rk3588-qos", "syscon"; 1009 reg = <0x0 0xfdf67200 0x0 0x20>; 1010 }; 1011 1012 qos_npu1: qos@fdf70000 { 1013 compatible = "rockchip,rk3588-qos", "syscon"; 1014 reg = <0x0 0xfdf70000 0x0 0x20>; 1015 }; 1016 1017 qos_npu2: qos@fdf71000 { 1018 compatible = "rockchip,rk3588-qos", "syscon"; 1019 reg = <0x0 0xfdf71000 0x0 0x20>; 1020 }; 1021 1022 qos_npu0_mwr: qos@fdf72000 { 1023 compatible = "rockchip,rk3588-qos", "syscon"; 1024 reg = <0x0 0xfdf72000 0x0 0x20>; 1025 }; 1026 1027 qos_npu0_mro: qos@fdf72200 { 1028 compatible = "rockchip,rk3588-qos", "syscon"; 1029 reg = <0x0 0xfdf72200 0x0 0x20>; 1030 }; 1031 1032 qos_mcu_npu: qos@fdf72400 { 1033 compatible = "rockchip,rk3588-qos", "syscon"; 1034 reg = <0x0 0xfdf72400 0x0 0x20>; 1035 }; 1036 1037 qos_hdcp0: qos@fdf80000 { 1038 compatible = "rockchip,rk3588-qos", "syscon"; 1039 reg = <0x0 0xfdf80000 0x0 0x20>; 1040 }; 1041 1042 qos_hdcp1: qos@fdf81000 { 1043 compatible = "rockchip,rk3588-qos", "syscon"; 1044 reg = <0x0 0xfdf81000 0x0 0x20>; 1045 }; 1046 1047 qos_hdmirx: qos@fdf81200 { 1048 compatible = "rockchip,rk3588-qos", "syscon"; 1049 reg = <0x0 0xfdf81200 0x0 0x20>; 1050 }; 1051 1052 qos_vop_m0: qos@fdf82000 { 1053 compatible = "rockchip,rk3588-qos", "syscon"; 1054 reg = <0x0 0xfdf82000 0x0 0x20>; 1055 }; 1056 1057 qos_vop_m1: qos@fdf82200 { 1058 compatible = "rockchip,rk3588-qos", "syscon"; 1059 reg = <0x0 0xfdf82200 0x0 0x20>; 1060 }; 1061 1062 gmac1: ethernet@fe1c0000 { 1063 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 1064 reg = <0x0 0xfe1c0000 0x0 0x10000>; 1065 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>, 1066 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 1067 interrupt-names = "macirq", "eth_wake_irq"; 1068 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, 1069 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, 1070 <&cru CLK_GMAC1_PTP_REF>; 1071 clock-names = "stmmaceth", "clk_mac_ref", 1072 "pclk_mac", "aclk_mac", 1073 "ptp_ref"; 1074 power-domains = <&power RK3588_PD_GMAC>; 1075 resets = <&cru SRST_A_GMAC1>; 1076 reset-names = "stmmaceth"; 1077 rockchip,grf = <&sys_grf>; 1078 rockchip,php-grf = <&php_grf>; 1079 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1080 snps,mixed-burst; 1081 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1082 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1083 snps,tso; 1084 status = "disabled"; 1085 1086 mdio1: mdio { 1087 compatible = "snps,dwmac-mdio"; 1088 #address-cells = <0x1>; 1089 #size-cells = <0x0>; 1090 }; 1091 1092 gmac1_stmmac_axi_setup: stmmac-axi-config { 1093 snps,blen = <0 0 0 0 16 8 4>; 1094 snps,wr_osr_lmt = <4>; 1095 snps,rd_osr_lmt = <8>; 1096 }; 1097 1098 gmac1_mtl_rx_setup: rx-queues-config { 1099 snps,rx-queues-to-use = <2>; 1100 queue0 {}; 1101 queue1 {}; 1102 }; 1103 1104 gmac1_mtl_tx_setup: tx-queues-config { 1105 snps,tx-queues-to-use = <2>; 1106 queue0 {}; 1107 queue1 {}; 1108 }; 1109 }; 1110 1111 sdhci: mmc@fe2e0000 { 1112 compatible = "rockchip,rk3588-dwcmshc"; 1113 reg = <0x0 0xfe2e0000 0x0 0x10000>; 1114 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 1115 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; 1116 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 1117 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1118 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1119 <&cru TMCLK_EMMC>; 1120 clock-names = "core", "bus", "axi", "block", "timer"; 1121 max-frequency = <200000000>; 1122 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 1123 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 1124 <&cru SRST_T_EMMC>; 1125 reset-names = "core", "bus", "axi", "block", "timer"; 1126 status = "disabled"; 1127 }; 1128 1129 gic: interrupt-controller@fe600000 { 1130 compatible = "arm,gic-v3"; 1131 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ 1132 <0x0 0xfe680000 0 0x100000>; /* GICR */ 1133 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 1134 interrupt-controller; 1135 mbi-alias = <0x0 0xfe610000>; 1136 mbi-ranges = <424 56>; 1137 msi-controller; 1138 #interrupt-cells = <4>; 1139 1140 ppi-partitions { 1141 ppi_partition0: interrupt-partition-0 { 1142 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 1143 }; 1144 1145 ppi_partition1: interrupt-partition-1 { 1146 affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; 1147 }; 1148 }; 1149 }; 1150 1151 dmac0: dma-controller@fea10000 { 1152 compatible = "arm,pl330", "arm,primecell"; 1153 reg = <0x0 0xfea10000 0x0 0x4000>; 1154 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>, 1155 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>; 1156 arm,pl330-periph-burst; 1157 clocks = <&cru ACLK_DMAC0>; 1158 clock-names = "apb_pclk"; 1159 #dma-cells = <1>; 1160 }; 1161 1162 dmac1: dma-controller@fea30000 { 1163 compatible = "arm,pl330", "arm,primecell"; 1164 reg = <0x0 0xfea30000 0x0 0x4000>; 1165 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>, 1166 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>; 1167 arm,pl330-periph-burst; 1168 clocks = <&cru ACLK_DMAC1>; 1169 clock-names = "apb_pclk"; 1170 #dma-cells = <1>; 1171 }; 1172 1173 i2c1: i2c@fea90000 { 1174 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1175 reg = <0x0 0xfea90000 0x0 0x1000>; 1176 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1177 clock-names = "i2c", "pclk"; 1178 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>; 1179 pinctrl-0 = <&i2c1m0_xfer>; 1180 pinctrl-names = "default"; 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 status = "disabled"; 1184 }; 1185 1186 i2c2: i2c@feaa0000 { 1187 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1188 reg = <0x0 0xfeaa0000 0x0 0x1000>; 1189 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1190 clock-names = "i2c", "pclk"; 1191 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>; 1192 pinctrl-0 = <&i2c2m0_xfer>; 1193 pinctrl-names = "default"; 1194 #address-cells = <1>; 1195 #size-cells = <0>; 1196 status = "disabled"; 1197 }; 1198 1199 i2c3: i2c@feab0000 { 1200 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1201 reg = <0x0 0xfeab0000 0x0 0x1000>; 1202 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1203 clock-names = "i2c", "pclk"; 1204 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>; 1205 pinctrl-0 = <&i2c3m0_xfer>; 1206 pinctrl-names = "default"; 1207 #address-cells = <1>; 1208 #size-cells = <0>; 1209 status = "disabled"; 1210 }; 1211 1212 i2c4: i2c@feac0000 { 1213 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1214 reg = <0x0 0xfeac0000 0x0 0x1000>; 1215 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1216 clock-names = "i2c", "pclk"; 1217 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>; 1218 pinctrl-0 = <&i2c4m0_xfer>; 1219 pinctrl-names = "default"; 1220 #address-cells = <1>; 1221 #size-cells = <0>; 1222 status = "disabled"; 1223 }; 1224 1225 i2c5: i2c@fead0000 { 1226 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1227 reg = <0x0 0xfead0000 0x0 0x1000>; 1228 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1229 clock-names = "i2c", "pclk"; 1230 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>; 1231 pinctrl-0 = <&i2c5m0_xfer>; 1232 pinctrl-names = "default"; 1233 #address-cells = <1>; 1234 #size-cells = <0>; 1235 status = "disabled"; 1236 }; 1237 1238 spi0: spi@feb00000 { 1239 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1240 reg = <0x0 0xfeb00000 0x0 0x1000>; 1241 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>; 1242 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 1243 clock-names = "spiclk", "apb_pclk"; 1244 dmas = <&dmac0 14>, <&dmac0 15>; 1245 dma-names = "tx", "rx"; 1246 num-cs = <2>; 1247 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 1248 pinctrl-names = "default"; 1249 #address-cells = <1>; 1250 #size-cells = <0>; 1251 status = "disabled"; 1252 }; 1253 1254 spi1: spi@feb10000 { 1255 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1256 reg = <0x0 0xfeb10000 0x0 0x1000>; 1257 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>; 1258 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1259 clock-names = "spiclk", "apb_pclk"; 1260 dmas = <&dmac0 16>, <&dmac0 17>; 1261 dma-names = "tx", "rx"; 1262 num-cs = <2>; 1263 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; 1264 pinctrl-names = "default"; 1265 #address-cells = <1>; 1266 #size-cells = <0>; 1267 status = "disabled"; 1268 }; 1269 1270 spi2: spi@feb20000 { 1271 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1272 reg = <0x0 0xfeb20000 0x0 0x1000>; 1273 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>; 1274 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 1275 clock-names = "spiclk", "apb_pclk"; 1276 dmas = <&dmac1 15>, <&dmac1 16>; 1277 dma-names = "tx", "rx"; 1278 num-cs = <2>; 1279 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; 1280 pinctrl-names = "default"; 1281 #address-cells = <1>; 1282 #size-cells = <0>; 1283 status = "disabled"; 1284 }; 1285 1286 spi3: spi@feb30000 { 1287 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1288 reg = <0x0 0xfeb30000 0x0 0x1000>; 1289 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>; 1290 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 1291 clock-names = "spiclk", "apb_pclk"; 1292 dmas = <&dmac1 17>, <&dmac1 18>; 1293 dma-names = "tx", "rx"; 1294 num-cs = <2>; 1295 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; 1296 pinctrl-names = "default"; 1297 #address-cells = <1>; 1298 #size-cells = <0>; 1299 status = "disabled"; 1300 }; 1301 1302 uart1: serial@feb40000 { 1303 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1304 reg = <0x0 0xfeb40000 0x0 0x100>; 1305 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>; 1306 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1307 clock-names = "baudclk", "apb_pclk"; 1308 dmas = <&dmac0 8>, <&dmac0 9>; 1309 dma-names = "tx", "rx"; 1310 pinctrl-0 = <&uart1m1_xfer>; 1311 pinctrl-names = "default"; 1312 reg-io-width = <4>; 1313 reg-shift = <2>; 1314 status = "disabled"; 1315 }; 1316 1317 uart2: serial@feb50000 { 1318 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1319 reg = <0x0 0xfeb50000 0x0 0x100>; 1320 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>; 1321 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1322 clock-names = "baudclk", "apb_pclk"; 1323 dmas = <&dmac0 10>, <&dmac0 11>; 1324 dma-names = "tx", "rx"; 1325 pinctrl-0 = <&uart2m1_xfer>; 1326 pinctrl-names = "default"; 1327 reg-io-width = <4>; 1328 reg-shift = <2>; 1329 status = "disabled"; 1330 }; 1331 1332 uart3: serial@feb60000 { 1333 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1334 reg = <0x0 0xfeb60000 0x0 0x100>; 1335 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>; 1336 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1337 clock-names = "baudclk", "apb_pclk"; 1338 dmas = <&dmac0 12>, <&dmac0 13>; 1339 dma-names = "tx", "rx"; 1340 pinctrl-0 = <&uart3m1_xfer>; 1341 pinctrl-names = "default"; 1342 reg-io-width = <4>; 1343 reg-shift = <2>; 1344 status = "disabled"; 1345 }; 1346 1347 uart4: serial@feb70000 { 1348 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1349 reg = <0x0 0xfeb70000 0x0 0x100>; 1350 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>; 1351 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1352 clock-names = "baudclk", "apb_pclk"; 1353 dmas = <&dmac1 9>, <&dmac1 10>; 1354 dma-names = "tx", "rx"; 1355 pinctrl-0 = <&uart4m1_xfer>; 1356 pinctrl-names = "default"; 1357 reg-io-width = <4>; 1358 reg-shift = <2>; 1359 status = "disabled"; 1360 }; 1361 1362 uart5: serial@feb80000 { 1363 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1364 reg = <0x0 0xfeb80000 0x0 0x100>; 1365 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>; 1366 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1367 clock-names = "baudclk", "apb_pclk"; 1368 dmas = <&dmac1 11>, <&dmac1 12>; 1369 dma-names = "tx", "rx"; 1370 pinctrl-0 = <&uart5m1_xfer>; 1371 pinctrl-names = "default"; 1372 reg-io-width = <4>; 1373 reg-shift = <2>; 1374 status = "disabled"; 1375 }; 1376 1377 uart6: serial@feb90000 { 1378 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1379 reg = <0x0 0xfeb90000 0x0 0x100>; 1380 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>; 1381 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1382 clock-names = "baudclk", "apb_pclk"; 1383 dmas = <&dmac1 13>, <&dmac1 14>; 1384 dma-names = "tx", "rx"; 1385 pinctrl-0 = <&uart6m1_xfer>; 1386 pinctrl-names = "default"; 1387 reg-io-width = <4>; 1388 reg-shift = <2>; 1389 status = "disabled"; 1390 }; 1391 1392 uart7: serial@feba0000 { 1393 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1394 reg = <0x0 0xfeba0000 0x0 0x100>; 1395 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>; 1396 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1397 clock-names = "baudclk", "apb_pclk"; 1398 dmas = <&dmac2 7>, <&dmac2 8>; 1399 dma-names = "tx", "rx"; 1400 pinctrl-0 = <&uart7m1_xfer>; 1401 pinctrl-names = "default"; 1402 reg-io-width = <4>; 1403 reg-shift = <2>; 1404 status = "disabled"; 1405 }; 1406 1407 uart8: serial@febb0000 { 1408 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1409 reg = <0x0 0xfebb0000 0x0 0x100>; 1410 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>; 1411 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 1412 clock-names = "baudclk", "apb_pclk"; 1413 dmas = <&dmac2 9>, <&dmac2 10>; 1414 dma-names = "tx", "rx"; 1415 pinctrl-0 = <&uart8m1_xfer>; 1416 pinctrl-names = "default"; 1417 reg-io-width = <4>; 1418 reg-shift = <2>; 1419 status = "disabled"; 1420 }; 1421 1422 uart9: serial@febc0000 { 1423 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1424 reg = <0x0 0xfebc0000 0x0 0x100>; 1425 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>; 1426 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 1427 clock-names = "baudclk", "apb_pclk"; 1428 dmas = <&dmac2 11>, <&dmac2 12>; 1429 dma-names = "tx", "rx"; 1430 pinctrl-0 = <&uart9m1_xfer>; 1431 pinctrl-names = "default"; 1432 reg-io-width = <4>; 1433 reg-shift = <2>; 1434 status = "disabled"; 1435 }; 1436 1437 pwm4: pwm@febd0000 { 1438 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1439 reg = <0x0 0xfebd0000 0x0 0x10>; 1440 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1441 clock-names = "pwm", "pclk"; 1442 pinctrl-0 = <&pwm4m0_pins>; 1443 pinctrl-names = "default"; 1444 #pwm-cells = <3>; 1445 status = "disabled"; 1446 }; 1447 1448 pwm5: pwm@febd0010 { 1449 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1450 reg = <0x0 0xfebd0010 0x0 0x10>; 1451 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1452 clock-names = "pwm", "pclk"; 1453 pinctrl-0 = <&pwm5m0_pins>; 1454 pinctrl-names = "default"; 1455 #pwm-cells = <3>; 1456 status = "disabled"; 1457 }; 1458 1459 pwm6: pwm@febd0020 { 1460 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1461 reg = <0x0 0xfebd0020 0x0 0x10>; 1462 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1463 clock-names = "pwm", "pclk"; 1464 pinctrl-0 = <&pwm6m0_pins>; 1465 pinctrl-names = "default"; 1466 #pwm-cells = <3>; 1467 status = "disabled"; 1468 }; 1469 1470 pwm7: pwm@febd0030 { 1471 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1472 reg = <0x0 0xfebd0030 0x0 0x10>; 1473 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1474 clock-names = "pwm", "pclk"; 1475 pinctrl-0 = <&pwm7m0_pins>; 1476 pinctrl-names = "default"; 1477 #pwm-cells = <3>; 1478 status = "disabled"; 1479 }; 1480 1481 pwm8: pwm@febe0000 { 1482 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1483 reg = <0x0 0xfebe0000 0x0 0x10>; 1484 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1485 clock-names = "pwm", "pclk"; 1486 pinctrl-0 = <&pwm8m0_pins>; 1487 pinctrl-names = "default"; 1488 #pwm-cells = <3>; 1489 status = "disabled"; 1490 }; 1491 1492 pwm9: pwm@febe0010 { 1493 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1494 reg = <0x0 0xfebe0010 0x0 0x10>; 1495 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1496 clock-names = "pwm", "pclk"; 1497 pinctrl-0 = <&pwm9m0_pins>; 1498 pinctrl-names = "default"; 1499 #pwm-cells = <3>; 1500 status = "disabled"; 1501 }; 1502 1503 pwm10: pwm@febe0020 { 1504 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1505 reg = <0x0 0xfebe0020 0x0 0x10>; 1506 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1507 clock-names = "pwm", "pclk"; 1508 pinctrl-0 = <&pwm10m0_pins>; 1509 pinctrl-names = "default"; 1510 #pwm-cells = <3>; 1511 status = "disabled"; 1512 }; 1513 1514 pwm11: pwm@febe0030 { 1515 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1516 reg = <0x0 0xfebe0030 0x0 0x10>; 1517 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1518 clock-names = "pwm", "pclk"; 1519 pinctrl-0 = <&pwm11m0_pins>; 1520 pinctrl-names = "default"; 1521 #pwm-cells = <3>; 1522 status = "disabled"; 1523 }; 1524 1525 pwm12: pwm@febf0000 { 1526 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1527 reg = <0x0 0xfebf0000 0x0 0x10>; 1528 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1529 clock-names = "pwm", "pclk"; 1530 pinctrl-0 = <&pwm12m0_pins>; 1531 pinctrl-names = "default"; 1532 #pwm-cells = <3>; 1533 status = "disabled"; 1534 }; 1535 1536 pwm13: pwm@febf0010 { 1537 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1538 reg = <0x0 0xfebf0010 0x0 0x10>; 1539 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1540 clock-names = "pwm", "pclk"; 1541 pinctrl-0 = <&pwm13m0_pins>; 1542 pinctrl-names = "default"; 1543 #pwm-cells = <3>; 1544 status = "disabled"; 1545 }; 1546 1547 pwm14: pwm@febf0020 { 1548 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1549 reg = <0x0 0xfebf0020 0x0 0x10>; 1550 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1551 clock-names = "pwm", "pclk"; 1552 pinctrl-0 = <&pwm14m0_pins>; 1553 pinctrl-names = "default"; 1554 #pwm-cells = <3>; 1555 status = "disabled"; 1556 }; 1557 1558 pwm15: pwm@febf0030 { 1559 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1560 reg = <0x0 0xfebf0030 0x0 0x10>; 1561 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1562 clock-names = "pwm", "pclk"; 1563 pinctrl-0 = <&pwm15m0_pins>; 1564 pinctrl-names = "default"; 1565 #pwm-cells = <3>; 1566 status = "disabled"; 1567 }; 1568 1569 i2c6: i2c@fec80000 { 1570 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1571 reg = <0x0 0xfec80000 0x0 0x1000>; 1572 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 1573 clock-names = "i2c", "pclk"; 1574 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>; 1575 pinctrl-0 = <&i2c6m0_xfer>; 1576 pinctrl-names = "default"; 1577 #address-cells = <1>; 1578 #size-cells = <0>; 1579 status = "disabled"; 1580 }; 1581 1582 i2c7: i2c@fec90000 { 1583 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1584 reg = <0x0 0xfec90000 0x0 0x1000>; 1585 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 1586 clock-names = "i2c", "pclk"; 1587 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; 1588 pinctrl-0 = <&i2c7m0_xfer>; 1589 pinctrl-names = "default"; 1590 #address-cells = <1>; 1591 #size-cells = <0>; 1592 status = "disabled"; 1593 }; 1594 1595 i2c8: i2c@feca0000 { 1596 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1597 reg = <0x0 0xfeca0000 0x0 0x1000>; 1598 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 1599 clock-names = "i2c", "pclk"; 1600 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>; 1601 pinctrl-0 = <&i2c8m0_xfer>; 1602 pinctrl-names = "default"; 1603 #address-cells = <1>; 1604 #size-cells = <0>; 1605 status = "disabled"; 1606 }; 1607 1608 spi4: spi@fecb0000 { 1609 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1610 reg = <0x0 0xfecb0000 0x0 0x1000>; 1611 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>; 1612 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 1613 clock-names = "spiclk", "apb_pclk"; 1614 dmas = <&dmac2 13>, <&dmac2 14>; 1615 dma-names = "tx", "rx"; 1616 num-cs = <2>; 1617 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; 1618 pinctrl-names = "default"; 1619 #address-cells = <1>; 1620 #size-cells = <0>; 1621 status = "disabled"; 1622 }; 1623 1624 dmac2: dma-controller@fed10000 { 1625 compatible = "arm,pl330", "arm,primecell"; 1626 reg = <0x0 0xfed10000 0x0 0x4000>; 1627 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>, 1628 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>; 1629 arm,pl330-periph-burst; 1630 clocks = <&cru ACLK_DMAC2>; 1631 clock-names = "apb_pclk"; 1632 #dma-cells = <1>; 1633 }; 1634 1635 system_sram2: sram@ff001000 { 1636 compatible = "mmio-sram"; 1637 reg = <0x0 0xff001000 0x0 0xef000>; 1638 ranges = <0x0 0x0 0xff001000 0xef000>; 1639 #address-cells = <1>; 1640 #size-cells = <1>; 1641 }; 1642 1643 pinctrl: pinctrl { 1644 compatible = "rockchip,rk3588-pinctrl"; 1645 ranges; 1646 rockchip,grf = <&ioc>; 1647 #address-cells = <2>; 1648 #size-cells = <2>; 1649 1650 gpio0: gpio@fd8a0000 { 1651 compatible = "rockchip,gpio-bank"; 1652 reg = <0x0 0xfd8a0000 0x0 0x100>; 1653 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 1654 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 1655 gpio-controller; 1656 gpio-ranges = <&pinctrl 0 0 32>; 1657 interrupt-controller; 1658 #gpio-cells = <2>; 1659 #interrupt-cells = <2>; 1660 }; 1661 1662 gpio1: gpio@fec20000 { 1663 compatible = "rockchip,gpio-bank"; 1664 reg = <0x0 0xfec20000 0x0 0x100>; 1665 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>; 1666 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1667 gpio-controller; 1668 gpio-ranges = <&pinctrl 0 32 32>; 1669 interrupt-controller; 1670 #gpio-cells = <2>; 1671 #interrupt-cells = <2>; 1672 }; 1673 1674 gpio2: gpio@fec30000 { 1675 compatible = "rockchip,gpio-bank"; 1676 reg = <0x0 0xfec30000 0x0 0x100>; 1677 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>; 1678 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1679 gpio-controller; 1680 gpio-ranges = <&pinctrl 0 64 32>; 1681 interrupt-controller; 1682 #gpio-cells = <2>; 1683 #interrupt-cells = <2>; 1684 }; 1685 1686 gpio3: gpio@fec40000 { 1687 compatible = "rockchip,gpio-bank"; 1688 reg = <0x0 0xfec40000 0x0 0x100>; 1689 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>; 1690 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1691 gpio-controller; 1692 gpio-ranges = <&pinctrl 0 96 32>; 1693 interrupt-controller; 1694 #gpio-cells = <2>; 1695 #interrupt-cells = <2>; 1696 }; 1697 1698 gpio4: gpio@fec50000 { 1699 compatible = "rockchip,gpio-bank"; 1700 reg = <0x0 0xfec50000 0x0 0x100>; 1701 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>; 1702 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1703 gpio-controller; 1704 gpio-ranges = <&pinctrl 0 128 32>; 1705 interrupt-controller; 1706 #gpio-cells = <2>; 1707 #interrupt-cells = <2>; 1708 }; 1709 }; 1710}; 1711 1712#include "rk3588s-pinctrl.dtsi" 1713