1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include "rk3588s.dtsi" 7#include "rk3588-pinctrl.dtsi" 8 9/ { 10 i2s8_8ch: i2s@fddc8000 { 11 compatible = "rockchip,rk3588-i2s-tdm"; 12 reg = <0x0 0xfddc8000 0x0 0x1000>; 13 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>; 14 clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; 15 clock-names = "mclk_tx", "mclk_rx", "hclk"; 16 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; 17 assigned-clock-parents = <&cru PLL_AUPLL>; 18 dmas = <&dmac2 22>; 19 dma-names = "tx"; 20 power-domains = <&power RK3588_PD_VO0>; 21 resets = <&cru SRST_M_I2S8_8CH_TX>; 22 reset-names = "tx-m"; 23 #sound-dai-cells = <0>; 24 status = "disabled"; 25 }; 26 27 i2s6_8ch: i2s@fddf4000 { 28 compatible = "rockchip,rk3588-i2s-tdm"; 29 reg = <0x0 0xfddf4000 0x0 0x1000>; 30 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; 31 clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; 32 clock-names = "mclk_tx", "mclk_rx", "hclk"; 33 assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; 34 assigned-clock-parents = <&cru PLL_AUPLL>; 35 dmas = <&dmac2 4>; 36 dma-names = "tx"; 37 power-domains = <&power RK3588_PD_VO1>; 38 resets = <&cru SRST_M_I2S6_8CH_TX>; 39 reset-names = "tx-m"; 40 #sound-dai-cells = <0>; 41 status = "disabled"; 42 }; 43 44 i2s7_8ch: i2s@fddf8000 { 45 compatible = "rockchip,rk3588-i2s-tdm"; 46 reg = <0x0 0xfddf8000 0x0 0x1000>; 47 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>; 48 clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; 49 clock-names = "mclk_tx", "mclk_rx", "hclk"; 50 assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; 51 assigned-clock-parents = <&cru PLL_AUPLL>; 52 dmas = <&dmac2 21>; 53 dma-names = "rx"; 54 power-domains = <&power RK3588_PD_VO1>; 55 resets = <&cru SRST_M_I2S7_8CH_RX>; 56 reset-names = "rx-m"; 57 #sound-dai-cells = <0>; 58 status = "disabled"; 59 }; 60 61 i2s10_8ch: i2s@fde00000 { 62 compatible = "rockchip,rk3588-i2s-tdm"; 63 reg = <0x0 0xfde00000 0x0 0x1000>; 64 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>; 65 clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; 66 clock-names = "mclk_tx", "mclk_rx", "hclk"; 67 assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; 68 assigned-clock-parents = <&cru PLL_AUPLL>; 69 dmas = <&dmac2 24>; 70 dma-names = "rx"; 71 power-domains = <&power RK3588_PD_VO1>; 72 resets = <&cru SRST_M_I2S10_8CH_RX>; 73 reset-names = "rx-m"; 74 #sound-dai-cells = <0>; 75 status = "disabled"; 76 }; 77 78 gmac0: ethernet@fe1b0000 { 79 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 80 reg = <0x0 0xfe1b0000 0x0 0x10000>; 81 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>, 82 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 83 interrupt-names = "macirq", "eth_wake_irq"; 84 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, 85 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, 86 <&cru CLK_GMAC0_PTP_REF>; 87 clock-names = "stmmaceth", "clk_mac_ref", 88 "pclk_mac", "aclk_mac", 89 "ptp_ref"; 90 power-domains = <&power RK3588_PD_GMAC>; 91 resets = <&cru SRST_A_GMAC0>; 92 reset-names = "stmmaceth"; 93 rockchip,grf = <&sys_grf>; 94 rockchip,php-grf = <&php_grf>; 95 snps,axi-config = <&gmac0_stmmac_axi_setup>; 96 snps,mixed-burst; 97 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 98 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 99 snps,tso; 100 status = "disabled"; 101 102 mdio0: mdio { 103 compatible = "snps,dwmac-mdio"; 104 #address-cells = <0x1>; 105 #size-cells = <0x0>; 106 }; 107 108 gmac0_stmmac_axi_setup: stmmac-axi-config { 109 snps,blen = <0 0 0 0 16 8 4>; 110 snps,wr_osr_lmt = <4>; 111 snps,rd_osr_lmt = <8>; 112 }; 113 114 gmac0_mtl_rx_setup: rx-queues-config { 115 snps,rx-queues-to-use = <2>; 116 queue0 {}; 117 queue1 {}; 118 }; 119 120 gmac0_mtl_tx_setup: tx-queues-config { 121 snps,tx-queues-to-use = <2>; 122 queue0 {}; 123 queue1 {}; 124 }; 125 }; 126}; 127