1a1d32814SChristopher Obbard// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2a1d32814SChristopher Obbard 3a1d32814SChristopher Obbard/dts-v1/; 4a1d32814SChristopher Obbard 5a1d32814SChristopher Obbard#include "rk3588.dtsi" 6a1d32814SChristopher Obbard 7a1d32814SChristopher Obbard/ { 8a1d32814SChristopher Obbard model = "Radxa ROCK 5 Model B"; 9a1d32814SChristopher Obbard compatible = "radxa,rock-5b", "rockchip,rk3588"; 10a1d32814SChristopher Obbard 11a1d32814SChristopher Obbard aliases { 126fb13f88SChristopher Obbard mmc0 = &sdhci; 13a1d32814SChristopher Obbard serial2 = &uart2; 14a1d32814SChristopher Obbard }; 15a1d32814SChristopher Obbard 16a1d32814SChristopher Obbard chosen { 17a1d32814SChristopher Obbard stdout-path = "serial2:1500000n8"; 18a1d32814SChristopher Obbard }; 19a1d32814SChristopher Obbard 20a1d32814SChristopher Obbard vcc5v0_sys: vcc5v0-sys-regulator { 21a1d32814SChristopher Obbard compatible = "regulator-fixed"; 22a1d32814SChristopher Obbard regulator-name = "vcc5v0_sys"; 23a1d32814SChristopher Obbard regulator-always-on; 24a1d32814SChristopher Obbard regulator-boot-on; 25a1d32814SChristopher Obbard regulator-min-microvolt = <5000000>; 26a1d32814SChristopher Obbard regulator-max-microvolt = <5000000>; 27a1d32814SChristopher Obbard }; 28a1d32814SChristopher Obbard}; 29a1d32814SChristopher Obbard 30*1e9c2404SShreeya Patel&i2c6 { 31*1e9c2404SShreeya Patel status = "okay"; 32*1e9c2404SShreeya Patel 33*1e9c2404SShreeya Patel hym8563: rtc@51 { 34*1e9c2404SShreeya Patel compatible = "haoyu,hym8563"; 35*1e9c2404SShreeya Patel reg = <0x51>; 36*1e9c2404SShreeya Patel #clock-cells = <0>; 37*1e9c2404SShreeya Patel clock-frequency = <32768>; 38*1e9c2404SShreeya Patel clock-output-names = "hym8563"; 39*1e9c2404SShreeya Patel pinctrl-names = "default"; 40*1e9c2404SShreeya Patel pinctrl-0 = <&hym8563_int>; 41*1e9c2404SShreeya Patel interrupt-parent = <&gpio0>; 42*1e9c2404SShreeya Patel interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; 43*1e9c2404SShreeya Patel wakeup-source; 44*1e9c2404SShreeya Patel }; 45*1e9c2404SShreeya Patel}; 46*1e9c2404SShreeya Patel 47*1e9c2404SShreeya Patel&pinctrl { 48*1e9c2404SShreeya Patel hym8563 { 49*1e9c2404SShreeya Patel hym8563_int: hym8563-int { 50*1e9c2404SShreeya Patel rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 51*1e9c2404SShreeya Patel }; 52*1e9c2404SShreeya Patel }; 53*1e9c2404SShreeya Patel}; 54*1e9c2404SShreeya Patel 55a1d32814SChristopher Obbard&sdhci { 56a1d32814SChristopher Obbard bus-width = <8>; 57a1d32814SChristopher Obbard no-sdio; 58a1d32814SChristopher Obbard no-sd; 59a1d32814SChristopher Obbard non-removable; 60a1d32814SChristopher Obbard max-frequency = <200000000>; 61a1d32814SChristopher Obbard mmc-hs400-1_8v; 62a1d32814SChristopher Obbard mmc-hs400-enhanced-strobe; 63a1d32814SChristopher Obbard status = "okay"; 64a1d32814SChristopher Obbard}; 65a1d32814SChristopher Obbard 66a1d32814SChristopher Obbard&uart2 { 67a1d32814SChristopher Obbard pinctrl-0 = <&uart2m0_xfer>; 68a1d32814SChristopher Obbard status = "okay"; 69a1d32814SChristopher Obbard}; 70