1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4 */
5
6#include <dt-bindings/clock/rk3568-cru.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/phy/phy.h>
10#include <dt-bindings/pinctrl/rockchip.h>
11#include <dt-bindings/power/rk3568-power.h>
12#include <dt-bindings/soc/rockchip,boot-mode.h>
13#include <dt-bindings/thermal/thermal.h>
14
15/ {
16	interrupt-parent = <&gic>;
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	aliases {
21		gpio0 = &gpio0;
22		gpio1 = &gpio1;
23		gpio2 = &gpio2;
24		gpio3 = &gpio3;
25		gpio4 = &gpio4;
26		i2c0 = &i2c0;
27		i2c1 = &i2c1;
28		i2c2 = &i2c2;
29		i2c3 = &i2c3;
30		i2c4 = &i2c4;
31		i2c5 = &i2c5;
32		serial0 = &uart0;
33		serial1 = &uart1;
34		serial2 = &uart2;
35		serial3 = &uart3;
36		serial4 = &uart4;
37		serial5 = &uart5;
38		serial6 = &uart6;
39		serial7 = &uart7;
40		serial8 = &uart8;
41		serial9 = &uart9;
42		spi0 = &spi0;
43		spi1 = &spi1;
44		spi2 = &spi2;
45		spi3 = &spi3;
46	};
47
48	cpus {
49		#address-cells = <2>;
50		#size-cells = <0>;
51
52		cpu0: cpu@0 {
53			device_type = "cpu";
54			compatible = "arm,cortex-a55";
55			reg = <0x0 0x0>;
56			clocks = <&scmi_clk 0>;
57			#cooling-cells = <2>;
58			enable-method = "psci";
59			operating-points-v2 = <&cpu0_opp_table>;
60		};
61
62		cpu1: cpu@100 {
63			device_type = "cpu";
64			compatible = "arm,cortex-a55";
65			reg = <0x0 0x100>;
66			#cooling-cells = <2>;
67			enable-method = "psci";
68			operating-points-v2 = <&cpu0_opp_table>;
69		};
70
71		cpu2: cpu@200 {
72			device_type = "cpu";
73			compatible = "arm,cortex-a55";
74			reg = <0x0 0x200>;
75			#cooling-cells = <2>;
76			enable-method = "psci";
77			operating-points-v2 = <&cpu0_opp_table>;
78		};
79
80		cpu3: cpu@300 {
81			device_type = "cpu";
82			compatible = "arm,cortex-a55";
83			reg = <0x0 0x300>;
84			#cooling-cells = <2>;
85			enable-method = "psci";
86			operating-points-v2 = <&cpu0_opp_table>;
87		};
88	};
89
90	cpu0_opp_table: opp-table-0 {
91		compatible = "operating-points-v2";
92		opp-shared;
93
94		opp-408000000 {
95			opp-hz = /bits/ 64 <408000000>;
96			opp-microvolt = <900000 900000 1150000>;
97			clock-latency-ns = <40000>;
98		};
99
100		opp-600000000 {
101			opp-hz = /bits/ 64 <600000000>;
102			opp-microvolt = <900000 900000 1150000>;
103		};
104
105		opp-816000000 {
106			opp-hz = /bits/ 64 <816000000>;
107			opp-microvolt = <900000 900000 1150000>;
108			opp-suspend;
109		};
110
111		opp-1104000000 {
112			opp-hz = /bits/ 64 <1104000000>;
113			opp-microvolt = <900000 900000 1150000>;
114		};
115
116		opp-1416000000 {
117			opp-hz = /bits/ 64 <1416000000>;
118			opp-microvolt = <900000 900000 1150000>;
119		};
120
121		opp-1608000000 {
122			opp-hz = /bits/ 64 <1608000000>;
123			opp-microvolt = <975000 975000 1150000>;
124		};
125
126		opp-1800000000 {
127			opp-hz = /bits/ 64 <1800000000>;
128			opp-microvolt = <1050000 1050000 1150000>;
129		};
130	};
131
132	display_subsystem: display-subsystem {
133		compatible = "rockchip,display-subsystem";
134		ports = <&vop_out>;
135	};
136
137	firmware {
138		scmi: scmi {
139			compatible = "arm,scmi-smc";
140			arm,smc-id = <0x82000010>;
141			shmem = <&scmi_shmem>;
142			#address-cells = <1>;
143			#size-cells = <0>;
144
145			scmi_clk: protocol@14 {
146				reg = <0x14>;
147				#clock-cells = <1>;
148			};
149		};
150	};
151
152	gpu_opp_table: opp-table-1 {
153		compatible = "operating-points-v2";
154
155		opp-200000000 {
156			opp-hz = /bits/ 64 <200000000>;
157			opp-microvolt = <825000>;
158		};
159
160		opp-300000000 {
161			opp-hz = /bits/ 64 <300000000>;
162			opp-microvolt = <825000>;
163		};
164
165		opp-400000000 {
166			opp-hz = /bits/ 64 <400000000>;
167			opp-microvolt = <825000>;
168		};
169
170		opp-600000000 {
171			opp-hz = /bits/ 64 <600000000>;
172			opp-microvolt = <825000>;
173		};
174
175		opp-700000000 {
176			opp-hz = /bits/ 64 <700000000>;
177			opp-microvolt = <900000>;
178		};
179
180		opp-800000000 {
181			opp-hz = /bits/ 64 <800000000>;
182			opp-microvolt = <1000000>;
183		};
184	};
185
186	hdmi_sound: hdmi-sound {
187		compatible = "simple-audio-card";
188		simple-audio-card,name = "HDMI";
189		simple-audio-card,format = "i2s";
190		simple-audio-card,mclk-fs = <256>;
191		status = "disabled";
192
193		simple-audio-card,codec {
194			sound-dai = <&hdmi>;
195		};
196
197		simple-audio-card,cpu {
198			sound-dai = <&i2s0_8ch>;
199		};
200	};
201
202	pmu {
203		compatible = "arm,cortex-a55-pmu";
204		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
205			     <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
206			     <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
207			     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
208		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
209	};
210
211	psci {
212		compatible = "arm,psci-1.0";
213		method = "smc";
214	};
215
216	timer {
217		compatible = "arm,armv8-timer";
218		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
219			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
220			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
221			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
222		arm,no-tick-in-suspend;
223	};
224
225	xin24m: xin24m {
226		compatible = "fixed-clock";
227		clock-frequency = <24000000>;
228		clock-output-names = "xin24m";
229		#clock-cells = <0>;
230	};
231
232	xin32k: xin32k {
233		compatible = "fixed-clock";
234		clock-frequency = <32768>;
235		clock-output-names = "xin32k";
236		pinctrl-0 = <&clk32k_out0>;
237		pinctrl-names = "default";
238		#clock-cells = <0>;
239	};
240
241	sram@10f000 {
242		compatible = "mmio-sram";
243		reg = <0x0 0x0010f000 0x0 0x100>;
244		#address-cells = <1>;
245		#size-cells = <1>;
246		ranges = <0 0x0 0x0010f000 0x100>;
247
248		scmi_shmem: sram@0 {
249			compatible = "arm,scmi-shmem";
250			reg = <0x0 0x100>;
251		};
252	};
253
254	sata1: sata@fc400000 {
255		compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
256		reg = <0 0xfc400000 0 0x1000>;
257		clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
258			 <&cru CLK_SATA1_RXOOB>;
259		clock-names = "sata", "pmalive", "rxoob";
260		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
261		phys = <&combphy1 PHY_TYPE_SATA>;
262		phy-names = "sata-phy";
263		ports-implemented = <0x1>;
264		power-domains = <&power RK3568_PD_PIPE>;
265		status = "disabled";
266	};
267
268	sata2: sata@fc800000 {
269		compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
270		reg = <0 0xfc800000 0 0x1000>;
271		clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
272			 <&cru CLK_SATA2_RXOOB>;
273		clock-names = "sata", "pmalive", "rxoob";
274		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
275		phys = <&combphy2 PHY_TYPE_SATA>;
276		phy-names = "sata-phy";
277		ports-implemented = <0x1>;
278		power-domains = <&power RK3568_PD_PIPE>;
279		status = "disabled";
280	};
281
282	usb_host0_xhci: usb@fcc00000 {
283		compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
284		reg = <0x0 0xfcc00000 0x0 0x400000>;
285		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
286		clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
287			 <&cru ACLK_USB3OTG0>;
288		clock-names = "ref_clk", "suspend_clk",
289			      "bus_clk";
290		dr_mode = "otg";
291		phy_type = "utmi_wide";
292		power-domains = <&power RK3568_PD_PIPE>;
293		resets = <&cru SRST_USB3OTG0>;
294		snps,dis_u2_susphy_quirk;
295		status = "disabled";
296	};
297
298	usb_host1_xhci: usb@fd000000 {
299		compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
300		reg = <0x0 0xfd000000 0x0 0x400000>;
301		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
302		clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
303			 <&cru ACLK_USB3OTG1>;
304		clock-names = "ref_clk", "suspend_clk",
305			      "bus_clk";
306		dr_mode = "host";
307		phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>;
308		phy-names = "usb2-phy", "usb3-phy";
309		phy_type = "utmi_wide";
310		power-domains = <&power RK3568_PD_PIPE>;
311		resets = <&cru SRST_USB3OTG1>;
312		snps,dis_u2_susphy_quirk;
313		status = "disabled";
314	};
315
316	gic: interrupt-controller@fd400000 {
317		compatible = "arm,gic-v3";
318		reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
319		      <0x0 0xfd460000 0 0x80000>; /* GICR */
320		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
321		interrupt-controller;
322		#interrupt-cells = <3>;
323		mbi-alias = <0x0 0xfd410000>;
324		mbi-ranges = <296 24>;
325		msi-controller;
326	};
327
328	usb_host0_ehci: usb@fd800000 {
329		compatible = "generic-ehci";
330		reg = <0x0 0xfd800000 0x0 0x40000>;
331		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
332		clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
333			 <&cru PCLK_USB>;
334		phys = <&usb2phy1_otg>;
335		phy-names = "usb";
336		status = "disabled";
337	};
338
339	usb_host0_ohci: usb@fd840000 {
340		compatible = "generic-ohci";
341		reg = <0x0 0xfd840000 0x0 0x40000>;
342		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
343		clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
344			 <&cru PCLK_USB>;
345		phys = <&usb2phy1_otg>;
346		phy-names = "usb";
347		status = "disabled";
348	};
349
350	usb_host1_ehci: usb@fd880000 {
351		compatible = "generic-ehci";
352		reg = <0x0 0xfd880000 0x0 0x40000>;
353		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
354		clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
355			 <&cru PCLK_USB>;
356		phys = <&usb2phy1_host>;
357		phy-names = "usb";
358		status = "disabled";
359	};
360
361	usb_host1_ohci: usb@fd8c0000 {
362		compatible = "generic-ohci";
363		reg = <0x0 0xfd8c0000 0x0 0x40000>;
364		interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
365		clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
366			 <&cru PCLK_USB>;
367		phys = <&usb2phy1_host>;
368		phy-names = "usb";
369		status = "disabled";
370	};
371
372	pmugrf: syscon@fdc20000 {
373		compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
374		reg = <0x0 0xfdc20000 0x0 0x10000>;
375
376		pmu_io_domains: io-domains {
377			compatible = "rockchip,rk3568-pmu-io-voltage-domain";
378			status = "disabled";
379		};
380	};
381
382	pipegrf: syscon@fdc50000 {
383		reg = <0x0 0xfdc50000 0x0 0x1000>;
384	};
385
386	grf: syscon@fdc60000 {
387		compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
388		reg = <0x0 0xfdc60000 0x0 0x10000>;
389	};
390
391	pipe_phy_grf1: syscon@fdc80000 {
392		compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
393		reg = <0x0 0xfdc80000 0x0 0x1000>;
394	};
395
396	pipe_phy_grf2: syscon@fdc90000 {
397		compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
398		reg = <0x0 0xfdc90000 0x0 0x1000>;
399	};
400
401	usb2phy0_grf: syscon@fdca0000 {
402		compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
403		reg = <0x0 0xfdca0000 0x0 0x8000>;
404	};
405
406	usb2phy1_grf: syscon@fdca8000 {
407		compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
408		reg = <0x0 0xfdca8000 0x0 0x8000>;
409	};
410
411	pmucru: clock-controller@fdd00000 {
412		compatible = "rockchip,rk3568-pmucru";
413		reg = <0x0 0xfdd00000 0x0 0x1000>;
414		#clock-cells = <1>;
415		#reset-cells = <1>;
416	};
417
418	cru: clock-controller@fdd20000 {
419		compatible = "rockchip,rk3568-cru";
420		reg = <0x0 0xfdd20000 0x0 0x1000>;
421		clocks = <&xin24m>;
422		clock-names = "xin24m";
423		#clock-cells = <1>;
424		#reset-cells = <1>;
425		assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
426		assigned-clock-rates = <32768>, <1200000000>, <200000000>;
427		assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
428		rockchip,grf = <&grf>;
429	};
430
431	i2c0: i2c@fdd40000 {
432		compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
433		reg = <0x0 0xfdd40000 0x0 0x1000>;
434		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
435		clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
436		clock-names = "i2c", "pclk";
437		pinctrl-0 = <&i2c0_xfer>;
438		pinctrl-names = "default";
439		#address-cells = <1>;
440		#size-cells = <0>;
441		status = "disabled";
442	};
443
444	uart0: serial@fdd50000 {
445		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
446		reg = <0x0 0xfdd50000 0x0 0x100>;
447		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
448		clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
449		clock-names = "baudclk", "apb_pclk";
450		dmas = <&dmac0 0>, <&dmac0 1>;
451		pinctrl-0 = <&uart0_xfer>;
452		pinctrl-names = "default";
453		reg-io-width = <4>;
454		reg-shift = <2>;
455		status = "disabled";
456	};
457
458	pwm0: pwm@fdd70000 {
459		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
460		reg = <0x0 0xfdd70000 0x0 0x10>;
461		clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
462		clock-names = "pwm", "pclk";
463		pinctrl-0 = <&pwm0m0_pins>;
464		pinctrl-names = "default";
465		#pwm-cells = <3>;
466		status = "disabled";
467	};
468
469	pwm1: pwm@fdd70010 {
470		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
471		reg = <0x0 0xfdd70010 0x0 0x10>;
472		clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
473		clock-names = "pwm", "pclk";
474		pinctrl-0 = <&pwm1m0_pins>;
475		pinctrl-names = "default";
476		#pwm-cells = <3>;
477		status = "disabled";
478	};
479
480	pwm2: pwm@fdd70020 {
481		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
482		reg = <0x0 0xfdd70020 0x0 0x10>;
483		clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
484		clock-names = "pwm", "pclk";
485		pinctrl-0 = <&pwm2m0_pins>;
486		pinctrl-names = "default";
487		#pwm-cells = <3>;
488		status = "disabled";
489	};
490
491	pwm3: pwm@fdd70030 {
492		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
493		reg = <0x0 0xfdd70030 0x0 0x10>;
494		clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
495		clock-names = "pwm", "pclk";
496		pinctrl-0 = <&pwm3_pins>;
497		pinctrl-names = "default";
498		#pwm-cells = <3>;
499		status = "disabled";
500	};
501
502	pmu: power-management@fdd90000 {
503		compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
504		reg = <0x0 0xfdd90000 0x0 0x1000>;
505
506		power: power-controller {
507			compatible = "rockchip,rk3568-power-controller";
508			#power-domain-cells = <1>;
509			#address-cells = <1>;
510			#size-cells = <0>;
511
512			/* These power domains are grouped by VD_GPU */
513			power-domain@RK3568_PD_GPU {
514				reg = <RK3568_PD_GPU>;
515				clocks = <&cru ACLK_GPU_PRE>,
516					 <&cru PCLK_GPU_PRE>;
517				pm_qos = <&qos_gpu>;
518				#power-domain-cells = <0>;
519			};
520
521			/* These power domains are grouped by VD_LOGIC */
522			power-domain@RK3568_PD_VI {
523				reg = <RK3568_PD_VI>;
524				clocks = <&cru HCLK_VI>,
525					 <&cru PCLK_VI>;
526				pm_qos = <&qos_isp>,
527					 <&qos_vicap0>,
528					 <&qos_vicap1>;
529				#power-domain-cells = <0>;
530			};
531
532			power-domain@RK3568_PD_VO {
533				reg = <RK3568_PD_VO>;
534				clocks = <&cru HCLK_VO>,
535					 <&cru PCLK_VO>,
536					 <&cru ACLK_VOP_PRE>;
537				pm_qos = <&qos_hdcp>,
538					 <&qos_vop_m0>,
539					 <&qos_vop_m1>;
540				#power-domain-cells = <0>;
541			};
542
543			power-domain@RK3568_PD_RGA {
544				reg = <RK3568_PD_RGA>;
545				clocks = <&cru HCLK_RGA_PRE>,
546					 <&cru PCLK_RGA_PRE>;
547				pm_qos = <&qos_ebc>,
548					 <&qos_iep>,
549					 <&qos_jpeg_dec>,
550					 <&qos_jpeg_enc>,
551					 <&qos_rga_rd>,
552					 <&qos_rga_wr>;
553				#power-domain-cells = <0>;
554			};
555
556			power-domain@RK3568_PD_VPU {
557				reg = <RK3568_PD_VPU>;
558				clocks = <&cru HCLK_VPU_PRE>;
559				pm_qos = <&qos_vpu>;
560				#power-domain-cells = <0>;
561			};
562
563			power-domain@RK3568_PD_RKVDEC {
564				clocks = <&cru HCLK_RKVDEC_PRE>;
565				reg = <RK3568_PD_RKVDEC>;
566				pm_qos = <&qos_rkvdec>;
567				#power-domain-cells = <0>;
568			};
569
570			power-domain@RK3568_PD_RKVENC {
571				reg = <RK3568_PD_RKVENC>;
572				clocks = <&cru HCLK_RKVENC_PRE>;
573				pm_qos = <&qos_rkvenc_rd_m0>,
574					 <&qos_rkvenc_rd_m1>,
575					 <&qos_rkvenc_wr_m0>;
576				#power-domain-cells = <0>;
577			};
578		};
579	};
580
581	gpu: gpu@fde60000 {
582		compatible = "rockchip,rk3568-mali", "arm,mali-bifrost";
583		reg = <0x0 0xfde60000 0x0 0x4000>;
584		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
585			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
586			     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
587		interrupt-names = "job", "mmu", "gpu";
588		clocks = <&scmi_clk 1>, <&cru CLK_GPU>;
589		clock-names = "gpu", "bus";
590		#cooling-cells = <2>;
591		operating-points-v2 = <&gpu_opp_table>;
592		power-domains = <&power RK3568_PD_GPU>;
593		status = "disabled";
594	};
595
596	vpu: video-codec@fdea0400 {
597		compatible = "rockchip,rk3568-vpu";
598		reg = <0x0 0xfdea0000 0x0 0x800>;
599		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
600		interrupt-names = "vdpu";
601		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
602		clock-names = "aclk", "hclk";
603		iommus = <&vdpu_mmu>;
604		power-domains = <&power RK3568_PD_VPU>;
605	};
606
607	vdpu_mmu: iommu@fdea0800 {
608		compatible = "rockchip,rk3568-iommu";
609		reg = <0x0 0xfdea0800 0x0 0x40>;
610		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
611		clock-names = "aclk", "iface";
612		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
613		power-domains = <&power RK3568_PD_VPU>;
614		#iommu-cells = <0>;
615	};
616
617	rga: rga@fdeb0000 {
618		compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga";
619		reg = <0x0 0xfdeb0000 0x0 0x180>;
620		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
621		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>;
622		clock-names = "aclk", "hclk", "sclk";
623		resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
624		reset-names = "core", "axi", "ahb";
625		power-domains = <&power RK3568_PD_RGA>;
626	};
627
628	vepu: video-codec@fdee0000 {
629		compatible = "rockchip,rk3568-vepu";
630		reg = <0x0 0xfdee0000 0x0 0x800>;
631		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
632		clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
633		clock-names = "aclk", "hclk";
634		iommus = <&vepu_mmu>;
635		power-domains = <&power RK3568_PD_RGA>;
636	};
637
638	vepu_mmu: iommu@fdee0800 {
639		compatible = "rockchip,rk3568-iommu";
640		reg = <0x0 0xfdee0800 0x0 0x40>;
641		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
642		clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
643		clock-names = "aclk", "iface";
644		power-domains = <&power RK3568_PD_RGA>;
645		#iommu-cells = <0>;
646	};
647
648	sdmmc2: mmc@fe000000 {
649		compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
650		reg = <0x0 0xfe000000 0x0 0x4000>;
651		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
652		clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
653			 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
654		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
655		fifo-depth = <0x100>;
656		max-frequency = <150000000>;
657		resets = <&cru SRST_SDMMC2>;
658		reset-names = "reset";
659		status = "disabled";
660	};
661
662	gmac1: ethernet@fe010000 {
663		compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
664		reg = <0x0 0xfe010000 0x0 0x10000>;
665		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
666			     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
667		interrupt-names = "macirq", "eth_wake_irq";
668		clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
669			 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
670			 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
671			 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>;
672		clock-names = "stmmaceth", "mac_clk_rx",
673			      "mac_clk_tx", "clk_mac_refout",
674			      "aclk_mac", "pclk_mac",
675			      "clk_mac_speed", "ptp_ref";
676		resets = <&cru SRST_A_GMAC1>;
677		reset-names = "stmmaceth";
678		rockchip,grf = <&grf>;
679		snps,axi-config = <&gmac1_stmmac_axi_setup>;
680		snps,mixed-burst;
681		snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
682		snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
683		snps,tso;
684		status = "disabled";
685
686		mdio1: mdio {
687			compatible = "snps,dwmac-mdio";
688			#address-cells = <0x1>;
689			#size-cells = <0x0>;
690		};
691
692		gmac1_stmmac_axi_setup: stmmac-axi-config {
693			snps,blen = <0 0 0 0 16 8 4>;
694			snps,rd_osr_lmt = <8>;
695			snps,wr_osr_lmt = <4>;
696		};
697
698		gmac1_mtl_rx_setup: rx-queues-config {
699			snps,rx-queues-to-use = <1>;
700			queue0 {};
701		};
702
703		gmac1_mtl_tx_setup: tx-queues-config {
704			snps,tx-queues-to-use = <1>;
705			queue0 {};
706		};
707	};
708
709	vop: vop@fe040000 {
710		reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
711		reg-names = "vop", "gamma-lut";
712		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
713		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>,
714			 <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
715		clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2";
716		iommus = <&vop_mmu>;
717		power-domains = <&power RK3568_PD_VO>;
718		rockchip,grf = <&grf>;
719		status = "disabled";
720
721		vop_out: ports {
722			#address-cells = <1>;
723			#size-cells = <0>;
724
725			vp0: port@0 {
726				reg = <0>;
727				#address-cells = <1>;
728				#size-cells = <0>;
729			};
730
731			vp1: port@1 {
732				reg = <1>;
733				#address-cells = <1>;
734				#size-cells = <0>;
735			};
736
737			vp2: port@2 {
738				reg = <2>;
739				#address-cells = <1>;
740				#size-cells = <0>;
741			};
742		};
743	};
744
745	vop_mmu: iommu@fe043e00 {
746		compatible = "rockchip,rk3568-iommu";
747		reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
748		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
749		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
750		clock-names = "aclk", "iface";
751		#iommu-cells = <0>;
752		status = "disabled";
753	};
754
755	dsi0: dsi@fe060000 {
756		compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
757		reg = <0x00 0xfe060000 0x00 0x10000>;
758		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
759		clock-names = "pclk";
760		clocks = <&cru PCLK_DSITX_0>;
761		phy-names = "dphy";
762		phys = <&dsi_dphy0>;
763		power-domains = <&power RK3568_PD_VO>;
764		reset-names = "apb";
765		resets = <&cru SRST_P_DSITX_0>;
766		rockchip,grf = <&grf>;
767		status = "disabled";
768
769		ports {
770			#address-cells = <1>;
771			#size-cells = <0>;
772
773			dsi0_in: port@0 {
774				reg = <0>;
775			};
776
777			dsi0_out: port@1 {
778				reg = <1>;
779			};
780		};
781	};
782
783	dsi1: dsi@fe070000 {
784		compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
785		reg = <0x0 0xfe070000 0x0 0x10000>;
786		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
787		clock-names = "pclk";
788		clocks = <&cru PCLK_DSITX_1>;
789		phy-names = "dphy";
790		phys = <&dsi_dphy1>;
791		power-domains = <&power RK3568_PD_VO>;
792		reset-names = "apb";
793		resets = <&cru SRST_P_DSITX_1>;
794		rockchip,grf = <&grf>;
795		status = "disabled";
796
797		ports {
798			#address-cells = <1>;
799			#size-cells = <0>;
800
801			dsi1_in: port@0 {
802				reg = <0>;
803			};
804
805			dsi1_out: port@1 {
806				reg = <1>;
807			};
808		};
809	};
810
811	hdmi: hdmi@fe0a0000 {
812		compatible = "rockchip,rk3568-dw-hdmi";
813		reg = <0x0 0xfe0a0000 0x0 0x20000>;
814		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
815		clocks = <&cru PCLK_HDMI_HOST>,
816			 <&cru CLK_HDMI_SFR>,
817			 <&cru CLK_HDMI_CEC>,
818			 <&pmucru CLK_HDMI_REF>,
819			 <&cru HCLK_VO>;
820		clock-names = "iahb", "isfr", "cec", "ref";
821		pinctrl-names = "default";
822		pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
823		power-domains = <&power RK3568_PD_VO>;
824		reg-io-width = <4>;
825		rockchip,grf = <&grf>;
826		#sound-dai-cells = <0>;
827		status = "disabled";
828
829		ports {
830			#address-cells = <1>;
831			#size-cells = <0>;
832
833			hdmi_in: port@0 {
834				reg = <0>;
835			};
836
837			hdmi_out: port@1 {
838				reg = <1>;
839			};
840		};
841	};
842
843	qos_gpu: qos@fe128000 {
844		compatible = "rockchip,rk3568-qos", "syscon";
845		reg = <0x0 0xfe128000 0x0 0x20>;
846	};
847
848	qos_rkvenc_rd_m0: qos@fe138080 {
849		compatible = "rockchip,rk3568-qos", "syscon";
850		reg = <0x0 0xfe138080 0x0 0x20>;
851	};
852
853	qos_rkvenc_rd_m1: qos@fe138100 {
854		compatible = "rockchip,rk3568-qos", "syscon";
855		reg = <0x0 0xfe138100 0x0 0x20>;
856	};
857
858	qos_rkvenc_wr_m0: qos@fe138180 {
859		compatible = "rockchip,rk3568-qos", "syscon";
860		reg = <0x0 0xfe138180 0x0 0x20>;
861	};
862
863	qos_isp: qos@fe148000 {
864		compatible = "rockchip,rk3568-qos", "syscon";
865		reg = <0x0 0xfe148000 0x0 0x20>;
866	};
867
868	qos_vicap0: qos@fe148080 {
869		compatible = "rockchip,rk3568-qos", "syscon";
870		reg = <0x0 0xfe148080 0x0 0x20>;
871	};
872
873	qos_vicap1: qos@fe148100 {
874		compatible = "rockchip,rk3568-qos", "syscon";
875		reg = <0x0 0xfe148100 0x0 0x20>;
876	};
877
878	qos_vpu: qos@fe150000 {
879		compatible = "rockchip,rk3568-qos", "syscon";
880		reg = <0x0 0xfe150000 0x0 0x20>;
881	};
882
883	qos_ebc: qos@fe158000 {
884		compatible = "rockchip,rk3568-qos", "syscon";
885		reg = <0x0 0xfe158000 0x0 0x20>;
886	};
887
888	qos_iep: qos@fe158100 {
889		compatible = "rockchip,rk3568-qos", "syscon";
890		reg = <0x0 0xfe158100 0x0 0x20>;
891	};
892
893	qos_jpeg_dec: qos@fe158180 {
894		compatible = "rockchip,rk3568-qos", "syscon";
895		reg = <0x0 0xfe158180 0x0 0x20>;
896	};
897
898	qos_jpeg_enc: qos@fe158200 {
899		compatible = "rockchip,rk3568-qos", "syscon";
900		reg = <0x0 0xfe158200 0x0 0x20>;
901	};
902
903	qos_rga_rd: qos@fe158280 {
904		compatible = "rockchip,rk3568-qos", "syscon";
905		reg = <0x0 0xfe158280 0x0 0x20>;
906	};
907
908	qos_rga_wr: qos@fe158300 {
909		compatible = "rockchip,rk3568-qos", "syscon";
910		reg = <0x0 0xfe158300 0x0 0x20>;
911	};
912
913	qos_npu: qos@fe180000 {
914		compatible = "rockchip,rk3568-qos", "syscon";
915		reg = <0x0 0xfe180000 0x0 0x20>;
916	};
917
918	qos_pcie2x1: qos@fe190000 {
919		compatible = "rockchip,rk3568-qos", "syscon";
920		reg = <0x0 0xfe190000 0x0 0x20>;
921	};
922
923	qos_sata1: qos@fe190280 {
924		compatible = "rockchip,rk3568-qos", "syscon";
925		reg = <0x0 0xfe190280 0x0 0x20>;
926	};
927
928	qos_sata2: qos@fe190300 {
929		compatible = "rockchip,rk3568-qos", "syscon";
930		reg = <0x0 0xfe190300 0x0 0x20>;
931	};
932
933	qos_usb3_0: qos@fe190380 {
934		compatible = "rockchip,rk3568-qos", "syscon";
935		reg = <0x0 0xfe190380 0x0 0x20>;
936	};
937
938	qos_usb3_1: qos@fe190400 {
939		compatible = "rockchip,rk3568-qos", "syscon";
940		reg = <0x0 0xfe190400 0x0 0x20>;
941	};
942
943	qos_rkvdec: qos@fe198000 {
944		compatible = "rockchip,rk3568-qos", "syscon";
945		reg = <0x0 0xfe198000 0x0 0x20>;
946	};
947
948	qos_hdcp: qos@fe1a8000 {
949		compatible = "rockchip,rk3568-qos", "syscon";
950		reg = <0x0 0xfe1a8000 0x0 0x20>;
951	};
952
953	qos_vop_m0: qos@fe1a8080 {
954		compatible = "rockchip,rk3568-qos", "syscon";
955		reg = <0x0 0xfe1a8080 0x0 0x20>;
956	};
957
958	qos_vop_m1: qos@fe1a8100 {
959		compatible = "rockchip,rk3568-qos", "syscon";
960		reg = <0x0 0xfe1a8100 0x0 0x20>;
961	};
962
963	pcie2x1: pcie@fe260000 {
964		compatible = "rockchip,rk3568-pcie";
965		reg = <0x3 0xc0000000 0x0 0x00400000>,
966		      <0x0 0xfe260000 0x0 0x00010000>,
967		      <0x0 0xf4000000 0x0 0x00100000>;
968		reg-names = "dbi", "apb", "config";
969		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
970			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
971			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
972			     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
973			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
974		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
975		bus-range = <0x0 0xf>;
976		clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
977			 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
978			 <&cru CLK_PCIE20_AUX_NDFT>;
979		clock-names = "aclk_mst", "aclk_slv",
980			      "aclk_dbi", "pclk", "aux";
981		device_type = "pci";
982		#interrupt-cells = <1>;
983		interrupt-map-mask = <0 0 0 7>;
984		interrupt-map = <0 0 0 1 &pcie_intc 0>,
985				<0 0 0 2 &pcie_intc 1>,
986				<0 0 0 3 &pcie_intc 2>,
987				<0 0 0 4 &pcie_intc 3>;
988		linux,pci-domain = <0>;
989		num-ib-windows = <6>;
990		num-ob-windows = <2>;
991		max-link-speed = <2>;
992		msi-map = <0x0 &gic 0x0 0x1000>;
993		num-lanes = <1>;
994		phys = <&combphy2 PHY_TYPE_PCIE>;
995		phy-names = "pcie-phy";
996		power-domains = <&power RK3568_PD_PIPE>;
997		ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
998			 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
999			 <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
1000		resets = <&cru SRST_PCIE20_POWERUP>;
1001		reset-names = "pipe";
1002		#address-cells = <3>;
1003		#size-cells = <2>;
1004		status = "disabled";
1005
1006		pcie_intc: legacy-interrupt-controller {
1007			#address-cells = <0>;
1008			#interrupt-cells = <1>;
1009			interrupt-controller;
1010			interrupt-parent = <&gic>;
1011			interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
1012		};
1013	};
1014
1015	sdmmc0: mmc@fe2b0000 {
1016		compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
1017		reg = <0x0 0xfe2b0000 0x0 0x4000>;
1018		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1019		clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
1020			 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
1021		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1022		fifo-depth = <0x100>;
1023		max-frequency = <150000000>;
1024		resets = <&cru SRST_SDMMC0>;
1025		reset-names = "reset";
1026		status = "disabled";
1027	};
1028
1029	sdmmc1: mmc@fe2c0000 {
1030		compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
1031		reg = <0x0 0xfe2c0000 0x0 0x4000>;
1032		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1033		clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
1034			 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
1035		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1036		fifo-depth = <0x100>;
1037		max-frequency = <150000000>;
1038		resets = <&cru SRST_SDMMC1>;
1039		reset-names = "reset";
1040		status = "disabled";
1041	};
1042
1043	sfc: spi@fe300000 {
1044		compatible = "rockchip,sfc";
1045		reg = <0x0 0xfe300000 0x0 0x4000>;
1046		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1047		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1048		clock-names = "clk_sfc", "hclk_sfc";
1049		pinctrl-0 = <&fspi_pins>;
1050		pinctrl-names = "default";
1051		status = "disabled";
1052	};
1053
1054	sdhci: mmc@fe310000 {
1055		compatible = "rockchip,rk3568-dwcmshc";
1056		reg = <0x0 0xfe310000 0x0 0x10000>;
1057		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1058		assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
1059		assigned-clock-rates = <200000000>, <24000000>;
1060		clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
1061			 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1062			 <&cru TCLK_EMMC>;
1063		clock-names = "core", "bus", "axi", "block", "timer";
1064		status = "disabled";
1065	};
1066
1067	i2s0_8ch: i2s@fe400000 {
1068		compatible = "rockchip,rk3568-i2s-tdm";
1069		reg = <0x0 0xfe400000 0x0 0x1000>;
1070		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1071		assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1072		assigned-clock-rates = <1188000000>, <1188000000>;
1073		clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
1074		clock-names = "mclk_tx", "mclk_rx", "hclk";
1075		dmas = <&dmac1 0>;
1076		dma-names = "tx";
1077		resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
1078		reset-names = "tx-m", "rx-m";
1079		rockchip,grf = <&grf>;
1080		#sound-dai-cells = <0>;
1081		status = "disabled";
1082	};
1083
1084	i2s1_8ch: i2s@fe410000 {
1085		compatible = "rockchip,rk3568-i2s-tdm";
1086		reg = <0x0 0xfe410000 0x0 0x1000>;
1087		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1088		assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>;
1089		assigned-clock-rates = <1188000000>, <1188000000>;
1090		clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>,
1091			 <&cru HCLK_I2S1_8CH>;
1092		clock-names = "mclk_tx", "mclk_rx", "hclk";
1093		dmas = <&dmac1 3>, <&dmac1 2>;
1094		dma-names = "rx", "tx";
1095		resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
1096		reset-names = "tx-m", "rx-m";
1097		rockchip,grf = <&grf>;
1098		pinctrl-names = "default";
1099		pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
1100			     &i2s1m0_lrcktx &i2s1m0_lrckrx
1101			     &i2s1m0_sdi0   &i2s1m0_sdi1
1102			     &i2s1m0_sdi2   &i2s1m0_sdi3
1103			     &i2s1m0_sdo0   &i2s1m0_sdo1
1104			     &i2s1m0_sdo2   &i2s1m0_sdo3>;
1105		#sound-dai-cells = <0>;
1106		status = "disabled";
1107	};
1108
1109	i2s2_2ch: i2s@fe420000 {
1110		compatible = "rockchip,rk3568-i2s-tdm";
1111		reg = <0x0 0xfe420000 0x0 0x1000>;
1112		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1113		assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1114		assigned-clock-rates = <1188000000>;
1115		clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
1116		clock-names = "mclk_tx", "mclk_rx", "hclk";
1117		dmas = <&dmac1 4>, <&dmac1 5>;
1118		dma-names = "tx", "rx";
1119		resets = <&cru SRST_M_I2S2_2CH>;
1120		reset-names = "tx-m";
1121		rockchip,grf = <&grf>;
1122		pinctrl-names = "default";
1123		pinctrl-0 = <&i2s2m0_sclktx
1124				&i2s2m0_lrcktx
1125				&i2s2m0_sdi
1126				&i2s2m0_sdo>;
1127		#sound-dai-cells = <0>;
1128		status = "disabled";
1129	};
1130
1131	i2s3_2ch: i2s@fe430000 {
1132		compatible = "rockchip,rk3568-i2s-tdm";
1133		reg = <0x0 0xfe430000 0x0 0x1000>;
1134		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1135		clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>,
1136			 <&cru HCLK_I2S3_2CH>;
1137		clock-names = "mclk_tx", "mclk_rx", "hclk";
1138		dmas = <&dmac1 6>, <&dmac1 7>;
1139		dma-names = "tx", "rx";
1140		resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>;
1141		reset-names = "tx-m", "rx-m";
1142		rockchip,grf = <&grf>;
1143		#sound-dai-cells = <0>;
1144		status = "disabled";
1145	};
1146
1147	pdm: pdm@fe440000 {
1148		compatible = "rockchip,rk3568-pdm";
1149		reg = <0x0 0xfe440000 0x0 0x1000>;
1150		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
1151		clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
1152		clock-names = "pdm_clk", "pdm_hclk";
1153		dmas = <&dmac1 9>;
1154		dma-names = "rx";
1155		pinctrl-0 = <&pdmm0_clk
1156			     &pdmm0_clk1
1157			     &pdmm0_sdi0
1158			     &pdmm0_sdi1
1159			     &pdmm0_sdi2
1160			     &pdmm0_sdi3>;
1161		pinctrl-names = "default";
1162		resets = <&cru SRST_M_PDM>;
1163		reset-names = "pdm-m";
1164		#sound-dai-cells = <0>;
1165		status = "disabled";
1166	};
1167
1168	spdif: spdif@fe460000 {
1169		compatible = "rockchip,rk3568-spdif";
1170		reg = <0x0 0xfe460000 0x0 0x1000>;
1171		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1172		clock-names = "mclk", "hclk";
1173		clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
1174		dmas = <&dmac1 1>;
1175		dma-names = "tx";
1176		pinctrl-names = "default";
1177		pinctrl-0 = <&spdifm0_tx>;
1178		#sound-dai-cells = <0>;
1179		status = "disabled";
1180	};
1181
1182	dmac0: dma-controller@fe530000 {
1183		compatible = "arm,pl330", "arm,primecell";
1184		reg = <0x0 0xfe530000 0x0 0x4000>;
1185		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1186			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1187		arm,pl330-periph-burst;
1188		clocks = <&cru ACLK_BUS>;
1189		clock-names = "apb_pclk";
1190		#dma-cells = <1>;
1191	};
1192
1193	dmac1: dma-controller@fe550000 {
1194		compatible = "arm,pl330", "arm,primecell";
1195		reg = <0x0 0xfe550000 0x0 0x4000>;
1196		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1197			     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1198		arm,pl330-periph-burst;
1199		clocks = <&cru ACLK_BUS>;
1200		clock-names = "apb_pclk";
1201		#dma-cells = <1>;
1202	};
1203
1204	i2c1: i2c@fe5a0000 {
1205		compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1206		reg = <0x0 0xfe5a0000 0x0 0x1000>;
1207		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1208		clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
1209		clock-names = "i2c", "pclk";
1210		pinctrl-0 = <&i2c1_xfer>;
1211		pinctrl-names = "default";
1212		#address-cells = <1>;
1213		#size-cells = <0>;
1214		status = "disabled";
1215	};
1216
1217	i2c2: i2c@fe5b0000 {
1218		compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1219		reg = <0x0 0xfe5b0000 0x0 0x1000>;
1220		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1221		clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
1222		clock-names = "i2c", "pclk";
1223		pinctrl-0 = <&i2c2m0_xfer>;
1224		pinctrl-names = "default";
1225		#address-cells = <1>;
1226		#size-cells = <0>;
1227		status = "disabled";
1228	};
1229
1230	i2c3: i2c@fe5c0000 {
1231		compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1232		reg = <0x0 0xfe5c0000 0x0 0x1000>;
1233		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1234		clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
1235		clock-names = "i2c", "pclk";
1236		pinctrl-0 = <&i2c3m0_xfer>;
1237		pinctrl-names = "default";
1238		#address-cells = <1>;
1239		#size-cells = <0>;
1240		status = "disabled";
1241	};
1242
1243	i2c4: i2c@fe5d0000 {
1244		compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1245		reg = <0x0 0xfe5d0000 0x0 0x1000>;
1246		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1247		clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
1248		clock-names = "i2c", "pclk";
1249		pinctrl-0 = <&i2c4m0_xfer>;
1250		pinctrl-names = "default";
1251		#address-cells = <1>;
1252		#size-cells = <0>;
1253		status = "disabled";
1254	};
1255
1256	i2c5: i2c@fe5e0000 {
1257		compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1258		reg = <0x0 0xfe5e0000 0x0 0x1000>;
1259		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1260		clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
1261		clock-names = "i2c", "pclk";
1262		pinctrl-0 = <&i2c5m0_xfer>;
1263		pinctrl-names = "default";
1264		#address-cells = <1>;
1265		#size-cells = <0>;
1266		status = "disabled";
1267	};
1268
1269	wdt: watchdog@fe600000 {
1270		compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
1271		reg = <0x0 0xfe600000 0x0 0x100>;
1272		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
1273		clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
1274		clock-names = "tclk", "pclk";
1275	};
1276
1277	spi0: spi@fe610000 {
1278		compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1279		reg = <0x0 0xfe610000 0x0 0x1000>;
1280		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1281		clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
1282		clock-names = "spiclk", "apb_pclk";
1283		dmas = <&dmac0 20>, <&dmac0 21>;
1284		dma-names = "tx", "rx";
1285		pinctrl-names = "default";
1286		pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1287		#address-cells = <1>;
1288		#size-cells = <0>;
1289		status = "disabled";
1290	};
1291
1292	spi1: spi@fe620000 {
1293		compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1294		reg = <0x0 0xfe620000 0x0 0x1000>;
1295		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1296		clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1297		clock-names = "spiclk", "apb_pclk";
1298		dmas = <&dmac0 22>, <&dmac0 23>;
1299		dma-names = "tx", "rx";
1300		pinctrl-names = "default";
1301		pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
1302		#address-cells = <1>;
1303		#size-cells = <0>;
1304		status = "disabled";
1305	};
1306
1307	spi2: spi@fe630000 {
1308		compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1309		reg = <0x0 0xfe630000 0x0 0x1000>;
1310		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1311		clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
1312		clock-names = "spiclk", "apb_pclk";
1313		dmas = <&dmac0 24>, <&dmac0 25>;
1314		dma-names = "tx", "rx";
1315		pinctrl-names = "default";
1316		pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
1317		#address-cells = <1>;
1318		#size-cells = <0>;
1319		status = "disabled";
1320	};
1321
1322	spi3: spi@fe640000 {
1323		compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1324		reg = <0x0 0xfe640000 0x0 0x1000>;
1325		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1326		clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
1327		clock-names = "spiclk", "apb_pclk";
1328		dmas = <&dmac0 26>, <&dmac0 27>;
1329		dma-names = "tx", "rx";
1330		pinctrl-names = "default";
1331		pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
1332		#address-cells = <1>;
1333		#size-cells = <0>;
1334		status = "disabled";
1335	};
1336
1337	uart1: serial@fe650000 {
1338		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1339		reg = <0x0 0xfe650000 0x0 0x100>;
1340		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1341		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
1342		clock-names = "baudclk", "apb_pclk";
1343		dmas = <&dmac0 2>, <&dmac0 3>;
1344		pinctrl-0 = <&uart1m0_xfer>;
1345		pinctrl-names = "default";
1346		reg-io-width = <4>;
1347		reg-shift = <2>;
1348		status = "disabled";
1349	};
1350
1351	uart2: serial@fe660000 {
1352		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1353		reg = <0x0 0xfe660000 0x0 0x100>;
1354		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1355		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1356		clock-names = "baudclk", "apb_pclk";
1357		dmas = <&dmac0 4>, <&dmac0 5>;
1358		pinctrl-0 = <&uart2m0_xfer>;
1359		pinctrl-names = "default";
1360		reg-io-width = <4>;
1361		reg-shift = <2>;
1362		status = "disabled";
1363	};
1364
1365	uart3: serial@fe670000 {
1366		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1367		reg = <0x0 0xfe670000 0x0 0x100>;
1368		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1369		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1370		clock-names = "baudclk", "apb_pclk";
1371		dmas = <&dmac0 6>, <&dmac0 7>;
1372		pinctrl-0 = <&uart3m0_xfer>;
1373		pinctrl-names = "default";
1374		reg-io-width = <4>;
1375		reg-shift = <2>;
1376		status = "disabled";
1377	};
1378
1379	uart4: serial@fe680000 {
1380		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1381		reg = <0x0 0xfe680000 0x0 0x100>;
1382		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1383		clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1384		clock-names = "baudclk", "apb_pclk";
1385		dmas = <&dmac0 8>, <&dmac0 9>;
1386		pinctrl-0 = <&uart4m0_xfer>;
1387		pinctrl-names = "default";
1388		reg-io-width = <4>;
1389		reg-shift = <2>;
1390		status = "disabled";
1391	};
1392
1393	uart5: serial@fe690000 {
1394		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1395		reg = <0x0 0xfe690000 0x0 0x100>;
1396		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1397		clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1398		clock-names = "baudclk", "apb_pclk";
1399		dmas = <&dmac0 10>, <&dmac0 11>;
1400		pinctrl-0 = <&uart5m0_xfer>;
1401		pinctrl-names = "default";
1402		reg-io-width = <4>;
1403		reg-shift = <2>;
1404		status = "disabled";
1405	};
1406
1407	uart6: serial@fe6a0000 {
1408		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1409		reg = <0x0 0xfe6a0000 0x0 0x100>;
1410		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1411		clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
1412		clock-names = "baudclk", "apb_pclk";
1413		dmas = <&dmac0 12>, <&dmac0 13>;
1414		pinctrl-0 = <&uart6m0_xfer>;
1415		pinctrl-names = "default";
1416		reg-io-width = <4>;
1417		reg-shift = <2>;
1418		status = "disabled";
1419	};
1420
1421	uart7: serial@fe6b0000 {
1422		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1423		reg = <0x0 0xfe6b0000 0x0 0x100>;
1424		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1425		clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
1426		clock-names = "baudclk", "apb_pclk";
1427		dmas = <&dmac0 14>, <&dmac0 15>;
1428		pinctrl-0 = <&uart7m0_xfer>;
1429		pinctrl-names = "default";
1430		reg-io-width = <4>;
1431		reg-shift = <2>;
1432		status = "disabled";
1433	};
1434
1435	uart8: serial@fe6c0000 {
1436		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1437		reg = <0x0 0xfe6c0000 0x0 0x100>;
1438		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1439		clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
1440		clock-names = "baudclk", "apb_pclk";
1441		dmas = <&dmac0 16>, <&dmac0 17>;
1442		pinctrl-0 = <&uart8m0_xfer>;
1443		pinctrl-names = "default";
1444		reg-io-width = <4>;
1445		reg-shift = <2>;
1446		status = "disabled";
1447	};
1448
1449	uart9: serial@fe6d0000 {
1450		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1451		reg = <0x0 0xfe6d0000 0x0 0x100>;
1452		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
1453		clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
1454		clock-names = "baudclk", "apb_pclk";
1455		dmas = <&dmac0 18>, <&dmac0 19>;
1456		pinctrl-0 = <&uart9m0_xfer>;
1457		pinctrl-names = "default";
1458		reg-io-width = <4>;
1459		reg-shift = <2>;
1460		status = "disabled";
1461	};
1462
1463	thermal_zones: thermal-zones {
1464		cpu_thermal: cpu-thermal {
1465			polling-delay-passive = <100>;
1466			polling-delay = <1000>;
1467
1468			thermal-sensors = <&tsadc 0>;
1469
1470			trips {
1471				cpu_alert0: cpu_alert0 {
1472					temperature = <70000>;
1473					hysteresis = <2000>;
1474					type = "passive";
1475				};
1476				cpu_alert1: cpu_alert1 {
1477					temperature = <75000>;
1478					hysteresis = <2000>;
1479					type = "passive";
1480				};
1481				cpu_crit: cpu_crit {
1482					temperature = <95000>;
1483					hysteresis = <2000>;
1484					type = "critical";
1485				};
1486			};
1487
1488			cooling-maps {
1489				map0 {
1490					trip = <&cpu_alert0>;
1491					cooling-device =
1492						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1493						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1494						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1495						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1496				};
1497			};
1498		};
1499
1500		gpu_thermal: gpu-thermal {
1501			polling-delay-passive = <20>; /* milliseconds */
1502			polling-delay = <1000>; /* milliseconds */
1503
1504			thermal-sensors = <&tsadc 1>;
1505
1506			trips {
1507				gpu_threshold: gpu-threshold {
1508					temperature = <70000>;
1509					hysteresis = <2000>;
1510					type = "passive";
1511				};
1512				gpu_target: gpu-target {
1513					temperature = <75000>;
1514					hysteresis = <2000>;
1515					type = "passive";
1516				};
1517				gpu_crit: gpu-crit {
1518					temperature = <95000>;
1519					hysteresis = <2000>;
1520					type = "critical";
1521				};
1522			};
1523
1524			cooling-maps {
1525				map0 {
1526					trip = <&gpu_target>;
1527					cooling-device =
1528						<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1529				};
1530			};
1531		};
1532	};
1533
1534	tsadc: tsadc@fe710000 {
1535		compatible = "rockchip,rk3568-tsadc";
1536		reg = <0x0 0xfe710000 0x0 0x100>;
1537		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1538		assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
1539		assigned-clock-rates = <17000000>, <700000>;
1540		clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
1541		clock-names = "tsadc", "apb_pclk";
1542		resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>,
1543			 <&cru SRST_TSADCPHY>;
1544		rockchip,grf = <&grf>;
1545		rockchip,hw-tshut-temp = <95000>;
1546		pinctrl-names = "init", "default", "sleep";
1547		pinctrl-0 = <&tsadc_pin>;
1548		pinctrl-1 = <&tsadc_shutorg>;
1549		pinctrl-2 = <&tsadc_pin>;
1550		#thermal-sensor-cells = <1>;
1551		status = "disabled";
1552	};
1553
1554	saradc: saradc@fe720000 {
1555		compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
1556		reg = <0x0 0xfe720000 0x0 0x100>;
1557		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1558		clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
1559		clock-names = "saradc", "apb_pclk";
1560		resets = <&cru SRST_P_SARADC>;
1561		reset-names = "saradc-apb";
1562		#io-channel-cells = <1>;
1563		status = "disabled";
1564	};
1565
1566	pwm4: pwm@fe6e0000 {
1567		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1568		reg = <0x0 0xfe6e0000 0x0 0x10>;
1569		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1570		clock-names = "pwm", "pclk";
1571		pinctrl-0 = <&pwm4_pins>;
1572		pinctrl-names = "default";
1573		#pwm-cells = <3>;
1574		status = "disabled";
1575	};
1576
1577	pwm5: pwm@fe6e0010 {
1578		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1579		reg = <0x0 0xfe6e0010 0x0 0x10>;
1580		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1581		clock-names = "pwm", "pclk";
1582		pinctrl-0 = <&pwm5_pins>;
1583		pinctrl-names = "default";
1584		#pwm-cells = <3>;
1585		status = "disabled";
1586	};
1587
1588	pwm6: pwm@fe6e0020 {
1589		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1590		reg = <0x0 0xfe6e0020 0x0 0x10>;
1591		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1592		clock-names = "pwm", "pclk";
1593		pinctrl-0 = <&pwm6_pins>;
1594		pinctrl-names = "default";
1595		#pwm-cells = <3>;
1596		status = "disabled";
1597	};
1598
1599	pwm7: pwm@fe6e0030 {
1600		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1601		reg = <0x0 0xfe6e0030 0x0 0x10>;
1602		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1603		clock-names = "pwm", "pclk";
1604		pinctrl-0 = <&pwm7_pins>;
1605		pinctrl-names = "default";
1606		#pwm-cells = <3>;
1607		status = "disabled";
1608	};
1609
1610	pwm8: pwm@fe6f0000 {
1611		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1612		reg = <0x0 0xfe6f0000 0x0 0x10>;
1613		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1614		clock-names = "pwm", "pclk";
1615		pinctrl-0 = <&pwm8m0_pins>;
1616		pinctrl-names = "default";
1617		#pwm-cells = <3>;
1618		status = "disabled";
1619	};
1620
1621	pwm9: pwm@fe6f0010 {
1622		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1623		reg = <0x0 0xfe6f0010 0x0 0x10>;
1624		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1625		clock-names = "pwm", "pclk";
1626		pinctrl-0 = <&pwm9m0_pins>;
1627		pinctrl-names = "default";
1628		#pwm-cells = <3>;
1629		status = "disabled";
1630	};
1631
1632	pwm10: pwm@fe6f0020 {
1633		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1634		reg = <0x0 0xfe6f0020 0x0 0x10>;
1635		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1636		clock-names = "pwm", "pclk";
1637		pinctrl-0 = <&pwm10m0_pins>;
1638		pinctrl-names = "default";
1639		#pwm-cells = <3>;
1640		status = "disabled";
1641	};
1642
1643	pwm11: pwm@fe6f0030 {
1644		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1645		reg = <0x0 0xfe6f0030 0x0 0x10>;
1646		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1647		clock-names = "pwm", "pclk";
1648		pinctrl-0 = <&pwm11m0_pins>;
1649		pinctrl-names = "default";
1650		#pwm-cells = <3>;
1651		status = "disabled";
1652	};
1653
1654	pwm12: pwm@fe700000 {
1655		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1656		reg = <0x0 0xfe700000 0x0 0x10>;
1657		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1658		clock-names = "pwm", "pclk";
1659		pinctrl-0 = <&pwm12m0_pins>;
1660		pinctrl-names = "default";
1661		#pwm-cells = <3>;
1662		status = "disabled";
1663	};
1664
1665	pwm13: pwm@fe700010 {
1666		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1667		reg = <0x0 0xfe700010 0x0 0x10>;
1668		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1669		clock-names = "pwm", "pclk";
1670		pinctrl-0 = <&pwm13m0_pins>;
1671		pinctrl-names = "default";
1672		#pwm-cells = <3>;
1673		status = "disabled";
1674	};
1675
1676	pwm14: pwm@fe700020 {
1677		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1678		reg = <0x0 0xfe700020 0x0 0x10>;
1679		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1680		clock-names = "pwm", "pclk";
1681		pinctrl-0 = <&pwm14m0_pins>;
1682		pinctrl-names = "default";
1683		#pwm-cells = <3>;
1684		status = "disabled";
1685	};
1686
1687	pwm15: pwm@fe700030 {
1688		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1689		reg = <0x0 0xfe700030 0x0 0x10>;
1690		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1691		clock-names = "pwm", "pclk";
1692		pinctrl-0 = <&pwm15m0_pins>;
1693		pinctrl-names = "default";
1694		#pwm-cells = <3>;
1695		status = "disabled";
1696	};
1697
1698	combphy1: phy@fe830000 {
1699		compatible = "rockchip,rk3568-naneng-combphy";
1700		reg = <0x0 0xfe830000 0x0 0x100>;
1701		clocks = <&pmucru CLK_PCIEPHY1_REF>,
1702			 <&cru PCLK_PIPEPHY1>,
1703			 <&cru PCLK_PIPE>;
1704		clock-names = "ref", "apb", "pipe";
1705		assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
1706		assigned-clock-rates = <100000000>;
1707		resets = <&cru SRST_PIPEPHY1>;
1708		rockchip,pipe-grf = <&pipegrf>;
1709		rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
1710		#phy-cells = <1>;
1711		status = "disabled";
1712	};
1713
1714	combphy2: phy@fe840000 {
1715		compatible = "rockchip,rk3568-naneng-combphy";
1716		reg = <0x0 0xfe840000 0x0 0x100>;
1717		clocks = <&pmucru CLK_PCIEPHY2_REF>,
1718			 <&cru PCLK_PIPEPHY2>,
1719			 <&cru PCLK_PIPE>;
1720		clock-names = "ref", "apb", "pipe";
1721		assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
1722		assigned-clock-rates = <100000000>;
1723		resets = <&cru SRST_PIPEPHY2>;
1724		rockchip,pipe-grf = <&pipegrf>;
1725		rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
1726		#phy-cells = <1>;
1727		status = "disabled";
1728	};
1729
1730	csi_dphy: phy@fe870000 {
1731		compatible = "rockchip,rk3568-csi-dphy";
1732		reg = <0x0 0xfe870000 0x0 0x10000>;
1733		clocks = <&cru PCLK_MIPICSIPHY>;
1734		clock-names = "pclk";
1735		#phy-cells = <0>;
1736		resets = <&cru SRST_P_MIPICSIPHY>;
1737		reset-names = "apb";
1738		rockchip,grf = <&grf>;
1739		status = "disabled";
1740	};
1741
1742	dsi_dphy0: mipi-dphy@fe850000 {
1743		compatible = "rockchip,rk3568-dsi-dphy";
1744		reg = <0x0 0xfe850000 0x0 0x10000>;
1745		clock-names = "ref", "pclk";
1746		clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>;
1747		#phy-cells = <0>;
1748		power-domains = <&power RK3568_PD_VO>;
1749		reset-names = "apb";
1750		resets = <&cru SRST_P_MIPIDSIPHY0>;
1751		status = "disabled";
1752	};
1753
1754	dsi_dphy1: mipi-dphy@fe860000 {
1755		compatible = "rockchip,rk3568-dsi-dphy";
1756		reg = <0x0 0xfe860000 0x0 0x10000>;
1757		clock-names = "ref", "pclk";
1758		clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>;
1759		#phy-cells = <0>;
1760		power-domains = <&power RK3568_PD_VO>;
1761		reset-names = "apb";
1762		resets = <&cru SRST_P_MIPIDSIPHY1>;
1763		status = "disabled";
1764	};
1765
1766	usb2phy0: usb2phy@fe8a0000 {
1767		compatible = "rockchip,rk3568-usb2phy";
1768		reg = <0x0 0xfe8a0000 0x0 0x10000>;
1769		clocks = <&pmucru CLK_USBPHY0_REF>;
1770		clock-names = "phyclk";
1771		clock-output-names = "clk_usbphy0_480m";
1772		interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
1773		rockchip,usbgrf = <&usb2phy0_grf>;
1774		#clock-cells = <0>;
1775		status = "disabled";
1776
1777		usb2phy0_host: host-port {
1778			#phy-cells = <0>;
1779			status = "disabled";
1780		};
1781
1782		usb2phy0_otg: otg-port {
1783			#phy-cells = <0>;
1784			status = "disabled";
1785		};
1786	};
1787
1788	usb2phy1: usb2phy@fe8b0000 {
1789		compatible = "rockchip,rk3568-usb2phy";
1790		reg = <0x0 0xfe8b0000 0x0 0x10000>;
1791		clocks = <&pmucru CLK_USBPHY1_REF>;
1792		clock-names = "phyclk";
1793		clock-output-names = "clk_usbphy1_480m";
1794		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1795		rockchip,usbgrf = <&usb2phy1_grf>;
1796		#clock-cells = <0>;
1797		status = "disabled";
1798
1799		usb2phy1_host: host-port {
1800			#phy-cells = <0>;
1801			status = "disabled";
1802		};
1803
1804		usb2phy1_otg: otg-port {
1805			#phy-cells = <0>;
1806			status = "disabled";
1807		};
1808	};
1809
1810	pinctrl: pinctrl {
1811		compatible = "rockchip,rk3568-pinctrl";
1812		rockchip,grf = <&grf>;
1813		rockchip,pmu = <&pmugrf>;
1814		#address-cells = <2>;
1815		#size-cells = <2>;
1816		ranges;
1817
1818		gpio0: gpio@fdd60000 {
1819			compatible = "rockchip,gpio-bank";
1820			reg = <0x0 0xfdd60000 0x0 0x100>;
1821			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1822			clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
1823			gpio-controller;
1824			gpio-ranges = <&pinctrl 0 0 32>;
1825			#gpio-cells = <2>;
1826			interrupt-controller;
1827			#interrupt-cells = <2>;
1828		};
1829
1830		gpio1: gpio@fe740000 {
1831			compatible = "rockchip,gpio-bank";
1832			reg = <0x0 0xfe740000 0x0 0x100>;
1833			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1834			clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
1835			gpio-controller;
1836			gpio-ranges = <&pinctrl 0 32 32>;
1837			#gpio-cells = <2>;
1838			interrupt-controller;
1839			#interrupt-cells = <2>;
1840		};
1841
1842		gpio2: gpio@fe750000 {
1843			compatible = "rockchip,gpio-bank";
1844			reg = <0x0 0xfe750000 0x0 0x100>;
1845			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1846			clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
1847			gpio-controller;
1848			gpio-ranges = <&pinctrl 0 64 32>;
1849			#gpio-cells = <2>;
1850			interrupt-controller;
1851			#interrupt-cells = <2>;
1852		};
1853
1854		gpio3: gpio@fe760000 {
1855			compatible = "rockchip,gpio-bank";
1856			reg = <0x0 0xfe760000 0x0 0x100>;
1857			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1858			clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
1859			gpio-controller;
1860			gpio-ranges = <&pinctrl 0 96 32>;
1861			#gpio-cells = <2>;
1862			interrupt-controller;
1863			#interrupt-cells = <2>;
1864		};
1865
1866		gpio4: gpio@fe770000 {
1867			compatible = "rockchip,gpio-bank";
1868			reg = <0x0 0xfe770000 0x0 0x100>;
1869			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1870			clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
1871			gpio-controller;
1872			gpio-ranges = <&pinctrl 0 128 32>;
1873			#gpio-cells = <2>;
1874			interrupt-controller;
1875			#interrupt-cells = <2>;
1876		};
1877	};
1878};
1879
1880#include "rk3568-pinctrl.dtsi"
1881