1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3568-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3568-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 gpio0 = &gpio0; 22 gpio1 = &gpio1; 23 gpio2 = &gpio2; 24 gpio3 = &gpio3; 25 gpio4 = &gpio4; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 i2c4 = &i2c4; 31 i2c5 = &i2c5; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 serial5 = &uart5; 38 serial6 = &uart6; 39 serial7 = &uart7; 40 serial8 = &uart8; 41 serial9 = &uart9; 42 spi0 = &spi0; 43 spi1 = &spi1; 44 spi2 = &spi2; 45 spi3 = &spi3; 46 }; 47 48 cpus { 49 #address-cells = <2>; 50 #size-cells = <0>; 51 52 cpu0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a55"; 55 reg = <0x0 0x0>; 56 clocks = <&scmi_clk 0>; 57 #cooling-cells = <2>; 58 enable-method = "psci"; 59 operating-points-v2 = <&cpu0_opp_table>; 60 }; 61 62 cpu1: cpu@100 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a55"; 65 reg = <0x0 0x100>; 66 #cooling-cells = <2>; 67 enable-method = "psci"; 68 operating-points-v2 = <&cpu0_opp_table>; 69 }; 70 71 cpu2: cpu@200 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a55"; 74 reg = <0x0 0x200>; 75 #cooling-cells = <2>; 76 enable-method = "psci"; 77 operating-points-v2 = <&cpu0_opp_table>; 78 }; 79 80 cpu3: cpu@300 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a55"; 83 reg = <0x0 0x300>; 84 #cooling-cells = <2>; 85 enable-method = "psci"; 86 operating-points-v2 = <&cpu0_opp_table>; 87 }; 88 }; 89 90 cpu0_opp_table: opp-table-0 { 91 compatible = "operating-points-v2"; 92 opp-shared; 93 94 opp-408000000 { 95 opp-hz = /bits/ 64 <408000000>; 96 opp-microvolt = <900000 900000 1150000>; 97 clock-latency-ns = <40000>; 98 }; 99 100 opp-600000000 { 101 opp-hz = /bits/ 64 <600000000>; 102 opp-microvolt = <900000 900000 1150000>; 103 }; 104 105 opp-816000000 { 106 opp-hz = /bits/ 64 <816000000>; 107 opp-microvolt = <900000 900000 1150000>; 108 opp-suspend; 109 }; 110 111 opp-1104000000 { 112 opp-hz = /bits/ 64 <1104000000>; 113 opp-microvolt = <900000 900000 1150000>; 114 }; 115 116 opp-1416000000 { 117 opp-hz = /bits/ 64 <1416000000>; 118 opp-microvolt = <900000 900000 1150000>; 119 }; 120 121 opp-1608000000 { 122 opp-hz = /bits/ 64 <1608000000>; 123 opp-microvolt = <975000 975000 1150000>; 124 }; 125 126 opp-1800000000 { 127 opp-hz = /bits/ 64 <1800000000>; 128 opp-microvolt = <1050000 1050000 1150000>; 129 }; 130 }; 131 132 firmware { 133 scmi: scmi { 134 compatible = "arm,scmi-smc"; 135 arm,smc-id = <0x82000010>; 136 shmem = <&scmi_shmem>; 137 #address-cells = <1>; 138 #size-cells = <0>; 139 140 scmi_clk: protocol@14 { 141 reg = <0x14>; 142 #clock-cells = <1>; 143 }; 144 }; 145 }; 146 147 gpu_opp_table: opp-table-1 { 148 compatible = "operating-points-v2"; 149 150 opp-200000000 { 151 opp-hz = /bits/ 64 <200000000>; 152 opp-microvolt = <825000>; 153 }; 154 155 opp-300000000 { 156 opp-hz = /bits/ 64 <300000000>; 157 opp-microvolt = <825000>; 158 }; 159 160 opp-400000000 { 161 opp-hz = /bits/ 64 <400000000>; 162 opp-microvolt = <825000>; 163 }; 164 165 opp-600000000 { 166 opp-hz = /bits/ 64 <600000000>; 167 opp-microvolt = <825000>; 168 }; 169 170 opp-700000000 { 171 opp-hz = /bits/ 64 <700000000>; 172 opp-microvolt = <900000>; 173 }; 174 175 opp-800000000 { 176 opp-hz = /bits/ 64 <800000000>; 177 opp-microvolt = <1000000>; 178 }; 179 }; 180 181 pmu { 182 compatible = "arm,cortex-a55-pmu"; 183 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 187 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 188 }; 189 190 psci { 191 compatible = "arm,psci-1.0"; 192 method = "smc"; 193 }; 194 195 timer { 196 compatible = "arm,armv8-timer"; 197 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 201 arm,no-tick-in-suspend; 202 }; 203 204 xin24m: xin24m { 205 compatible = "fixed-clock"; 206 clock-frequency = <24000000>; 207 clock-output-names = "xin24m"; 208 #clock-cells = <0>; 209 }; 210 211 xin32k: xin32k { 212 compatible = "fixed-clock"; 213 clock-frequency = <32768>; 214 clock-output-names = "xin32k"; 215 pinctrl-0 = <&clk32k_out0>; 216 pinctrl-names = "default"; 217 #clock-cells = <0>; 218 }; 219 220 sram@10f000 { 221 compatible = "mmio-sram"; 222 reg = <0x0 0x0010f000 0x0 0x100>; 223 #address-cells = <1>; 224 #size-cells = <1>; 225 ranges = <0 0x0 0x0010f000 0x100>; 226 227 scmi_shmem: sram@0 { 228 compatible = "arm,scmi-shmem"; 229 reg = <0x0 0x100>; 230 }; 231 }; 232 233 sata1: sata@fc400000 { 234 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; 235 reg = <0 0xfc400000 0 0x1000>; 236 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, 237 <&cru CLK_SATA1_RXOOB>; 238 clock-names = "sata", "pmalive", "rxoob"; 239 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 240 phys = <&combphy1 PHY_TYPE_SATA>; 241 phy-names = "sata-phy"; 242 ports-implemented = <0x1>; 243 power-domains = <&power RK3568_PD_PIPE>; 244 status = "disabled"; 245 }; 246 247 sata2: sata@fc800000 { 248 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; 249 reg = <0 0xfc800000 0 0x1000>; 250 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, 251 <&cru CLK_SATA2_RXOOB>; 252 clock-names = "sata", "pmalive", "rxoob"; 253 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 254 phys = <&combphy2 PHY_TYPE_SATA>; 255 phy-names = "sata-phy"; 256 ports-implemented = <0x1>; 257 power-domains = <&power RK3568_PD_PIPE>; 258 status = "disabled"; 259 }; 260 261 usb_host0_xhci: usb@fcc00000 { 262 compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; 263 reg = <0x0 0xfcc00000 0x0 0x400000>; 264 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, 266 <&cru ACLK_USB3OTG0>; 267 clock-names = "ref_clk", "suspend_clk", 268 "bus_clk"; 269 dr_mode = "otg"; 270 phy_type = "utmi_wide"; 271 power-domains = <&power RK3568_PD_PIPE>; 272 resets = <&cru SRST_USB3OTG0>; 273 snps,dis_u2_susphy_quirk; 274 status = "disabled"; 275 }; 276 277 usb_host1_xhci: usb@fd000000 { 278 compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; 279 reg = <0x0 0xfd000000 0x0 0x400000>; 280 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, 282 <&cru ACLK_USB3OTG1>; 283 clock-names = "ref_clk", "suspend_clk", 284 "bus_clk"; 285 dr_mode = "host"; 286 phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>; 287 phy-names = "usb2-phy", "usb3-phy"; 288 phy_type = "utmi_wide"; 289 power-domains = <&power RK3568_PD_PIPE>; 290 resets = <&cru SRST_USB3OTG1>; 291 snps,dis_u2_susphy_quirk; 292 status = "disabled"; 293 }; 294 295 gic: interrupt-controller@fd400000 { 296 compatible = "arm,gic-v3"; 297 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ 298 <0x0 0xfd460000 0 0x80000>; /* GICR */ 299 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 300 interrupt-controller; 301 #interrupt-cells = <3>; 302 mbi-alias = <0x0 0xfd410000>; 303 mbi-ranges = <296 24>; 304 msi-controller; 305 }; 306 307 usb_host0_ehci: usb@fd800000 { 308 compatible = "generic-ehci"; 309 reg = <0x0 0xfd800000 0x0 0x40000>; 310 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 312 <&cru PCLK_USB>; 313 phys = <&usb2phy1_otg>; 314 phy-names = "usb"; 315 status = "disabled"; 316 }; 317 318 usb_host0_ohci: usb@fd840000 { 319 compatible = "generic-ohci"; 320 reg = <0x0 0xfd840000 0x0 0x40000>; 321 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 323 <&cru PCLK_USB>; 324 phys = <&usb2phy1_otg>; 325 phy-names = "usb"; 326 status = "disabled"; 327 }; 328 329 usb_host1_ehci: usb@fd880000 { 330 compatible = "generic-ehci"; 331 reg = <0x0 0xfd880000 0x0 0x40000>; 332 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 334 <&cru PCLK_USB>; 335 phys = <&usb2phy1_host>; 336 phy-names = "usb"; 337 status = "disabled"; 338 }; 339 340 usb_host1_ohci: usb@fd8c0000 { 341 compatible = "generic-ohci"; 342 reg = <0x0 0xfd8c0000 0x0 0x40000>; 343 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 345 <&cru PCLK_USB>; 346 phys = <&usb2phy1_host>; 347 phy-names = "usb"; 348 status = "disabled"; 349 }; 350 351 pmugrf: syscon@fdc20000 { 352 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; 353 reg = <0x0 0xfdc20000 0x0 0x10000>; 354 355 pmu_io_domains: io-domains { 356 compatible = "rockchip,rk3568-pmu-io-voltage-domain"; 357 status = "disabled"; 358 }; 359 }; 360 361 pipegrf: syscon@fdc50000 { 362 reg = <0x0 0xfdc50000 0x0 0x1000>; 363 }; 364 365 grf: syscon@fdc60000 { 366 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; 367 reg = <0x0 0xfdc60000 0x0 0x10000>; 368 }; 369 370 pipe_phy_grf1: syscon@fdc80000 { 371 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; 372 reg = <0x0 0xfdc80000 0x0 0x1000>; 373 }; 374 375 pipe_phy_grf2: syscon@fdc90000 { 376 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; 377 reg = <0x0 0xfdc90000 0x0 0x1000>; 378 }; 379 380 usb2phy0_grf: syscon@fdca0000 { 381 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 382 reg = <0x0 0xfdca0000 0x0 0x8000>; 383 }; 384 385 usb2phy1_grf: syscon@fdca8000 { 386 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 387 reg = <0x0 0xfdca8000 0x0 0x8000>; 388 }; 389 390 pmucru: clock-controller@fdd00000 { 391 compatible = "rockchip,rk3568-pmucru"; 392 reg = <0x0 0xfdd00000 0x0 0x1000>; 393 #clock-cells = <1>; 394 #reset-cells = <1>; 395 }; 396 397 cru: clock-controller@fdd20000 { 398 compatible = "rockchip,rk3568-cru"; 399 reg = <0x0 0xfdd20000 0x0 0x1000>; 400 #clock-cells = <1>; 401 #reset-cells = <1>; 402 assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; 403 assigned-clock-rates = <1200000000>, <200000000>; 404 rockchip,grf = <&grf>; 405 }; 406 407 i2c0: i2c@fdd40000 { 408 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 409 reg = <0x0 0xfdd40000 0x0 0x1000>; 410 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 411 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 412 clock-names = "i2c", "pclk"; 413 pinctrl-0 = <&i2c0_xfer>; 414 pinctrl-names = "default"; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 status = "disabled"; 418 }; 419 420 uart0: serial@fdd50000 { 421 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 422 reg = <0x0 0xfdd50000 0x0 0x100>; 423 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 424 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; 425 clock-names = "baudclk", "apb_pclk"; 426 dmas = <&dmac0 0>, <&dmac0 1>; 427 pinctrl-0 = <&uart0_xfer>; 428 pinctrl-names = "default"; 429 reg-io-width = <4>; 430 reg-shift = <2>; 431 status = "disabled"; 432 }; 433 434 pwm0: pwm@fdd70000 { 435 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 436 reg = <0x0 0xfdd70000 0x0 0x10>; 437 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 438 clock-names = "pwm", "pclk"; 439 pinctrl-0 = <&pwm0m0_pins>; 440 pinctrl-names = "default"; 441 #pwm-cells = <3>; 442 status = "disabled"; 443 }; 444 445 pwm1: pwm@fdd70010 { 446 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 447 reg = <0x0 0xfdd70010 0x0 0x10>; 448 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 449 clock-names = "pwm", "pclk"; 450 pinctrl-0 = <&pwm1m0_pins>; 451 pinctrl-names = "default"; 452 #pwm-cells = <3>; 453 status = "disabled"; 454 }; 455 456 pwm2: pwm@fdd70020 { 457 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 458 reg = <0x0 0xfdd70020 0x0 0x10>; 459 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 460 clock-names = "pwm", "pclk"; 461 pinctrl-0 = <&pwm2m0_pins>; 462 pinctrl-names = "default"; 463 #pwm-cells = <3>; 464 status = "disabled"; 465 }; 466 467 pwm3: pwm@fdd70030 { 468 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 469 reg = <0x0 0xfdd70030 0x0 0x10>; 470 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 471 clock-names = "pwm", "pclk"; 472 pinctrl-0 = <&pwm3_pins>; 473 pinctrl-names = "default"; 474 #pwm-cells = <3>; 475 status = "disabled"; 476 }; 477 478 pmu: power-management@fdd90000 { 479 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; 480 reg = <0x0 0xfdd90000 0x0 0x1000>; 481 482 power: power-controller { 483 compatible = "rockchip,rk3568-power-controller"; 484 #power-domain-cells = <1>; 485 #address-cells = <1>; 486 #size-cells = <0>; 487 488 /* These power domains are grouped by VD_GPU */ 489 power-domain@RK3568_PD_GPU { 490 reg = <RK3568_PD_GPU>; 491 clocks = <&cru ACLK_GPU_PRE>, 492 <&cru PCLK_GPU_PRE>; 493 pm_qos = <&qos_gpu>; 494 #power-domain-cells = <0>; 495 }; 496 497 /* These power domains are grouped by VD_LOGIC */ 498 power-domain@RK3568_PD_VI { 499 reg = <RK3568_PD_VI>; 500 clocks = <&cru HCLK_VI>, 501 <&cru PCLK_VI>; 502 pm_qos = <&qos_isp>, 503 <&qos_vicap0>, 504 <&qos_vicap1>; 505 #power-domain-cells = <0>; 506 }; 507 508 power-domain@RK3568_PD_VO { 509 reg = <RK3568_PD_VO>; 510 clocks = <&cru HCLK_VO>, 511 <&cru PCLK_VO>, 512 <&cru ACLK_VOP_PRE>; 513 pm_qos = <&qos_hdcp>, 514 <&qos_vop_m0>, 515 <&qos_vop_m1>; 516 #power-domain-cells = <0>; 517 }; 518 519 power-domain@RK3568_PD_RGA { 520 reg = <RK3568_PD_RGA>; 521 clocks = <&cru HCLK_RGA_PRE>, 522 <&cru PCLK_RGA_PRE>; 523 pm_qos = <&qos_ebc>, 524 <&qos_iep>, 525 <&qos_jpeg_dec>, 526 <&qos_jpeg_enc>, 527 <&qos_rga_rd>, 528 <&qos_rga_wr>; 529 #power-domain-cells = <0>; 530 }; 531 532 power-domain@RK3568_PD_VPU { 533 reg = <RK3568_PD_VPU>; 534 clocks = <&cru HCLK_VPU_PRE>; 535 pm_qos = <&qos_vpu>; 536 #power-domain-cells = <0>; 537 }; 538 539 power-domain@RK3568_PD_RKVDEC { 540 clocks = <&cru HCLK_RKVDEC_PRE>; 541 reg = <RK3568_PD_RKVDEC>; 542 pm_qos = <&qos_rkvdec>; 543 #power-domain-cells = <0>; 544 }; 545 546 power-domain@RK3568_PD_RKVENC { 547 reg = <RK3568_PD_RKVENC>; 548 clocks = <&cru HCLK_RKVENC_PRE>; 549 pm_qos = <&qos_rkvenc_rd_m0>, 550 <&qos_rkvenc_rd_m1>, 551 <&qos_rkvenc_wr_m0>; 552 #power-domain-cells = <0>; 553 }; 554 }; 555 }; 556 557 gpu: gpu@fde60000 { 558 compatible = "rockchip,rk3568-mali", "arm,mali-bifrost"; 559 reg = <0x0 0xfde60000 0x0 0x4000>; 560 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 563 interrupt-names = "job", "mmu", "gpu"; 564 clocks = <&scmi_clk 1>, <&cru CLK_GPU>; 565 clock-names = "gpu", "bus"; 566 #cooling-cells = <2>; 567 operating-points-v2 = <&gpu_opp_table>; 568 power-domains = <&power RK3568_PD_GPU>; 569 status = "disabled"; 570 }; 571 572 sdmmc2: mmc@fe000000 { 573 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 574 reg = <0x0 0xfe000000 0x0 0x4000>; 575 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, 577 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; 578 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 579 fifo-depth = <0x100>; 580 max-frequency = <150000000>; 581 resets = <&cru SRST_SDMMC2>; 582 reset-names = "reset"; 583 status = "disabled"; 584 }; 585 586 gmac1: ethernet@fe010000 { 587 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; 588 reg = <0x0 0xfe010000 0x0 0x10000>; 589 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 591 interrupt-names = "macirq", "eth_wake_irq"; 592 clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, 593 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, 594 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, 595 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; 596 clock-names = "stmmaceth", "mac_clk_rx", 597 "mac_clk_tx", "clk_mac_refout", 598 "aclk_mac", "pclk_mac", 599 "clk_mac_speed", "ptp_ref"; 600 resets = <&cru SRST_A_GMAC1>; 601 reset-names = "stmmaceth"; 602 rockchip,grf = <&grf>; 603 snps,axi-config = <&gmac1_stmmac_axi_setup>; 604 snps,mixed-burst; 605 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 606 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 607 snps,tso; 608 status = "disabled"; 609 610 mdio1: mdio { 611 compatible = "snps,dwmac-mdio"; 612 #address-cells = <0x1>; 613 #size-cells = <0x0>; 614 }; 615 616 gmac1_stmmac_axi_setup: stmmac-axi-config { 617 snps,blen = <0 0 0 0 16 8 4>; 618 snps,rd_osr_lmt = <8>; 619 snps,wr_osr_lmt = <4>; 620 }; 621 622 gmac1_mtl_rx_setup: rx-queues-config { 623 snps,rx-queues-to-use = <1>; 624 queue0 {}; 625 }; 626 627 gmac1_mtl_tx_setup: tx-queues-config { 628 snps,tx-queues-to-use = <1>; 629 queue0 {}; 630 }; 631 }; 632 633 qos_gpu: qos@fe128000 { 634 compatible = "rockchip,rk3568-qos", "syscon"; 635 reg = <0x0 0xfe128000 0x0 0x20>; 636 }; 637 638 qos_rkvenc_rd_m0: qos@fe138080 { 639 compatible = "rockchip,rk3568-qos", "syscon"; 640 reg = <0x0 0xfe138080 0x0 0x20>; 641 }; 642 643 qos_rkvenc_rd_m1: qos@fe138100 { 644 compatible = "rockchip,rk3568-qos", "syscon"; 645 reg = <0x0 0xfe138100 0x0 0x20>; 646 }; 647 648 qos_rkvenc_wr_m0: qos@fe138180 { 649 compatible = "rockchip,rk3568-qos", "syscon"; 650 reg = <0x0 0xfe138180 0x0 0x20>; 651 }; 652 653 qos_isp: qos@fe148000 { 654 compatible = "rockchip,rk3568-qos", "syscon"; 655 reg = <0x0 0xfe148000 0x0 0x20>; 656 }; 657 658 qos_vicap0: qos@fe148080 { 659 compatible = "rockchip,rk3568-qos", "syscon"; 660 reg = <0x0 0xfe148080 0x0 0x20>; 661 }; 662 663 qos_vicap1: qos@fe148100 { 664 compatible = "rockchip,rk3568-qos", "syscon"; 665 reg = <0x0 0xfe148100 0x0 0x20>; 666 }; 667 668 qos_vpu: qos@fe150000 { 669 compatible = "rockchip,rk3568-qos", "syscon"; 670 reg = <0x0 0xfe150000 0x0 0x20>; 671 }; 672 673 qos_ebc: qos@fe158000 { 674 compatible = "rockchip,rk3568-qos", "syscon"; 675 reg = <0x0 0xfe158000 0x0 0x20>; 676 }; 677 678 qos_iep: qos@fe158100 { 679 compatible = "rockchip,rk3568-qos", "syscon"; 680 reg = <0x0 0xfe158100 0x0 0x20>; 681 }; 682 683 qos_jpeg_dec: qos@fe158180 { 684 compatible = "rockchip,rk3568-qos", "syscon"; 685 reg = <0x0 0xfe158180 0x0 0x20>; 686 }; 687 688 qos_jpeg_enc: qos@fe158200 { 689 compatible = "rockchip,rk3568-qos", "syscon"; 690 reg = <0x0 0xfe158200 0x0 0x20>; 691 }; 692 693 qos_rga_rd: qos@fe158280 { 694 compatible = "rockchip,rk3568-qos", "syscon"; 695 reg = <0x0 0xfe158280 0x0 0x20>; 696 }; 697 698 qos_rga_wr: qos@fe158300 { 699 compatible = "rockchip,rk3568-qos", "syscon"; 700 reg = <0x0 0xfe158300 0x0 0x20>; 701 }; 702 703 qos_npu: qos@fe180000 { 704 compatible = "rockchip,rk3568-qos", "syscon"; 705 reg = <0x0 0xfe180000 0x0 0x20>; 706 }; 707 708 qos_pcie2x1: qos@fe190000 { 709 compatible = "rockchip,rk3568-qos", "syscon"; 710 reg = <0x0 0xfe190000 0x0 0x20>; 711 }; 712 713 qos_sata1: qos@fe190280 { 714 compatible = "rockchip,rk3568-qos", "syscon"; 715 reg = <0x0 0xfe190280 0x0 0x20>; 716 }; 717 718 qos_sata2: qos@fe190300 { 719 compatible = "rockchip,rk3568-qos", "syscon"; 720 reg = <0x0 0xfe190300 0x0 0x20>; 721 }; 722 723 qos_usb3_0: qos@fe190380 { 724 compatible = "rockchip,rk3568-qos", "syscon"; 725 reg = <0x0 0xfe190380 0x0 0x20>; 726 }; 727 728 qos_usb3_1: qos@fe190400 { 729 compatible = "rockchip,rk3568-qos", "syscon"; 730 reg = <0x0 0xfe190400 0x0 0x20>; 731 }; 732 733 qos_rkvdec: qos@fe198000 { 734 compatible = "rockchip,rk3568-qos", "syscon"; 735 reg = <0x0 0xfe198000 0x0 0x20>; 736 }; 737 738 qos_hdcp: qos@fe1a8000 { 739 compatible = "rockchip,rk3568-qos", "syscon"; 740 reg = <0x0 0xfe1a8000 0x0 0x20>; 741 }; 742 743 qos_vop_m0: qos@fe1a8080 { 744 compatible = "rockchip,rk3568-qos", "syscon"; 745 reg = <0x0 0xfe1a8080 0x0 0x20>; 746 }; 747 748 qos_vop_m1: qos@fe1a8100 { 749 compatible = "rockchip,rk3568-qos", "syscon"; 750 reg = <0x0 0xfe1a8100 0x0 0x20>; 751 }; 752 753 sdmmc0: mmc@fe2b0000 { 754 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 755 reg = <0x0 0xfe2b0000 0x0 0x4000>; 756 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 757 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, 758 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; 759 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 760 fifo-depth = <0x100>; 761 max-frequency = <150000000>; 762 resets = <&cru SRST_SDMMC0>; 763 reset-names = "reset"; 764 status = "disabled"; 765 }; 766 767 sdmmc1: mmc@fe2c0000 { 768 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 769 reg = <0x0 0xfe2c0000 0x0 0x4000>; 770 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, 772 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; 773 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 774 fifo-depth = <0x100>; 775 max-frequency = <150000000>; 776 resets = <&cru SRST_SDMMC1>; 777 reset-names = "reset"; 778 status = "disabled"; 779 }; 780 781 sfc: spi@fe300000 { 782 compatible = "rockchip,sfc"; 783 reg = <0x0 0xfe300000 0x0 0x4000>; 784 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 785 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 786 clock-names = "clk_sfc", "hclk_sfc"; 787 pinctrl-0 = <&fspi_pins>; 788 pinctrl-names = "default"; 789 status = "disabled"; 790 }; 791 792 sdhci: mmc@fe310000 { 793 compatible = "rockchip,rk3568-dwcmshc"; 794 reg = <0x0 0xfe310000 0x0 0x10000>; 795 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 796 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; 797 assigned-clock-rates = <200000000>, <24000000>; 798 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 799 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 800 <&cru TCLK_EMMC>; 801 clock-names = "core", "bus", "axi", "block", "timer"; 802 status = "disabled"; 803 }; 804 805 spdif: spdif@fe460000 { 806 compatible = "rockchip,rk3568-spdif"; 807 reg = <0x0 0xfe460000 0x0 0x1000>; 808 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 809 clock-names = "mclk", "hclk"; 810 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; 811 dmas = <&dmac1 1>; 812 dma-names = "tx"; 813 pinctrl-names = "default"; 814 pinctrl-0 = <&spdifm0_tx>; 815 #sound-dai-cells = <0>; 816 status = "disabled"; 817 }; 818 819 i2s1_8ch: i2s@fe410000 { 820 compatible = "rockchip,rk3568-i2s-tdm"; 821 reg = <0x0 0xfe410000 0x0 0x1000>; 822 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 823 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>; 824 assigned-clock-rates = <1188000000>, <1188000000>; 825 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, 826 <&cru HCLK_I2S1_8CH>; 827 clock-names = "mclk_tx", "mclk_rx", "hclk"; 828 dmas = <&dmac1 3>, <&dmac1 2>; 829 dma-names = "rx", "tx"; 830 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 831 reset-names = "tx-m", "rx-m"; 832 rockchip,grf = <&grf>; 833 pinctrl-names = "default"; 834 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx 835 &i2s1m0_lrcktx &i2s1m0_lrckrx 836 &i2s1m0_sdi0 &i2s1m0_sdi1 837 &i2s1m0_sdi2 &i2s1m0_sdi3 838 &i2s1m0_sdo0 &i2s1m0_sdo1 839 &i2s1m0_sdo2 &i2s1m0_sdo3>; 840 #sound-dai-cells = <0>; 841 status = "disabled"; 842 }; 843 844 i2s3_2ch: i2s@fe430000 { 845 compatible = "rockchip,rk3568-i2s-tdm"; 846 reg = <0x0 0xfe430000 0x0 0x1000>; 847 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 848 clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, 849 <&cru HCLK_I2S3_2CH>; 850 clock-names = "mclk_tx", "mclk_rx", "hclk"; 851 dmas = <&dmac1 6>, <&dmac1 7>; 852 dma-names = "tx", "rx"; 853 resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>; 854 reset-names = "tx-m", "rx-m"; 855 rockchip,grf = <&grf>; 856 #sound-dai-cells = <0>; 857 status = "disabled"; 858 }; 859 860 pdm: pdm@fe440000 { 861 compatible = "rockchip,rk3568-pdm"; 862 reg = <0x0 0xfe440000 0x0 0x1000>; 863 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 864 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; 865 clock-names = "pdm_clk", "pdm_hclk"; 866 dmas = <&dmac1 9>; 867 dma-names = "rx"; 868 pinctrl-0 = <&pdmm0_clk 869 &pdmm0_clk1 870 &pdmm0_sdi0 871 &pdmm0_sdi1 872 &pdmm0_sdi2 873 &pdmm0_sdi3>; 874 pinctrl-names = "default"; 875 resets = <&cru SRST_M_PDM>; 876 reset-names = "pdm-m"; 877 #sound-dai-cells = <0>; 878 status = "disabled"; 879 }; 880 881 dmac0: dma-controller@fe530000 { 882 compatible = "arm,pl330", "arm,primecell"; 883 reg = <0x0 0xfe530000 0x0 0x4000>; 884 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 886 arm,pl330-periph-burst; 887 clocks = <&cru ACLK_BUS>; 888 clock-names = "apb_pclk"; 889 #dma-cells = <1>; 890 }; 891 892 dmac1: dma-controller@fe550000 { 893 compatible = "arm,pl330", "arm,primecell"; 894 reg = <0x0 0xfe550000 0x0 0x4000>; 895 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 897 arm,pl330-periph-burst; 898 clocks = <&cru ACLK_BUS>; 899 clock-names = "apb_pclk"; 900 #dma-cells = <1>; 901 }; 902 903 i2c1: i2c@fe5a0000 { 904 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 905 reg = <0x0 0xfe5a0000 0x0 0x1000>; 906 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 907 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 908 clock-names = "i2c", "pclk"; 909 pinctrl-0 = <&i2c1_xfer>; 910 pinctrl-names = "default"; 911 #address-cells = <1>; 912 #size-cells = <0>; 913 status = "disabled"; 914 }; 915 916 i2c2: i2c@fe5b0000 { 917 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 918 reg = <0x0 0xfe5b0000 0x0 0x1000>; 919 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 920 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 921 clock-names = "i2c", "pclk"; 922 pinctrl-0 = <&i2c2m0_xfer>; 923 pinctrl-names = "default"; 924 #address-cells = <1>; 925 #size-cells = <0>; 926 status = "disabled"; 927 }; 928 929 i2c3: i2c@fe5c0000 { 930 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 931 reg = <0x0 0xfe5c0000 0x0 0x1000>; 932 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 933 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 934 clock-names = "i2c", "pclk"; 935 pinctrl-0 = <&i2c3m0_xfer>; 936 pinctrl-names = "default"; 937 #address-cells = <1>; 938 #size-cells = <0>; 939 status = "disabled"; 940 }; 941 942 i2c4: i2c@fe5d0000 { 943 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 944 reg = <0x0 0xfe5d0000 0x0 0x1000>; 945 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 946 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 947 clock-names = "i2c", "pclk"; 948 pinctrl-0 = <&i2c4m0_xfer>; 949 pinctrl-names = "default"; 950 #address-cells = <1>; 951 #size-cells = <0>; 952 status = "disabled"; 953 }; 954 955 i2c5: i2c@fe5e0000 { 956 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 957 reg = <0x0 0xfe5e0000 0x0 0x1000>; 958 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 959 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 960 clock-names = "i2c", "pclk"; 961 pinctrl-0 = <&i2c5m0_xfer>; 962 pinctrl-names = "default"; 963 #address-cells = <1>; 964 #size-cells = <0>; 965 status = "disabled"; 966 }; 967 968 wdt: watchdog@fe600000 { 969 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; 970 reg = <0x0 0xfe600000 0x0 0x100>; 971 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 972 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; 973 clock-names = "tclk", "pclk"; 974 }; 975 976 spi0: spi@fe610000 { 977 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 978 reg = <0x0 0xfe610000 0x0 0x1000>; 979 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 980 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 981 clock-names = "spiclk", "apb_pclk"; 982 dmas = <&dmac0 20>, <&dmac0 21>; 983 dma-names = "tx", "rx"; 984 pinctrl-names = "default"; 985 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 986 #address-cells = <1>; 987 #size-cells = <0>; 988 status = "disabled"; 989 }; 990 991 spi1: spi@fe620000 { 992 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 993 reg = <0x0 0xfe620000 0x0 0x1000>; 994 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 995 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 996 clock-names = "spiclk", "apb_pclk"; 997 dmas = <&dmac0 22>, <&dmac0 23>; 998 dma-names = "tx", "rx"; 999 pinctrl-names = "default"; 1000 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; 1001 #address-cells = <1>; 1002 #size-cells = <0>; 1003 status = "disabled"; 1004 }; 1005 1006 spi2: spi@fe630000 { 1007 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1008 reg = <0x0 0xfe630000 0x0 0x1000>; 1009 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1010 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 1011 clock-names = "spiclk", "apb_pclk"; 1012 dmas = <&dmac0 24>, <&dmac0 25>; 1013 dma-names = "tx", "rx"; 1014 pinctrl-names = "default"; 1015 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; 1016 #address-cells = <1>; 1017 #size-cells = <0>; 1018 status = "disabled"; 1019 }; 1020 1021 spi3: spi@fe640000 { 1022 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1023 reg = <0x0 0xfe640000 0x0 0x1000>; 1024 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1025 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 1026 clock-names = "spiclk", "apb_pclk"; 1027 dmas = <&dmac0 26>, <&dmac0 27>; 1028 dma-names = "tx", "rx"; 1029 pinctrl-names = "default"; 1030 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>; 1031 #address-cells = <1>; 1032 #size-cells = <0>; 1033 status = "disabled"; 1034 }; 1035 1036 uart1: serial@fe650000 { 1037 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1038 reg = <0x0 0xfe650000 0x0 0x100>; 1039 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1040 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1041 clock-names = "baudclk", "apb_pclk"; 1042 dmas = <&dmac0 2>, <&dmac0 3>; 1043 pinctrl-0 = <&uart1m0_xfer>; 1044 pinctrl-names = "default"; 1045 reg-io-width = <4>; 1046 reg-shift = <2>; 1047 status = "disabled"; 1048 }; 1049 1050 uart2: serial@fe660000 { 1051 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1052 reg = <0x0 0xfe660000 0x0 0x100>; 1053 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1054 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1055 clock-names = "baudclk", "apb_pclk"; 1056 dmas = <&dmac0 4>, <&dmac0 5>; 1057 pinctrl-0 = <&uart2m0_xfer>; 1058 pinctrl-names = "default"; 1059 reg-io-width = <4>; 1060 reg-shift = <2>; 1061 status = "disabled"; 1062 }; 1063 1064 uart3: serial@fe670000 { 1065 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1066 reg = <0x0 0xfe670000 0x0 0x100>; 1067 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1068 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1069 clock-names = "baudclk", "apb_pclk"; 1070 dmas = <&dmac0 6>, <&dmac0 7>; 1071 pinctrl-0 = <&uart3m0_xfer>; 1072 pinctrl-names = "default"; 1073 reg-io-width = <4>; 1074 reg-shift = <2>; 1075 status = "disabled"; 1076 }; 1077 1078 uart4: serial@fe680000 { 1079 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1080 reg = <0x0 0xfe680000 0x0 0x100>; 1081 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1082 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1083 clock-names = "baudclk", "apb_pclk"; 1084 dmas = <&dmac0 8>, <&dmac0 9>; 1085 pinctrl-0 = <&uart4m0_xfer>; 1086 pinctrl-names = "default"; 1087 reg-io-width = <4>; 1088 reg-shift = <2>; 1089 status = "disabled"; 1090 }; 1091 1092 uart5: serial@fe690000 { 1093 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1094 reg = <0x0 0xfe690000 0x0 0x100>; 1095 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1096 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1097 clock-names = "baudclk", "apb_pclk"; 1098 dmas = <&dmac0 10>, <&dmac0 11>; 1099 pinctrl-0 = <&uart5m0_xfer>; 1100 pinctrl-names = "default"; 1101 reg-io-width = <4>; 1102 reg-shift = <2>; 1103 status = "disabled"; 1104 }; 1105 1106 uart6: serial@fe6a0000 { 1107 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1108 reg = <0x0 0xfe6a0000 0x0 0x100>; 1109 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1110 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1111 clock-names = "baudclk", "apb_pclk"; 1112 dmas = <&dmac0 12>, <&dmac0 13>; 1113 pinctrl-0 = <&uart6m0_xfer>; 1114 pinctrl-names = "default"; 1115 reg-io-width = <4>; 1116 reg-shift = <2>; 1117 status = "disabled"; 1118 }; 1119 1120 uart7: serial@fe6b0000 { 1121 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1122 reg = <0x0 0xfe6b0000 0x0 0x100>; 1123 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1124 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1125 clock-names = "baudclk", "apb_pclk"; 1126 dmas = <&dmac0 14>, <&dmac0 15>; 1127 pinctrl-0 = <&uart7m0_xfer>; 1128 pinctrl-names = "default"; 1129 reg-io-width = <4>; 1130 reg-shift = <2>; 1131 status = "disabled"; 1132 }; 1133 1134 uart8: serial@fe6c0000 { 1135 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1136 reg = <0x0 0xfe6c0000 0x0 0x100>; 1137 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1138 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 1139 clock-names = "baudclk", "apb_pclk"; 1140 dmas = <&dmac0 16>, <&dmac0 17>; 1141 pinctrl-0 = <&uart8m0_xfer>; 1142 pinctrl-names = "default"; 1143 reg-io-width = <4>; 1144 reg-shift = <2>; 1145 status = "disabled"; 1146 }; 1147 1148 uart9: serial@fe6d0000 { 1149 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1150 reg = <0x0 0xfe6d0000 0x0 0x100>; 1151 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1152 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 1153 clock-names = "baudclk", "apb_pclk"; 1154 dmas = <&dmac0 18>, <&dmac0 19>; 1155 pinctrl-0 = <&uart9m0_xfer>; 1156 pinctrl-names = "default"; 1157 reg-io-width = <4>; 1158 reg-shift = <2>; 1159 status = "disabled"; 1160 }; 1161 1162 thermal_zones: thermal-zones { 1163 cpu_thermal: cpu-thermal { 1164 polling-delay-passive = <100>; 1165 polling-delay = <1000>; 1166 1167 thermal-sensors = <&tsadc 0>; 1168 1169 trips { 1170 cpu_alert0: cpu_alert0 { 1171 temperature = <70000>; 1172 hysteresis = <2000>; 1173 type = "passive"; 1174 }; 1175 cpu_alert1: cpu_alert1 { 1176 temperature = <75000>; 1177 hysteresis = <2000>; 1178 type = "passive"; 1179 }; 1180 cpu_crit: cpu_crit { 1181 temperature = <95000>; 1182 hysteresis = <2000>; 1183 type = "critical"; 1184 }; 1185 }; 1186 1187 cooling-maps { 1188 map0 { 1189 trip = <&cpu_alert0>; 1190 cooling-device = 1191 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1192 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1193 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1194 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1195 }; 1196 }; 1197 }; 1198 1199 gpu_thermal: gpu-thermal { 1200 polling-delay-passive = <20>; /* milliseconds */ 1201 polling-delay = <1000>; /* milliseconds */ 1202 1203 thermal-sensors = <&tsadc 1>; 1204 1205 trips { 1206 gpu_threshold: gpu-threshold { 1207 temperature = <70000>; 1208 hysteresis = <2000>; 1209 type = "passive"; 1210 }; 1211 gpu_target: gpu-target { 1212 temperature = <75000>; 1213 hysteresis = <2000>; 1214 type = "passive"; 1215 }; 1216 gpu_crit: gpu-crit { 1217 temperature = <95000>; 1218 hysteresis = <2000>; 1219 type = "critical"; 1220 }; 1221 }; 1222 1223 cooling-maps { 1224 map0 { 1225 trip = <&gpu_target>; 1226 cooling-device = 1227 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1228 }; 1229 }; 1230 }; 1231 }; 1232 1233 tsadc: tsadc@fe710000 { 1234 compatible = "rockchip,rk3568-tsadc"; 1235 reg = <0x0 0xfe710000 0x0 0x100>; 1236 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1237 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; 1238 assigned-clock-rates = <17000000>, <700000>; 1239 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 1240 clock-names = "tsadc", "apb_pclk"; 1241 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>, 1242 <&cru SRST_TSADCPHY>; 1243 rockchip,grf = <&grf>; 1244 rockchip,hw-tshut-temp = <95000>; 1245 pinctrl-names = "init", "default", "sleep"; 1246 pinctrl-0 = <&tsadc_pin>; 1247 pinctrl-1 = <&tsadc_shutorg>; 1248 pinctrl-2 = <&tsadc_pin>; 1249 #thermal-sensor-cells = <1>; 1250 status = "disabled"; 1251 }; 1252 1253 saradc: saradc@fe720000 { 1254 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; 1255 reg = <0x0 0xfe720000 0x0 0x100>; 1256 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1257 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1258 clock-names = "saradc", "apb_pclk"; 1259 resets = <&cru SRST_P_SARADC>; 1260 reset-names = "saradc-apb"; 1261 #io-channel-cells = <1>; 1262 status = "disabled"; 1263 }; 1264 1265 pwm4: pwm@fe6e0000 { 1266 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1267 reg = <0x0 0xfe6e0000 0x0 0x10>; 1268 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1269 clock-names = "pwm", "pclk"; 1270 pinctrl-0 = <&pwm4_pins>; 1271 pinctrl-names = "default"; 1272 #pwm-cells = <3>; 1273 status = "disabled"; 1274 }; 1275 1276 pwm5: pwm@fe6e0010 { 1277 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1278 reg = <0x0 0xfe6e0010 0x0 0x10>; 1279 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1280 clock-names = "pwm", "pclk"; 1281 pinctrl-0 = <&pwm5_pins>; 1282 pinctrl-names = "default"; 1283 #pwm-cells = <3>; 1284 status = "disabled"; 1285 }; 1286 1287 pwm6: pwm@fe6e0020 { 1288 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1289 reg = <0x0 0xfe6e0020 0x0 0x10>; 1290 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1291 clock-names = "pwm", "pclk"; 1292 pinctrl-0 = <&pwm6_pins>; 1293 pinctrl-names = "default"; 1294 #pwm-cells = <3>; 1295 status = "disabled"; 1296 }; 1297 1298 pwm7: pwm@fe6e0030 { 1299 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1300 reg = <0x0 0xfe6e0030 0x0 0x10>; 1301 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1302 clock-names = "pwm", "pclk"; 1303 pinctrl-0 = <&pwm7_pins>; 1304 pinctrl-names = "default"; 1305 #pwm-cells = <3>; 1306 status = "disabled"; 1307 }; 1308 1309 pwm8: pwm@fe6f0000 { 1310 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1311 reg = <0x0 0xfe6f0000 0x0 0x10>; 1312 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1313 clock-names = "pwm", "pclk"; 1314 pinctrl-0 = <&pwm8m0_pins>; 1315 pinctrl-names = "default"; 1316 #pwm-cells = <3>; 1317 status = "disabled"; 1318 }; 1319 1320 pwm9: pwm@fe6f0010 { 1321 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1322 reg = <0x0 0xfe6f0010 0x0 0x10>; 1323 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1324 clock-names = "pwm", "pclk"; 1325 pinctrl-0 = <&pwm9m0_pins>; 1326 pinctrl-names = "default"; 1327 #pwm-cells = <3>; 1328 status = "disabled"; 1329 }; 1330 1331 pwm10: pwm@fe6f0020 { 1332 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1333 reg = <0x0 0xfe6f0020 0x0 0x10>; 1334 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1335 clock-names = "pwm", "pclk"; 1336 pinctrl-0 = <&pwm10m0_pins>; 1337 pinctrl-names = "default"; 1338 #pwm-cells = <3>; 1339 status = "disabled"; 1340 }; 1341 1342 pwm11: pwm@fe6f0030 { 1343 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1344 reg = <0x0 0xfe6f0030 0x0 0x10>; 1345 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1346 clock-names = "pwm", "pclk"; 1347 pinctrl-0 = <&pwm11m0_pins>; 1348 pinctrl-names = "default"; 1349 #pwm-cells = <3>; 1350 status = "disabled"; 1351 }; 1352 1353 pwm12: pwm@fe700000 { 1354 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1355 reg = <0x0 0xfe700000 0x0 0x10>; 1356 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1357 clock-names = "pwm", "pclk"; 1358 pinctrl-0 = <&pwm12m0_pins>; 1359 pinctrl-names = "default"; 1360 #pwm-cells = <3>; 1361 status = "disabled"; 1362 }; 1363 1364 pwm13: pwm@fe700010 { 1365 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1366 reg = <0x0 0xfe700010 0x0 0x10>; 1367 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1368 clock-names = "pwm", "pclk"; 1369 pinctrl-0 = <&pwm13m0_pins>; 1370 pinctrl-names = "default"; 1371 #pwm-cells = <3>; 1372 status = "disabled"; 1373 }; 1374 1375 pwm14: pwm@fe700020 { 1376 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1377 reg = <0x0 0xfe700020 0x0 0x10>; 1378 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1379 clock-names = "pwm", "pclk"; 1380 pinctrl-0 = <&pwm14m0_pins>; 1381 pinctrl-names = "default"; 1382 #pwm-cells = <3>; 1383 status = "disabled"; 1384 }; 1385 1386 pwm15: pwm@fe700030 { 1387 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1388 reg = <0x0 0xfe700030 0x0 0x10>; 1389 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1390 clock-names = "pwm", "pclk"; 1391 pinctrl-0 = <&pwm15m0_pins>; 1392 pinctrl-names = "default"; 1393 #pwm-cells = <3>; 1394 status = "disabled"; 1395 }; 1396 1397 combphy1: phy@fe830000 { 1398 compatible = "rockchip,rk3568-naneng-combphy"; 1399 reg = <0x0 0xfe830000 0x0 0x100>; 1400 clocks = <&pmucru CLK_PCIEPHY1_REF>, 1401 <&cru PCLK_PIPEPHY1>, 1402 <&cru PCLK_PIPE>; 1403 clock-names = "ref", "apb", "pipe"; 1404 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; 1405 assigned-clock-rates = <100000000>; 1406 resets = <&cru SRST_PIPEPHY1>; 1407 rockchip,pipe-grf = <&pipegrf>; 1408 rockchip,pipe-phy-grf = <&pipe_phy_grf1>; 1409 #phy-cells = <1>; 1410 status = "disabled"; 1411 }; 1412 1413 combphy2: phy@fe840000 { 1414 compatible = "rockchip,rk3568-naneng-combphy"; 1415 reg = <0x0 0xfe840000 0x0 0x100>; 1416 clocks = <&pmucru CLK_PCIEPHY2_REF>, 1417 <&cru PCLK_PIPEPHY2>, 1418 <&cru PCLK_PIPE>; 1419 clock-names = "ref", "apb", "pipe"; 1420 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; 1421 assigned-clock-rates = <100000000>; 1422 resets = <&cru SRST_PIPEPHY2>; 1423 rockchip,pipe-grf = <&pipegrf>; 1424 rockchip,pipe-phy-grf = <&pipe_phy_grf2>; 1425 #phy-cells = <1>; 1426 status = "disabled"; 1427 }; 1428 1429 usb2phy0: usb2phy@fe8a0000 { 1430 compatible = "rockchip,rk3568-usb2phy"; 1431 reg = <0x0 0xfe8a0000 0x0 0x10000>; 1432 clocks = <&pmucru CLK_USBPHY0_REF>; 1433 clock-names = "phyclk"; 1434 clock-output-names = "clk_usbphy0_480m"; 1435 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 1436 rockchip,usbgrf = <&usb2phy0_grf>; 1437 #clock-cells = <0>; 1438 status = "disabled"; 1439 1440 usb2phy0_host: host-port { 1441 #phy-cells = <0>; 1442 status = "disabled"; 1443 }; 1444 1445 usb2phy0_otg: otg-port { 1446 #phy-cells = <0>; 1447 status = "disabled"; 1448 }; 1449 }; 1450 1451 usb2phy1: usb2phy@fe8b0000 { 1452 compatible = "rockchip,rk3568-usb2phy"; 1453 reg = <0x0 0xfe8b0000 0x0 0x10000>; 1454 clocks = <&pmucru CLK_USBPHY1_REF>; 1455 clock-names = "phyclk"; 1456 clock-output-names = "clk_usbphy1_480m"; 1457 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1458 rockchip,usbgrf = <&usb2phy1_grf>; 1459 #clock-cells = <0>; 1460 status = "disabled"; 1461 1462 usb2phy1_host: host-port { 1463 #phy-cells = <0>; 1464 status = "disabled"; 1465 }; 1466 1467 usb2phy1_otg: otg-port { 1468 #phy-cells = <0>; 1469 status = "disabled"; 1470 }; 1471 }; 1472 1473 pinctrl: pinctrl { 1474 compatible = "rockchip,rk3568-pinctrl"; 1475 rockchip,grf = <&grf>; 1476 rockchip,pmu = <&pmugrf>; 1477 #address-cells = <2>; 1478 #size-cells = <2>; 1479 ranges; 1480 1481 gpio0: gpio@fdd60000 { 1482 compatible = "rockchip,gpio-bank"; 1483 reg = <0x0 0xfdd60000 0x0 0x100>; 1484 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1485 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 1486 gpio-controller; 1487 #gpio-cells = <2>; 1488 interrupt-controller; 1489 #interrupt-cells = <2>; 1490 }; 1491 1492 gpio1: gpio@fe740000 { 1493 compatible = "rockchip,gpio-bank"; 1494 reg = <0x0 0xfe740000 0x0 0x100>; 1495 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1496 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1497 gpio-controller; 1498 #gpio-cells = <2>; 1499 interrupt-controller; 1500 #interrupt-cells = <2>; 1501 }; 1502 1503 gpio2: gpio@fe750000 { 1504 compatible = "rockchip,gpio-bank"; 1505 reg = <0x0 0xfe750000 0x0 0x100>; 1506 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1507 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1508 gpio-controller; 1509 #gpio-cells = <2>; 1510 interrupt-controller; 1511 #interrupt-cells = <2>; 1512 }; 1513 1514 gpio3: gpio@fe760000 { 1515 compatible = "rockchip,gpio-bank"; 1516 reg = <0x0 0xfe760000 0x0 0x100>; 1517 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1518 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1519 gpio-controller; 1520 #gpio-cells = <2>; 1521 interrupt-controller; 1522 #interrupt-cells = <2>; 1523 }; 1524 1525 gpio4: gpio@fe770000 { 1526 compatible = "rockchip,gpio-bank"; 1527 reg = <0x0 0xfe770000 0x0 0x100>; 1528 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1529 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1530 gpio-controller; 1531 #gpio-cells = <2>; 1532 interrupt-controller; 1533 #interrupt-cells = <2>; 1534 }; 1535 }; 1536}; 1537 1538#include "rk3568-pinctrl.dtsi" 1539