1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3568-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3568-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 gpio0 = &gpio0; 22 gpio1 = &gpio1; 23 gpio2 = &gpio2; 24 gpio3 = &gpio3; 25 gpio4 = &gpio4; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 i2c4 = &i2c4; 31 i2c5 = &i2c5; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 serial5 = &uart5; 38 serial6 = &uart6; 39 serial7 = &uart7; 40 serial8 = &uart8; 41 serial9 = &uart9; 42 }; 43 44 cpus { 45 #address-cells = <2>; 46 #size-cells = <0>; 47 48 cpu0: cpu@0 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a55"; 51 reg = <0x0 0x0>; 52 clocks = <&scmi_clk 0>; 53 #cooling-cells = <2>; 54 enable-method = "psci"; 55 operating-points-v2 = <&cpu0_opp_table>; 56 }; 57 58 cpu1: cpu@100 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a55"; 61 reg = <0x0 0x100>; 62 #cooling-cells = <2>; 63 enable-method = "psci"; 64 operating-points-v2 = <&cpu0_opp_table>; 65 }; 66 67 cpu2: cpu@200 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a55"; 70 reg = <0x0 0x200>; 71 #cooling-cells = <2>; 72 enable-method = "psci"; 73 operating-points-v2 = <&cpu0_opp_table>; 74 }; 75 76 cpu3: cpu@300 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a55"; 79 reg = <0x0 0x300>; 80 #cooling-cells = <2>; 81 enable-method = "psci"; 82 operating-points-v2 = <&cpu0_opp_table>; 83 }; 84 }; 85 86 cpu0_opp_table: opp-table-0 { 87 compatible = "operating-points-v2"; 88 opp-shared; 89 90 opp-408000000 { 91 opp-hz = /bits/ 64 <408000000>; 92 opp-microvolt = <900000 900000 1150000>; 93 clock-latency-ns = <40000>; 94 }; 95 96 opp-600000000 { 97 opp-hz = /bits/ 64 <600000000>; 98 opp-microvolt = <900000 900000 1150000>; 99 }; 100 101 opp-816000000 { 102 opp-hz = /bits/ 64 <816000000>; 103 opp-microvolt = <900000 900000 1150000>; 104 opp-suspend; 105 }; 106 107 opp-1104000000 { 108 opp-hz = /bits/ 64 <1104000000>; 109 opp-microvolt = <900000 900000 1150000>; 110 }; 111 112 opp-1416000000 { 113 opp-hz = /bits/ 64 <1416000000>; 114 opp-microvolt = <900000 900000 1150000>; 115 }; 116 117 opp-1608000000 { 118 opp-hz = /bits/ 64 <1608000000>; 119 opp-microvolt = <975000 975000 1150000>; 120 }; 121 122 opp-1800000000 { 123 opp-hz = /bits/ 64 <1800000000>; 124 opp-microvolt = <1050000 1050000 1150000>; 125 }; 126 }; 127 128 firmware { 129 scmi: scmi { 130 compatible = "arm,scmi-smc"; 131 arm,smc-id = <0x82000010>; 132 shmem = <&scmi_shmem>; 133 #address-cells = <1>; 134 #size-cells = <0>; 135 136 scmi_clk: protocol@14 { 137 reg = <0x14>; 138 #clock-cells = <1>; 139 }; 140 }; 141 }; 142 143 pmu { 144 compatible = "arm,cortex-a55-pmu"; 145 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 149 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 150 }; 151 152 psci { 153 compatible = "arm,psci-1.0"; 154 method = "smc"; 155 }; 156 157 timer { 158 compatible = "arm,armv8-timer"; 159 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 163 arm,no-tick-in-suspend; 164 }; 165 166 xin24m: xin24m { 167 compatible = "fixed-clock"; 168 clock-frequency = <24000000>; 169 clock-output-names = "xin24m"; 170 #clock-cells = <0>; 171 }; 172 173 xin32k: xin32k { 174 compatible = "fixed-clock"; 175 clock-frequency = <32768>; 176 clock-output-names = "xin32k"; 177 pinctrl-0 = <&clk32k_out0>; 178 pinctrl-names = "default"; 179 #clock-cells = <0>; 180 }; 181 182 sram@10f000 { 183 compatible = "mmio-sram"; 184 reg = <0x0 0x0010f000 0x0 0x100>; 185 #address-cells = <1>; 186 #size-cells = <1>; 187 ranges = <0 0x0 0x0010f000 0x100>; 188 189 scmi_shmem: sram@0 { 190 compatible = "arm,scmi-shmem"; 191 reg = <0x0 0x100>; 192 }; 193 }; 194 195 gic: interrupt-controller@fd400000 { 196 compatible = "arm,gic-v3"; 197 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ 198 <0x0 0xfd460000 0 0x80000>; /* GICR */ 199 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 200 interrupt-controller; 201 #interrupt-cells = <3>; 202 mbi-alias = <0x0 0xfd410000>; 203 mbi-ranges = <296 24>; 204 msi-controller; 205 }; 206 207 pmugrf: syscon@fdc20000 { 208 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; 209 reg = <0x0 0xfdc20000 0x0 0x10000>; 210 211 pmu_io_domains: io-domains { 212 compatible = "rockchip,rk3568-pmu-io-voltage-domain"; 213 status = "disabled"; 214 }; 215 }; 216 217 grf: syscon@fdc60000 { 218 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; 219 reg = <0x0 0xfdc60000 0x0 0x10000>; 220 }; 221 222 pmucru: clock-controller@fdd00000 { 223 compatible = "rockchip,rk3568-pmucru"; 224 reg = <0x0 0xfdd00000 0x0 0x1000>; 225 #clock-cells = <1>; 226 #reset-cells = <1>; 227 }; 228 229 cru: clock-controller@fdd20000 { 230 compatible = "rockchip,rk3568-cru"; 231 reg = <0x0 0xfdd20000 0x0 0x1000>; 232 #clock-cells = <1>; 233 #reset-cells = <1>; 234 assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; 235 assigned-clock-rates = <1200000000>, <200000000>; 236 rockchip,grf = <&grf>; 237 }; 238 239 i2c0: i2c@fdd40000 { 240 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 241 reg = <0x0 0xfdd40000 0x0 0x1000>; 242 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 244 clock-names = "i2c", "pclk"; 245 pinctrl-0 = <&i2c0_xfer>; 246 pinctrl-names = "default"; 247 #address-cells = <1>; 248 #size-cells = <0>; 249 status = "disabled"; 250 }; 251 252 uart0: serial@fdd50000 { 253 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 254 reg = <0x0 0xfdd50000 0x0 0x100>; 255 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 256 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; 257 clock-names = "baudclk", "apb_pclk"; 258 dmas = <&dmac0 0>, <&dmac0 1>; 259 pinctrl-0 = <&uart0_xfer>; 260 pinctrl-names = "default"; 261 reg-io-width = <4>; 262 reg-shift = <2>; 263 status = "disabled"; 264 }; 265 266 pwm0: pwm@fdd70000 { 267 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 268 reg = <0x0 0xfdd70000 0x0 0x10>; 269 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 270 clock-names = "pwm", "pclk"; 271 pinctrl-0 = <&pwm0m0_pins>; 272 pinctrl-names = "active"; 273 #pwm-cells = <3>; 274 status = "disabled"; 275 }; 276 277 pwm1: pwm@fdd70010 { 278 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 279 reg = <0x0 0xfdd70010 0x0 0x10>; 280 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 281 clock-names = "pwm", "pclk"; 282 pinctrl-0 = <&pwm1m0_pins>; 283 pinctrl-names = "active"; 284 #pwm-cells = <3>; 285 status = "disabled"; 286 }; 287 288 pwm2: pwm@fdd70020 { 289 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 290 reg = <0x0 0xfdd70020 0x0 0x10>; 291 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 292 clock-names = "pwm", "pclk"; 293 pinctrl-0 = <&pwm2m0_pins>; 294 pinctrl-names = "active"; 295 #pwm-cells = <3>; 296 status = "disabled"; 297 }; 298 299 pwm3: pwm@fdd70030 { 300 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 301 reg = <0x0 0xfdd70030 0x0 0x10>; 302 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 303 clock-names = "pwm", "pclk"; 304 pinctrl-0 = <&pwm3_pins>; 305 pinctrl-names = "active"; 306 #pwm-cells = <3>; 307 status = "disabled"; 308 }; 309 310 pmu: power-management@fdd90000 { 311 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; 312 reg = <0x0 0xfdd90000 0x0 0x1000>; 313 314 power: power-controller { 315 compatible = "rockchip,rk3568-power-controller"; 316 #power-domain-cells = <1>; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 320 /* These power domains are grouped by VD_GPU */ 321 power-domain@RK3568_PD_GPU { 322 reg = <RK3568_PD_GPU>; 323 clocks = <&cru ACLK_GPU_PRE>, 324 <&cru PCLK_GPU_PRE>; 325 pm_qos = <&qos_gpu>; 326 #power-domain-cells = <0>; 327 }; 328 329 /* These power domains are grouped by VD_LOGIC */ 330 power-domain@RK3568_PD_VI { 331 reg = <RK3568_PD_VI>; 332 clocks = <&cru HCLK_VI>, 333 <&cru PCLK_VI>; 334 pm_qos = <&qos_isp>, 335 <&qos_vicap0>, 336 <&qos_vicap1>; 337 #power-domain-cells = <0>; 338 }; 339 340 power-domain@RK3568_PD_VO { 341 reg = <RK3568_PD_VO>; 342 clocks = <&cru HCLK_VO>, 343 <&cru PCLK_VO>, 344 <&cru ACLK_VOP_PRE>; 345 pm_qos = <&qos_hdcp>, 346 <&qos_vop_m0>, 347 <&qos_vop_m1>; 348 #power-domain-cells = <0>; 349 }; 350 351 power-domain@RK3568_PD_RGA { 352 reg = <RK3568_PD_RGA>; 353 clocks = <&cru HCLK_RGA_PRE>, 354 <&cru PCLK_RGA_PRE>; 355 pm_qos = <&qos_ebc>, 356 <&qos_iep>, 357 <&qos_jpeg_dec>, 358 <&qos_jpeg_enc>, 359 <&qos_rga_rd>, 360 <&qos_rga_wr>; 361 #power-domain-cells = <0>; 362 }; 363 364 power-domain@RK3568_PD_VPU { 365 reg = <RK3568_PD_VPU>; 366 clocks = <&cru HCLK_VPU_PRE>; 367 pm_qos = <&qos_vpu>; 368 #power-domain-cells = <0>; 369 }; 370 371 power-domain@RK3568_PD_RKVDEC { 372 clocks = <&cru HCLK_RKVDEC_PRE>; 373 reg = <RK3568_PD_RKVDEC>; 374 pm_qos = <&qos_rkvdec>; 375 #power-domain-cells = <0>; 376 }; 377 378 power-domain@RK3568_PD_RKVENC { 379 reg = <RK3568_PD_RKVENC>; 380 clocks = <&cru HCLK_RKVENC_PRE>; 381 pm_qos = <&qos_rkvenc_rd_m0>, 382 <&qos_rkvenc_rd_m1>, 383 <&qos_rkvenc_wr_m0>; 384 #power-domain-cells = <0>; 385 }; 386 }; 387 }; 388 389 sdmmc2: mmc@fe000000 { 390 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 391 reg = <0x0 0xfe000000 0x0 0x4000>; 392 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, 394 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; 395 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 396 fifo-depth = <0x100>; 397 max-frequency = <150000000>; 398 resets = <&cru SRST_SDMMC2>; 399 reset-names = "reset"; 400 status = "disabled"; 401 }; 402 403 gmac1: ethernet@fe010000 { 404 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; 405 reg = <0x0 0xfe010000 0x0 0x10000>; 406 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 408 interrupt-names = "macirq", "eth_wake_irq"; 409 clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, 410 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, 411 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, 412 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; 413 clock-names = "stmmaceth", "mac_clk_rx", 414 "mac_clk_tx", "clk_mac_refout", 415 "aclk_mac", "pclk_mac", 416 "clk_mac_speed", "ptp_ref"; 417 resets = <&cru SRST_A_GMAC1>; 418 reset-names = "stmmaceth"; 419 rockchip,grf = <&grf>; 420 snps,axi-config = <&gmac1_stmmac_axi_setup>; 421 snps,mixed-burst; 422 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 423 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 424 snps,tso; 425 status = "disabled"; 426 427 mdio1: mdio { 428 compatible = "snps,dwmac-mdio"; 429 #address-cells = <0x1>; 430 #size-cells = <0x0>; 431 }; 432 433 gmac1_stmmac_axi_setup: stmmac-axi-config { 434 snps,blen = <0 0 0 0 16 8 4>; 435 snps,rd_osr_lmt = <8>; 436 snps,wr_osr_lmt = <4>; 437 }; 438 439 gmac1_mtl_rx_setup: rx-queues-config { 440 snps,rx-queues-to-use = <1>; 441 queue0 {}; 442 }; 443 444 gmac1_mtl_tx_setup: tx-queues-config { 445 snps,tx-queues-to-use = <1>; 446 queue0 {}; 447 }; 448 }; 449 450 qos_gpu: qos@fe128000 { 451 compatible = "rockchip,rk3568-qos", "syscon"; 452 reg = <0x0 0xfe128000 0x0 0x20>; 453 }; 454 455 qos_rkvenc_rd_m0: qos@fe138080 { 456 compatible = "rockchip,rk3568-qos", "syscon"; 457 reg = <0x0 0xfe138080 0x0 0x20>; 458 }; 459 460 qos_rkvenc_rd_m1: qos@fe138100 { 461 compatible = "rockchip,rk3568-qos", "syscon"; 462 reg = <0x0 0xfe138100 0x0 0x20>; 463 }; 464 465 qos_rkvenc_wr_m0: qos@fe138180 { 466 compatible = "rockchip,rk3568-qos", "syscon"; 467 reg = <0x0 0xfe138180 0x0 0x20>; 468 }; 469 470 qos_isp: qos@fe148000 { 471 compatible = "rockchip,rk3568-qos", "syscon"; 472 reg = <0x0 0xfe148000 0x0 0x20>; 473 }; 474 475 qos_vicap0: qos@fe148080 { 476 compatible = "rockchip,rk3568-qos", "syscon"; 477 reg = <0x0 0xfe148080 0x0 0x20>; 478 }; 479 480 qos_vicap1: qos@fe148100 { 481 compatible = "rockchip,rk3568-qos", "syscon"; 482 reg = <0x0 0xfe148100 0x0 0x20>; 483 }; 484 485 qos_vpu: qos@fe150000 { 486 compatible = "rockchip,rk3568-qos", "syscon"; 487 reg = <0x0 0xfe150000 0x0 0x20>; 488 }; 489 490 qos_ebc: qos@fe158000 { 491 compatible = "rockchip,rk3568-qos", "syscon"; 492 reg = <0x0 0xfe158000 0x0 0x20>; 493 }; 494 495 qos_iep: qos@fe158100 { 496 compatible = "rockchip,rk3568-qos", "syscon"; 497 reg = <0x0 0xfe158100 0x0 0x20>; 498 }; 499 500 qos_jpeg_dec: qos@fe158180 { 501 compatible = "rockchip,rk3568-qos", "syscon"; 502 reg = <0x0 0xfe158180 0x0 0x20>; 503 }; 504 505 qos_jpeg_enc: qos@fe158200 { 506 compatible = "rockchip,rk3568-qos", "syscon"; 507 reg = <0x0 0xfe158200 0x0 0x20>; 508 }; 509 510 qos_rga_rd: qos@fe158280 { 511 compatible = "rockchip,rk3568-qos", "syscon"; 512 reg = <0x0 0xfe158280 0x0 0x20>; 513 }; 514 515 qos_rga_wr: qos@fe158300 { 516 compatible = "rockchip,rk3568-qos", "syscon"; 517 reg = <0x0 0xfe158300 0x0 0x20>; 518 }; 519 520 qos_npu: qos@fe180000 { 521 compatible = "rockchip,rk3568-qos", "syscon"; 522 reg = <0x0 0xfe180000 0x0 0x20>; 523 }; 524 525 qos_pcie2x1: qos@fe190000 { 526 compatible = "rockchip,rk3568-qos", "syscon"; 527 reg = <0x0 0xfe190000 0x0 0x20>; 528 }; 529 530 qos_sata1: qos@fe190280 { 531 compatible = "rockchip,rk3568-qos", "syscon"; 532 reg = <0x0 0xfe190280 0x0 0x20>; 533 }; 534 535 qos_sata2: qos@fe190300 { 536 compatible = "rockchip,rk3568-qos", "syscon"; 537 reg = <0x0 0xfe190300 0x0 0x20>; 538 }; 539 540 qos_usb3_0: qos@fe190380 { 541 compatible = "rockchip,rk3568-qos", "syscon"; 542 reg = <0x0 0xfe190380 0x0 0x20>; 543 }; 544 545 qos_usb3_1: qos@fe190400 { 546 compatible = "rockchip,rk3568-qos", "syscon"; 547 reg = <0x0 0xfe190400 0x0 0x20>; 548 }; 549 550 qos_rkvdec: qos@fe198000 { 551 compatible = "rockchip,rk3568-qos", "syscon"; 552 reg = <0x0 0xfe198000 0x0 0x20>; 553 }; 554 555 qos_hdcp: qos@fe1a8000 { 556 compatible = "rockchip,rk3568-qos", "syscon"; 557 reg = <0x0 0xfe1a8000 0x0 0x20>; 558 }; 559 560 qos_vop_m0: qos@fe1a8080 { 561 compatible = "rockchip,rk3568-qos", "syscon"; 562 reg = <0x0 0xfe1a8080 0x0 0x20>; 563 }; 564 565 qos_vop_m1: qos@fe1a8100 { 566 compatible = "rockchip,rk3568-qos", "syscon"; 567 reg = <0x0 0xfe1a8100 0x0 0x20>; 568 }; 569 570 sdmmc0: mmc@fe2b0000 { 571 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 572 reg = <0x0 0xfe2b0000 0x0 0x4000>; 573 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, 575 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; 576 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 577 fifo-depth = <0x100>; 578 max-frequency = <150000000>; 579 resets = <&cru SRST_SDMMC0>; 580 reset-names = "reset"; 581 status = "disabled"; 582 }; 583 584 sdmmc1: mmc@fe2c0000 { 585 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 586 reg = <0x0 0xfe2c0000 0x0 0x4000>; 587 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, 589 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; 590 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 591 fifo-depth = <0x100>; 592 max-frequency = <150000000>; 593 resets = <&cru SRST_SDMMC1>; 594 reset-names = "reset"; 595 status = "disabled"; 596 }; 597 598 sdhci: mmc@fe310000 { 599 compatible = "rockchip,rk3568-dwcmshc"; 600 reg = <0x0 0xfe310000 0x0 0x10000>; 601 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 602 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; 603 assigned-clock-rates = <200000000>, <24000000>; 604 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 605 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 606 <&cru TCLK_EMMC>; 607 clock-names = "core", "bus", "axi", "block", "timer"; 608 status = "disabled"; 609 }; 610 611 spdif: spdif@fe460000 { 612 compatible = "rockchip,rk3568-spdif"; 613 reg = <0x0 0xfe460000 0x0 0x1000>; 614 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 615 clock-names = "mclk", "hclk"; 616 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; 617 dmas = <&dmac1 1>; 618 dma-names = "tx"; 619 pinctrl-names = "default"; 620 pinctrl-0 = <&spdifm0_tx>; 621 #sound-dai-cells = <0>; 622 status = "disabled"; 623 }; 624 625 i2s1_8ch: i2s@fe410000 { 626 compatible = "rockchip,rk3568-i2s-tdm"; 627 reg = <0x0 0xfe410000 0x0 0x1000>; 628 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 629 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>; 630 assigned-clock-rates = <1188000000>, <1188000000>; 631 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, 632 <&cru HCLK_I2S1_8CH>; 633 clock-names = "mclk_tx", "mclk_rx", "hclk"; 634 dmas = <&dmac1 3>, <&dmac1 2>; 635 dma-names = "rx", "tx"; 636 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 637 reset-names = "tx-m", "rx-m"; 638 rockchip,grf = <&grf>; 639 pinctrl-names = "default"; 640 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx 641 &i2s1m0_lrcktx &i2s1m0_lrckrx 642 &i2s1m0_sdi0 &i2s1m0_sdi1 643 &i2s1m0_sdi2 &i2s1m0_sdi3 644 &i2s1m0_sdo0 &i2s1m0_sdo1 645 &i2s1m0_sdo2 &i2s1m0_sdo3>; 646 #sound-dai-cells = <0>; 647 status = "disabled"; 648 }; 649 650 dmac0: dmac@fe530000 { 651 compatible = "arm,pl330", "arm,primecell"; 652 reg = <0x0 0xfe530000 0x0 0x4000>; 653 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 655 arm,pl330-periph-burst; 656 clocks = <&cru ACLK_BUS>; 657 clock-names = "apb_pclk"; 658 #dma-cells = <1>; 659 }; 660 661 dmac1: dmac@fe550000 { 662 compatible = "arm,pl330", "arm,primecell"; 663 reg = <0x0 0xfe550000 0x0 0x4000>; 664 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 666 arm,pl330-periph-burst; 667 clocks = <&cru ACLK_BUS>; 668 clock-names = "apb_pclk"; 669 #dma-cells = <1>; 670 }; 671 672 i2c1: i2c@fe5a0000 { 673 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 674 reg = <0x0 0xfe5a0000 0x0 0x1000>; 675 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 676 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 677 clock-names = "i2c", "pclk"; 678 pinctrl-0 = <&i2c1_xfer>; 679 pinctrl-names = "default"; 680 #address-cells = <1>; 681 #size-cells = <0>; 682 status = "disabled"; 683 }; 684 685 i2c2: i2c@fe5b0000 { 686 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 687 reg = <0x0 0xfe5b0000 0x0 0x1000>; 688 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 690 clock-names = "i2c", "pclk"; 691 pinctrl-0 = <&i2c2m0_xfer>; 692 pinctrl-names = "default"; 693 #address-cells = <1>; 694 #size-cells = <0>; 695 status = "disabled"; 696 }; 697 698 i2c3: i2c@fe5c0000 { 699 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 700 reg = <0x0 0xfe5c0000 0x0 0x1000>; 701 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 703 clock-names = "i2c", "pclk"; 704 pinctrl-0 = <&i2c3m0_xfer>; 705 pinctrl-names = "default"; 706 #address-cells = <1>; 707 #size-cells = <0>; 708 status = "disabled"; 709 }; 710 711 i2c4: i2c@fe5d0000 { 712 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 713 reg = <0x0 0xfe5d0000 0x0 0x1000>; 714 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 715 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 716 clock-names = "i2c", "pclk"; 717 pinctrl-0 = <&i2c4m0_xfer>; 718 pinctrl-names = "default"; 719 #address-cells = <1>; 720 #size-cells = <0>; 721 status = "disabled"; 722 }; 723 724 i2c5: i2c@fe5e0000 { 725 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 726 reg = <0x0 0xfe5e0000 0x0 0x1000>; 727 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 728 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 729 clock-names = "i2c", "pclk"; 730 pinctrl-0 = <&i2c5m0_xfer>; 731 pinctrl-names = "default"; 732 #address-cells = <1>; 733 #size-cells = <0>; 734 status = "disabled"; 735 }; 736 737 wdt: watchdog@fe600000 { 738 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; 739 reg = <0x0 0xfe600000 0x0 0x100>; 740 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 741 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; 742 clock-names = "tclk", "pclk"; 743 }; 744 745 uart1: serial@fe650000 { 746 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 747 reg = <0x0 0xfe650000 0x0 0x100>; 748 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 750 clock-names = "baudclk", "apb_pclk"; 751 dmas = <&dmac0 2>, <&dmac0 3>; 752 pinctrl-0 = <&uart1m0_xfer>; 753 pinctrl-names = "default"; 754 reg-io-width = <4>; 755 reg-shift = <2>; 756 status = "disabled"; 757 }; 758 759 uart2: serial@fe660000 { 760 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 761 reg = <0x0 0xfe660000 0x0 0x100>; 762 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 763 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 764 clock-names = "baudclk", "apb_pclk"; 765 dmas = <&dmac0 4>, <&dmac0 5>; 766 pinctrl-0 = <&uart2m0_xfer>; 767 pinctrl-names = "default"; 768 reg-io-width = <4>; 769 reg-shift = <2>; 770 status = "disabled"; 771 }; 772 773 uart3: serial@fe670000 { 774 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 775 reg = <0x0 0xfe670000 0x0 0x100>; 776 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 777 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 778 clock-names = "baudclk", "apb_pclk"; 779 dmas = <&dmac0 6>, <&dmac0 7>; 780 pinctrl-0 = <&uart3m0_xfer>; 781 pinctrl-names = "default"; 782 reg-io-width = <4>; 783 reg-shift = <2>; 784 status = "disabled"; 785 }; 786 787 uart4: serial@fe680000 { 788 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 789 reg = <0x0 0xfe680000 0x0 0x100>; 790 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 791 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 792 clock-names = "baudclk", "apb_pclk"; 793 dmas = <&dmac0 8>, <&dmac0 9>; 794 pinctrl-0 = <&uart4m0_xfer>; 795 pinctrl-names = "default"; 796 reg-io-width = <4>; 797 reg-shift = <2>; 798 status = "disabled"; 799 }; 800 801 uart5: serial@fe690000 { 802 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 803 reg = <0x0 0xfe690000 0x0 0x100>; 804 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 805 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 806 clock-names = "baudclk", "apb_pclk"; 807 dmas = <&dmac0 10>, <&dmac0 11>; 808 pinctrl-0 = <&uart5m0_xfer>; 809 pinctrl-names = "default"; 810 reg-io-width = <4>; 811 reg-shift = <2>; 812 status = "disabled"; 813 }; 814 815 uart6: serial@fe6a0000 { 816 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 817 reg = <0x0 0xfe6a0000 0x0 0x100>; 818 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 819 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 820 clock-names = "baudclk", "apb_pclk"; 821 dmas = <&dmac0 12>, <&dmac0 13>; 822 pinctrl-0 = <&uart6m0_xfer>; 823 pinctrl-names = "default"; 824 reg-io-width = <4>; 825 reg-shift = <2>; 826 status = "disabled"; 827 }; 828 829 uart7: serial@fe6b0000 { 830 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 831 reg = <0x0 0xfe6b0000 0x0 0x100>; 832 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 833 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 834 clock-names = "baudclk", "apb_pclk"; 835 dmas = <&dmac0 14>, <&dmac0 15>; 836 pinctrl-0 = <&uart7m0_xfer>; 837 pinctrl-names = "default"; 838 reg-io-width = <4>; 839 reg-shift = <2>; 840 status = "disabled"; 841 }; 842 843 uart8: serial@fe6c0000 { 844 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 845 reg = <0x0 0xfe6c0000 0x0 0x100>; 846 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 847 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 848 clock-names = "baudclk", "apb_pclk"; 849 dmas = <&dmac0 16>, <&dmac0 17>; 850 pinctrl-0 = <&uart8m0_xfer>; 851 pinctrl-names = "default"; 852 reg-io-width = <4>; 853 reg-shift = <2>; 854 status = "disabled"; 855 }; 856 857 uart9: serial@fe6d0000 { 858 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 859 reg = <0x0 0xfe6d0000 0x0 0x100>; 860 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 862 clock-names = "baudclk", "apb_pclk"; 863 dmas = <&dmac0 18>, <&dmac0 19>; 864 pinctrl-0 = <&uart9m0_xfer>; 865 pinctrl-names = "default"; 866 reg-io-width = <4>; 867 reg-shift = <2>; 868 status = "disabled"; 869 }; 870 871 thermal_zones: thermal-zones { 872 cpu_thermal: cpu-thermal { 873 polling-delay-passive = <100>; 874 polling-delay = <1000>; 875 876 thermal-sensors = <&tsadc 0>; 877 878 trips { 879 cpu_alert0: cpu_alert0 { 880 temperature = <70000>; 881 hysteresis = <2000>; 882 type = "passive"; 883 }; 884 cpu_alert1: cpu_alert1 { 885 temperature = <75000>; 886 hysteresis = <2000>; 887 type = "passive"; 888 }; 889 cpu_crit: cpu_crit { 890 temperature = <95000>; 891 hysteresis = <2000>; 892 type = "critical"; 893 }; 894 }; 895 896 cooling-maps { 897 map0 { 898 trip = <&cpu_alert0>; 899 cooling-device = 900 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 901 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 902 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 903 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 904 }; 905 }; 906 }; 907 908 gpu_thermal: gpu-thermal { 909 polling-delay-passive = <20>; /* milliseconds */ 910 polling-delay = <1000>; /* milliseconds */ 911 912 thermal-sensors = <&tsadc 1>; 913 }; 914 }; 915 916 tsadc: tsadc@fe710000 { 917 compatible = "rockchip,rk3568-tsadc"; 918 reg = <0x0 0xfe710000 0x0 0x100>; 919 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 920 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; 921 assigned-clock-rates = <17000000>, <700000>; 922 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 923 clock-names = "tsadc", "apb_pclk"; 924 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>, 925 <&cru SRST_TSADCPHY>; 926 rockchip,grf = <&grf>; 927 rockchip,hw-tshut-temp = <95000>; 928 pinctrl-names = "init", "default", "sleep"; 929 pinctrl-0 = <&tsadc_pin>; 930 pinctrl-1 = <&tsadc_shutorg>; 931 pinctrl-2 = <&tsadc_pin>; 932 #thermal-sensor-cells = <1>; 933 status = "disabled"; 934 }; 935 936 saradc: saradc@fe720000 { 937 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; 938 reg = <0x0 0xfe720000 0x0 0x100>; 939 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 940 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 941 clock-names = "saradc", "apb_pclk"; 942 resets = <&cru SRST_P_SARADC>; 943 reset-names = "saradc-apb"; 944 #io-channel-cells = <1>; 945 status = "disabled"; 946 }; 947 948 pwm4: pwm@fe6e0000 { 949 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 950 reg = <0x0 0xfe6e0000 0x0 0x10>; 951 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 952 clock-names = "pwm", "pclk"; 953 pinctrl-0 = <&pwm4_pins>; 954 pinctrl-names = "active"; 955 #pwm-cells = <3>; 956 status = "disabled"; 957 }; 958 959 pwm5: pwm@fe6e0010 { 960 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 961 reg = <0x0 0xfe6e0010 0x0 0x10>; 962 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 963 clock-names = "pwm", "pclk"; 964 pinctrl-0 = <&pwm5_pins>; 965 pinctrl-names = "active"; 966 #pwm-cells = <3>; 967 status = "disabled"; 968 }; 969 970 pwm6: pwm@fe6e0020 { 971 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 972 reg = <0x0 0xfe6e0020 0x0 0x10>; 973 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 974 clock-names = "pwm", "pclk"; 975 pinctrl-0 = <&pwm6_pins>; 976 pinctrl-names = "active"; 977 #pwm-cells = <3>; 978 status = "disabled"; 979 }; 980 981 pwm7: pwm@fe6e0030 { 982 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 983 reg = <0x0 0xfe6e0030 0x0 0x10>; 984 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 985 clock-names = "pwm", "pclk"; 986 pinctrl-0 = <&pwm7_pins>; 987 pinctrl-names = "active"; 988 #pwm-cells = <3>; 989 status = "disabled"; 990 }; 991 992 pwm8: pwm@fe6f0000 { 993 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 994 reg = <0x0 0xfe6f0000 0x0 0x10>; 995 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 996 clock-names = "pwm", "pclk"; 997 pinctrl-0 = <&pwm8m0_pins>; 998 pinctrl-names = "active"; 999 #pwm-cells = <3>; 1000 status = "disabled"; 1001 }; 1002 1003 pwm9: pwm@fe6f0010 { 1004 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1005 reg = <0x0 0xfe6f0010 0x0 0x10>; 1006 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1007 clock-names = "pwm", "pclk"; 1008 pinctrl-0 = <&pwm9m0_pins>; 1009 pinctrl-names = "active"; 1010 #pwm-cells = <3>; 1011 status = "disabled"; 1012 }; 1013 1014 pwm10: pwm@fe6f0020 { 1015 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1016 reg = <0x0 0xfe6f0020 0x0 0x10>; 1017 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1018 clock-names = "pwm", "pclk"; 1019 pinctrl-0 = <&pwm10m0_pins>; 1020 pinctrl-names = "active"; 1021 #pwm-cells = <3>; 1022 status = "disabled"; 1023 }; 1024 1025 pwm11: pwm@fe6f0030 { 1026 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1027 reg = <0x0 0xfe6f0030 0x0 0x10>; 1028 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1029 clock-names = "pwm", "pclk"; 1030 pinctrl-0 = <&pwm11m0_pins>; 1031 pinctrl-names = "active"; 1032 #pwm-cells = <3>; 1033 status = "disabled"; 1034 }; 1035 1036 pwm12: pwm@fe700000 { 1037 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1038 reg = <0x0 0xfe700000 0x0 0x10>; 1039 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1040 clock-names = "pwm", "pclk"; 1041 pinctrl-0 = <&pwm12m0_pins>; 1042 pinctrl-names = "active"; 1043 #pwm-cells = <3>; 1044 status = "disabled"; 1045 }; 1046 1047 pwm13: pwm@fe700010 { 1048 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1049 reg = <0x0 0xfe700010 0x0 0x10>; 1050 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1051 clock-names = "pwm", "pclk"; 1052 pinctrl-0 = <&pwm13m0_pins>; 1053 pinctrl-names = "active"; 1054 #pwm-cells = <3>; 1055 status = "disabled"; 1056 }; 1057 1058 pwm14: pwm@fe700020 { 1059 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1060 reg = <0x0 0xfe700020 0x0 0x10>; 1061 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1062 clock-names = "pwm", "pclk"; 1063 pinctrl-0 = <&pwm14m0_pins>; 1064 pinctrl-names = "active"; 1065 #pwm-cells = <3>; 1066 status = "disabled"; 1067 }; 1068 1069 pwm15: pwm@fe700030 { 1070 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1071 reg = <0x0 0xfe700030 0x0 0x10>; 1072 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1073 clock-names = "pwm", "pclk"; 1074 pinctrl-0 = <&pwm15m0_pins>; 1075 pinctrl-names = "active"; 1076 #pwm-cells = <3>; 1077 status = "disabled"; 1078 }; 1079 1080 pinctrl: pinctrl { 1081 compatible = "rockchip,rk3568-pinctrl"; 1082 rockchip,grf = <&grf>; 1083 rockchip,pmu = <&pmugrf>; 1084 #address-cells = <2>; 1085 #size-cells = <2>; 1086 ranges; 1087 1088 gpio0: gpio@fdd60000 { 1089 compatible = "rockchip,gpio-bank"; 1090 reg = <0x0 0xfdd60000 0x0 0x100>; 1091 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1092 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 1093 gpio-controller; 1094 #gpio-cells = <2>; 1095 interrupt-controller; 1096 #interrupt-cells = <2>; 1097 }; 1098 1099 gpio1: gpio@fe740000 { 1100 compatible = "rockchip,gpio-bank"; 1101 reg = <0x0 0xfe740000 0x0 0x100>; 1102 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1103 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1104 gpio-controller; 1105 #gpio-cells = <2>; 1106 interrupt-controller; 1107 #interrupt-cells = <2>; 1108 }; 1109 1110 gpio2: gpio@fe750000 { 1111 compatible = "rockchip,gpio-bank"; 1112 reg = <0x0 0xfe750000 0x0 0x100>; 1113 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1114 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1115 gpio-controller; 1116 #gpio-cells = <2>; 1117 interrupt-controller; 1118 #interrupt-cells = <2>; 1119 }; 1120 1121 gpio3: gpio@fe760000 { 1122 compatible = "rockchip,gpio-bank"; 1123 reg = <0x0 0xfe760000 0x0 0x100>; 1124 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1125 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1126 gpio-controller; 1127 #gpio-cells = <2>; 1128 interrupt-controller; 1129 #interrupt-cells = <2>; 1130 }; 1131 1132 gpio4: gpio@fe770000 { 1133 compatible = "rockchip,gpio-bank"; 1134 reg = <0x0 0xfe770000 0x0 0x100>; 1135 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1136 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1137 gpio-controller; 1138 #gpio-cells = <2>; 1139 interrupt-controller; 1140 #interrupt-cells = <2>; 1141 }; 1142 }; 1143}; 1144 1145#include "rk3568-pinctrl.dtsi" 1146