1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3568-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3568-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 gpio0 = &gpio0; 22 gpio1 = &gpio1; 23 gpio2 = &gpio2; 24 gpio3 = &gpio3; 25 gpio4 = &gpio4; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 i2c4 = &i2c4; 31 i2c5 = &i2c5; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 serial5 = &uart5; 38 serial6 = &uart6; 39 serial7 = &uart7; 40 serial8 = &uart8; 41 serial9 = &uart9; 42 spi0 = &spi0; 43 spi1 = &spi1; 44 spi2 = &spi2; 45 spi3 = &spi3; 46 }; 47 48 cpus { 49 #address-cells = <2>; 50 #size-cells = <0>; 51 52 cpu0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a55"; 55 reg = <0x0 0x0>; 56 clocks = <&scmi_clk 0>; 57 #cooling-cells = <2>; 58 enable-method = "psci"; 59 operating-points-v2 = <&cpu0_opp_table>; 60 }; 61 62 cpu1: cpu@100 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a55"; 65 reg = <0x0 0x100>; 66 #cooling-cells = <2>; 67 enable-method = "psci"; 68 operating-points-v2 = <&cpu0_opp_table>; 69 }; 70 71 cpu2: cpu@200 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a55"; 74 reg = <0x0 0x200>; 75 #cooling-cells = <2>; 76 enable-method = "psci"; 77 operating-points-v2 = <&cpu0_opp_table>; 78 }; 79 80 cpu3: cpu@300 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a55"; 83 reg = <0x0 0x300>; 84 #cooling-cells = <2>; 85 enable-method = "psci"; 86 operating-points-v2 = <&cpu0_opp_table>; 87 }; 88 }; 89 90 cpu0_opp_table: opp-table-0 { 91 compatible = "operating-points-v2"; 92 opp-shared; 93 94 opp-408000000 { 95 opp-hz = /bits/ 64 <408000000>; 96 opp-microvolt = <900000 900000 1150000>; 97 clock-latency-ns = <40000>; 98 }; 99 100 opp-600000000 { 101 opp-hz = /bits/ 64 <600000000>; 102 opp-microvolt = <900000 900000 1150000>; 103 }; 104 105 opp-816000000 { 106 opp-hz = /bits/ 64 <816000000>; 107 opp-microvolt = <900000 900000 1150000>; 108 opp-suspend; 109 }; 110 111 opp-1104000000 { 112 opp-hz = /bits/ 64 <1104000000>; 113 opp-microvolt = <900000 900000 1150000>; 114 }; 115 116 opp-1416000000 { 117 opp-hz = /bits/ 64 <1416000000>; 118 opp-microvolt = <900000 900000 1150000>; 119 }; 120 121 opp-1608000000 { 122 opp-hz = /bits/ 64 <1608000000>; 123 opp-microvolt = <975000 975000 1150000>; 124 }; 125 126 opp-1800000000 { 127 opp-hz = /bits/ 64 <1800000000>; 128 opp-microvolt = <1050000 1050000 1150000>; 129 }; 130 }; 131 132 firmware { 133 scmi: scmi { 134 compatible = "arm,scmi-smc"; 135 arm,smc-id = <0x82000010>; 136 shmem = <&scmi_shmem>; 137 #address-cells = <1>; 138 #size-cells = <0>; 139 140 scmi_clk: protocol@14 { 141 reg = <0x14>; 142 #clock-cells = <1>; 143 }; 144 }; 145 }; 146 147 pmu { 148 compatible = "arm,cortex-a55-pmu"; 149 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 153 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 154 }; 155 156 psci { 157 compatible = "arm,psci-1.0"; 158 method = "smc"; 159 }; 160 161 timer { 162 compatible = "arm,armv8-timer"; 163 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 167 arm,no-tick-in-suspend; 168 }; 169 170 xin24m: xin24m { 171 compatible = "fixed-clock"; 172 clock-frequency = <24000000>; 173 clock-output-names = "xin24m"; 174 #clock-cells = <0>; 175 }; 176 177 xin32k: xin32k { 178 compatible = "fixed-clock"; 179 clock-frequency = <32768>; 180 clock-output-names = "xin32k"; 181 pinctrl-0 = <&clk32k_out0>; 182 pinctrl-names = "default"; 183 #clock-cells = <0>; 184 }; 185 186 sram@10f000 { 187 compatible = "mmio-sram"; 188 reg = <0x0 0x0010f000 0x0 0x100>; 189 #address-cells = <1>; 190 #size-cells = <1>; 191 ranges = <0 0x0 0x0010f000 0x100>; 192 193 scmi_shmem: sram@0 { 194 compatible = "arm,scmi-shmem"; 195 reg = <0x0 0x100>; 196 }; 197 }; 198 199 gic: interrupt-controller@fd400000 { 200 compatible = "arm,gic-v3"; 201 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ 202 <0x0 0xfd460000 0 0x80000>; /* GICR */ 203 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 204 interrupt-controller; 205 #interrupt-cells = <3>; 206 mbi-alias = <0x0 0xfd410000>; 207 mbi-ranges = <296 24>; 208 msi-controller; 209 }; 210 211 pmugrf: syscon@fdc20000 { 212 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; 213 reg = <0x0 0xfdc20000 0x0 0x10000>; 214 215 pmu_io_domains: io-domains { 216 compatible = "rockchip,rk3568-pmu-io-voltage-domain"; 217 status = "disabled"; 218 }; 219 }; 220 221 grf: syscon@fdc60000 { 222 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; 223 reg = <0x0 0xfdc60000 0x0 0x10000>; 224 }; 225 226 pmucru: clock-controller@fdd00000 { 227 compatible = "rockchip,rk3568-pmucru"; 228 reg = <0x0 0xfdd00000 0x0 0x1000>; 229 #clock-cells = <1>; 230 #reset-cells = <1>; 231 }; 232 233 cru: clock-controller@fdd20000 { 234 compatible = "rockchip,rk3568-cru"; 235 reg = <0x0 0xfdd20000 0x0 0x1000>; 236 #clock-cells = <1>; 237 #reset-cells = <1>; 238 assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; 239 assigned-clock-rates = <1200000000>, <200000000>; 240 rockchip,grf = <&grf>; 241 }; 242 243 i2c0: i2c@fdd40000 { 244 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 245 reg = <0x0 0xfdd40000 0x0 0x1000>; 246 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 247 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 248 clock-names = "i2c", "pclk"; 249 pinctrl-0 = <&i2c0_xfer>; 250 pinctrl-names = "default"; 251 #address-cells = <1>; 252 #size-cells = <0>; 253 status = "disabled"; 254 }; 255 256 uart0: serial@fdd50000 { 257 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 258 reg = <0x0 0xfdd50000 0x0 0x100>; 259 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 260 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; 261 clock-names = "baudclk", "apb_pclk"; 262 dmas = <&dmac0 0>, <&dmac0 1>; 263 pinctrl-0 = <&uart0_xfer>; 264 pinctrl-names = "default"; 265 reg-io-width = <4>; 266 reg-shift = <2>; 267 status = "disabled"; 268 }; 269 270 pwm0: pwm@fdd70000 { 271 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 272 reg = <0x0 0xfdd70000 0x0 0x10>; 273 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 274 clock-names = "pwm", "pclk"; 275 pinctrl-0 = <&pwm0m0_pins>; 276 pinctrl-names = "default"; 277 #pwm-cells = <3>; 278 status = "disabled"; 279 }; 280 281 pwm1: pwm@fdd70010 { 282 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 283 reg = <0x0 0xfdd70010 0x0 0x10>; 284 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 285 clock-names = "pwm", "pclk"; 286 pinctrl-0 = <&pwm1m0_pins>; 287 pinctrl-names = "default"; 288 #pwm-cells = <3>; 289 status = "disabled"; 290 }; 291 292 pwm2: pwm@fdd70020 { 293 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 294 reg = <0x0 0xfdd70020 0x0 0x10>; 295 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 296 clock-names = "pwm", "pclk"; 297 pinctrl-0 = <&pwm2m0_pins>; 298 pinctrl-names = "default"; 299 #pwm-cells = <3>; 300 status = "disabled"; 301 }; 302 303 pwm3: pwm@fdd70030 { 304 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 305 reg = <0x0 0xfdd70030 0x0 0x10>; 306 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 307 clock-names = "pwm", "pclk"; 308 pinctrl-0 = <&pwm3_pins>; 309 pinctrl-names = "default"; 310 #pwm-cells = <3>; 311 status = "disabled"; 312 }; 313 314 pmu: power-management@fdd90000 { 315 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; 316 reg = <0x0 0xfdd90000 0x0 0x1000>; 317 318 power: power-controller { 319 compatible = "rockchip,rk3568-power-controller"; 320 #power-domain-cells = <1>; 321 #address-cells = <1>; 322 #size-cells = <0>; 323 324 /* These power domains are grouped by VD_GPU */ 325 power-domain@RK3568_PD_GPU { 326 reg = <RK3568_PD_GPU>; 327 clocks = <&cru ACLK_GPU_PRE>, 328 <&cru PCLK_GPU_PRE>; 329 pm_qos = <&qos_gpu>; 330 #power-domain-cells = <0>; 331 }; 332 333 /* These power domains are grouped by VD_LOGIC */ 334 power-domain@RK3568_PD_VI { 335 reg = <RK3568_PD_VI>; 336 clocks = <&cru HCLK_VI>, 337 <&cru PCLK_VI>; 338 pm_qos = <&qos_isp>, 339 <&qos_vicap0>, 340 <&qos_vicap1>; 341 #power-domain-cells = <0>; 342 }; 343 344 power-domain@RK3568_PD_VO { 345 reg = <RK3568_PD_VO>; 346 clocks = <&cru HCLK_VO>, 347 <&cru PCLK_VO>, 348 <&cru ACLK_VOP_PRE>; 349 pm_qos = <&qos_hdcp>, 350 <&qos_vop_m0>, 351 <&qos_vop_m1>; 352 #power-domain-cells = <0>; 353 }; 354 355 power-domain@RK3568_PD_RGA { 356 reg = <RK3568_PD_RGA>; 357 clocks = <&cru HCLK_RGA_PRE>, 358 <&cru PCLK_RGA_PRE>; 359 pm_qos = <&qos_ebc>, 360 <&qos_iep>, 361 <&qos_jpeg_dec>, 362 <&qos_jpeg_enc>, 363 <&qos_rga_rd>, 364 <&qos_rga_wr>; 365 #power-domain-cells = <0>; 366 }; 367 368 power-domain@RK3568_PD_VPU { 369 reg = <RK3568_PD_VPU>; 370 clocks = <&cru HCLK_VPU_PRE>; 371 pm_qos = <&qos_vpu>; 372 #power-domain-cells = <0>; 373 }; 374 375 power-domain@RK3568_PD_RKVDEC { 376 clocks = <&cru HCLK_RKVDEC_PRE>; 377 reg = <RK3568_PD_RKVDEC>; 378 pm_qos = <&qos_rkvdec>; 379 #power-domain-cells = <0>; 380 }; 381 382 power-domain@RK3568_PD_RKVENC { 383 reg = <RK3568_PD_RKVENC>; 384 clocks = <&cru HCLK_RKVENC_PRE>; 385 pm_qos = <&qos_rkvenc_rd_m0>, 386 <&qos_rkvenc_rd_m1>, 387 <&qos_rkvenc_wr_m0>; 388 #power-domain-cells = <0>; 389 }; 390 }; 391 }; 392 393 sdmmc2: mmc@fe000000 { 394 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 395 reg = <0x0 0xfe000000 0x0 0x4000>; 396 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 397 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, 398 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; 399 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 400 fifo-depth = <0x100>; 401 max-frequency = <150000000>; 402 resets = <&cru SRST_SDMMC2>; 403 reset-names = "reset"; 404 status = "disabled"; 405 }; 406 407 gmac1: ethernet@fe010000 { 408 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; 409 reg = <0x0 0xfe010000 0x0 0x10000>; 410 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 412 interrupt-names = "macirq", "eth_wake_irq"; 413 clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, 414 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, 415 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, 416 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; 417 clock-names = "stmmaceth", "mac_clk_rx", 418 "mac_clk_tx", "clk_mac_refout", 419 "aclk_mac", "pclk_mac", 420 "clk_mac_speed", "ptp_ref"; 421 resets = <&cru SRST_A_GMAC1>; 422 reset-names = "stmmaceth"; 423 rockchip,grf = <&grf>; 424 snps,axi-config = <&gmac1_stmmac_axi_setup>; 425 snps,mixed-burst; 426 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 427 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 428 snps,tso; 429 status = "disabled"; 430 431 mdio1: mdio { 432 compatible = "snps,dwmac-mdio"; 433 #address-cells = <0x1>; 434 #size-cells = <0x0>; 435 }; 436 437 gmac1_stmmac_axi_setup: stmmac-axi-config { 438 snps,blen = <0 0 0 0 16 8 4>; 439 snps,rd_osr_lmt = <8>; 440 snps,wr_osr_lmt = <4>; 441 }; 442 443 gmac1_mtl_rx_setup: rx-queues-config { 444 snps,rx-queues-to-use = <1>; 445 queue0 {}; 446 }; 447 448 gmac1_mtl_tx_setup: tx-queues-config { 449 snps,tx-queues-to-use = <1>; 450 queue0 {}; 451 }; 452 }; 453 454 qos_gpu: qos@fe128000 { 455 compatible = "rockchip,rk3568-qos", "syscon"; 456 reg = <0x0 0xfe128000 0x0 0x20>; 457 }; 458 459 qos_rkvenc_rd_m0: qos@fe138080 { 460 compatible = "rockchip,rk3568-qos", "syscon"; 461 reg = <0x0 0xfe138080 0x0 0x20>; 462 }; 463 464 qos_rkvenc_rd_m1: qos@fe138100 { 465 compatible = "rockchip,rk3568-qos", "syscon"; 466 reg = <0x0 0xfe138100 0x0 0x20>; 467 }; 468 469 qos_rkvenc_wr_m0: qos@fe138180 { 470 compatible = "rockchip,rk3568-qos", "syscon"; 471 reg = <0x0 0xfe138180 0x0 0x20>; 472 }; 473 474 qos_isp: qos@fe148000 { 475 compatible = "rockchip,rk3568-qos", "syscon"; 476 reg = <0x0 0xfe148000 0x0 0x20>; 477 }; 478 479 qos_vicap0: qos@fe148080 { 480 compatible = "rockchip,rk3568-qos", "syscon"; 481 reg = <0x0 0xfe148080 0x0 0x20>; 482 }; 483 484 qos_vicap1: qos@fe148100 { 485 compatible = "rockchip,rk3568-qos", "syscon"; 486 reg = <0x0 0xfe148100 0x0 0x20>; 487 }; 488 489 qos_vpu: qos@fe150000 { 490 compatible = "rockchip,rk3568-qos", "syscon"; 491 reg = <0x0 0xfe150000 0x0 0x20>; 492 }; 493 494 qos_ebc: qos@fe158000 { 495 compatible = "rockchip,rk3568-qos", "syscon"; 496 reg = <0x0 0xfe158000 0x0 0x20>; 497 }; 498 499 qos_iep: qos@fe158100 { 500 compatible = "rockchip,rk3568-qos", "syscon"; 501 reg = <0x0 0xfe158100 0x0 0x20>; 502 }; 503 504 qos_jpeg_dec: qos@fe158180 { 505 compatible = "rockchip,rk3568-qos", "syscon"; 506 reg = <0x0 0xfe158180 0x0 0x20>; 507 }; 508 509 qos_jpeg_enc: qos@fe158200 { 510 compatible = "rockchip,rk3568-qos", "syscon"; 511 reg = <0x0 0xfe158200 0x0 0x20>; 512 }; 513 514 qos_rga_rd: qos@fe158280 { 515 compatible = "rockchip,rk3568-qos", "syscon"; 516 reg = <0x0 0xfe158280 0x0 0x20>; 517 }; 518 519 qos_rga_wr: qos@fe158300 { 520 compatible = "rockchip,rk3568-qos", "syscon"; 521 reg = <0x0 0xfe158300 0x0 0x20>; 522 }; 523 524 qos_npu: qos@fe180000 { 525 compatible = "rockchip,rk3568-qos", "syscon"; 526 reg = <0x0 0xfe180000 0x0 0x20>; 527 }; 528 529 qos_pcie2x1: qos@fe190000 { 530 compatible = "rockchip,rk3568-qos", "syscon"; 531 reg = <0x0 0xfe190000 0x0 0x20>; 532 }; 533 534 qos_sata1: qos@fe190280 { 535 compatible = "rockchip,rk3568-qos", "syscon"; 536 reg = <0x0 0xfe190280 0x0 0x20>; 537 }; 538 539 qos_sata2: qos@fe190300 { 540 compatible = "rockchip,rk3568-qos", "syscon"; 541 reg = <0x0 0xfe190300 0x0 0x20>; 542 }; 543 544 qos_usb3_0: qos@fe190380 { 545 compatible = "rockchip,rk3568-qos", "syscon"; 546 reg = <0x0 0xfe190380 0x0 0x20>; 547 }; 548 549 qos_usb3_1: qos@fe190400 { 550 compatible = "rockchip,rk3568-qos", "syscon"; 551 reg = <0x0 0xfe190400 0x0 0x20>; 552 }; 553 554 qos_rkvdec: qos@fe198000 { 555 compatible = "rockchip,rk3568-qos", "syscon"; 556 reg = <0x0 0xfe198000 0x0 0x20>; 557 }; 558 559 qos_hdcp: qos@fe1a8000 { 560 compatible = "rockchip,rk3568-qos", "syscon"; 561 reg = <0x0 0xfe1a8000 0x0 0x20>; 562 }; 563 564 qos_vop_m0: qos@fe1a8080 { 565 compatible = "rockchip,rk3568-qos", "syscon"; 566 reg = <0x0 0xfe1a8080 0x0 0x20>; 567 }; 568 569 qos_vop_m1: qos@fe1a8100 { 570 compatible = "rockchip,rk3568-qos", "syscon"; 571 reg = <0x0 0xfe1a8100 0x0 0x20>; 572 }; 573 574 sdmmc0: mmc@fe2b0000 { 575 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 576 reg = <0x0 0xfe2b0000 0x0 0x4000>; 577 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, 579 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; 580 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 581 fifo-depth = <0x100>; 582 max-frequency = <150000000>; 583 resets = <&cru SRST_SDMMC0>; 584 reset-names = "reset"; 585 status = "disabled"; 586 }; 587 588 sdmmc1: mmc@fe2c0000 { 589 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 590 reg = <0x0 0xfe2c0000 0x0 0x4000>; 591 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 592 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, 593 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; 594 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 595 fifo-depth = <0x100>; 596 max-frequency = <150000000>; 597 resets = <&cru SRST_SDMMC1>; 598 reset-names = "reset"; 599 status = "disabled"; 600 }; 601 602 sdhci: mmc@fe310000 { 603 compatible = "rockchip,rk3568-dwcmshc"; 604 reg = <0x0 0xfe310000 0x0 0x10000>; 605 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 606 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; 607 assigned-clock-rates = <200000000>, <24000000>; 608 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 609 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 610 <&cru TCLK_EMMC>; 611 clock-names = "core", "bus", "axi", "block", "timer"; 612 status = "disabled"; 613 }; 614 615 spdif: spdif@fe460000 { 616 compatible = "rockchip,rk3568-spdif"; 617 reg = <0x0 0xfe460000 0x0 0x1000>; 618 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 619 clock-names = "mclk", "hclk"; 620 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; 621 dmas = <&dmac1 1>; 622 dma-names = "tx"; 623 pinctrl-names = "default"; 624 pinctrl-0 = <&spdifm0_tx>; 625 #sound-dai-cells = <0>; 626 status = "disabled"; 627 }; 628 629 i2s1_8ch: i2s@fe410000 { 630 compatible = "rockchip,rk3568-i2s-tdm"; 631 reg = <0x0 0xfe410000 0x0 0x1000>; 632 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 633 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>; 634 assigned-clock-rates = <1188000000>, <1188000000>; 635 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, 636 <&cru HCLK_I2S1_8CH>; 637 clock-names = "mclk_tx", "mclk_rx", "hclk"; 638 dmas = <&dmac1 3>, <&dmac1 2>; 639 dma-names = "rx", "tx"; 640 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 641 reset-names = "tx-m", "rx-m"; 642 rockchip,grf = <&grf>; 643 pinctrl-names = "default"; 644 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx 645 &i2s1m0_lrcktx &i2s1m0_lrckrx 646 &i2s1m0_sdi0 &i2s1m0_sdi1 647 &i2s1m0_sdi2 &i2s1m0_sdi3 648 &i2s1m0_sdo0 &i2s1m0_sdo1 649 &i2s1m0_sdo2 &i2s1m0_sdo3>; 650 #sound-dai-cells = <0>; 651 status = "disabled"; 652 }; 653 654 dmac0: dmac@fe530000 { 655 compatible = "arm,pl330", "arm,primecell"; 656 reg = <0x0 0xfe530000 0x0 0x4000>; 657 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 659 arm,pl330-periph-burst; 660 clocks = <&cru ACLK_BUS>; 661 clock-names = "apb_pclk"; 662 #dma-cells = <1>; 663 }; 664 665 dmac1: dmac@fe550000 { 666 compatible = "arm,pl330", "arm,primecell"; 667 reg = <0x0 0xfe550000 0x0 0x4000>; 668 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 670 arm,pl330-periph-burst; 671 clocks = <&cru ACLK_BUS>; 672 clock-names = "apb_pclk"; 673 #dma-cells = <1>; 674 }; 675 676 i2c1: i2c@fe5a0000 { 677 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 678 reg = <0x0 0xfe5a0000 0x0 0x1000>; 679 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 680 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 681 clock-names = "i2c", "pclk"; 682 pinctrl-0 = <&i2c1_xfer>; 683 pinctrl-names = "default"; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 status = "disabled"; 687 }; 688 689 i2c2: i2c@fe5b0000 { 690 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 691 reg = <0x0 0xfe5b0000 0x0 0x1000>; 692 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 693 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 694 clock-names = "i2c", "pclk"; 695 pinctrl-0 = <&i2c2m0_xfer>; 696 pinctrl-names = "default"; 697 #address-cells = <1>; 698 #size-cells = <0>; 699 status = "disabled"; 700 }; 701 702 i2c3: i2c@fe5c0000 { 703 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 704 reg = <0x0 0xfe5c0000 0x0 0x1000>; 705 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 706 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 707 clock-names = "i2c", "pclk"; 708 pinctrl-0 = <&i2c3m0_xfer>; 709 pinctrl-names = "default"; 710 #address-cells = <1>; 711 #size-cells = <0>; 712 status = "disabled"; 713 }; 714 715 i2c4: i2c@fe5d0000 { 716 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 717 reg = <0x0 0xfe5d0000 0x0 0x1000>; 718 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 719 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 720 clock-names = "i2c", "pclk"; 721 pinctrl-0 = <&i2c4m0_xfer>; 722 pinctrl-names = "default"; 723 #address-cells = <1>; 724 #size-cells = <0>; 725 status = "disabled"; 726 }; 727 728 i2c5: i2c@fe5e0000 { 729 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 730 reg = <0x0 0xfe5e0000 0x0 0x1000>; 731 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 732 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 733 clock-names = "i2c", "pclk"; 734 pinctrl-0 = <&i2c5m0_xfer>; 735 pinctrl-names = "default"; 736 #address-cells = <1>; 737 #size-cells = <0>; 738 status = "disabled"; 739 }; 740 741 wdt: watchdog@fe600000 { 742 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; 743 reg = <0x0 0xfe600000 0x0 0x100>; 744 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 745 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; 746 clock-names = "tclk", "pclk"; 747 }; 748 749 spi0: spi@fe610000 { 750 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 751 reg = <0x0 0xfe610000 0x0 0x1000>; 752 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 753 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 754 clock-names = "spiclk", "apb_pclk"; 755 dmas = <&dmac0 20>, <&dmac0 21>; 756 dma-names = "tx", "rx"; 757 pinctrl-names = "default"; 758 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 759 #address-cells = <1>; 760 #size-cells = <0>; 761 status = "disabled"; 762 }; 763 764 spi1: spi@fe620000 { 765 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 766 reg = <0x0 0xfe620000 0x0 0x1000>; 767 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 768 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 769 clock-names = "spiclk", "apb_pclk"; 770 dmas = <&dmac0 22>, <&dmac0 23>; 771 dma-names = "tx", "rx"; 772 pinctrl-names = "default"; 773 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; 774 #address-cells = <1>; 775 #size-cells = <0>; 776 status = "disabled"; 777 }; 778 779 spi2: spi@fe630000 { 780 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 781 reg = <0x0 0xfe630000 0x0 0x1000>; 782 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 783 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 784 clock-names = "spiclk", "apb_pclk"; 785 dmas = <&dmac0 24>, <&dmac0 25>; 786 dma-names = "tx", "rx"; 787 pinctrl-names = "default"; 788 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; 789 #address-cells = <1>; 790 #size-cells = <0>; 791 status = "disabled"; 792 }; 793 794 spi3: spi@fe640000 { 795 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 796 reg = <0x0 0xfe640000 0x0 0x1000>; 797 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 798 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 799 clock-names = "spiclk", "apb_pclk"; 800 dmas = <&dmac0 26>, <&dmac0 27>; 801 dma-names = "tx", "rx"; 802 pinctrl-names = "default"; 803 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>; 804 #address-cells = <1>; 805 #size-cells = <0>; 806 status = "disabled"; 807 }; 808 809 uart1: serial@fe650000 { 810 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 811 reg = <0x0 0xfe650000 0x0 0x100>; 812 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 814 clock-names = "baudclk", "apb_pclk"; 815 dmas = <&dmac0 2>, <&dmac0 3>; 816 pinctrl-0 = <&uart1m0_xfer>; 817 pinctrl-names = "default"; 818 reg-io-width = <4>; 819 reg-shift = <2>; 820 status = "disabled"; 821 }; 822 823 uart2: serial@fe660000 { 824 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 825 reg = <0x0 0xfe660000 0x0 0x100>; 826 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 827 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 828 clock-names = "baudclk", "apb_pclk"; 829 dmas = <&dmac0 4>, <&dmac0 5>; 830 pinctrl-0 = <&uart2m0_xfer>; 831 pinctrl-names = "default"; 832 reg-io-width = <4>; 833 reg-shift = <2>; 834 status = "disabled"; 835 }; 836 837 uart3: serial@fe670000 { 838 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 839 reg = <0x0 0xfe670000 0x0 0x100>; 840 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 841 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 842 clock-names = "baudclk", "apb_pclk"; 843 dmas = <&dmac0 6>, <&dmac0 7>; 844 pinctrl-0 = <&uart3m0_xfer>; 845 pinctrl-names = "default"; 846 reg-io-width = <4>; 847 reg-shift = <2>; 848 status = "disabled"; 849 }; 850 851 uart4: serial@fe680000 { 852 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 853 reg = <0x0 0xfe680000 0x0 0x100>; 854 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 855 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 856 clock-names = "baudclk", "apb_pclk"; 857 dmas = <&dmac0 8>, <&dmac0 9>; 858 pinctrl-0 = <&uart4m0_xfer>; 859 pinctrl-names = "default"; 860 reg-io-width = <4>; 861 reg-shift = <2>; 862 status = "disabled"; 863 }; 864 865 uart5: serial@fe690000 { 866 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 867 reg = <0x0 0xfe690000 0x0 0x100>; 868 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 870 clock-names = "baudclk", "apb_pclk"; 871 dmas = <&dmac0 10>, <&dmac0 11>; 872 pinctrl-0 = <&uart5m0_xfer>; 873 pinctrl-names = "default"; 874 reg-io-width = <4>; 875 reg-shift = <2>; 876 status = "disabled"; 877 }; 878 879 uart6: serial@fe6a0000 { 880 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 881 reg = <0x0 0xfe6a0000 0x0 0x100>; 882 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 883 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 884 clock-names = "baudclk", "apb_pclk"; 885 dmas = <&dmac0 12>, <&dmac0 13>; 886 pinctrl-0 = <&uart6m0_xfer>; 887 pinctrl-names = "default"; 888 reg-io-width = <4>; 889 reg-shift = <2>; 890 status = "disabled"; 891 }; 892 893 uart7: serial@fe6b0000 { 894 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 895 reg = <0x0 0xfe6b0000 0x0 0x100>; 896 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 897 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 898 clock-names = "baudclk", "apb_pclk"; 899 dmas = <&dmac0 14>, <&dmac0 15>; 900 pinctrl-0 = <&uart7m0_xfer>; 901 pinctrl-names = "default"; 902 reg-io-width = <4>; 903 reg-shift = <2>; 904 status = "disabled"; 905 }; 906 907 uart8: serial@fe6c0000 { 908 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 909 reg = <0x0 0xfe6c0000 0x0 0x100>; 910 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 911 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 912 clock-names = "baudclk", "apb_pclk"; 913 dmas = <&dmac0 16>, <&dmac0 17>; 914 pinctrl-0 = <&uart8m0_xfer>; 915 pinctrl-names = "default"; 916 reg-io-width = <4>; 917 reg-shift = <2>; 918 status = "disabled"; 919 }; 920 921 uart9: serial@fe6d0000 { 922 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 923 reg = <0x0 0xfe6d0000 0x0 0x100>; 924 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 925 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 926 clock-names = "baudclk", "apb_pclk"; 927 dmas = <&dmac0 18>, <&dmac0 19>; 928 pinctrl-0 = <&uart9m0_xfer>; 929 pinctrl-names = "default"; 930 reg-io-width = <4>; 931 reg-shift = <2>; 932 status = "disabled"; 933 }; 934 935 thermal_zones: thermal-zones { 936 cpu_thermal: cpu-thermal { 937 polling-delay-passive = <100>; 938 polling-delay = <1000>; 939 940 thermal-sensors = <&tsadc 0>; 941 942 trips { 943 cpu_alert0: cpu_alert0 { 944 temperature = <70000>; 945 hysteresis = <2000>; 946 type = "passive"; 947 }; 948 cpu_alert1: cpu_alert1 { 949 temperature = <75000>; 950 hysteresis = <2000>; 951 type = "passive"; 952 }; 953 cpu_crit: cpu_crit { 954 temperature = <95000>; 955 hysteresis = <2000>; 956 type = "critical"; 957 }; 958 }; 959 960 cooling-maps { 961 map0 { 962 trip = <&cpu_alert0>; 963 cooling-device = 964 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 965 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 966 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 967 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 968 }; 969 }; 970 }; 971 972 gpu_thermal: gpu-thermal { 973 polling-delay-passive = <20>; /* milliseconds */ 974 polling-delay = <1000>; /* milliseconds */ 975 976 thermal-sensors = <&tsadc 1>; 977 }; 978 }; 979 980 tsadc: tsadc@fe710000 { 981 compatible = "rockchip,rk3568-tsadc"; 982 reg = <0x0 0xfe710000 0x0 0x100>; 983 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 984 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; 985 assigned-clock-rates = <17000000>, <700000>; 986 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 987 clock-names = "tsadc", "apb_pclk"; 988 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>, 989 <&cru SRST_TSADCPHY>; 990 rockchip,grf = <&grf>; 991 rockchip,hw-tshut-temp = <95000>; 992 pinctrl-names = "init", "default", "sleep"; 993 pinctrl-0 = <&tsadc_pin>; 994 pinctrl-1 = <&tsadc_shutorg>; 995 pinctrl-2 = <&tsadc_pin>; 996 #thermal-sensor-cells = <1>; 997 status = "disabled"; 998 }; 999 1000 saradc: saradc@fe720000 { 1001 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; 1002 reg = <0x0 0xfe720000 0x0 0x100>; 1003 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1004 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1005 clock-names = "saradc", "apb_pclk"; 1006 resets = <&cru SRST_P_SARADC>; 1007 reset-names = "saradc-apb"; 1008 #io-channel-cells = <1>; 1009 status = "disabled"; 1010 }; 1011 1012 pwm4: pwm@fe6e0000 { 1013 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1014 reg = <0x0 0xfe6e0000 0x0 0x10>; 1015 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1016 clock-names = "pwm", "pclk"; 1017 pinctrl-0 = <&pwm4_pins>; 1018 pinctrl-names = "default"; 1019 #pwm-cells = <3>; 1020 status = "disabled"; 1021 }; 1022 1023 pwm5: pwm@fe6e0010 { 1024 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1025 reg = <0x0 0xfe6e0010 0x0 0x10>; 1026 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1027 clock-names = "pwm", "pclk"; 1028 pinctrl-0 = <&pwm5_pins>; 1029 pinctrl-names = "default"; 1030 #pwm-cells = <3>; 1031 status = "disabled"; 1032 }; 1033 1034 pwm6: pwm@fe6e0020 { 1035 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1036 reg = <0x0 0xfe6e0020 0x0 0x10>; 1037 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1038 clock-names = "pwm", "pclk"; 1039 pinctrl-0 = <&pwm6_pins>; 1040 pinctrl-names = "default"; 1041 #pwm-cells = <3>; 1042 status = "disabled"; 1043 }; 1044 1045 pwm7: pwm@fe6e0030 { 1046 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1047 reg = <0x0 0xfe6e0030 0x0 0x10>; 1048 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1049 clock-names = "pwm", "pclk"; 1050 pinctrl-0 = <&pwm7_pins>; 1051 pinctrl-names = "default"; 1052 #pwm-cells = <3>; 1053 status = "disabled"; 1054 }; 1055 1056 pwm8: pwm@fe6f0000 { 1057 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1058 reg = <0x0 0xfe6f0000 0x0 0x10>; 1059 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1060 clock-names = "pwm", "pclk"; 1061 pinctrl-0 = <&pwm8m0_pins>; 1062 pinctrl-names = "default"; 1063 #pwm-cells = <3>; 1064 status = "disabled"; 1065 }; 1066 1067 pwm9: pwm@fe6f0010 { 1068 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1069 reg = <0x0 0xfe6f0010 0x0 0x10>; 1070 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1071 clock-names = "pwm", "pclk"; 1072 pinctrl-0 = <&pwm9m0_pins>; 1073 pinctrl-names = "default"; 1074 #pwm-cells = <3>; 1075 status = "disabled"; 1076 }; 1077 1078 pwm10: pwm@fe6f0020 { 1079 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1080 reg = <0x0 0xfe6f0020 0x0 0x10>; 1081 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1082 clock-names = "pwm", "pclk"; 1083 pinctrl-0 = <&pwm10m0_pins>; 1084 pinctrl-names = "default"; 1085 #pwm-cells = <3>; 1086 status = "disabled"; 1087 }; 1088 1089 pwm11: pwm@fe6f0030 { 1090 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1091 reg = <0x0 0xfe6f0030 0x0 0x10>; 1092 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1093 clock-names = "pwm", "pclk"; 1094 pinctrl-0 = <&pwm11m0_pins>; 1095 pinctrl-names = "default"; 1096 #pwm-cells = <3>; 1097 status = "disabled"; 1098 }; 1099 1100 pwm12: pwm@fe700000 { 1101 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1102 reg = <0x0 0xfe700000 0x0 0x10>; 1103 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1104 clock-names = "pwm", "pclk"; 1105 pinctrl-0 = <&pwm12m0_pins>; 1106 pinctrl-names = "default"; 1107 #pwm-cells = <3>; 1108 status = "disabled"; 1109 }; 1110 1111 pwm13: pwm@fe700010 { 1112 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1113 reg = <0x0 0xfe700010 0x0 0x10>; 1114 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1115 clock-names = "pwm", "pclk"; 1116 pinctrl-0 = <&pwm13m0_pins>; 1117 pinctrl-names = "default"; 1118 #pwm-cells = <3>; 1119 status = "disabled"; 1120 }; 1121 1122 pwm14: pwm@fe700020 { 1123 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1124 reg = <0x0 0xfe700020 0x0 0x10>; 1125 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1126 clock-names = "pwm", "pclk"; 1127 pinctrl-0 = <&pwm14m0_pins>; 1128 pinctrl-names = "default"; 1129 #pwm-cells = <3>; 1130 status = "disabled"; 1131 }; 1132 1133 pwm15: pwm@fe700030 { 1134 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1135 reg = <0x0 0xfe700030 0x0 0x10>; 1136 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1137 clock-names = "pwm", "pclk"; 1138 pinctrl-0 = <&pwm15m0_pins>; 1139 pinctrl-names = "default"; 1140 #pwm-cells = <3>; 1141 status = "disabled"; 1142 }; 1143 1144 pinctrl: pinctrl { 1145 compatible = "rockchip,rk3568-pinctrl"; 1146 rockchip,grf = <&grf>; 1147 rockchip,pmu = <&pmugrf>; 1148 #address-cells = <2>; 1149 #size-cells = <2>; 1150 ranges; 1151 1152 gpio0: gpio@fdd60000 { 1153 compatible = "rockchip,gpio-bank"; 1154 reg = <0x0 0xfdd60000 0x0 0x100>; 1155 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1156 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 1157 gpio-controller; 1158 #gpio-cells = <2>; 1159 interrupt-controller; 1160 #interrupt-cells = <2>; 1161 }; 1162 1163 gpio1: gpio@fe740000 { 1164 compatible = "rockchip,gpio-bank"; 1165 reg = <0x0 0xfe740000 0x0 0x100>; 1166 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1167 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1168 gpio-controller; 1169 #gpio-cells = <2>; 1170 interrupt-controller; 1171 #interrupt-cells = <2>; 1172 }; 1173 1174 gpio2: gpio@fe750000 { 1175 compatible = "rockchip,gpio-bank"; 1176 reg = <0x0 0xfe750000 0x0 0x100>; 1177 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1178 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1179 gpio-controller; 1180 #gpio-cells = <2>; 1181 interrupt-controller; 1182 #interrupt-cells = <2>; 1183 }; 1184 1185 gpio3: gpio@fe760000 { 1186 compatible = "rockchip,gpio-bank"; 1187 reg = <0x0 0xfe760000 0x0 0x100>; 1188 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1189 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1190 gpio-controller; 1191 #gpio-cells = <2>; 1192 interrupt-controller; 1193 #interrupt-cells = <2>; 1194 }; 1195 1196 gpio4: gpio@fe770000 { 1197 compatible = "rockchip,gpio-bank"; 1198 reg = <0x0 0xfe770000 0x0 0x100>; 1199 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1200 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1201 gpio-controller; 1202 #gpio-cells = <2>; 1203 interrupt-controller; 1204 #interrupt-cells = <2>; 1205 }; 1206 }; 1207}; 1208 1209#include "rk3568-pinctrl.dtsi" 1210