1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3568-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3568-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 gpio0 = &gpio0; 22 gpio1 = &gpio1; 23 gpio2 = &gpio2; 24 gpio3 = &gpio3; 25 gpio4 = &gpio4; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 i2c4 = &i2c4; 31 i2c5 = &i2c5; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 serial5 = &uart5; 38 serial6 = &uart6; 39 serial7 = &uart7; 40 serial8 = &uart8; 41 serial9 = &uart9; 42 spi0 = &spi0; 43 spi1 = &spi1; 44 spi2 = &spi2; 45 spi3 = &spi3; 46 }; 47 48 cpus { 49 #address-cells = <2>; 50 #size-cells = <0>; 51 52 cpu0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a55"; 55 reg = <0x0 0x0>; 56 clocks = <&scmi_clk 0>; 57 #cooling-cells = <2>; 58 enable-method = "psci"; 59 operating-points-v2 = <&cpu0_opp_table>; 60 }; 61 62 cpu1: cpu@100 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a55"; 65 reg = <0x0 0x100>; 66 #cooling-cells = <2>; 67 enable-method = "psci"; 68 operating-points-v2 = <&cpu0_opp_table>; 69 }; 70 71 cpu2: cpu@200 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a55"; 74 reg = <0x0 0x200>; 75 #cooling-cells = <2>; 76 enable-method = "psci"; 77 operating-points-v2 = <&cpu0_opp_table>; 78 }; 79 80 cpu3: cpu@300 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a55"; 83 reg = <0x0 0x300>; 84 #cooling-cells = <2>; 85 enable-method = "psci"; 86 operating-points-v2 = <&cpu0_opp_table>; 87 }; 88 }; 89 90 cpu0_opp_table: opp-table-0 { 91 compatible = "operating-points-v2"; 92 opp-shared; 93 94 opp-408000000 { 95 opp-hz = /bits/ 64 <408000000>; 96 opp-microvolt = <900000 900000 1150000>; 97 clock-latency-ns = <40000>; 98 }; 99 100 opp-600000000 { 101 opp-hz = /bits/ 64 <600000000>; 102 opp-microvolt = <900000 900000 1150000>; 103 }; 104 105 opp-816000000 { 106 opp-hz = /bits/ 64 <816000000>; 107 opp-microvolt = <900000 900000 1150000>; 108 opp-suspend; 109 }; 110 111 opp-1104000000 { 112 opp-hz = /bits/ 64 <1104000000>; 113 opp-microvolt = <900000 900000 1150000>; 114 }; 115 116 opp-1416000000 { 117 opp-hz = /bits/ 64 <1416000000>; 118 opp-microvolt = <900000 900000 1150000>; 119 }; 120 121 opp-1608000000 { 122 opp-hz = /bits/ 64 <1608000000>; 123 opp-microvolt = <975000 975000 1150000>; 124 }; 125 126 opp-1800000000 { 127 opp-hz = /bits/ 64 <1800000000>; 128 opp-microvolt = <1050000 1050000 1150000>; 129 }; 130 }; 131 132 display_subsystem: display-subsystem { 133 compatible = "rockchip,display-subsystem"; 134 ports = <&vop_out>; 135 }; 136 137 firmware { 138 scmi: scmi { 139 compatible = "arm,scmi-smc"; 140 arm,smc-id = <0x82000010>; 141 shmem = <&scmi_shmem>; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 145 scmi_clk: protocol@14 { 146 reg = <0x14>; 147 #clock-cells = <1>; 148 }; 149 }; 150 }; 151 152 gpu_opp_table: opp-table-1 { 153 compatible = "operating-points-v2"; 154 155 opp-200000000 { 156 opp-hz = /bits/ 64 <200000000>; 157 opp-microvolt = <825000>; 158 }; 159 160 opp-300000000 { 161 opp-hz = /bits/ 64 <300000000>; 162 opp-microvolt = <825000>; 163 }; 164 165 opp-400000000 { 166 opp-hz = /bits/ 64 <400000000>; 167 opp-microvolt = <825000>; 168 }; 169 170 opp-600000000 { 171 opp-hz = /bits/ 64 <600000000>; 172 opp-microvolt = <825000>; 173 }; 174 175 opp-700000000 { 176 opp-hz = /bits/ 64 <700000000>; 177 opp-microvolt = <900000>; 178 }; 179 180 opp-800000000 { 181 opp-hz = /bits/ 64 <800000000>; 182 opp-microvolt = <1000000>; 183 }; 184 }; 185 186 hdmi_sound: hdmi-sound { 187 compatible = "simple-audio-card"; 188 simple-audio-card,name = "HDMI"; 189 simple-audio-card,format = "i2s"; 190 simple-audio-card,mclk-fs = <256>; 191 status = "disabled"; 192 193 simple-audio-card,codec { 194 sound-dai = <&hdmi>; 195 }; 196 197 simple-audio-card,cpu { 198 sound-dai = <&i2s0_8ch>; 199 }; 200 }; 201 202 pmu { 203 compatible = "arm,cortex-a55-pmu"; 204 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 208 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 209 }; 210 211 psci { 212 compatible = "arm,psci-1.0"; 213 method = "smc"; 214 }; 215 216 timer { 217 compatible = "arm,armv8-timer"; 218 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 222 arm,no-tick-in-suspend; 223 }; 224 225 xin24m: xin24m { 226 compatible = "fixed-clock"; 227 clock-frequency = <24000000>; 228 clock-output-names = "xin24m"; 229 #clock-cells = <0>; 230 }; 231 232 xin32k: xin32k { 233 compatible = "fixed-clock"; 234 clock-frequency = <32768>; 235 clock-output-names = "xin32k"; 236 pinctrl-0 = <&clk32k_out0>; 237 pinctrl-names = "default"; 238 #clock-cells = <0>; 239 }; 240 241 sram@10f000 { 242 compatible = "mmio-sram"; 243 reg = <0x0 0x0010f000 0x0 0x100>; 244 #address-cells = <1>; 245 #size-cells = <1>; 246 ranges = <0 0x0 0x0010f000 0x100>; 247 248 scmi_shmem: sram@0 { 249 compatible = "arm,scmi-shmem"; 250 reg = <0x0 0x100>; 251 }; 252 }; 253 254 sata1: sata@fc400000 { 255 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; 256 reg = <0 0xfc400000 0 0x1000>; 257 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, 258 <&cru CLK_SATA1_RXOOB>; 259 clock-names = "sata", "pmalive", "rxoob"; 260 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 261 phys = <&combphy1 PHY_TYPE_SATA>; 262 phy-names = "sata-phy"; 263 ports-implemented = <0x1>; 264 power-domains = <&power RK3568_PD_PIPE>; 265 status = "disabled"; 266 }; 267 268 sata2: sata@fc800000 { 269 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; 270 reg = <0 0xfc800000 0 0x1000>; 271 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, 272 <&cru CLK_SATA2_RXOOB>; 273 clock-names = "sata", "pmalive", "rxoob"; 274 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 275 phys = <&combphy2 PHY_TYPE_SATA>; 276 phy-names = "sata-phy"; 277 ports-implemented = <0x1>; 278 power-domains = <&power RK3568_PD_PIPE>; 279 status = "disabled"; 280 }; 281 282 usb_host0_xhci: usb@fcc00000 { 283 compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; 284 reg = <0x0 0xfcc00000 0x0 0x400000>; 285 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, 287 <&cru ACLK_USB3OTG0>; 288 clock-names = "ref_clk", "suspend_clk", 289 "bus_clk"; 290 dr_mode = "otg"; 291 phy_type = "utmi_wide"; 292 power-domains = <&power RK3568_PD_PIPE>; 293 resets = <&cru SRST_USB3OTG0>; 294 snps,dis_u2_susphy_quirk; 295 status = "disabled"; 296 }; 297 298 usb_host1_xhci: usb@fd000000 { 299 compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; 300 reg = <0x0 0xfd000000 0x0 0x400000>; 301 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, 303 <&cru ACLK_USB3OTG1>; 304 clock-names = "ref_clk", "suspend_clk", 305 "bus_clk"; 306 dr_mode = "host"; 307 phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>; 308 phy-names = "usb2-phy", "usb3-phy"; 309 phy_type = "utmi_wide"; 310 power-domains = <&power RK3568_PD_PIPE>; 311 resets = <&cru SRST_USB3OTG1>; 312 snps,dis_u2_susphy_quirk; 313 status = "disabled"; 314 }; 315 316 gic: interrupt-controller@fd400000 { 317 compatible = "arm,gic-v3"; 318 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ 319 <0x0 0xfd460000 0 0x80000>; /* GICR */ 320 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 321 interrupt-controller; 322 #interrupt-cells = <3>; 323 mbi-alias = <0x0 0xfd410000>; 324 mbi-ranges = <296 24>; 325 msi-controller; 326 }; 327 328 usb_host0_ehci: usb@fd800000 { 329 compatible = "generic-ehci"; 330 reg = <0x0 0xfd800000 0x0 0x40000>; 331 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 333 <&cru PCLK_USB>; 334 phys = <&usb2phy1_otg>; 335 phy-names = "usb"; 336 status = "disabled"; 337 }; 338 339 usb_host0_ohci: usb@fd840000 { 340 compatible = "generic-ohci"; 341 reg = <0x0 0xfd840000 0x0 0x40000>; 342 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 344 <&cru PCLK_USB>; 345 phys = <&usb2phy1_otg>; 346 phy-names = "usb"; 347 status = "disabled"; 348 }; 349 350 usb_host1_ehci: usb@fd880000 { 351 compatible = "generic-ehci"; 352 reg = <0x0 0xfd880000 0x0 0x40000>; 353 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 355 <&cru PCLK_USB>; 356 phys = <&usb2phy1_host>; 357 phy-names = "usb"; 358 status = "disabled"; 359 }; 360 361 usb_host1_ohci: usb@fd8c0000 { 362 compatible = "generic-ohci"; 363 reg = <0x0 0xfd8c0000 0x0 0x40000>; 364 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 366 <&cru PCLK_USB>; 367 phys = <&usb2phy1_host>; 368 phy-names = "usb"; 369 status = "disabled"; 370 }; 371 372 pmugrf: syscon@fdc20000 { 373 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; 374 reg = <0x0 0xfdc20000 0x0 0x10000>; 375 376 pmu_io_domains: io-domains { 377 compatible = "rockchip,rk3568-pmu-io-voltage-domain"; 378 status = "disabled"; 379 }; 380 }; 381 382 pipegrf: syscon@fdc50000 { 383 reg = <0x0 0xfdc50000 0x0 0x1000>; 384 }; 385 386 grf: syscon@fdc60000 { 387 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; 388 reg = <0x0 0xfdc60000 0x0 0x10000>; 389 }; 390 391 pipe_phy_grf1: syscon@fdc80000 { 392 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; 393 reg = <0x0 0xfdc80000 0x0 0x1000>; 394 }; 395 396 pipe_phy_grf2: syscon@fdc90000 { 397 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; 398 reg = <0x0 0xfdc90000 0x0 0x1000>; 399 }; 400 401 usb2phy0_grf: syscon@fdca0000 { 402 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 403 reg = <0x0 0xfdca0000 0x0 0x8000>; 404 }; 405 406 usb2phy1_grf: syscon@fdca8000 { 407 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 408 reg = <0x0 0xfdca8000 0x0 0x8000>; 409 }; 410 411 pmucru: clock-controller@fdd00000 { 412 compatible = "rockchip,rk3568-pmucru"; 413 reg = <0x0 0xfdd00000 0x0 0x1000>; 414 #clock-cells = <1>; 415 #reset-cells = <1>; 416 }; 417 418 cru: clock-controller@fdd20000 { 419 compatible = "rockchip,rk3568-cru"; 420 reg = <0x0 0xfdd20000 0x0 0x1000>; 421 clocks = <&xin24m>; 422 clock-names = "xin24m"; 423 #clock-cells = <1>; 424 #reset-cells = <1>; 425 assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; 426 assigned-clock-rates = <1200000000>, <200000000>; 427 rockchip,grf = <&grf>; 428 }; 429 430 i2c0: i2c@fdd40000 { 431 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 432 reg = <0x0 0xfdd40000 0x0 0x1000>; 433 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 434 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 435 clock-names = "i2c", "pclk"; 436 pinctrl-0 = <&i2c0_xfer>; 437 pinctrl-names = "default"; 438 #address-cells = <1>; 439 #size-cells = <0>; 440 status = "disabled"; 441 }; 442 443 uart0: serial@fdd50000 { 444 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 445 reg = <0x0 0xfdd50000 0x0 0x100>; 446 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 447 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; 448 clock-names = "baudclk", "apb_pclk"; 449 dmas = <&dmac0 0>, <&dmac0 1>; 450 pinctrl-0 = <&uart0_xfer>; 451 pinctrl-names = "default"; 452 reg-io-width = <4>; 453 reg-shift = <2>; 454 status = "disabled"; 455 }; 456 457 pwm0: pwm@fdd70000 { 458 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 459 reg = <0x0 0xfdd70000 0x0 0x10>; 460 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 461 clock-names = "pwm", "pclk"; 462 pinctrl-0 = <&pwm0m0_pins>; 463 pinctrl-names = "default"; 464 #pwm-cells = <3>; 465 status = "disabled"; 466 }; 467 468 pwm1: pwm@fdd70010 { 469 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 470 reg = <0x0 0xfdd70010 0x0 0x10>; 471 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 472 clock-names = "pwm", "pclk"; 473 pinctrl-0 = <&pwm1m0_pins>; 474 pinctrl-names = "default"; 475 #pwm-cells = <3>; 476 status = "disabled"; 477 }; 478 479 pwm2: pwm@fdd70020 { 480 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 481 reg = <0x0 0xfdd70020 0x0 0x10>; 482 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 483 clock-names = "pwm", "pclk"; 484 pinctrl-0 = <&pwm2m0_pins>; 485 pinctrl-names = "default"; 486 #pwm-cells = <3>; 487 status = "disabled"; 488 }; 489 490 pwm3: pwm@fdd70030 { 491 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 492 reg = <0x0 0xfdd70030 0x0 0x10>; 493 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 494 clock-names = "pwm", "pclk"; 495 pinctrl-0 = <&pwm3_pins>; 496 pinctrl-names = "default"; 497 #pwm-cells = <3>; 498 status = "disabled"; 499 }; 500 501 pmu: power-management@fdd90000 { 502 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; 503 reg = <0x0 0xfdd90000 0x0 0x1000>; 504 505 power: power-controller { 506 compatible = "rockchip,rk3568-power-controller"; 507 #power-domain-cells = <1>; 508 #address-cells = <1>; 509 #size-cells = <0>; 510 511 /* These power domains are grouped by VD_GPU */ 512 power-domain@RK3568_PD_GPU { 513 reg = <RK3568_PD_GPU>; 514 clocks = <&cru ACLK_GPU_PRE>, 515 <&cru PCLK_GPU_PRE>; 516 pm_qos = <&qos_gpu>; 517 #power-domain-cells = <0>; 518 }; 519 520 /* These power domains are grouped by VD_LOGIC */ 521 power-domain@RK3568_PD_VI { 522 reg = <RK3568_PD_VI>; 523 clocks = <&cru HCLK_VI>, 524 <&cru PCLK_VI>; 525 pm_qos = <&qos_isp>, 526 <&qos_vicap0>, 527 <&qos_vicap1>; 528 #power-domain-cells = <0>; 529 }; 530 531 power-domain@RK3568_PD_VO { 532 reg = <RK3568_PD_VO>; 533 clocks = <&cru HCLK_VO>, 534 <&cru PCLK_VO>, 535 <&cru ACLK_VOP_PRE>; 536 pm_qos = <&qos_hdcp>, 537 <&qos_vop_m0>, 538 <&qos_vop_m1>; 539 #power-domain-cells = <0>; 540 }; 541 542 power-domain@RK3568_PD_RGA { 543 reg = <RK3568_PD_RGA>; 544 clocks = <&cru HCLK_RGA_PRE>, 545 <&cru PCLK_RGA_PRE>; 546 pm_qos = <&qos_ebc>, 547 <&qos_iep>, 548 <&qos_jpeg_dec>, 549 <&qos_jpeg_enc>, 550 <&qos_rga_rd>, 551 <&qos_rga_wr>; 552 #power-domain-cells = <0>; 553 }; 554 555 power-domain@RK3568_PD_VPU { 556 reg = <RK3568_PD_VPU>; 557 clocks = <&cru HCLK_VPU_PRE>; 558 pm_qos = <&qos_vpu>; 559 #power-domain-cells = <0>; 560 }; 561 562 power-domain@RK3568_PD_RKVDEC { 563 clocks = <&cru HCLK_RKVDEC_PRE>; 564 reg = <RK3568_PD_RKVDEC>; 565 pm_qos = <&qos_rkvdec>; 566 #power-domain-cells = <0>; 567 }; 568 569 power-domain@RK3568_PD_RKVENC { 570 reg = <RK3568_PD_RKVENC>; 571 clocks = <&cru HCLK_RKVENC_PRE>; 572 pm_qos = <&qos_rkvenc_rd_m0>, 573 <&qos_rkvenc_rd_m1>, 574 <&qos_rkvenc_wr_m0>; 575 #power-domain-cells = <0>; 576 }; 577 }; 578 }; 579 580 gpu: gpu@fde60000 { 581 compatible = "rockchip,rk3568-mali", "arm,mali-bifrost"; 582 reg = <0x0 0xfde60000 0x0 0x4000>; 583 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 586 interrupt-names = "job", "mmu", "gpu"; 587 clocks = <&scmi_clk 1>, <&cru CLK_GPU>; 588 clock-names = "gpu", "bus"; 589 #cooling-cells = <2>; 590 operating-points-v2 = <&gpu_opp_table>; 591 power-domains = <&power RK3568_PD_GPU>; 592 status = "disabled"; 593 }; 594 595 vpu: video-codec@fdea0400 { 596 compatible = "rockchip,rk3568-vpu"; 597 reg = <0x0 0xfdea0000 0x0 0x800>; 598 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 599 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 600 clock-names = "aclk", "hclk"; 601 iommus = <&vdpu_mmu>; 602 power-domains = <&power RK3568_PD_VPU>; 603 }; 604 605 vdpu_mmu: iommu@fdea0800 { 606 compatible = "rockchip,rk3568-iommu"; 607 reg = <0x0 0xfdea0800 0x0 0x40>; 608 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 609 clock-names = "aclk", "iface"; 610 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 611 power-domains = <&power RK3568_PD_VPU>; 612 #iommu-cells = <0>; 613 }; 614 615 vepu: video-codec@fdee0000 { 616 compatible = "rockchip,rk3568-vepu"; 617 reg = <0x0 0xfdee0000 0x0 0x800>; 618 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; 620 clock-names = "aclk", "hclk"; 621 iommus = <&vepu_mmu>; 622 power-domains = <&power RK3568_PD_RGA>; 623 }; 624 625 vepu_mmu: iommu@fdee0800 { 626 compatible = "rockchip,rk3568-iommu"; 627 reg = <0x0 0xfdee0800 0x0 0x40>; 628 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; 630 clock-names = "aclk", "iface"; 631 power-domains = <&power RK3568_PD_RGA>; 632 #iommu-cells = <0>; 633 }; 634 635 sdmmc2: mmc@fe000000 { 636 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 637 reg = <0x0 0xfe000000 0x0 0x4000>; 638 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 639 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, 640 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; 641 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 642 fifo-depth = <0x100>; 643 max-frequency = <150000000>; 644 resets = <&cru SRST_SDMMC2>; 645 reset-names = "reset"; 646 status = "disabled"; 647 }; 648 649 gmac1: ethernet@fe010000 { 650 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; 651 reg = <0x0 0xfe010000 0x0 0x10000>; 652 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 654 interrupt-names = "macirq", "eth_wake_irq"; 655 clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, 656 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, 657 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, 658 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; 659 clock-names = "stmmaceth", "mac_clk_rx", 660 "mac_clk_tx", "clk_mac_refout", 661 "aclk_mac", "pclk_mac", 662 "clk_mac_speed", "ptp_ref"; 663 resets = <&cru SRST_A_GMAC1>; 664 reset-names = "stmmaceth"; 665 rockchip,grf = <&grf>; 666 snps,axi-config = <&gmac1_stmmac_axi_setup>; 667 snps,mixed-burst; 668 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 669 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 670 snps,tso; 671 status = "disabled"; 672 673 mdio1: mdio { 674 compatible = "snps,dwmac-mdio"; 675 #address-cells = <0x1>; 676 #size-cells = <0x0>; 677 }; 678 679 gmac1_stmmac_axi_setup: stmmac-axi-config { 680 snps,blen = <0 0 0 0 16 8 4>; 681 snps,rd_osr_lmt = <8>; 682 snps,wr_osr_lmt = <4>; 683 }; 684 685 gmac1_mtl_rx_setup: rx-queues-config { 686 snps,rx-queues-to-use = <1>; 687 queue0 {}; 688 }; 689 690 gmac1_mtl_tx_setup: tx-queues-config { 691 snps,tx-queues-to-use = <1>; 692 queue0 {}; 693 }; 694 }; 695 696 vop: vop@fe040000 { 697 reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; 698 reg-names = "vop", "gamma-lut"; 699 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, 701 <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; 702 clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2"; 703 iommus = <&vop_mmu>; 704 power-domains = <&power RK3568_PD_VO>; 705 rockchip,grf = <&grf>; 706 status = "disabled"; 707 708 vop_out: ports { 709 #address-cells = <1>; 710 #size-cells = <0>; 711 712 vp0: port@0 { 713 reg = <0>; 714 #address-cells = <1>; 715 #size-cells = <0>; 716 }; 717 718 vp1: port@1 { 719 reg = <1>; 720 #address-cells = <1>; 721 #size-cells = <0>; 722 }; 723 724 vp2: port@2 { 725 reg = <2>; 726 #address-cells = <1>; 727 #size-cells = <0>; 728 }; 729 }; 730 }; 731 732 vop_mmu: iommu@fe043e00 { 733 compatible = "rockchip,rk3568-iommu"; 734 reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; 735 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 736 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 737 clock-names = "aclk", "iface"; 738 #iommu-cells = <0>; 739 status = "disabled"; 740 }; 741 742 dsi0: dsi@fe060000 { 743 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; 744 reg = <0x00 0xfe060000 0x00 0x10000>; 745 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 746 clock-names = "pclk", "hclk"; 747 clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>; 748 phy-names = "dphy"; 749 phys = <&dsi_dphy0>; 750 power-domains = <&power RK3568_PD_VO>; 751 reset-names = "apb"; 752 resets = <&cru SRST_P_DSITX_0>; 753 rockchip,grf = <&grf>; 754 status = "disabled"; 755 756 ports { 757 #address-cells = <1>; 758 #size-cells = <0>; 759 760 dsi0_in: port@0 { 761 reg = <0>; 762 }; 763 764 dsi0_out: port@1 { 765 reg = <1>; 766 }; 767 }; 768 }; 769 770 dsi1: dsi@fe070000 { 771 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; 772 reg = <0x0 0xfe070000 0x0 0x10000>; 773 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 774 clock-names = "pclk", "hclk"; 775 clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>; 776 phy-names = "dphy"; 777 phys = <&dsi_dphy1>; 778 power-domains = <&power RK3568_PD_VO>; 779 reset-names = "apb"; 780 resets = <&cru SRST_P_DSITX_1>; 781 rockchip,grf = <&grf>; 782 status = "disabled"; 783 784 ports { 785 #address-cells = <1>; 786 #size-cells = <0>; 787 788 dsi1_in: port@0 { 789 reg = <0>; 790 }; 791 792 dsi1_out: port@1 { 793 reg = <1>; 794 }; 795 }; 796 }; 797 798 hdmi: hdmi@fe0a0000 { 799 compatible = "rockchip,rk3568-dw-hdmi"; 800 reg = <0x0 0xfe0a0000 0x0 0x20000>; 801 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 802 clocks = <&cru PCLK_HDMI_HOST>, 803 <&cru CLK_HDMI_SFR>, 804 <&cru CLK_HDMI_CEC>, 805 <&pmucru CLK_HDMI_REF>, 806 <&cru HCLK_VO>; 807 clock-names = "iahb", "isfr", "cec", "ref"; 808 pinctrl-names = "default"; 809 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; 810 power-domains = <&power RK3568_PD_VO>; 811 reg-io-width = <4>; 812 rockchip,grf = <&grf>; 813 #sound-dai-cells = <0>; 814 status = "disabled"; 815 816 ports { 817 #address-cells = <1>; 818 #size-cells = <0>; 819 820 hdmi_in: port@0 { 821 reg = <0>; 822 }; 823 824 hdmi_out: port@1 { 825 reg = <1>; 826 }; 827 }; 828 }; 829 830 qos_gpu: qos@fe128000 { 831 compatible = "rockchip,rk3568-qos", "syscon"; 832 reg = <0x0 0xfe128000 0x0 0x20>; 833 }; 834 835 qos_rkvenc_rd_m0: qos@fe138080 { 836 compatible = "rockchip,rk3568-qos", "syscon"; 837 reg = <0x0 0xfe138080 0x0 0x20>; 838 }; 839 840 qos_rkvenc_rd_m1: qos@fe138100 { 841 compatible = "rockchip,rk3568-qos", "syscon"; 842 reg = <0x0 0xfe138100 0x0 0x20>; 843 }; 844 845 qos_rkvenc_wr_m0: qos@fe138180 { 846 compatible = "rockchip,rk3568-qos", "syscon"; 847 reg = <0x0 0xfe138180 0x0 0x20>; 848 }; 849 850 qos_isp: qos@fe148000 { 851 compatible = "rockchip,rk3568-qos", "syscon"; 852 reg = <0x0 0xfe148000 0x0 0x20>; 853 }; 854 855 qos_vicap0: qos@fe148080 { 856 compatible = "rockchip,rk3568-qos", "syscon"; 857 reg = <0x0 0xfe148080 0x0 0x20>; 858 }; 859 860 qos_vicap1: qos@fe148100 { 861 compatible = "rockchip,rk3568-qos", "syscon"; 862 reg = <0x0 0xfe148100 0x0 0x20>; 863 }; 864 865 qos_vpu: qos@fe150000 { 866 compatible = "rockchip,rk3568-qos", "syscon"; 867 reg = <0x0 0xfe150000 0x0 0x20>; 868 }; 869 870 qos_ebc: qos@fe158000 { 871 compatible = "rockchip,rk3568-qos", "syscon"; 872 reg = <0x0 0xfe158000 0x0 0x20>; 873 }; 874 875 qos_iep: qos@fe158100 { 876 compatible = "rockchip,rk3568-qos", "syscon"; 877 reg = <0x0 0xfe158100 0x0 0x20>; 878 }; 879 880 qos_jpeg_dec: qos@fe158180 { 881 compatible = "rockchip,rk3568-qos", "syscon"; 882 reg = <0x0 0xfe158180 0x0 0x20>; 883 }; 884 885 qos_jpeg_enc: qos@fe158200 { 886 compatible = "rockchip,rk3568-qos", "syscon"; 887 reg = <0x0 0xfe158200 0x0 0x20>; 888 }; 889 890 qos_rga_rd: qos@fe158280 { 891 compatible = "rockchip,rk3568-qos", "syscon"; 892 reg = <0x0 0xfe158280 0x0 0x20>; 893 }; 894 895 qos_rga_wr: qos@fe158300 { 896 compatible = "rockchip,rk3568-qos", "syscon"; 897 reg = <0x0 0xfe158300 0x0 0x20>; 898 }; 899 900 qos_npu: qos@fe180000 { 901 compatible = "rockchip,rk3568-qos", "syscon"; 902 reg = <0x0 0xfe180000 0x0 0x20>; 903 }; 904 905 qos_pcie2x1: qos@fe190000 { 906 compatible = "rockchip,rk3568-qos", "syscon"; 907 reg = <0x0 0xfe190000 0x0 0x20>; 908 }; 909 910 qos_sata1: qos@fe190280 { 911 compatible = "rockchip,rk3568-qos", "syscon"; 912 reg = <0x0 0xfe190280 0x0 0x20>; 913 }; 914 915 qos_sata2: qos@fe190300 { 916 compatible = "rockchip,rk3568-qos", "syscon"; 917 reg = <0x0 0xfe190300 0x0 0x20>; 918 }; 919 920 qos_usb3_0: qos@fe190380 { 921 compatible = "rockchip,rk3568-qos", "syscon"; 922 reg = <0x0 0xfe190380 0x0 0x20>; 923 }; 924 925 qos_usb3_1: qos@fe190400 { 926 compatible = "rockchip,rk3568-qos", "syscon"; 927 reg = <0x0 0xfe190400 0x0 0x20>; 928 }; 929 930 qos_rkvdec: qos@fe198000 { 931 compatible = "rockchip,rk3568-qos", "syscon"; 932 reg = <0x0 0xfe198000 0x0 0x20>; 933 }; 934 935 qos_hdcp: qos@fe1a8000 { 936 compatible = "rockchip,rk3568-qos", "syscon"; 937 reg = <0x0 0xfe1a8000 0x0 0x20>; 938 }; 939 940 qos_vop_m0: qos@fe1a8080 { 941 compatible = "rockchip,rk3568-qos", "syscon"; 942 reg = <0x0 0xfe1a8080 0x0 0x20>; 943 }; 944 945 qos_vop_m1: qos@fe1a8100 { 946 compatible = "rockchip,rk3568-qos", "syscon"; 947 reg = <0x0 0xfe1a8100 0x0 0x20>; 948 }; 949 950 pcie2x1: pcie@fe260000 { 951 compatible = "rockchip,rk3568-pcie"; 952 reg = <0x3 0xc0000000 0x0 0x00400000>, 953 <0x0 0xfe260000 0x0 0x00010000>, 954 <0x3 0x3f000000 0x0 0x01000000>; 955 reg-names = "dbi", "apb", "config"; 956 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 961 interrupt-names = "sys", "pmc", "msi", "legacy", "err"; 962 bus-range = <0x0 0xf>; 963 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, 964 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, 965 <&cru CLK_PCIE20_AUX_NDFT>; 966 clock-names = "aclk_mst", "aclk_slv", 967 "aclk_dbi", "pclk", "aux"; 968 device_type = "pci"; 969 #interrupt-cells = <1>; 970 interrupt-map-mask = <0 0 0 7>; 971 interrupt-map = <0 0 0 1 &pcie_intc 0>, 972 <0 0 0 2 &pcie_intc 1>, 973 <0 0 0 3 &pcie_intc 2>, 974 <0 0 0 4 &pcie_intc 3>; 975 linux,pci-domain = <0>; 976 num-ib-windows = <6>; 977 num-ob-windows = <2>; 978 max-link-speed = <2>; 979 msi-map = <0x0 &gic 0x0 0x1000>; 980 num-lanes = <1>; 981 phys = <&combphy2 PHY_TYPE_PCIE>; 982 phy-names = "pcie-phy"; 983 power-domains = <&power RK3568_PD_PIPE>; 984 ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000 985 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>; 986 resets = <&cru SRST_PCIE20_POWERUP>; 987 reset-names = "pipe"; 988 #address-cells = <3>; 989 #size-cells = <2>; 990 status = "disabled"; 991 992 pcie_intc: legacy-interrupt-controller { 993 #address-cells = <0>; 994 #interrupt-cells = <1>; 995 interrupt-controller; 996 interrupt-parent = <&gic>; 997 interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; 998 }; 999 }; 1000 1001 sdmmc0: mmc@fe2b0000 { 1002 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 1003 reg = <0x0 0xfe2b0000 0x0 0x4000>; 1004 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1005 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, 1006 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; 1007 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1008 fifo-depth = <0x100>; 1009 max-frequency = <150000000>; 1010 resets = <&cru SRST_SDMMC0>; 1011 reset-names = "reset"; 1012 status = "disabled"; 1013 }; 1014 1015 sdmmc1: mmc@fe2c0000 { 1016 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 1017 reg = <0x0 0xfe2c0000 0x0 0x4000>; 1018 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1019 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, 1020 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; 1021 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1022 fifo-depth = <0x100>; 1023 max-frequency = <150000000>; 1024 resets = <&cru SRST_SDMMC1>; 1025 reset-names = "reset"; 1026 status = "disabled"; 1027 }; 1028 1029 sfc: spi@fe300000 { 1030 compatible = "rockchip,sfc"; 1031 reg = <0x0 0xfe300000 0x0 0x4000>; 1032 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1033 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1034 clock-names = "clk_sfc", "hclk_sfc"; 1035 pinctrl-0 = <&fspi_pins>; 1036 pinctrl-names = "default"; 1037 status = "disabled"; 1038 }; 1039 1040 sdhci: mmc@fe310000 { 1041 compatible = "rockchip,rk3568-dwcmshc"; 1042 reg = <0x0 0xfe310000 0x0 0x10000>; 1043 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1044 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; 1045 assigned-clock-rates = <200000000>, <24000000>; 1046 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1047 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1048 <&cru TCLK_EMMC>; 1049 clock-names = "core", "bus", "axi", "block", "timer"; 1050 status = "disabled"; 1051 }; 1052 1053 i2s0_8ch: i2s@fe400000 { 1054 compatible = "rockchip,rk3568-i2s-tdm"; 1055 reg = <0x0 0xfe400000 0x0 0x1000>; 1056 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1057 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; 1058 assigned-clock-rates = <1188000000>, <1188000000>; 1059 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1060 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1061 dmas = <&dmac1 0>; 1062 dma-names = "tx"; 1063 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1064 reset-names = "tx-m", "rx-m"; 1065 rockchip,grf = <&grf>; 1066 #sound-dai-cells = <0>; 1067 status = "disabled"; 1068 }; 1069 1070 i2s1_8ch: i2s@fe410000 { 1071 compatible = "rockchip,rk3568-i2s-tdm"; 1072 reg = <0x0 0xfe410000 0x0 0x1000>; 1073 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1074 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>; 1075 assigned-clock-rates = <1188000000>, <1188000000>; 1076 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, 1077 <&cru HCLK_I2S1_8CH>; 1078 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1079 dmas = <&dmac1 3>, <&dmac1 2>; 1080 dma-names = "rx", "tx"; 1081 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 1082 reset-names = "tx-m", "rx-m"; 1083 rockchip,grf = <&grf>; 1084 pinctrl-names = "default"; 1085 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx 1086 &i2s1m0_lrcktx &i2s1m0_lrckrx 1087 &i2s1m0_sdi0 &i2s1m0_sdi1 1088 &i2s1m0_sdi2 &i2s1m0_sdi3 1089 &i2s1m0_sdo0 &i2s1m0_sdo1 1090 &i2s1m0_sdo2 &i2s1m0_sdo3>; 1091 #sound-dai-cells = <0>; 1092 status = "disabled"; 1093 }; 1094 1095 i2s2_2ch: i2s@fe420000 { 1096 compatible = "rockchip,rk3568-i2s-tdm"; 1097 reg = <0x0 0xfe420000 0x0 0x1000>; 1098 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1099 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; 1100 assigned-clock-rates = <1188000000>; 1101 clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 1102 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1103 dmas = <&dmac1 4>, <&dmac1 5>; 1104 dma-names = "tx", "rx"; 1105 resets = <&cru SRST_M_I2S2_2CH>; 1106 reset-names = "m"; 1107 rockchip,grf = <&grf>; 1108 pinctrl-names = "default"; 1109 pinctrl-0 = <&i2s2m0_sclktx 1110 &i2s2m0_lrcktx 1111 &i2s2m0_sdi 1112 &i2s2m0_sdo>; 1113 #sound-dai-cells = <0>; 1114 status = "disabled"; 1115 }; 1116 1117 i2s3_2ch: i2s@fe430000 { 1118 compatible = "rockchip,rk3568-i2s-tdm"; 1119 reg = <0x0 0xfe430000 0x0 0x1000>; 1120 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1121 clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, 1122 <&cru HCLK_I2S3_2CH>; 1123 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1124 dmas = <&dmac1 6>, <&dmac1 7>; 1125 dma-names = "tx", "rx"; 1126 resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>; 1127 reset-names = "tx-m", "rx-m"; 1128 rockchip,grf = <&grf>; 1129 #sound-dai-cells = <0>; 1130 status = "disabled"; 1131 }; 1132 1133 pdm: pdm@fe440000 { 1134 compatible = "rockchip,rk3568-pdm"; 1135 reg = <0x0 0xfe440000 0x0 0x1000>; 1136 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1137 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; 1138 clock-names = "pdm_clk", "pdm_hclk"; 1139 dmas = <&dmac1 9>; 1140 dma-names = "rx"; 1141 pinctrl-0 = <&pdmm0_clk 1142 &pdmm0_clk1 1143 &pdmm0_sdi0 1144 &pdmm0_sdi1 1145 &pdmm0_sdi2 1146 &pdmm0_sdi3>; 1147 pinctrl-names = "default"; 1148 resets = <&cru SRST_M_PDM>; 1149 reset-names = "pdm-m"; 1150 #sound-dai-cells = <0>; 1151 status = "disabled"; 1152 }; 1153 1154 spdif: spdif@fe460000 { 1155 compatible = "rockchip,rk3568-spdif"; 1156 reg = <0x0 0xfe460000 0x0 0x1000>; 1157 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1158 clock-names = "mclk", "hclk"; 1159 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; 1160 dmas = <&dmac1 1>; 1161 dma-names = "tx"; 1162 pinctrl-names = "default"; 1163 pinctrl-0 = <&spdifm0_tx>; 1164 #sound-dai-cells = <0>; 1165 status = "disabled"; 1166 }; 1167 1168 dmac0: dma-controller@fe530000 { 1169 compatible = "arm,pl330", "arm,primecell"; 1170 reg = <0x0 0xfe530000 0x0 0x4000>; 1171 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1173 arm,pl330-periph-burst; 1174 clocks = <&cru ACLK_BUS>; 1175 clock-names = "apb_pclk"; 1176 #dma-cells = <1>; 1177 }; 1178 1179 dmac1: dma-controller@fe550000 { 1180 compatible = "arm,pl330", "arm,primecell"; 1181 reg = <0x0 0xfe550000 0x0 0x4000>; 1182 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1184 arm,pl330-periph-burst; 1185 clocks = <&cru ACLK_BUS>; 1186 clock-names = "apb_pclk"; 1187 #dma-cells = <1>; 1188 }; 1189 1190 i2c1: i2c@fe5a0000 { 1191 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1192 reg = <0x0 0xfe5a0000 0x0 0x1000>; 1193 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1194 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1195 clock-names = "i2c", "pclk"; 1196 pinctrl-0 = <&i2c1_xfer>; 1197 pinctrl-names = "default"; 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 status = "disabled"; 1201 }; 1202 1203 i2c2: i2c@fe5b0000 { 1204 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1205 reg = <0x0 0xfe5b0000 0x0 0x1000>; 1206 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1207 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1208 clock-names = "i2c", "pclk"; 1209 pinctrl-0 = <&i2c2m0_xfer>; 1210 pinctrl-names = "default"; 1211 #address-cells = <1>; 1212 #size-cells = <0>; 1213 status = "disabled"; 1214 }; 1215 1216 i2c3: i2c@fe5c0000 { 1217 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1218 reg = <0x0 0xfe5c0000 0x0 0x1000>; 1219 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1220 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1221 clock-names = "i2c", "pclk"; 1222 pinctrl-0 = <&i2c3m0_xfer>; 1223 pinctrl-names = "default"; 1224 #address-cells = <1>; 1225 #size-cells = <0>; 1226 status = "disabled"; 1227 }; 1228 1229 i2c4: i2c@fe5d0000 { 1230 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1231 reg = <0x0 0xfe5d0000 0x0 0x1000>; 1232 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1233 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1234 clock-names = "i2c", "pclk"; 1235 pinctrl-0 = <&i2c4m0_xfer>; 1236 pinctrl-names = "default"; 1237 #address-cells = <1>; 1238 #size-cells = <0>; 1239 status = "disabled"; 1240 }; 1241 1242 i2c5: i2c@fe5e0000 { 1243 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1244 reg = <0x0 0xfe5e0000 0x0 0x1000>; 1245 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1246 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1247 clock-names = "i2c", "pclk"; 1248 pinctrl-0 = <&i2c5m0_xfer>; 1249 pinctrl-names = "default"; 1250 #address-cells = <1>; 1251 #size-cells = <0>; 1252 status = "disabled"; 1253 }; 1254 1255 wdt: watchdog@fe600000 { 1256 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; 1257 reg = <0x0 0xfe600000 0x0 0x100>; 1258 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 1259 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; 1260 clock-names = "tclk", "pclk"; 1261 }; 1262 1263 spi0: spi@fe610000 { 1264 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1265 reg = <0x0 0xfe610000 0x0 0x1000>; 1266 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1267 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 1268 clock-names = "spiclk", "apb_pclk"; 1269 dmas = <&dmac0 20>, <&dmac0 21>; 1270 dma-names = "tx", "rx"; 1271 pinctrl-names = "default"; 1272 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 1273 #address-cells = <1>; 1274 #size-cells = <0>; 1275 status = "disabled"; 1276 }; 1277 1278 spi1: spi@fe620000 { 1279 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1280 reg = <0x0 0xfe620000 0x0 0x1000>; 1281 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1282 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1283 clock-names = "spiclk", "apb_pclk"; 1284 dmas = <&dmac0 22>, <&dmac0 23>; 1285 dma-names = "tx", "rx"; 1286 pinctrl-names = "default"; 1287 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; 1288 #address-cells = <1>; 1289 #size-cells = <0>; 1290 status = "disabled"; 1291 }; 1292 1293 spi2: spi@fe630000 { 1294 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1295 reg = <0x0 0xfe630000 0x0 0x1000>; 1296 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1297 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 1298 clock-names = "spiclk", "apb_pclk"; 1299 dmas = <&dmac0 24>, <&dmac0 25>; 1300 dma-names = "tx", "rx"; 1301 pinctrl-names = "default"; 1302 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; 1303 #address-cells = <1>; 1304 #size-cells = <0>; 1305 status = "disabled"; 1306 }; 1307 1308 spi3: spi@fe640000 { 1309 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1310 reg = <0x0 0xfe640000 0x0 0x1000>; 1311 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1312 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 1313 clock-names = "spiclk", "apb_pclk"; 1314 dmas = <&dmac0 26>, <&dmac0 27>; 1315 dma-names = "tx", "rx"; 1316 pinctrl-names = "default"; 1317 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>; 1318 #address-cells = <1>; 1319 #size-cells = <0>; 1320 status = "disabled"; 1321 }; 1322 1323 uart1: serial@fe650000 { 1324 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1325 reg = <0x0 0xfe650000 0x0 0x100>; 1326 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1327 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1328 clock-names = "baudclk", "apb_pclk"; 1329 dmas = <&dmac0 2>, <&dmac0 3>; 1330 pinctrl-0 = <&uart1m0_xfer>; 1331 pinctrl-names = "default"; 1332 reg-io-width = <4>; 1333 reg-shift = <2>; 1334 status = "disabled"; 1335 }; 1336 1337 uart2: serial@fe660000 { 1338 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1339 reg = <0x0 0xfe660000 0x0 0x100>; 1340 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1341 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1342 clock-names = "baudclk", "apb_pclk"; 1343 dmas = <&dmac0 4>, <&dmac0 5>; 1344 pinctrl-0 = <&uart2m0_xfer>; 1345 pinctrl-names = "default"; 1346 reg-io-width = <4>; 1347 reg-shift = <2>; 1348 status = "disabled"; 1349 }; 1350 1351 uart3: serial@fe670000 { 1352 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1353 reg = <0x0 0xfe670000 0x0 0x100>; 1354 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1355 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1356 clock-names = "baudclk", "apb_pclk"; 1357 dmas = <&dmac0 6>, <&dmac0 7>; 1358 pinctrl-0 = <&uart3m0_xfer>; 1359 pinctrl-names = "default"; 1360 reg-io-width = <4>; 1361 reg-shift = <2>; 1362 status = "disabled"; 1363 }; 1364 1365 uart4: serial@fe680000 { 1366 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1367 reg = <0x0 0xfe680000 0x0 0x100>; 1368 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1369 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1370 clock-names = "baudclk", "apb_pclk"; 1371 dmas = <&dmac0 8>, <&dmac0 9>; 1372 pinctrl-0 = <&uart4m0_xfer>; 1373 pinctrl-names = "default"; 1374 reg-io-width = <4>; 1375 reg-shift = <2>; 1376 status = "disabled"; 1377 }; 1378 1379 uart5: serial@fe690000 { 1380 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1381 reg = <0x0 0xfe690000 0x0 0x100>; 1382 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1383 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1384 clock-names = "baudclk", "apb_pclk"; 1385 dmas = <&dmac0 10>, <&dmac0 11>; 1386 pinctrl-0 = <&uart5m0_xfer>; 1387 pinctrl-names = "default"; 1388 reg-io-width = <4>; 1389 reg-shift = <2>; 1390 status = "disabled"; 1391 }; 1392 1393 uart6: serial@fe6a0000 { 1394 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1395 reg = <0x0 0xfe6a0000 0x0 0x100>; 1396 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1397 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1398 clock-names = "baudclk", "apb_pclk"; 1399 dmas = <&dmac0 12>, <&dmac0 13>; 1400 pinctrl-0 = <&uart6m0_xfer>; 1401 pinctrl-names = "default"; 1402 reg-io-width = <4>; 1403 reg-shift = <2>; 1404 status = "disabled"; 1405 }; 1406 1407 uart7: serial@fe6b0000 { 1408 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1409 reg = <0x0 0xfe6b0000 0x0 0x100>; 1410 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1411 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1412 clock-names = "baudclk", "apb_pclk"; 1413 dmas = <&dmac0 14>, <&dmac0 15>; 1414 pinctrl-0 = <&uart7m0_xfer>; 1415 pinctrl-names = "default"; 1416 reg-io-width = <4>; 1417 reg-shift = <2>; 1418 status = "disabled"; 1419 }; 1420 1421 uart8: serial@fe6c0000 { 1422 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1423 reg = <0x0 0xfe6c0000 0x0 0x100>; 1424 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1425 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 1426 clock-names = "baudclk", "apb_pclk"; 1427 dmas = <&dmac0 16>, <&dmac0 17>; 1428 pinctrl-0 = <&uart8m0_xfer>; 1429 pinctrl-names = "default"; 1430 reg-io-width = <4>; 1431 reg-shift = <2>; 1432 status = "disabled"; 1433 }; 1434 1435 uart9: serial@fe6d0000 { 1436 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1437 reg = <0x0 0xfe6d0000 0x0 0x100>; 1438 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1439 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 1440 clock-names = "baudclk", "apb_pclk"; 1441 dmas = <&dmac0 18>, <&dmac0 19>; 1442 pinctrl-0 = <&uart9m0_xfer>; 1443 pinctrl-names = "default"; 1444 reg-io-width = <4>; 1445 reg-shift = <2>; 1446 status = "disabled"; 1447 }; 1448 1449 thermal_zones: thermal-zones { 1450 cpu_thermal: cpu-thermal { 1451 polling-delay-passive = <100>; 1452 polling-delay = <1000>; 1453 1454 thermal-sensors = <&tsadc 0>; 1455 1456 trips { 1457 cpu_alert0: cpu_alert0 { 1458 temperature = <70000>; 1459 hysteresis = <2000>; 1460 type = "passive"; 1461 }; 1462 cpu_alert1: cpu_alert1 { 1463 temperature = <75000>; 1464 hysteresis = <2000>; 1465 type = "passive"; 1466 }; 1467 cpu_crit: cpu_crit { 1468 temperature = <95000>; 1469 hysteresis = <2000>; 1470 type = "critical"; 1471 }; 1472 }; 1473 1474 cooling-maps { 1475 map0 { 1476 trip = <&cpu_alert0>; 1477 cooling-device = 1478 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1479 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1480 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1481 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1482 }; 1483 }; 1484 }; 1485 1486 gpu_thermal: gpu-thermal { 1487 polling-delay-passive = <20>; /* milliseconds */ 1488 polling-delay = <1000>; /* milliseconds */ 1489 1490 thermal-sensors = <&tsadc 1>; 1491 1492 trips { 1493 gpu_threshold: gpu-threshold { 1494 temperature = <70000>; 1495 hysteresis = <2000>; 1496 type = "passive"; 1497 }; 1498 gpu_target: gpu-target { 1499 temperature = <75000>; 1500 hysteresis = <2000>; 1501 type = "passive"; 1502 }; 1503 gpu_crit: gpu-crit { 1504 temperature = <95000>; 1505 hysteresis = <2000>; 1506 type = "critical"; 1507 }; 1508 }; 1509 1510 cooling-maps { 1511 map0 { 1512 trip = <&gpu_target>; 1513 cooling-device = 1514 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1515 }; 1516 }; 1517 }; 1518 }; 1519 1520 tsadc: tsadc@fe710000 { 1521 compatible = "rockchip,rk3568-tsadc"; 1522 reg = <0x0 0xfe710000 0x0 0x100>; 1523 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1524 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; 1525 assigned-clock-rates = <17000000>, <700000>; 1526 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 1527 clock-names = "tsadc", "apb_pclk"; 1528 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>, 1529 <&cru SRST_TSADCPHY>; 1530 rockchip,grf = <&grf>; 1531 rockchip,hw-tshut-temp = <95000>; 1532 pinctrl-names = "init", "default", "sleep"; 1533 pinctrl-0 = <&tsadc_pin>; 1534 pinctrl-1 = <&tsadc_shutorg>; 1535 pinctrl-2 = <&tsadc_pin>; 1536 #thermal-sensor-cells = <1>; 1537 status = "disabled"; 1538 }; 1539 1540 saradc: saradc@fe720000 { 1541 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; 1542 reg = <0x0 0xfe720000 0x0 0x100>; 1543 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1544 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1545 clock-names = "saradc", "apb_pclk"; 1546 resets = <&cru SRST_P_SARADC>; 1547 reset-names = "saradc-apb"; 1548 #io-channel-cells = <1>; 1549 status = "disabled"; 1550 }; 1551 1552 pwm4: pwm@fe6e0000 { 1553 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1554 reg = <0x0 0xfe6e0000 0x0 0x10>; 1555 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1556 clock-names = "pwm", "pclk"; 1557 pinctrl-0 = <&pwm4_pins>; 1558 pinctrl-names = "default"; 1559 #pwm-cells = <3>; 1560 status = "disabled"; 1561 }; 1562 1563 pwm5: pwm@fe6e0010 { 1564 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1565 reg = <0x0 0xfe6e0010 0x0 0x10>; 1566 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1567 clock-names = "pwm", "pclk"; 1568 pinctrl-0 = <&pwm5_pins>; 1569 pinctrl-names = "default"; 1570 #pwm-cells = <3>; 1571 status = "disabled"; 1572 }; 1573 1574 pwm6: pwm@fe6e0020 { 1575 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1576 reg = <0x0 0xfe6e0020 0x0 0x10>; 1577 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1578 clock-names = "pwm", "pclk"; 1579 pinctrl-0 = <&pwm6_pins>; 1580 pinctrl-names = "default"; 1581 #pwm-cells = <3>; 1582 status = "disabled"; 1583 }; 1584 1585 pwm7: pwm@fe6e0030 { 1586 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1587 reg = <0x0 0xfe6e0030 0x0 0x10>; 1588 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1589 clock-names = "pwm", "pclk"; 1590 pinctrl-0 = <&pwm7_pins>; 1591 pinctrl-names = "default"; 1592 #pwm-cells = <3>; 1593 status = "disabled"; 1594 }; 1595 1596 pwm8: pwm@fe6f0000 { 1597 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1598 reg = <0x0 0xfe6f0000 0x0 0x10>; 1599 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1600 clock-names = "pwm", "pclk"; 1601 pinctrl-0 = <&pwm8m0_pins>; 1602 pinctrl-names = "default"; 1603 #pwm-cells = <3>; 1604 status = "disabled"; 1605 }; 1606 1607 pwm9: pwm@fe6f0010 { 1608 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1609 reg = <0x0 0xfe6f0010 0x0 0x10>; 1610 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1611 clock-names = "pwm", "pclk"; 1612 pinctrl-0 = <&pwm9m0_pins>; 1613 pinctrl-names = "default"; 1614 #pwm-cells = <3>; 1615 status = "disabled"; 1616 }; 1617 1618 pwm10: pwm@fe6f0020 { 1619 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1620 reg = <0x0 0xfe6f0020 0x0 0x10>; 1621 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1622 clock-names = "pwm", "pclk"; 1623 pinctrl-0 = <&pwm10m0_pins>; 1624 pinctrl-names = "default"; 1625 #pwm-cells = <3>; 1626 status = "disabled"; 1627 }; 1628 1629 pwm11: pwm@fe6f0030 { 1630 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1631 reg = <0x0 0xfe6f0030 0x0 0x10>; 1632 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1633 clock-names = "pwm", "pclk"; 1634 pinctrl-0 = <&pwm11m0_pins>; 1635 pinctrl-names = "default"; 1636 #pwm-cells = <3>; 1637 status = "disabled"; 1638 }; 1639 1640 pwm12: pwm@fe700000 { 1641 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1642 reg = <0x0 0xfe700000 0x0 0x10>; 1643 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1644 clock-names = "pwm", "pclk"; 1645 pinctrl-0 = <&pwm12m0_pins>; 1646 pinctrl-names = "default"; 1647 #pwm-cells = <3>; 1648 status = "disabled"; 1649 }; 1650 1651 pwm13: pwm@fe700010 { 1652 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1653 reg = <0x0 0xfe700010 0x0 0x10>; 1654 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1655 clock-names = "pwm", "pclk"; 1656 pinctrl-0 = <&pwm13m0_pins>; 1657 pinctrl-names = "default"; 1658 #pwm-cells = <3>; 1659 status = "disabled"; 1660 }; 1661 1662 pwm14: pwm@fe700020 { 1663 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1664 reg = <0x0 0xfe700020 0x0 0x10>; 1665 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1666 clock-names = "pwm", "pclk"; 1667 pinctrl-0 = <&pwm14m0_pins>; 1668 pinctrl-names = "default"; 1669 #pwm-cells = <3>; 1670 status = "disabled"; 1671 }; 1672 1673 pwm15: pwm@fe700030 { 1674 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1675 reg = <0x0 0xfe700030 0x0 0x10>; 1676 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1677 clock-names = "pwm", "pclk"; 1678 pinctrl-0 = <&pwm15m0_pins>; 1679 pinctrl-names = "default"; 1680 #pwm-cells = <3>; 1681 status = "disabled"; 1682 }; 1683 1684 combphy1: phy@fe830000 { 1685 compatible = "rockchip,rk3568-naneng-combphy"; 1686 reg = <0x0 0xfe830000 0x0 0x100>; 1687 clocks = <&pmucru CLK_PCIEPHY1_REF>, 1688 <&cru PCLK_PIPEPHY1>, 1689 <&cru PCLK_PIPE>; 1690 clock-names = "ref", "apb", "pipe"; 1691 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; 1692 assigned-clock-rates = <100000000>; 1693 resets = <&cru SRST_PIPEPHY1>; 1694 rockchip,pipe-grf = <&pipegrf>; 1695 rockchip,pipe-phy-grf = <&pipe_phy_grf1>; 1696 #phy-cells = <1>; 1697 status = "disabled"; 1698 }; 1699 1700 combphy2: phy@fe840000 { 1701 compatible = "rockchip,rk3568-naneng-combphy"; 1702 reg = <0x0 0xfe840000 0x0 0x100>; 1703 clocks = <&pmucru CLK_PCIEPHY2_REF>, 1704 <&cru PCLK_PIPEPHY2>, 1705 <&cru PCLK_PIPE>; 1706 clock-names = "ref", "apb", "pipe"; 1707 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; 1708 assigned-clock-rates = <100000000>; 1709 resets = <&cru SRST_PIPEPHY2>; 1710 rockchip,pipe-grf = <&pipegrf>; 1711 rockchip,pipe-phy-grf = <&pipe_phy_grf2>; 1712 #phy-cells = <1>; 1713 status = "disabled"; 1714 }; 1715 1716 csi_dphy: phy@fe870000 { 1717 compatible = "rockchip,rk3568-csi-dphy"; 1718 reg = <0x0 0xfe870000 0x0 0x10000>; 1719 clocks = <&cru PCLK_MIPICSIPHY>; 1720 clock-names = "pclk"; 1721 #phy-cells = <0>; 1722 resets = <&cru SRST_P_MIPICSIPHY>; 1723 reset-names = "apb"; 1724 rockchip,grf = <&grf>; 1725 status = "disabled"; 1726 }; 1727 1728 dsi_dphy0: mipi-dphy@fe850000 { 1729 compatible = "rockchip,rk3568-dsi-dphy"; 1730 reg = <0x0 0xfe850000 0x0 0x10000>; 1731 clock-names = "ref", "pclk"; 1732 clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>; 1733 #phy-cells = <0>; 1734 power-domains = <&power RK3568_PD_VO>; 1735 reset-names = "apb"; 1736 resets = <&cru SRST_P_MIPIDSIPHY0>; 1737 status = "disabled"; 1738 }; 1739 1740 dsi_dphy1: mipi-dphy@fe860000 { 1741 compatible = "rockchip,rk3568-dsi-dphy"; 1742 reg = <0x0 0xfe860000 0x0 0x10000>; 1743 clock-names = "ref", "pclk"; 1744 clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>; 1745 #phy-cells = <0>; 1746 power-domains = <&power RK3568_PD_VO>; 1747 reset-names = "apb"; 1748 resets = <&cru SRST_P_MIPIDSIPHY1>; 1749 status = "disabled"; 1750 }; 1751 1752 usb2phy0: usb2phy@fe8a0000 { 1753 compatible = "rockchip,rk3568-usb2phy"; 1754 reg = <0x0 0xfe8a0000 0x0 0x10000>; 1755 clocks = <&pmucru CLK_USBPHY0_REF>; 1756 clock-names = "phyclk"; 1757 clock-output-names = "clk_usbphy0_480m"; 1758 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 1759 rockchip,usbgrf = <&usb2phy0_grf>; 1760 #clock-cells = <0>; 1761 status = "disabled"; 1762 1763 usb2phy0_host: host-port { 1764 #phy-cells = <0>; 1765 status = "disabled"; 1766 }; 1767 1768 usb2phy0_otg: otg-port { 1769 #phy-cells = <0>; 1770 status = "disabled"; 1771 }; 1772 }; 1773 1774 usb2phy1: usb2phy@fe8b0000 { 1775 compatible = "rockchip,rk3568-usb2phy"; 1776 reg = <0x0 0xfe8b0000 0x0 0x10000>; 1777 clocks = <&pmucru CLK_USBPHY1_REF>; 1778 clock-names = "phyclk"; 1779 clock-output-names = "clk_usbphy1_480m"; 1780 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1781 rockchip,usbgrf = <&usb2phy1_grf>; 1782 #clock-cells = <0>; 1783 status = "disabled"; 1784 1785 usb2phy1_host: host-port { 1786 #phy-cells = <0>; 1787 status = "disabled"; 1788 }; 1789 1790 usb2phy1_otg: otg-port { 1791 #phy-cells = <0>; 1792 status = "disabled"; 1793 }; 1794 }; 1795 1796 pinctrl: pinctrl { 1797 compatible = "rockchip,rk3568-pinctrl"; 1798 rockchip,grf = <&grf>; 1799 rockchip,pmu = <&pmugrf>; 1800 #address-cells = <2>; 1801 #size-cells = <2>; 1802 ranges; 1803 1804 gpio0: gpio@fdd60000 { 1805 compatible = "rockchip,gpio-bank"; 1806 reg = <0x0 0xfdd60000 0x0 0x100>; 1807 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1808 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 1809 gpio-controller; 1810 #gpio-cells = <2>; 1811 interrupt-controller; 1812 #interrupt-cells = <2>; 1813 }; 1814 1815 gpio1: gpio@fe740000 { 1816 compatible = "rockchip,gpio-bank"; 1817 reg = <0x0 0xfe740000 0x0 0x100>; 1818 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1819 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1820 gpio-controller; 1821 #gpio-cells = <2>; 1822 interrupt-controller; 1823 #interrupt-cells = <2>; 1824 }; 1825 1826 gpio2: gpio@fe750000 { 1827 compatible = "rockchip,gpio-bank"; 1828 reg = <0x0 0xfe750000 0x0 0x100>; 1829 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1830 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1831 gpio-controller; 1832 #gpio-cells = <2>; 1833 interrupt-controller; 1834 #interrupt-cells = <2>; 1835 }; 1836 1837 gpio3: gpio@fe760000 { 1838 compatible = "rockchip,gpio-bank"; 1839 reg = <0x0 0xfe760000 0x0 0x100>; 1840 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1841 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1842 gpio-controller; 1843 #gpio-cells = <2>; 1844 interrupt-controller; 1845 #interrupt-cells = <2>; 1846 }; 1847 1848 gpio4: gpio@fe770000 { 1849 compatible = "rockchip,gpio-bank"; 1850 reg = <0x0 0xfe770000 0x0 0x100>; 1851 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1852 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1853 gpio-controller; 1854 #gpio-cells = <2>; 1855 interrupt-controller; 1856 #interrupt-cells = <2>; 1857 }; 1858 }; 1859}; 1860 1861#include "rk3568-pinctrl.dtsi" 1862