1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include "rk356x.dtsi" 7 8/ { 9 compatible = "rockchip,rk3568"; 10 11 sata0: sata@fc000000 { 12 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; 13 reg = <0 0xfc000000 0 0x1000>; 14 clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>, 15 <&cru CLK_SATA0_RXOOB>; 16 clock-names = "sata", "pmalive", "rxoob"; 17 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 18 phys = <&combphy0 PHY_TYPE_SATA>; 19 phy-names = "sata-phy"; 20 ports-implemented = <0x1>; 21 power-domains = <&power RK3568_PD_PIPE>; 22 status = "disabled"; 23 }; 24 25 pipe_phy_grf0: syscon@fdc70000 { 26 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; 27 reg = <0x0 0xfdc70000 0x0 0x1000>; 28 }; 29 30 qos_pcie3x1: qos@fe190080 { 31 compatible = "rockchip,rk3568-qos", "syscon"; 32 reg = <0x0 0xfe190080 0x0 0x20>; 33 }; 34 35 qos_pcie3x2: qos@fe190100 { 36 compatible = "rockchip,rk3568-qos", "syscon"; 37 reg = <0x0 0xfe190100 0x0 0x20>; 38 }; 39 40 qos_sata0: qos@fe190200 { 41 compatible = "rockchip,rk3568-qos", "syscon"; 42 reg = <0x0 0xfe190200 0x0 0x20>; 43 }; 44 45 pcie30_phy_grf: syscon@fdcb8000 { 46 compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon"; 47 reg = <0x0 0xfdcb8000 0x0 0x10000>; 48 }; 49 50 pcie30phy: phy@fe8c0000 { 51 compatible = "rockchip,rk3568-pcie3-phy"; 52 reg = <0x0 0xfe8c0000 0x0 0x20000>; 53 #phy-cells = <0>; 54 clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, 55 <&cru PCLK_PCIE30PHY>; 56 clock-names = "refclk_m", "refclk_n", "pclk"; 57 resets = <&cru SRST_PCIE30PHY>; 58 reset-names = "phy"; 59 rockchip,phy-grf = <&pcie30_phy_grf>; 60 status = "disabled"; 61 }; 62 63 pcie3x1: pcie@fe270000 { 64 compatible = "rockchip,rk3568-pcie"; 65 #address-cells = <3>; 66 #size-cells = <2>; 67 bus-range = <0x0 0xf>; 68 clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, 69 <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, 70 <&cru CLK_PCIE30X1_AUX_NDFT>; 71 clock-names = "aclk_mst", "aclk_slv", 72 "aclk_dbi", "pclk", "aux"; 73 device_type = "pci"; 74 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 79 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 80 #interrupt-cells = <1>; 81 interrupt-map-mask = <0 0 0 7>; 82 interrupt-map = <0 0 0 1 &pcie3x1_intc 0>, 83 <0 0 0 2 &pcie3x1_intc 1>, 84 <0 0 0 3 &pcie3x1_intc 2>, 85 <0 0 0 4 &pcie3x1_intc 3>; 86 linux,pci-domain = <1>; 87 num-ib-windows = <6>; 88 num-ob-windows = <2>; 89 max-link-speed = <3>; 90 msi-map = <0x0 &gic 0x1000 0x1000>; 91 num-lanes = <1>; 92 phys = <&pcie30phy>; 93 phy-names = "pcie-phy"; 94 power-domains = <&power RK3568_PD_PIPE>; 95 reg = <0x3 0xc0400000 0x0 0x00400000>, 96 <0x0 0xfe270000 0x0 0x00010000>, 97 <0x3 0x7f000000 0x0 0x01000000>; 98 ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>, 99 <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>; 100 reg-names = "dbi", "apb", "config"; 101 resets = <&cru SRST_PCIE30X1_POWERUP>; 102 reset-names = "pipe"; 103 /* bifurcation; lane1 when using 1+1 */ 104 status = "disabled"; 105 106 pcie3x1_intc: legacy-interrupt-controller { 107 interrupt-controller; 108 #address-cells = <0>; 109 #interrupt-cells = <1>; 110 interrupt-parent = <&gic>; 111 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 112 }; 113 }; 114 115 pcie3x2: pcie@fe280000 { 116 compatible = "rockchip,rk3568-pcie"; 117 #address-cells = <3>; 118 #size-cells = <2>; 119 bus-range = <0x0 0xf>; 120 clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, 121 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, 122 <&cru CLK_PCIE30X2_AUX_NDFT>; 123 clock-names = "aclk_mst", "aclk_slv", 124 "aclk_dbi", "pclk", "aux"; 125 device_type = "pci"; 126 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 131 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 132 #interrupt-cells = <1>; 133 interrupt-map-mask = <0 0 0 7>; 134 interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, 135 <0 0 0 2 &pcie3x2_intc 1>, 136 <0 0 0 3 &pcie3x2_intc 2>, 137 <0 0 0 4 &pcie3x2_intc 3>; 138 linux,pci-domain = <2>; 139 num-ib-windows = <6>; 140 num-ob-windows = <2>; 141 max-link-speed = <3>; 142 msi-map = <0x0 &gic 0x2000 0x1000>; 143 num-lanes = <2>; 144 phys = <&pcie30phy>; 145 phy-names = "pcie-phy"; 146 power-domains = <&power RK3568_PD_PIPE>; 147 reg = <0x3 0xc0800000 0x0 0x00400000>, 148 <0x0 0xfe280000 0x0 0x00010000>, 149 <0x3 0xbf000000 0x0 0x01000000>; 150 ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>, 151 <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>; 152 reg-names = "dbi", "apb", "config"; 153 resets = <&cru SRST_PCIE30X2_POWERUP>; 154 reset-names = "pipe"; 155 /* bifurcation; lane0 when using 1+1 */ 156 status = "disabled"; 157 158 pcie3x2_intc: legacy-interrupt-controller { 159 interrupt-controller; 160 #address-cells = <0>; 161 #interrupt-cells = <1>; 162 interrupt-parent = <&gic>; 163 interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>; 164 }; 165 }; 166 167 gmac0: ethernet@fe2a0000 { 168 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; 169 reg = <0x0 0xfe2a0000 0x0 0x10000>; 170 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 172 interrupt-names = "macirq", "eth_wake_irq"; 173 clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>, 174 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>, 175 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>, 176 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>; 177 clock-names = "stmmaceth", "mac_clk_rx", 178 "mac_clk_tx", "clk_mac_refout", 179 "aclk_mac", "pclk_mac", 180 "clk_mac_speed", "ptp_ref"; 181 resets = <&cru SRST_A_GMAC0>; 182 reset-names = "stmmaceth"; 183 rockchip,grf = <&grf>; 184 snps,axi-config = <&gmac0_stmmac_axi_setup>; 185 snps,mixed-burst; 186 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 187 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 188 snps,tso; 189 status = "disabled"; 190 191 mdio0: mdio { 192 compatible = "snps,dwmac-mdio"; 193 #address-cells = <0x1>; 194 #size-cells = <0x0>; 195 }; 196 197 gmac0_stmmac_axi_setup: stmmac-axi-config { 198 snps,blen = <0 0 0 0 16 8 4>; 199 snps,rd_osr_lmt = <8>; 200 snps,wr_osr_lmt = <4>; 201 }; 202 203 gmac0_mtl_rx_setup: rx-queues-config { 204 snps,rx-queues-to-use = <1>; 205 queue0 {}; 206 }; 207 208 gmac0_mtl_tx_setup: tx-queues-config { 209 snps,tx-queues-to-use = <1>; 210 queue0 {}; 211 }; 212 }; 213 214 combphy0: phy@fe820000 { 215 compatible = "rockchip,rk3568-naneng-combphy"; 216 reg = <0x0 0xfe820000 0x0 0x100>; 217 clocks = <&pmucru CLK_PCIEPHY0_REF>, 218 <&cru PCLK_PIPEPHY0>, 219 <&cru PCLK_PIPE>; 220 clock-names = "ref", "apb", "pipe"; 221 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; 222 assigned-clock-rates = <100000000>; 223 resets = <&cru SRST_PIPEPHY0>; 224 rockchip,pipe-grf = <&pipegrf>; 225 rockchip,pipe-phy-grf = <&pipe_phy_grf0>; 226 #phy-cells = <1>; 227 status = "disabled"; 228 }; 229}; 230 231&cpu0_opp_table { 232 opp-1992000000 { 233 opp-hz = /bits/ 64 <1992000000>; 234 opp-microvolt = <1150000 1150000 1150000>; 235 }; 236}; 237 238&pipegrf { 239 compatible = "rockchip,rk3568-pipe-grf", "syscon"; 240}; 241 242&power { 243 power-domain@RK3568_PD_PIPE { 244 reg = <RK3568_PD_PIPE>; 245 clocks = <&cru PCLK_PIPE>; 246 pm_qos = <&qos_pcie2x1>, 247 <&qos_pcie3x1>, 248 <&qos_pcie3x2>, 249 <&qos_sata0>, 250 <&qos_sata1>, 251 <&qos_sata2>, 252 <&qos_usb3_0>, 253 <&qos_usb3_1>; 254 #power-domain-cells = <0>; 255 }; 256}; 257 258&usb_host0_xhci { 259 phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>; 260 phy-names = "usb2-phy", "usb3-phy"; 261}; 262 263&vop { 264 compatible = "rockchip,rk3568-vop"; 265}; 266