1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3568-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/soc/rockchip,boot-mode.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "rockchip,rk3568"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 gpio0 = &gpio0; 23 gpio1 = &gpio1; 24 gpio2 = &gpio2; 25 gpio3 = &gpio3; 26 gpio4 = &gpio4; 27 i2c0 = &i2c0; 28 i2c1 = &i2c1; 29 i2c2 = &i2c2; 30 i2c3 = &i2c3; 31 i2c4 = &i2c4; 32 i2c5 = &i2c5; 33 serial0 = &uart0; 34 serial1 = &uart1; 35 serial2 = &uart2; 36 serial3 = &uart3; 37 serial4 = &uart4; 38 serial5 = &uart5; 39 serial6 = &uart6; 40 serial7 = &uart7; 41 serial8 = &uart8; 42 serial9 = &uart9; 43 }; 44 45 cpus { 46 #address-cells = <2>; 47 #size-cells = <0>; 48 49 cpu0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a55"; 52 reg = <0x0 0x0>; 53 clocks = <&scmi_clk 0>; 54 enable-method = "psci"; 55 operating-points-v2 = <&cpu0_opp_table>; 56 }; 57 58 cpu1: cpu@100 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a55"; 61 reg = <0x0 0x100>; 62 enable-method = "psci"; 63 operating-points-v2 = <&cpu0_opp_table>; 64 }; 65 66 cpu2: cpu@200 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a55"; 69 reg = <0x0 0x200>; 70 enable-method = "psci"; 71 operating-points-v2 = <&cpu0_opp_table>; 72 }; 73 74 cpu3: cpu@300 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a55"; 77 reg = <0x0 0x300>; 78 enable-method = "psci"; 79 operating-points-v2 = <&cpu0_opp_table>; 80 }; 81 }; 82 83 cpu0_opp_table: cpu0-opp-table { 84 compatible = "operating-points-v2"; 85 opp-shared; 86 87 opp-408000000 { 88 opp-hz = /bits/ 64 <408000000>; 89 opp-microvolt = <900000 900000 1150000>; 90 clock-latency-ns = <40000>; 91 }; 92 93 opp-600000000 { 94 opp-hz = /bits/ 64 <600000000>; 95 opp-microvolt = <900000 900000 1150000>; 96 }; 97 98 opp-816000000 { 99 opp-hz = /bits/ 64 <816000000>; 100 opp-microvolt = <900000 900000 1150000>; 101 opp-suspend; 102 }; 103 104 opp-1104000000 { 105 opp-hz = /bits/ 64 <1104000000>; 106 opp-microvolt = <900000 900000 1150000>; 107 }; 108 109 opp-1416000000 { 110 opp-hz = /bits/ 64 <1416000000>; 111 opp-microvolt = <900000 900000 1150000>; 112 }; 113 114 opp-1608000000 { 115 opp-hz = /bits/ 64 <1608000000>; 116 opp-microvolt = <975000 975000 1150000>; 117 }; 118 119 opp-1800000000 { 120 opp-hz = /bits/ 64 <1800000000>; 121 opp-microvolt = <1050000 1050000 1150000>; 122 }; 123 124 opp-1992000000 { 125 opp-hz = /bits/ 64 <1992000000>; 126 opp-microvolt = <1150000 1150000 1150000>; 127 }; 128 }; 129 130 firmware { 131 scmi: scmi { 132 compatible = "arm,scmi-smc"; 133 arm,smc-id = <0x82000010>; 134 shmem = <&scmi_shmem>; 135 #address-cells = <1>; 136 #size-cells = <0>; 137 138 scmi_clk: protocol@14 { 139 reg = <0x14>; 140 #clock-cells = <1>; 141 }; 142 }; 143 }; 144 145 pmu { 146 compatible = "arm,cortex-a55-pmu"; 147 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 152 }; 153 154 psci { 155 compatible = "arm,psci-1.0"; 156 method = "smc"; 157 }; 158 159 timer { 160 compatible = "arm,armv8-timer"; 161 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 165 arm,no-tick-in-suspend; 166 }; 167 168 xin24m: xin24m { 169 compatible = "fixed-clock"; 170 clock-frequency = <24000000>; 171 clock-output-names = "xin24m"; 172 #clock-cells = <0>; 173 }; 174 175 xin32k: xin32k { 176 compatible = "fixed-clock"; 177 clock-frequency = <32768>; 178 clock-output-names = "xin32k"; 179 pinctrl-0 = <&clk32k_out0>; 180 pinctrl-names = "default"; 181 #clock-cells = <0>; 182 }; 183 184 sram@10f000 { 185 compatible = "mmio-sram"; 186 reg = <0x0 0x0010f000 0x0 0x100>; 187 #address-cells = <1>; 188 #size-cells = <1>; 189 ranges = <0 0x0 0x0010f000 0x100>; 190 191 scmi_shmem: sram@0 { 192 compatible = "arm,scmi-shmem"; 193 reg = <0x0 0x100>; 194 }; 195 }; 196 197 gic: interrupt-controller@fd400000 { 198 compatible = "arm,gic-v3"; 199 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ 200 <0x0 0xfd460000 0 0x80000>; /* GICR */ 201 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 202 interrupt-controller; 203 #interrupt-cells = <3>; 204 mbi-alias = <0x0 0xfd100000>; 205 mbi-ranges = <296 24>; 206 msi-controller; 207 }; 208 209 pmugrf: syscon@fdc20000 { 210 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; 211 reg = <0x0 0xfdc20000 0x0 0x10000>; 212 }; 213 214 grf: syscon@fdc60000 { 215 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; 216 reg = <0x0 0xfdc60000 0x0 0x10000>; 217 }; 218 219 pmucru: clock-controller@fdd00000 { 220 compatible = "rockchip,rk3568-pmucru"; 221 reg = <0x0 0xfdd00000 0x0 0x1000>; 222 #clock-cells = <1>; 223 #reset-cells = <1>; 224 }; 225 226 cru: clock-controller@fdd20000 { 227 compatible = "rockchip,rk3568-cru"; 228 reg = <0x0 0xfdd20000 0x0 0x1000>; 229 #clock-cells = <1>; 230 #reset-cells = <1>; 231 }; 232 233 i2c0: i2c@fdd40000 { 234 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 235 reg = <0x0 0xfdd40000 0x0 0x1000>; 236 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 238 clock-names = "i2c", "pclk"; 239 pinctrl-0 = <&i2c0_xfer>; 240 pinctrl-names = "default"; 241 #address-cells = <1>; 242 #size-cells = <0>; 243 status = "disabled"; 244 }; 245 246 uart0: serial@fdd50000 { 247 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 248 reg = <0x0 0xfdd50000 0x0 0x100>; 249 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; 251 clock-names = "baudclk", "apb_pclk"; 252 dmas = <&dmac0 0>, <&dmac0 1>; 253 pinctrl-0 = <&uart0_xfer>; 254 pinctrl-names = "default"; 255 reg-io-width = <4>; 256 reg-shift = <2>; 257 status = "disabled"; 258 }; 259 260 sdmmc2: mmc@fe000000 { 261 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 262 reg = <0x0 0xfe000000 0x0 0x4000>; 263 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 264 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, 265 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; 266 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 267 fifo-depth = <0x100>; 268 max-frequency = <150000000>; 269 resets = <&cru SRST_SDMMC2>; 270 reset-names = "reset"; 271 status = "disabled"; 272 }; 273 274 sdmmc0: mmc@fe2b0000 { 275 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 276 reg = <0x0 0xfe2b0000 0x0 0x4000>; 277 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, 279 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; 280 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 281 fifo-depth = <0x100>; 282 max-frequency = <150000000>; 283 resets = <&cru SRST_SDMMC0>; 284 reset-names = "reset"; 285 status = "disabled"; 286 }; 287 288 sdmmc1: mmc@fe2c0000 { 289 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 290 reg = <0x0 0xfe2c0000 0x0 0x4000>; 291 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 292 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, 293 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; 294 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 295 fifo-depth = <0x100>; 296 max-frequency = <150000000>; 297 resets = <&cru SRST_SDMMC1>; 298 reset-names = "reset"; 299 status = "disabled"; 300 }; 301 302 sdhci: mmc@fe310000 { 303 compatible = "rockchip,rk3568-dwcmshc"; 304 reg = <0x0 0xfe310000 0x0 0x10000>; 305 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 306 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; 307 assigned-clock-rates = <200000000>, <24000000>; 308 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 309 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 310 <&cru TCLK_EMMC>; 311 clock-names = "core", "bus", "axi", "block", "timer"; 312 status = "disabled"; 313 }; 314 315 dmac0: dmac@fe530000 { 316 compatible = "arm,pl330", "arm,primecell"; 317 reg = <0x0 0xfe530000 0x0 0x4000>; 318 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 320 arm,pl330-periph-burst; 321 clocks = <&cru ACLK_BUS>; 322 clock-names = "apb_pclk"; 323 #dma-cells = <1>; 324 }; 325 326 dmac1: dmac@fe550000 { 327 compatible = "arm,pl330", "arm,primecell"; 328 reg = <0x0 0xfe550000 0x0 0x4000>; 329 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 331 arm,pl330-periph-burst; 332 clocks = <&cru ACLK_BUS>; 333 clock-names = "apb_pclk"; 334 #dma-cells = <1>; 335 }; 336 337 i2c1: i2c@fe5a0000 { 338 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 339 reg = <0x0 0xfe5a0000 0x0 0x1000>; 340 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 341 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 342 clock-names = "i2c", "pclk"; 343 pinctrl-0 = <&i2c1_xfer>; 344 pinctrl-names = "default"; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 status = "disabled"; 348 }; 349 350 i2c2: i2c@fe5b0000 { 351 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 352 reg = <0x0 0xfe5b0000 0x0 0x1000>; 353 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 355 clock-names = "i2c", "pclk"; 356 pinctrl-0 = <&i2c2m0_xfer>; 357 pinctrl-names = "default"; 358 #address-cells = <1>; 359 #size-cells = <0>; 360 status = "disabled"; 361 }; 362 363 i2c3: i2c@fe5c0000 { 364 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 365 reg = <0x0 0xfe5c0000 0x0 0x1000>; 366 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 368 clock-names = "i2c", "pclk"; 369 pinctrl-0 = <&i2c3m0_xfer>; 370 pinctrl-names = "default"; 371 #address-cells = <1>; 372 #size-cells = <0>; 373 status = "disabled"; 374 }; 375 376 i2c4: i2c@fe5d0000 { 377 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 378 reg = <0x0 0xfe5d0000 0x0 0x1000>; 379 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 380 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 381 clock-names = "i2c", "pclk"; 382 pinctrl-0 = <&i2c4m0_xfer>; 383 pinctrl-names = "default"; 384 #address-cells = <1>; 385 #size-cells = <0>; 386 status = "disabled"; 387 }; 388 389 i2c5: i2c@fe5e0000 { 390 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 391 reg = <0x0 0xfe5e0000 0x0 0x1000>; 392 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 394 clock-names = "i2c", "pclk"; 395 pinctrl-0 = <&i2c5m0_xfer>; 396 pinctrl-names = "default"; 397 #address-cells = <1>; 398 #size-cells = <0>; 399 status = "disabled"; 400 }; 401 402 uart1: serial@fe650000 { 403 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 404 reg = <0x0 0xfe650000 0x0 0x100>; 405 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 407 clock-names = "baudclk", "apb_pclk"; 408 dmas = <&dmac0 2>, <&dmac0 3>; 409 pinctrl-0 = <&uart1m0_xfer>; 410 pinctrl-names = "default"; 411 reg-io-width = <4>; 412 reg-shift = <2>; 413 status = "disabled"; 414 }; 415 416 uart2: serial@fe660000 { 417 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 418 reg = <0x0 0xfe660000 0x0 0x100>; 419 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 421 clock-names = "baudclk", "apb_pclk"; 422 dmas = <&dmac0 4>, <&dmac0 5>; 423 pinctrl-0 = <&uart2m0_xfer>; 424 pinctrl-names = "default"; 425 reg-io-width = <4>; 426 reg-shift = <2>; 427 status = "disabled"; 428 }; 429 430 uart3: serial@fe670000 { 431 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 432 reg = <0x0 0xfe670000 0x0 0x100>; 433 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 434 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 435 clock-names = "baudclk", "apb_pclk"; 436 dmas = <&dmac0 6>, <&dmac0 7>; 437 pinctrl-0 = <&uart3m0_xfer>; 438 pinctrl-names = "default"; 439 reg-io-width = <4>; 440 reg-shift = <2>; 441 status = "disabled"; 442 }; 443 444 uart4: serial@fe680000 { 445 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 446 reg = <0x0 0xfe680000 0x0 0x100>; 447 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 449 clock-names = "baudclk", "apb_pclk"; 450 dmas = <&dmac0 8>, <&dmac0 9>; 451 pinctrl-0 = <&uart4m0_xfer>; 452 pinctrl-names = "default"; 453 reg-io-width = <4>; 454 reg-shift = <2>; 455 status = "disabled"; 456 }; 457 458 uart5: serial@fe690000 { 459 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 460 reg = <0x0 0xfe690000 0x0 0x100>; 461 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 463 clock-names = "baudclk", "apb_pclk"; 464 dmas = <&dmac0 10>, <&dmac0 11>; 465 pinctrl-0 = <&uart5m0_xfer>; 466 pinctrl-names = "default"; 467 reg-io-width = <4>; 468 reg-shift = <2>; 469 status = "disabled"; 470 }; 471 472 uart6: serial@fe6a0000 { 473 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 474 reg = <0x0 0xfe6a0000 0x0 0x100>; 475 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 477 clock-names = "baudclk", "apb_pclk"; 478 dmas = <&dmac0 12>, <&dmac0 13>; 479 pinctrl-0 = <&uart6m0_xfer>; 480 pinctrl-names = "default"; 481 reg-io-width = <4>; 482 reg-shift = <2>; 483 status = "disabled"; 484 }; 485 486 uart7: serial@fe6b0000 { 487 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 488 reg = <0x0 0xfe6b0000 0x0 0x100>; 489 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 490 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 491 clock-names = "baudclk", "apb_pclk"; 492 dmas = <&dmac0 14>, <&dmac0 15>; 493 pinctrl-0 = <&uart7m0_xfer>; 494 pinctrl-names = "default"; 495 reg-io-width = <4>; 496 reg-shift = <2>; 497 status = "disabled"; 498 }; 499 500 uart8: serial@fe6c0000 { 501 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 502 reg = <0x0 0xfe6c0000 0x0 0x100>; 503 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 505 clock-names = "baudclk", "apb_pclk"; 506 dmas = <&dmac0 16>, <&dmac0 17>; 507 pinctrl-0 = <&uart8m0_xfer>; 508 pinctrl-names = "default"; 509 reg-io-width = <4>; 510 reg-shift = <2>; 511 status = "disabled"; 512 }; 513 514 uart9: serial@fe6d0000 { 515 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 516 reg = <0x0 0xfe6d0000 0x0 0x100>; 517 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 519 clock-names = "baudclk", "apb_pclk"; 520 dmas = <&dmac0 18>, <&dmac0 19>; 521 pinctrl-0 = <&uart9m0_xfer>; 522 pinctrl-names = "default"; 523 reg-io-width = <4>; 524 reg-shift = <2>; 525 status = "disabled"; 526 }; 527 528 pinctrl: pinctrl { 529 compatible = "rockchip,rk3568-pinctrl"; 530 rockchip,grf = <&grf>; 531 rockchip,pmu = <&pmugrf>; 532 #address-cells = <2>; 533 #size-cells = <2>; 534 ranges; 535 536 gpio0: gpio@fdd60000 { 537 compatible = "rockchip,gpio-bank"; 538 reg = <0x0 0xfdd60000 0x0 0x100>; 539 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&pmucru PCLK_GPIO0>; 541 gpio-controller; 542 #gpio-cells = <2>; 543 interrupt-controller; 544 #interrupt-cells = <2>; 545 }; 546 547 gpio1: gpio@fe740000 { 548 compatible = "rockchip,gpio-bank"; 549 reg = <0x0 0xfe740000 0x0 0x100>; 550 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&cru PCLK_GPIO1>; 552 gpio-controller; 553 #gpio-cells = <2>; 554 interrupt-controller; 555 #interrupt-cells = <2>; 556 }; 557 558 gpio2: gpio@fe750000 { 559 compatible = "rockchip,gpio-bank"; 560 reg = <0x0 0xfe750000 0x0 0x100>; 561 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 562 clocks = <&cru PCLK_GPIO2>; 563 gpio-controller; 564 #gpio-cells = <2>; 565 interrupt-controller; 566 #interrupt-cells = <2>; 567 }; 568 569 gpio3: gpio@fe760000 { 570 compatible = "rockchip,gpio-bank"; 571 reg = <0x0 0xfe760000 0x0 0x100>; 572 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&cru PCLK_GPIO3>; 574 gpio-controller; 575 #gpio-cells = <2>; 576 interrupt-controller; 577 #interrupt-cells = <2>; 578 }; 579 580 gpio4: gpio@fe770000 { 581 compatible = "rockchip,gpio-bank"; 582 reg = <0x0 0xfe770000 0x0 0x100>; 583 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 584 clocks = <&cru PCLK_GPIO4>; 585 gpio-controller; 586 #gpio-cells = <2>; 587 interrupt-controller; 588 #interrupt-cells = <2>; 589 }; 590 }; 591}; 592 593#include "rk3568-pinctrl.dtsi" 594