1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Hardkernel Co., Ltd. 4 * 5 */ 6 7/dts-v1/; 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/leds/common.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/soc/rockchip,vop2.h> 12#include "rk3568.dtsi" 13 14/ { 15 model = "Hardkernel ODROID-M1"; 16 compatible = "rockchip,rk3568-odroid-m1", "rockchip,rk3568"; 17 18 aliases { 19 ethernet0 = &gmac0; 20 i2c0 = &i2c3; 21 i2c3 = &i2c0; 22 mmc0 = &sdhci; 23 mmc1 = &sdmmc0; 24 serial0 = &uart1; 25 serial1 = &uart0; 26 }; 27 28 chosen { 29 stdout-path = "serial2:1500000n8"; 30 }; 31 32 dc_12v: dc-12v-regulator { 33 compatible = "regulator-fixed"; 34 regulator-name = "dc_12v"; 35 regulator-always-on; 36 regulator-boot-on; 37 regulator-min-microvolt = <12000000>; 38 regulator-max-microvolt = <12000000>; 39 }; 40 41 hdmi-con { 42 compatible = "hdmi-connector"; 43 type = "a"; 44 45 port { 46 hdmi_con_in: endpoint { 47 remote-endpoint = <&hdmi_out_con>; 48 }; 49 }; 50 }; 51 52 leds { 53 compatible = "gpio-leds"; 54 55 led_power: led-0 { 56 gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; 57 function = LED_FUNCTION_POWER; 58 color = <LED_COLOR_ID_RED>; 59 default-state = "keep"; 60 linux,default-trigger = "default-on"; 61 pinctrl-names = "default"; 62 pinctrl-0 = <&led_power_pin>; 63 }; 64 led_work: led-1 { 65 gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; 66 function = LED_FUNCTION_HEARTBEAT; 67 color = <LED_COLOR_ID_BLUE>; 68 linux,default-trigger = "heartbeat"; 69 pinctrl-names = "default"; 70 pinctrl-0 = <&led_work_pin>; 71 }; 72 }; 73 74 rk809-sound { 75 compatible = "simple-audio-card"; 76 pinctrl-names = "default"; 77 pinctrl-0 = <&hp_det_pin>; 78 simple-audio-card,name = "Analog RK817"; 79 simple-audio-card,format = "i2s"; 80 simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; 81 simple-audio-card,mclk-fs = <256>; 82 simple-audio-card,widgets = 83 "Headphone", "Headphones", 84 "Speaker", "Speaker"; 85 simple-audio-card,routing = 86 "Headphones", "HPOL", 87 "Headphones", "HPOR", 88 "Speaker", "SPKO"; 89 90 simple-audio-card,cpu { 91 sound-dai = <&i2s1_8ch>; 92 }; 93 94 simple-audio-card,codec { 95 sound-dai = <&rk809>; 96 }; 97 }; 98 99 vcc3v3_sys: vcc3v3-sys-regulator { 100 compatible = "regulator-fixed"; 101 regulator-name = "vcc3v3_sys"; 102 regulator-always-on; 103 regulator-boot-on; 104 regulator-min-microvolt = <3300000>; 105 regulator-max-microvolt = <3300000>; 106 vin-supply = <&dc_12v>; 107 }; 108}; 109 110&cpu0 { 111 cpu-supply = <&vdd_cpu>; 112}; 113 114&cpu1 { 115 cpu-supply = <&vdd_cpu>; 116}; 117 118&cpu2 { 119 cpu-supply = <&vdd_cpu>; 120}; 121 122&cpu3 { 123 cpu-supply = <&vdd_cpu>; 124}; 125 126&gmac0 { 127 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; 128 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; 129 assigned-clock-rates = <0>, <125000000>; 130 clock_in_out = "output"; 131 phy-handle = <&rgmii_phy0>; 132 phy-mode = "rgmii"; 133 phy-supply = <&vcc3v3_sys>; 134 pinctrl-names = "default"; 135 pinctrl-0 = <&gmac0_miim 136 &gmac0_tx_bus2 137 &gmac0_rx_bus2 138 &gmac0_rgmii_clk 139 &gmac0_rgmii_bus>; 140 status = "okay"; 141 142 tx_delay = <0x4f>; 143 rx_delay = <0x2d>; 144}; 145 146&hdmi { 147 avdd-0v9-supply = <&vdda0v9_image>; 148 avdd-1v8-supply = <&vcca1v8_image>; 149 status = "okay"; 150}; 151 152&hdmi_in { 153 hdmi_in_vp0: endpoint { 154 remote-endpoint = <&vp0_out_hdmi>; 155 }; 156}; 157 158&hdmi_out { 159 hdmi_out_con: endpoint { 160 remote-endpoint = <&hdmi_con_in>; 161 }; 162}; 163 164&i2c0 { 165 status = "okay"; 166 167 vdd_cpu: regulator@1c { 168 compatible = "tcs,tcs4525"; 169 reg = <0x1c>; 170 fcs,suspend-voltage-selector = <1>; 171 regulator-name = "vdd_cpu"; 172 regulator-always-on; 173 regulator-boot-on; 174 regulator-min-microvolt = <800000>; 175 regulator-max-microvolt = <1150000>; 176 regulator-ramp-delay = <2300>; 177 vin-supply = <&vcc3v3_sys>; 178 179 regulator-state-mem { 180 regulator-off-in-suspend; 181 }; 182 }; 183 184 rk809: pmic@20 { 185 compatible = "rockchip,rk809"; 186 reg = <0x20>; 187 interrupt-parent = <&gpio0>; 188 interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; 189 assigned-clocks = <&cru I2S1_MCLKOUT_TX>; 190 assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; 191 #clock-cells = <1>; 192 clock-names = "mclk"; 193 clocks = <&cru I2S1_MCLKOUT_TX>; 194 pinctrl-names = "default"; 195 pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; 196 rockchip,system-power-controller; 197 #sound-dai-cells = <0>; 198 vcc1-supply = <&vcc3v3_sys>; 199 vcc2-supply = <&vcc3v3_sys>; 200 vcc3-supply = <&vcc3v3_sys>; 201 vcc4-supply = <&vcc3v3_sys>; 202 vcc5-supply = <&vcc3v3_sys>; 203 vcc6-supply = <&vcc3v3_sys>; 204 vcc7-supply = <&vcc3v3_sys>; 205 vcc8-supply = <&vcc3v3_sys>; 206 vcc9-supply = <&vcc3v3_sys>; 207 wakeup-source; 208 209 regulators { 210 vdd_logic: DCDC_REG1 { 211 regulator-name = "vdd_logic"; 212 regulator-always-on; 213 regulator-boot-on; 214 regulator-init-microvolt = <900000>; 215 regulator-initial-mode = <0x2>; 216 regulator-min-microvolt = <500000>; 217 regulator-max-microvolt = <1350000>; 218 regulator-ramp-delay = <6001>; 219 220 regulator-state-mem { 221 regulator-off-in-suspend; 222 }; 223 }; 224 225 vdd_gpu: DCDC_REG2 { 226 regulator-name = "vdd_gpu"; 227 regulator-always-on; 228 regulator-init-microvolt = <900000>; 229 regulator-initial-mode = <0x2>; 230 regulator-min-microvolt = <500000>; 231 regulator-max-microvolt = <1350000>; 232 regulator-ramp-delay = <6001>; 233 234 regulator-state-mem { 235 regulator-off-in-suspend; 236 }; 237 }; 238 239 vcc_ddr: DCDC_REG3 { 240 regulator-name = "vcc_ddr"; 241 regulator-always-on; 242 regulator-boot-on; 243 regulator-initial-mode = <0x2>; 244 245 regulator-state-mem { 246 regulator-on-in-suspend; 247 }; 248 }; 249 250 vdd_npu: DCDC_REG4 { 251 regulator-name = "vdd_npu"; 252 regulator-init-microvolt = <900000>; 253 regulator-initial-mode = <0x2>; 254 regulator-min-microvolt = <500000>; 255 regulator-max-microvolt = <1350000>; 256 regulator-ramp-delay = <6001>; 257 258 regulator-state-mem { 259 regulator-off-in-suspend; 260 }; 261 }; 262 263 vcc_1v8: DCDC_REG5 { 264 regulator-name = "vcc_1v8"; 265 regulator-always-on; 266 regulator-boot-on; 267 regulator-min-microvolt = <1800000>; 268 regulator-max-microvolt = <1800000>; 269 270 regulator-state-mem { 271 regulator-off-in-suspend; 272 }; 273 }; 274 275 vdda0v9_image: LDO_REG1 { 276 regulator-name = "vdda0v9_image"; 277 regulator-always-on; 278 regulator-min-microvolt = <900000>; 279 regulator-max-microvolt = <900000>; 280 281 regulator-state-mem { 282 regulator-off-in-suspend; 283 }; 284 }; 285 286 vdda_0v9: LDO_REG2 { 287 regulator-name = "vdda_0v9"; 288 regulator-always-on; 289 regulator-boot-on; 290 regulator-min-microvolt = <900000>; 291 regulator-max-microvolt = <900000>; 292 293 regulator-state-mem { 294 regulator-off-in-suspend; 295 }; 296 }; 297 298 vdda0v9_pmu: LDO_REG3 { 299 regulator-name = "vdda0v9_pmu"; 300 regulator-always-on; 301 regulator-boot-on; 302 regulator-min-microvolt = <900000>; 303 regulator-max-microvolt = <900000>; 304 305 regulator-state-mem { 306 regulator-on-in-suspend; 307 regulator-suspend-microvolt = <900000>; 308 }; 309 }; 310 311 vccio_acodec: LDO_REG4 { 312 regulator-name = "vccio_acodec"; 313 regulator-always-on; 314 regulator-boot-on; 315 regulator-min-microvolt = <3300000>; 316 regulator-max-microvolt = <3300000>; 317 318 regulator-state-mem { 319 regulator-off-in-suspend; 320 }; 321 }; 322 323 vccio_sd: LDO_REG5 { 324 regulator-name = "vccio_sd"; 325 regulator-min-microvolt = <1800000>; 326 regulator-max-microvolt = <3300000>; 327 328 regulator-state-mem { 329 regulator-off-in-suspend; 330 }; 331 }; 332 333 vcc3v3_pmu: LDO_REG6 { 334 regulator-name = "vcc3v3_pmu"; 335 regulator-always-on; 336 regulator-boot-on; 337 regulator-min-microvolt = <3300000>; 338 regulator-max-microvolt = <3300000>; 339 340 regulator-state-mem { 341 regulator-on-in-suspend; 342 regulator-suspend-microvolt = <3300000>; 343 }; 344 }; 345 346 vcca_1v8: LDO_REG7 { 347 regulator-name = "vcca_1v8"; 348 regulator-always-on; 349 regulator-boot-on; 350 regulator-min-microvolt = <1800000>; 351 regulator-max-microvolt = <1800000>; 352 353 regulator-state-mem { 354 regulator-off-in-suspend; 355 }; 356 }; 357 358 vcca1v8_pmu: LDO_REG8 { 359 regulator-name = "vcca1v8_pmu"; 360 regulator-always-on; 361 regulator-boot-on; 362 regulator-min-microvolt = <1800000>; 363 regulator-max-microvolt = <1800000>; 364 365 regulator-state-mem { 366 regulator-on-in-suspend; 367 regulator-suspend-microvolt = <1800000>; 368 }; 369 }; 370 371 vcca1v8_image: LDO_REG9 { 372 regulator-name = "vcca1v8_image"; 373 regulator-always-on; 374 regulator-min-microvolt = <1800000>; 375 regulator-max-microvolt = <1800000>; 376 377 regulator-state-mem { 378 regulator-off-in-suspend; 379 }; 380 }; 381 382 vcc_3v3: SWITCH_REG1 { 383 regulator-name = "vcc_3v3"; 384 regulator-always-on; 385 regulator-boot-on; 386 387 regulator-state-mem { 388 regulator-off-in-suspend; 389 }; 390 }; 391 392 vcc3v3_sd: SWITCH_REG2 { 393 regulator-name = "vcc3v3_sd"; 394 395 regulator-state-mem { 396 regulator-off-in-suspend; 397 }; 398 }; 399 }; 400 }; 401}; 402 403&i2s1_8ch { 404 rockchip,trcm-sync-tx-only; 405 status = "okay"; 406}; 407 408&mdio0 { 409 rgmii_phy0: ethernet-phy@0 { 410 compatible = "ethernet-phy-ieee802.3-c22"; 411 reg = <0x0>; 412 reset-assert-us = <20000>; 413 reset-deassert-us = <100000>; 414 reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; 415 }; 416}; 417 418&pinctrl { 419 fspi { 420 fspi_dual_io_pins: fspi-dual-io-pins { 421 rockchip,pins = 422 /* fspi_clk */ 423 <1 RK_PD0 1 &pcfg_pull_none>, 424 /* fspi_cs0n */ 425 <1 RK_PD3 1 &pcfg_pull_none>, 426 /* fspi_d0 */ 427 <1 RK_PD1 1 &pcfg_pull_none>, 428 /* fspi_d1 */ 429 <1 RK_PD2 1 &pcfg_pull_none>; 430 }; 431 }; 432 433 leds { 434 led_power_pin: led-power-pin { 435 rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 436 }; 437 led_work_pin: led-work-pin { 438 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; 439 }; 440 }; 441 442 pmic { 443 pmic_int_l: pmic-int-l { 444 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; 445 }; 446 }; 447 448 rk809 { 449 hp_det_pin: hp-det-pin { 450 rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 451 }; 452 }; 453}; 454 455&pmu_io_domains { 456 pmuio1-supply = <&vcc3v3_pmu>; 457 pmuio2-supply = <&vcc3v3_pmu>; 458 vccio1-supply = <&vccio_acodec>; 459 vccio2-supply = <&vcc_1v8>; 460 vccio3-supply = <&vccio_sd>; 461 vccio4-supply = <&vcc_1v8>; 462 vccio5-supply = <&vcc_3v3>; 463 vccio6-supply = <&vcc_3v3>; 464 vccio7-supply = <&vcc_3v3>; 465 status = "okay"; 466}; 467 468&saradc { 469 vref-supply = <&vcca_1v8>; 470 status = "okay"; 471}; 472 473&sdhci { 474 bus-width = <8>; 475 max-frequency = <200000000>; 476 non-removable; 477 pinctrl-names = "default"; 478 pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>; 479 vmmc-supply = <&vcc_3v3>; 480 vqmmc-supply = <&vcc_1v8>; 481 status = "okay"; 482}; 483 484&sdmmc0 { 485 bus-width = <4>; 486 cap-sd-highspeed; 487 cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; 488 disable-wp; 489 pinctrl-names = "default"; 490 pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; 491 sd-uhs-sdr50; 492 vmmc-supply = <&vcc3v3_sd>; 493 vqmmc-supply = <&vccio_sd>; 494 status = "okay"; 495}; 496 497&sfc { 498 /* Dual I/O mode as the D2 pin conflicts with the eMMC */ 499 pinctrl-0 = <&fspi_dual_io_pins>; 500 pinctrl-names = "default"; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 status = "okay"; 504 505 flash@0 { 506 compatible = "jedec,spi-nor"; 507 reg = <0>; 508 spi-max-frequency = <100000000>; 509 spi-rx-bus-width = <2>; 510 spi-tx-bus-width = <1>; 511 512 partitions { 513 compatible = "fixed-partitions"; 514 #address-cells = <1>; 515 #size-cells = <1>; 516 517 partition@0 { 518 label = "SPL"; 519 reg = <0x0 0xe0000>; 520 }; 521 partition@e0000 { 522 label = "U-Boot Env"; 523 reg = <0xe0000 0x20000>; 524 }; 525 partition@100000 { 526 label = "U-Boot"; 527 reg = <0x100000 0x200000>; 528 }; 529 partition@300000 { 530 label = "splash"; 531 reg = <0x300000 0x100000>; 532 }; 533 partition@400000 { 534 label = "Filesystem"; 535 reg = <0x400000 0xc00000>; 536 }; 537 }; 538 }; 539}; 540 541&tsadc { 542 rockchip,hw-tshut-mode = <1>; 543 rockchip,hw-tshut-polarity = <0>; 544 status = "okay"; 545}; 546 547&uart2 { 548 status = "okay"; 549}; 550 551&vop { 552 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; 553 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; 554 status = "okay"; 555}; 556 557&vop_mmu { 558 status = "okay"; 559}; 560 561&vp0 { 562 vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { 563 reg = <ROCKCHIP_VOP2_EP_HDMI0>; 564 remote-endpoint = <&hdmi_in_vp0>; 565 }; 566}; 567