1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Hardkernel Co., Ltd. 4 * 5 */ 6 7/dts-v1/; 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/leds/common.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/soc/rockchip,vop2.h> 12#include "rk3568.dtsi" 13 14/ { 15 model = "Hardkernel ODROID-M1"; 16 compatible = "rockchip,rk3568-odroid-m1", "rockchip,rk3568"; 17 18 aliases { 19 ethernet0 = &gmac0; 20 i2c0 = &i2c3; 21 i2c3 = &i2c0; 22 mmc0 = &sdhci; 23 mmc1 = &sdmmc0; 24 serial0 = &uart1; 25 serial1 = &uart0; 26 }; 27 28 chosen { 29 stdout-path = "serial2:1500000n8"; 30 }; 31 32 dc_12v: dc-12v-regulator { 33 compatible = "regulator-fixed"; 34 regulator-name = "dc_12v"; 35 regulator-always-on; 36 regulator-boot-on; 37 regulator-min-microvolt = <12000000>; 38 regulator-max-microvolt = <12000000>; 39 }; 40 41 hdmi-con { 42 compatible = "hdmi-connector"; 43 type = "a"; 44 45 port { 46 hdmi_con_in: endpoint { 47 remote-endpoint = <&hdmi_out_con>; 48 }; 49 }; 50 }; 51 52 leds { 53 compatible = "gpio-leds"; 54 55 led_power: led-0 { 56 gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; 57 function = LED_FUNCTION_POWER; 58 color = <LED_COLOR_ID_RED>; 59 default-state = "keep"; 60 linux,default-trigger = "default-on"; 61 pinctrl-names = "default"; 62 pinctrl-0 = <&led_power_pin>; 63 }; 64 led_work: led-1 { 65 gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; 66 function = LED_FUNCTION_HEARTBEAT; 67 color = <LED_COLOR_ID_BLUE>; 68 linux,default-trigger = "heartbeat"; 69 pinctrl-names = "default"; 70 pinctrl-0 = <&led_work_pin>; 71 }; 72 }; 73 74 rk809-sound { 75 compatible = "simple-audio-card"; 76 pinctrl-names = "default"; 77 pinctrl-0 = <&hp_det_pin>; 78 simple-audio-card,name = "Analog RK817"; 79 simple-audio-card,format = "i2s"; 80 simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; 81 simple-audio-card,mclk-fs = <256>; 82 simple-audio-card,widgets = 83 "Headphone", "Headphones", 84 "Speaker", "Speaker"; 85 simple-audio-card,routing = 86 "Headphones", "HPOL", 87 "Headphones", "HPOR", 88 "Speaker", "SPKO"; 89 90 simple-audio-card,cpu { 91 sound-dai = <&i2s1_8ch>; 92 }; 93 94 simple-audio-card,codec { 95 sound-dai = <&rk809>; 96 }; 97 }; 98 99 vcc3v3_sys: vcc3v3-sys-regulator { 100 compatible = "regulator-fixed"; 101 regulator-name = "vcc3v3_sys"; 102 regulator-always-on; 103 regulator-boot-on; 104 regulator-min-microvolt = <3300000>; 105 regulator-max-microvolt = <3300000>; 106 vin-supply = <&dc_12v>; 107 }; 108}; 109 110&cpu0 { 111 cpu-supply = <&vdd_cpu>; 112}; 113 114&cpu1 { 115 cpu-supply = <&vdd_cpu>; 116}; 117 118&cpu2 { 119 cpu-supply = <&vdd_cpu>; 120}; 121 122&cpu3 { 123 cpu-supply = <&vdd_cpu>; 124}; 125 126&gmac0 { 127 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; 128 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; 129 assigned-clock-rates = <0>, <125000000>; 130 clock_in_out = "output"; 131 phy-handle = <&rgmii_phy0>; 132 phy-mode = "rgmii"; 133 phy-supply = <&vcc3v3_sys>; 134 pinctrl-names = "default"; 135 pinctrl-0 = <&gmac0_miim 136 &gmac0_tx_bus2 137 &gmac0_rx_bus2 138 &gmac0_rgmii_clk 139 &gmac0_rgmii_bus>; 140 status = "okay"; 141 142 tx_delay = <0x4f>; 143 rx_delay = <0x2d>; 144}; 145 146&hdmi { 147 avdd-0v9-supply = <&vdda0v9_image>; 148 avdd-1v8-supply = <&vcca1v8_image>; 149 status = "okay"; 150}; 151 152&hdmi_in { 153 hdmi_in_vp0: endpoint { 154 remote-endpoint = <&vp0_out_hdmi>; 155 }; 156}; 157 158&hdmi_out { 159 hdmi_out_con: endpoint { 160 remote-endpoint = <&hdmi_con_in>; 161 }; 162}; 163 164&hdmi_sound { 165 status = "okay"; 166}; 167 168&i2c0 { 169 status = "okay"; 170 171 vdd_cpu: regulator@1c { 172 compatible = "tcs,tcs4525"; 173 reg = <0x1c>; 174 fcs,suspend-voltage-selector = <1>; 175 regulator-name = "vdd_cpu"; 176 regulator-always-on; 177 regulator-boot-on; 178 regulator-min-microvolt = <800000>; 179 regulator-max-microvolt = <1150000>; 180 regulator-ramp-delay = <2300>; 181 vin-supply = <&vcc3v3_sys>; 182 183 regulator-state-mem { 184 regulator-off-in-suspend; 185 }; 186 }; 187 188 rk809: pmic@20 { 189 compatible = "rockchip,rk809"; 190 reg = <0x20>; 191 interrupt-parent = <&gpio0>; 192 interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; 193 assigned-clocks = <&cru I2S1_MCLKOUT_TX>; 194 assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; 195 #clock-cells = <1>; 196 clock-names = "mclk"; 197 clocks = <&cru I2S1_MCLKOUT_TX>; 198 pinctrl-names = "default"; 199 pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; 200 rockchip,system-power-controller; 201 #sound-dai-cells = <0>; 202 vcc1-supply = <&vcc3v3_sys>; 203 vcc2-supply = <&vcc3v3_sys>; 204 vcc3-supply = <&vcc3v3_sys>; 205 vcc4-supply = <&vcc3v3_sys>; 206 vcc5-supply = <&vcc3v3_sys>; 207 vcc6-supply = <&vcc3v3_sys>; 208 vcc7-supply = <&vcc3v3_sys>; 209 vcc8-supply = <&vcc3v3_sys>; 210 vcc9-supply = <&vcc3v3_sys>; 211 wakeup-source; 212 213 regulators { 214 vdd_logic: DCDC_REG1 { 215 regulator-name = "vdd_logic"; 216 regulator-always-on; 217 regulator-boot-on; 218 regulator-init-microvolt = <900000>; 219 regulator-initial-mode = <0x2>; 220 regulator-min-microvolt = <500000>; 221 regulator-max-microvolt = <1350000>; 222 regulator-ramp-delay = <6001>; 223 224 regulator-state-mem { 225 regulator-off-in-suspend; 226 }; 227 }; 228 229 vdd_gpu: DCDC_REG2 { 230 regulator-name = "vdd_gpu"; 231 regulator-always-on; 232 regulator-init-microvolt = <900000>; 233 regulator-initial-mode = <0x2>; 234 regulator-min-microvolt = <500000>; 235 regulator-max-microvolt = <1350000>; 236 regulator-ramp-delay = <6001>; 237 238 regulator-state-mem { 239 regulator-off-in-suspend; 240 }; 241 }; 242 243 vcc_ddr: DCDC_REG3 { 244 regulator-name = "vcc_ddr"; 245 regulator-always-on; 246 regulator-boot-on; 247 regulator-initial-mode = <0x2>; 248 249 regulator-state-mem { 250 regulator-on-in-suspend; 251 }; 252 }; 253 254 vdd_npu: DCDC_REG4 { 255 regulator-name = "vdd_npu"; 256 regulator-init-microvolt = <900000>; 257 regulator-initial-mode = <0x2>; 258 regulator-min-microvolt = <500000>; 259 regulator-max-microvolt = <1350000>; 260 regulator-ramp-delay = <6001>; 261 262 regulator-state-mem { 263 regulator-off-in-suspend; 264 }; 265 }; 266 267 vcc_1v8: DCDC_REG5 { 268 regulator-name = "vcc_1v8"; 269 regulator-always-on; 270 regulator-boot-on; 271 regulator-min-microvolt = <1800000>; 272 regulator-max-microvolt = <1800000>; 273 274 regulator-state-mem { 275 regulator-off-in-suspend; 276 }; 277 }; 278 279 vdda0v9_image: LDO_REG1 { 280 regulator-name = "vdda0v9_image"; 281 regulator-always-on; 282 regulator-min-microvolt = <900000>; 283 regulator-max-microvolt = <900000>; 284 285 regulator-state-mem { 286 regulator-off-in-suspend; 287 }; 288 }; 289 290 vdda_0v9: LDO_REG2 { 291 regulator-name = "vdda_0v9"; 292 regulator-always-on; 293 regulator-boot-on; 294 regulator-min-microvolt = <900000>; 295 regulator-max-microvolt = <900000>; 296 297 regulator-state-mem { 298 regulator-off-in-suspend; 299 }; 300 }; 301 302 vdda0v9_pmu: LDO_REG3 { 303 regulator-name = "vdda0v9_pmu"; 304 regulator-always-on; 305 regulator-boot-on; 306 regulator-min-microvolt = <900000>; 307 regulator-max-microvolt = <900000>; 308 309 regulator-state-mem { 310 regulator-on-in-suspend; 311 regulator-suspend-microvolt = <900000>; 312 }; 313 }; 314 315 vccio_acodec: LDO_REG4 { 316 regulator-name = "vccio_acodec"; 317 regulator-always-on; 318 regulator-boot-on; 319 regulator-min-microvolt = <3300000>; 320 regulator-max-microvolt = <3300000>; 321 322 regulator-state-mem { 323 regulator-off-in-suspend; 324 }; 325 }; 326 327 vccio_sd: LDO_REG5 { 328 regulator-name = "vccio_sd"; 329 regulator-min-microvolt = <1800000>; 330 regulator-max-microvolt = <3300000>; 331 332 regulator-state-mem { 333 regulator-off-in-suspend; 334 }; 335 }; 336 337 vcc3v3_pmu: LDO_REG6 { 338 regulator-name = "vcc3v3_pmu"; 339 regulator-always-on; 340 regulator-boot-on; 341 regulator-min-microvolt = <3300000>; 342 regulator-max-microvolt = <3300000>; 343 344 regulator-state-mem { 345 regulator-on-in-suspend; 346 regulator-suspend-microvolt = <3300000>; 347 }; 348 }; 349 350 vcca_1v8: LDO_REG7 { 351 regulator-name = "vcca_1v8"; 352 regulator-always-on; 353 regulator-boot-on; 354 regulator-min-microvolt = <1800000>; 355 regulator-max-microvolt = <1800000>; 356 357 regulator-state-mem { 358 regulator-off-in-suspend; 359 }; 360 }; 361 362 vcca1v8_pmu: LDO_REG8 { 363 regulator-name = "vcca1v8_pmu"; 364 regulator-always-on; 365 regulator-boot-on; 366 regulator-min-microvolt = <1800000>; 367 regulator-max-microvolt = <1800000>; 368 369 regulator-state-mem { 370 regulator-on-in-suspend; 371 regulator-suspend-microvolt = <1800000>; 372 }; 373 }; 374 375 vcca1v8_image: LDO_REG9 { 376 regulator-name = "vcca1v8_image"; 377 regulator-always-on; 378 regulator-min-microvolt = <1800000>; 379 regulator-max-microvolt = <1800000>; 380 381 regulator-state-mem { 382 regulator-off-in-suspend; 383 }; 384 }; 385 386 vcc_3v3: SWITCH_REG1 { 387 regulator-name = "vcc_3v3"; 388 regulator-always-on; 389 regulator-boot-on; 390 391 regulator-state-mem { 392 regulator-off-in-suspend; 393 }; 394 }; 395 396 vcc3v3_sd: SWITCH_REG2 { 397 regulator-name = "vcc3v3_sd"; 398 399 regulator-state-mem { 400 regulator-off-in-suspend; 401 }; 402 }; 403 }; 404 }; 405}; 406 407&i2s0_8ch { 408 status = "okay"; 409}; 410 411&i2s1_8ch { 412 rockchip,trcm-sync-tx-only; 413 status = "okay"; 414}; 415 416&mdio0 { 417 rgmii_phy0: ethernet-phy@0 { 418 compatible = "ethernet-phy-ieee802.3-c22"; 419 reg = <0x0>; 420 reset-assert-us = <20000>; 421 reset-deassert-us = <100000>; 422 reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; 423 }; 424}; 425 426&pinctrl { 427 fspi { 428 fspi_dual_io_pins: fspi-dual-io-pins { 429 rockchip,pins = 430 /* fspi_clk */ 431 <1 RK_PD0 1 &pcfg_pull_none>, 432 /* fspi_cs0n */ 433 <1 RK_PD3 1 &pcfg_pull_none>, 434 /* fspi_d0 */ 435 <1 RK_PD1 1 &pcfg_pull_none>, 436 /* fspi_d1 */ 437 <1 RK_PD2 1 &pcfg_pull_none>; 438 }; 439 }; 440 441 leds { 442 led_power_pin: led-power-pin { 443 rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 444 }; 445 led_work_pin: led-work-pin { 446 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; 447 }; 448 }; 449 450 pmic { 451 pmic_int_l: pmic-int-l { 452 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; 453 }; 454 }; 455 456 rk809 { 457 hp_det_pin: hp-det-pin { 458 rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 459 }; 460 }; 461}; 462 463&pmu_io_domains { 464 pmuio1-supply = <&vcc3v3_pmu>; 465 pmuio2-supply = <&vcc3v3_pmu>; 466 vccio1-supply = <&vccio_acodec>; 467 vccio2-supply = <&vcc_1v8>; 468 vccio3-supply = <&vccio_sd>; 469 vccio4-supply = <&vcc_1v8>; 470 vccio5-supply = <&vcc_3v3>; 471 vccio6-supply = <&vcc_3v3>; 472 vccio7-supply = <&vcc_3v3>; 473 status = "okay"; 474}; 475 476&saradc { 477 vref-supply = <&vcca_1v8>; 478 status = "okay"; 479}; 480 481&sdhci { 482 bus-width = <8>; 483 max-frequency = <200000000>; 484 non-removable; 485 pinctrl-names = "default"; 486 pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>; 487 vmmc-supply = <&vcc_3v3>; 488 vqmmc-supply = <&vcc_1v8>; 489 status = "okay"; 490}; 491 492&sdmmc0 { 493 bus-width = <4>; 494 cap-sd-highspeed; 495 cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; 496 disable-wp; 497 pinctrl-names = "default"; 498 pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; 499 sd-uhs-sdr50; 500 vmmc-supply = <&vcc3v3_sd>; 501 vqmmc-supply = <&vccio_sd>; 502 status = "okay"; 503}; 504 505&sfc { 506 /* Dual I/O mode as the D2 pin conflicts with the eMMC */ 507 pinctrl-0 = <&fspi_dual_io_pins>; 508 pinctrl-names = "default"; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 status = "okay"; 512 513 flash@0 { 514 compatible = "jedec,spi-nor"; 515 reg = <0>; 516 spi-max-frequency = <100000000>; 517 spi-rx-bus-width = <2>; 518 spi-tx-bus-width = <1>; 519 520 partitions { 521 compatible = "fixed-partitions"; 522 #address-cells = <1>; 523 #size-cells = <1>; 524 525 partition@0 { 526 label = "SPL"; 527 reg = <0x0 0xe0000>; 528 }; 529 partition@e0000 { 530 label = "U-Boot Env"; 531 reg = <0xe0000 0x20000>; 532 }; 533 partition@100000 { 534 label = "U-Boot"; 535 reg = <0x100000 0x200000>; 536 }; 537 partition@300000 { 538 label = "splash"; 539 reg = <0x300000 0x100000>; 540 }; 541 partition@400000 { 542 label = "Filesystem"; 543 reg = <0x400000 0xc00000>; 544 }; 545 }; 546 }; 547}; 548 549&tsadc { 550 rockchip,hw-tshut-mode = <1>; 551 rockchip,hw-tshut-polarity = <0>; 552 status = "okay"; 553}; 554 555&uart2 { 556 status = "okay"; 557}; 558 559&vop { 560 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; 561 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; 562 status = "okay"; 563}; 564 565&vop_mmu { 566 status = "okay"; 567}; 568 569&vp0 { 570 vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { 571 reg = <ROCKCHIP_VOP2_EP_HDMI0>; 572 remote-endpoint = <&hdmi_in_vp0>; 573 }; 574}; 575