1fd358326SDongjin Kim// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2fd358326SDongjin Kim/* 3fd358326SDongjin Kim * Copyright (c) 2022 Hardkernel Co., Ltd. 4fd358326SDongjin Kim * 5fd358326SDongjin Kim */ 6fd358326SDongjin Kim 7fd358326SDongjin Kim/dts-v1/; 8fd358326SDongjin Kim#include <dt-bindings/gpio/gpio.h> 9fd358326SDongjin Kim#include <dt-bindings/leds/common.h> 10fd358326SDongjin Kim#include <dt-bindings/pinctrl/rockchip.h> 11fd358326SDongjin Kim#include "rk3568.dtsi" 12fd358326SDongjin Kim 13fd358326SDongjin Kim/ { 14fd358326SDongjin Kim model = "Hardkernel ODROID-M1"; 15fd358326SDongjin Kim compatible = "rockchip,rk3568-odroid-m1", "rockchip,rk3568"; 16fd358326SDongjin Kim 17fd358326SDongjin Kim aliases { 18fd358326SDongjin Kim ethernet0 = &gmac0; 19fd358326SDongjin Kim i2c0 = &i2c3; 20fd358326SDongjin Kim i2c3 = &i2c0; 21fd358326SDongjin Kim mmc0 = &sdhci; 22fd358326SDongjin Kim mmc1 = &sdmmc0; 23fd358326SDongjin Kim serial0 = &uart1; 24fd358326SDongjin Kim serial1 = &uart0; 25fd358326SDongjin Kim }; 26fd358326SDongjin Kim 27fd358326SDongjin Kim chosen { 28fd358326SDongjin Kim stdout-path = "serial2:1500000n8"; 29fd358326SDongjin Kim }; 30fd358326SDongjin Kim 31fd358326SDongjin Kim dc_12v: dc-12v-regulator { 32fd358326SDongjin Kim compatible = "regulator-fixed"; 33fd358326SDongjin Kim regulator-name = "dc_12v"; 34fd358326SDongjin Kim regulator-always-on; 35fd358326SDongjin Kim regulator-boot-on; 36fd358326SDongjin Kim regulator-min-microvolt = <12000000>; 37fd358326SDongjin Kim regulator-max-microvolt = <12000000>; 38fd358326SDongjin Kim }; 39fd358326SDongjin Kim 40fd358326SDongjin Kim leds { 41fd358326SDongjin Kim compatible = "gpio-leds"; 42fd358326SDongjin Kim 43fd358326SDongjin Kim led_power: led-0 { 44fd358326SDongjin Kim gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; 45fd358326SDongjin Kim function = LED_FUNCTION_POWER; 46fd358326SDongjin Kim color = <LED_COLOR_ID_RED>; 47fd358326SDongjin Kim default-state = "keep"; 48fd358326SDongjin Kim linux,default-trigger = "default-on"; 49fd358326SDongjin Kim pinctrl-names = "default"; 50fd358326SDongjin Kim pinctrl-0 = <&led_power_pin>; 51fd358326SDongjin Kim }; 52fd358326SDongjin Kim led_work: led-1 { 53fd358326SDongjin Kim gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; 54fd358326SDongjin Kim function = LED_FUNCTION_HEARTBEAT; 55fd358326SDongjin Kim color = <LED_COLOR_ID_BLUE>; 56fd358326SDongjin Kim linux,default-trigger = "heartbeat"; 57fd358326SDongjin Kim pinctrl-names = "default"; 58fd358326SDongjin Kim pinctrl-0 = <&led_work_pin>; 59fd358326SDongjin Kim }; 60fd358326SDongjin Kim }; 61fd358326SDongjin Kim 62fd358326SDongjin Kim vcc3v3_sys: vcc3v3-sys-regulator { 63fd358326SDongjin Kim compatible = "regulator-fixed"; 64fd358326SDongjin Kim regulator-name = "vcc3v3_sys"; 65fd358326SDongjin Kim regulator-always-on; 66fd358326SDongjin Kim regulator-boot-on; 67fd358326SDongjin Kim regulator-min-microvolt = <3300000>; 68fd358326SDongjin Kim regulator-max-microvolt = <3300000>; 69fd358326SDongjin Kim vin-supply = <&dc_12v>; 70fd358326SDongjin Kim }; 71fd358326SDongjin Kim}; 72fd358326SDongjin Kim 73fd358326SDongjin Kim&cpu0 { 74fd358326SDongjin Kim cpu-supply = <&vdd_cpu>; 75fd358326SDongjin Kim}; 76fd358326SDongjin Kim 77fd358326SDongjin Kim&cpu1 { 78fd358326SDongjin Kim cpu-supply = <&vdd_cpu>; 79fd358326SDongjin Kim}; 80fd358326SDongjin Kim 81fd358326SDongjin Kim&cpu2 { 82fd358326SDongjin Kim cpu-supply = <&vdd_cpu>; 83fd358326SDongjin Kim}; 84fd358326SDongjin Kim 85fd358326SDongjin Kim&cpu3 { 86fd358326SDongjin Kim cpu-supply = <&vdd_cpu>; 87fd358326SDongjin Kim}; 88fd358326SDongjin Kim 89fd358326SDongjin Kim&gmac0 { 90fd358326SDongjin Kim assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; 91fd358326SDongjin Kim assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; 92fd358326SDongjin Kim assigned-clock-rates = <0>, <125000000>; 93fd358326SDongjin Kim clock_in_out = "output"; 94fd358326SDongjin Kim phy-handle = <&rgmii_phy0>; 95fd358326SDongjin Kim phy-mode = "rgmii"; 96fd358326SDongjin Kim phy-supply = <&vcc3v3_sys>; 97fd358326SDongjin Kim pinctrl-names = "default"; 98fd358326SDongjin Kim pinctrl-0 = <&gmac0_miim 99fd358326SDongjin Kim &gmac0_tx_bus2 100fd358326SDongjin Kim &gmac0_rx_bus2 101fd358326SDongjin Kim &gmac0_rgmii_clk 102fd358326SDongjin Kim &gmac0_rgmii_bus>; 103fd358326SDongjin Kim status = "okay"; 104fd358326SDongjin Kim 105fd358326SDongjin Kim tx_delay = <0x4f>; 106fd358326SDongjin Kim rx_delay = <0x2d>; 107fd358326SDongjin Kim}; 108fd358326SDongjin Kim 109fd358326SDongjin Kim&i2c0 { 110fd358326SDongjin Kim status = "okay"; 111fd358326SDongjin Kim 112fd358326SDongjin Kim vdd_cpu: regulator@1c { 113fd358326SDongjin Kim compatible = "tcs,tcs4525"; 114fd358326SDongjin Kim reg = <0x1c>; 115fd358326SDongjin Kim fcs,suspend-voltage-selector = <1>; 116fd358326SDongjin Kim regulator-name = "vdd_cpu"; 117fd358326SDongjin Kim regulator-always-on; 118fd358326SDongjin Kim regulator-boot-on; 119fd358326SDongjin Kim regulator-min-microvolt = <800000>; 120fd358326SDongjin Kim regulator-max-microvolt = <1150000>; 121fd358326SDongjin Kim regulator-ramp-delay = <2300>; 122fd358326SDongjin Kim vin-supply = <&vcc3v3_sys>; 123fd358326SDongjin Kim 124fd358326SDongjin Kim regulator-state-mem { 125fd358326SDongjin Kim regulator-off-in-suspend; 126fd358326SDongjin Kim }; 127fd358326SDongjin Kim }; 128fd358326SDongjin Kim 129fd358326SDongjin Kim rk809: pmic@20 { 130fd358326SDongjin Kim compatible = "rockchip,rk809"; 131fd358326SDongjin Kim reg = <0x20>; 132fd358326SDongjin Kim interrupt-parent = <&gpio0>; 133fd358326SDongjin Kim interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; 134fd358326SDongjin Kim #clock-cells = <1>; 135fd358326SDongjin Kim pinctrl-names = "default"; 136fd358326SDongjin Kim pinctrl-0 = <&pmic_int_l>; 137fd358326SDongjin Kim rockchip,system-power-controller; 138fd358326SDongjin Kim vcc1-supply = <&vcc3v3_sys>; 139fd358326SDongjin Kim vcc2-supply = <&vcc3v3_sys>; 140fd358326SDongjin Kim vcc3-supply = <&vcc3v3_sys>; 141fd358326SDongjin Kim vcc4-supply = <&vcc3v3_sys>; 142fd358326SDongjin Kim vcc5-supply = <&vcc3v3_sys>; 143fd358326SDongjin Kim vcc6-supply = <&vcc3v3_sys>; 144fd358326SDongjin Kim vcc7-supply = <&vcc3v3_sys>; 145fd358326SDongjin Kim vcc8-supply = <&vcc3v3_sys>; 146fd358326SDongjin Kim vcc9-supply = <&vcc3v3_sys>; 147fd358326SDongjin Kim wakeup-source; 148fd358326SDongjin Kim 149fd358326SDongjin Kim regulators { 150fd358326SDongjin Kim vdd_logic: DCDC_REG1 { 151fd358326SDongjin Kim regulator-name = "vdd_logic"; 152fd358326SDongjin Kim regulator-always-on; 153fd358326SDongjin Kim regulator-boot-on; 154fd358326SDongjin Kim regulator-init-microvolt = <900000>; 155fd358326SDongjin Kim regulator-initial-mode = <0x2>; 156fd358326SDongjin Kim regulator-min-microvolt = <500000>; 157fd358326SDongjin Kim regulator-max-microvolt = <1350000>; 158fd358326SDongjin Kim regulator-ramp-delay = <6001>; 159fd358326SDongjin Kim 160fd358326SDongjin Kim regulator-state-mem { 161fd358326SDongjin Kim regulator-off-in-suspend; 162fd358326SDongjin Kim }; 163fd358326SDongjin Kim }; 164fd358326SDongjin Kim 165fd358326SDongjin Kim vdd_gpu: DCDC_REG2 { 166fd358326SDongjin Kim regulator-name = "vdd_gpu"; 167fd358326SDongjin Kim regulator-always-on; 168fd358326SDongjin Kim regulator-init-microvolt = <900000>; 169fd358326SDongjin Kim regulator-initial-mode = <0x2>; 170fd358326SDongjin Kim regulator-min-microvolt = <500000>; 171fd358326SDongjin Kim regulator-max-microvolt = <1350000>; 172fd358326SDongjin Kim regulator-ramp-delay = <6001>; 173fd358326SDongjin Kim 174fd358326SDongjin Kim regulator-state-mem { 175fd358326SDongjin Kim regulator-off-in-suspend; 176fd358326SDongjin Kim }; 177fd358326SDongjin Kim }; 178fd358326SDongjin Kim 179fd358326SDongjin Kim vcc_ddr: DCDC_REG3 { 180fd358326SDongjin Kim regulator-name = "vcc_ddr"; 181fd358326SDongjin Kim regulator-always-on; 182fd358326SDongjin Kim regulator-boot-on; 183fd358326SDongjin Kim regulator-initial-mode = <0x2>; 184fd358326SDongjin Kim 185fd358326SDongjin Kim regulator-state-mem { 186fd358326SDongjin Kim regulator-on-in-suspend; 187fd358326SDongjin Kim }; 188fd358326SDongjin Kim }; 189fd358326SDongjin Kim 190fd358326SDongjin Kim vdd_npu: DCDC_REG4 { 191fd358326SDongjin Kim regulator-name = "vdd_npu"; 192fd358326SDongjin Kim regulator-init-microvolt = <900000>; 193fd358326SDongjin Kim regulator-initial-mode = <0x2>; 194fd358326SDongjin Kim regulator-min-microvolt = <500000>; 195fd358326SDongjin Kim regulator-max-microvolt = <1350000>; 196fd358326SDongjin Kim regulator-ramp-delay = <6001>; 197fd358326SDongjin Kim 198fd358326SDongjin Kim regulator-state-mem { 199fd358326SDongjin Kim regulator-off-in-suspend; 200fd358326SDongjin Kim }; 201fd358326SDongjin Kim }; 202fd358326SDongjin Kim 203fd358326SDongjin Kim vcc_1v8: DCDC_REG5 { 204fd358326SDongjin Kim regulator-name = "vcc_1v8"; 205fd358326SDongjin Kim regulator-always-on; 206fd358326SDongjin Kim regulator-boot-on; 207fd358326SDongjin Kim regulator-min-microvolt = <1800000>; 208fd358326SDongjin Kim regulator-max-microvolt = <1800000>; 209fd358326SDongjin Kim 210fd358326SDongjin Kim regulator-state-mem { 211fd358326SDongjin Kim regulator-off-in-suspend; 212fd358326SDongjin Kim }; 213fd358326SDongjin Kim }; 214fd358326SDongjin Kim 215fd358326SDongjin Kim vdda0v9_image: LDO_REG1 { 216fd358326SDongjin Kim regulator-name = "vdda0v9_image"; 217fd358326SDongjin Kim regulator-always-on; 218fd358326SDongjin Kim regulator-min-microvolt = <900000>; 219fd358326SDongjin Kim regulator-max-microvolt = <900000>; 220fd358326SDongjin Kim 221fd358326SDongjin Kim regulator-state-mem { 222fd358326SDongjin Kim regulator-off-in-suspend; 223fd358326SDongjin Kim }; 224fd358326SDongjin Kim }; 225fd358326SDongjin Kim 226fd358326SDongjin Kim vdda_0v9: LDO_REG2 { 227fd358326SDongjin Kim regulator-name = "vdda_0v9"; 228fd358326SDongjin Kim regulator-always-on; 229fd358326SDongjin Kim regulator-boot-on; 230fd358326SDongjin Kim regulator-min-microvolt = <900000>; 231fd358326SDongjin Kim regulator-max-microvolt = <900000>; 232fd358326SDongjin Kim 233fd358326SDongjin Kim regulator-state-mem { 234fd358326SDongjin Kim regulator-off-in-suspend; 235fd358326SDongjin Kim }; 236fd358326SDongjin Kim }; 237fd358326SDongjin Kim 238fd358326SDongjin Kim vdda0v9_pmu: LDO_REG3 { 239fd358326SDongjin Kim regulator-name = "vdda0v9_pmu"; 240fd358326SDongjin Kim regulator-always-on; 241fd358326SDongjin Kim regulator-boot-on; 242fd358326SDongjin Kim regulator-min-microvolt = <900000>; 243fd358326SDongjin Kim regulator-max-microvolt = <900000>; 244fd358326SDongjin Kim 245fd358326SDongjin Kim regulator-state-mem { 246fd358326SDongjin Kim regulator-on-in-suspend; 247fd358326SDongjin Kim regulator-suspend-microvolt = <900000>; 248fd358326SDongjin Kim }; 249fd358326SDongjin Kim }; 250fd358326SDongjin Kim 251fd358326SDongjin Kim vccio_acodec: LDO_REG4 { 252fd358326SDongjin Kim regulator-name = "vccio_acodec"; 253fd358326SDongjin Kim regulator-always-on; 254fd358326SDongjin Kim regulator-boot-on; 255fd358326SDongjin Kim regulator-min-microvolt = <3300000>; 256fd358326SDongjin Kim regulator-max-microvolt = <3300000>; 257fd358326SDongjin Kim 258fd358326SDongjin Kim regulator-state-mem { 259fd358326SDongjin Kim regulator-off-in-suspend; 260fd358326SDongjin Kim }; 261fd358326SDongjin Kim }; 262fd358326SDongjin Kim 263fd358326SDongjin Kim vccio_sd: LDO_REG5 { 264fd358326SDongjin Kim regulator-name = "vccio_sd"; 265fd358326SDongjin Kim regulator-min-microvolt = <1800000>; 266fd358326SDongjin Kim regulator-max-microvolt = <3300000>; 267fd358326SDongjin Kim 268fd358326SDongjin Kim regulator-state-mem { 269fd358326SDongjin Kim regulator-off-in-suspend; 270fd358326SDongjin Kim }; 271fd358326SDongjin Kim }; 272fd358326SDongjin Kim 273fd358326SDongjin Kim vcc3v3_pmu: LDO_REG6 { 274fd358326SDongjin Kim regulator-name = "vcc3v3_pmu"; 275fd358326SDongjin Kim regulator-always-on; 276fd358326SDongjin Kim regulator-boot-on; 277fd358326SDongjin Kim regulator-min-microvolt = <3300000>; 278fd358326SDongjin Kim regulator-max-microvolt = <3300000>; 279fd358326SDongjin Kim 280fd358326SDongjin Kim regulator-state-mem { 281fd358326SDongjin Kim regulator-on-in-suspend; 282fd358326SDongjin Kim regulator-suspend-microvolt = <3300000>; 283fd358326SDongjin Kim }; 284fd358326SDongjin Kim }; 285fd358326SDongjin Kim 286fd358326SDongjin Kim vcca_1v8: LDO_REG7 { 287fd358326SDongjin Kim regulator-name = "vcca_1v8"; 288fd358326SDongjin Kim regulator-always-on; 289fd358326SDongjin Kim regulator-boot-on; 290fd358326SDongjin Kim regulator-min-microvolt = <1800000>; 291fd358326SDongjin Kim regulator-max-microvolt = <1800000>; 292fd358326SDongjin Kim 293fd358326SDongjin Kim regulator-state-mem { 294fd358326SDongjin Kim regulator-off-in-suspend; 295fd358326SDongjin Kim }; 296fd358326SDongjin Kim }; 297fd358326SDongjin Kim 298fd358326SDongjin Kim vcca1v8_pmu: LDO_REG8 { 299fd358326SDongjin Kim regulator-name = "vcca1v8_pmu"; 300fd358326SDongjin Kim regulator-always-on; 301fd358326SDongjin Kim regulator-boot-on; 302fd358326SDongjin Kim regulator-min-microvolt = <1800000>; 303fd358326SDongjin Kim regulator-max-microvolt = <1800000>; 304fd358326SDongjin Kim 305fd358326SDongjin Kim regulator-state-mem { 306fd358326SDongjin Kim regulator-on-in-suspend; 307fd358326SDongjin Kim regulator-suspend-microvolt = <1800000>; 308fd358326SDongjin Kim }; 309fd358326SDongjin Kim }; 310fd358326SDongjin Kim 311fd358326SDongjin Kim vcca1v8_image: LDO_REG9 { 312fd358326SDongjin Kim regulator-name = "vcca1v8_image"; 313fd358326SDongjin Kim regulator-always-on; 314fd358326SDongjin Kim regulator-min-microvolt = <1800000>; 315fd358326SDongjin Kim regulator-max-microvolt = <1800000>; 316fd358326SDongjin Kim 317fd358326SDongjin Kim regulator-state-mem { 318fd358326SDongjin Kim regulator-off-in-suspend; 319fd358326SDongjin Kim }; 320fd358326SDongjin Kim }; 321fd358326SDongjin Kim 322fd358326SDongjin Kim vcc_3v3: SWITCH_REG1 { 323fd358326SDongjin Kim regulator-name = "vcc_3v3"; 324fd358326SDongjin Kim regulator-always-on; 325fd358326SDongjin Kim regulator-boot-on; 326fd358326SDongjin Kim 327fd358326SDongjin Kim regulator-state-mem { 328fd358326SDongjin Kim regulator-off-in-suspend; 329fd358326SDongjin Kim }; 330fd358326SDongjin Kim }; 331fd358326SDongjin Kim 332fd358326SDongjin Kim vcc3v3_sd: SWITCH_REG2 { 333fd358326SDongjin Kim regulator-name = "vcc3v3_sd"; 334fd358326SDongjin Kim 335fd358326SDongjin Kim regulator-state-mem { 336fd358326SDongjin Kim regulator-off-in-suspend; 337fd358326SDongjin Kim }; 338fd358326SDongjin Kim }; 339fd358326SDongjin Kim }; 340fd358326SDongjin Kim }; 341fd358326SDongjin Kim}; 342fd358326SDongjin Kim 343fd358326SDongjin Kim&mdio0 { 344fd358326SDongjin Kim rgmii_phy0: ethernet-phy@0 { 345fd358326SDongjin Kim compatible = "ethernet-phy-ieee802.3-c22"; 346fd358326SDongjin Kim reg = <0x0>; 347fd358326SDongjin Kim reset-assert-us = <20000>; 348fd358326SDongjin Kim reset-deassert-us = <100000>; 349fd358326SDongjin Kim reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; 350fd358326SDongjin Kim }; 351fd358326SDongjin Kim}; 352fd358326SDongjin Kim 353fd358326SDongjin Kim&pinctrl { 354*9f96204bSAurelien Jarno fspi { 355*9f96204bSAurelien Jarno fspi_dual_io_pins: fspi-dual-io-pins { 356*9f96204bSAurelien Jarno rockchip,pins = 357*9f96204bSAurelien Jarno /* fspi_clk */ 358*9f96204bSAurelien Jarno <1 RK_PD0 1 &pcfg_pull_none>, 359*9f96204bSAurelien Jarno /* fspi_cs0n */ 360*9f96204bSAurelien Jarno <1 RK_PD3 1 &pcfg_pull_none>, 361*9f96204bSAurelien Jarno /* fspi_d0 */ 362*9f96204bSAurelien Jarno <1 RK_PD1 1 &pcfg_pull_none>, 363*9f96204bSAurelien Jarno /* fspi_d1 */ 364*9f96204bSAurelien Jarno <1 RK_PD2 1 &pcfg_pull_none>; 365*9f96204bSAurelien Jarno }; 366*9f96204bSAurelien Jarno }; 367*9f96204bSAurelien Jarno 368fd358326SDongjin Kim leds { 369fd358326SDongjin Kim led_power_pin: led-power-pin { 370fd358326SDongjin Kim rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 371fd358326SDongjin Kim }; 372fd358326SDongjin Kim led_work_pin: led-work-pin { 373fd358326SDongjin Kim rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; 374fd358326SDongjin Kim }; 375fd358326SDongjin Kim }; 376fd358326SDongjin Kim 377fd358326SDongjin Kim pmic { 378fd358326SDongjin Kim pmic_int_l: pmic-int-l { 379fd358326SDongjin Kim rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; 380fd358326SDongjin Kim }; 381fd358326SDongjin Kim }; 382fd358326SDongjin Kim}; 383fd358326SDongjin Kim 384fd358326SDongjin Kim&pmu_io_domains { 385fd358326SDongjin Kim pmuio1-supply = <&vcc3v3_pmu>; 386fd358326SDongjin Kim pmuio2-supply = <&vcc3v3_pmu>; 387fd358326SDongjin Kim vccio1-supply = <&vccio_acodec>; 388fd358326SDongjin Kim vccio2-supply = <&vcc_1v8>; 389fd358326SDongjin Kim vccio3-supply = <&vccio_sd>; 390fd358326SDongjin Kim vccio4-supply = <&vcc_1v8>; 391fd358326SDongjin Kim vccio5-supply = <&vcc_3v3>; 392fd358326SDongjin Kim vccio6-supply = <&vcc_3v3>; 393fd358326SDongjin Kim vccio7-supply = <&vcc_3v3>; 394fd358326SDongjin Kim status = "okay"; 395fd358326SDongjin Kim}; 396fd358326SDongjin Kim 397fd358326SDongjin Kim&saradc { 398fd358326SDongjin Kim vref-supply = <&vcca_1v8>; 399fd358326SDongjin Kim status = "okay"; 400fd358326SDongjin Kim}; 401fd358326SDongjin Kim 402fd358326SDongjin Kim&sdhci { 403fd358326SDongjin Kim bus-width = <8>; 404fd358326SDongjin Kim max-frequency = <200000000>; 405fd358326SDongjin Kim non-removable; 406fd358326SDongjin Kim pinctrl-names = "default"; 407fd358326SDongjin Kim pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>; 408fd358326SDongjin Kim vmmc-supply = <&vcc_3v3>; 409fd358326SDongjin Kim vqmmc-supply = <&vcc_1v8>; 410fd358326SDongjin Kim status = "okay"; 411fd358326SDongjin Kim}; 412fd358326SDongjin Kim 413fd358326SDongjin Kim&sdmmc0 { 414fd358326SDongjin Kim bus-width = <4>; 415fd358326SDongjin Kim cap-sd-highspeed; 416fd358326SDongjin Kim cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; 417fd358326SDongjin Kim disable-wp; 418fd358326SDongjin Kim pinctrl-names = "default"; 419fd358326SDongjin Kim pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; 420fd358326SDongjin Kim sd-uhs-sdr50; 421fd358326SDongjin Kim vmmc-supply = <&vcc3v3_sd>; 422fd358326SDongjin Kim vqmmc-supply = <&vccio_sd>; 423fd358326SDongjin Kim status = "okay"; 424fd358326SDongjin Kim}; 425fd358326SDongjin Kim 426*9f96204bSAurelien Jarno&sfc { 427*9f96204bSAurelien Jarno /* Dual I/O mode as the D2 pin conflicts with the eMMC */ 428*9f96204bSAurelien Jarno pinctrl-0 = <&fspi_dual_io_pins>; 429*9f96204bSAurelien Jarno pinctrl-names = "default"; 430*9f96204bSAurelien Jarno #address-cells = <1>; 431*9f96204bSAurelien Jarno #size-cells = <0>; 432*9f96204bSAurelien Jarno status = "okay"; 433*9f96204bSAurelien Jarno 434*9f96204bSAurelien Jarno flash@0 { 435*9f96204bSAurelien Jarno compatible = "jedec,spi-nor"; 436*9f96204bSAurelien Jarno reg = <0>; 437*9f96204bSAurelien Jarno spi-max-frequency = <100000000>; 438*9f96204bSAurelien Jarno spi-rx-bus-width = <2>; 439*9f96204bSAurelien Jarno spi-tx-bus-width = <1>; 440*9f96204bSAurelien Jarno 441*9f96204bSAurelien Jarno partitions { 442*9f96204bSAurelien Jarno compatible = "fixed-partitions"; 443*9f96204bSAurelien Jarno #address-cells = <1>; 444*9f96204bSAurelien Jarno #size-cells = <1>; 445*9f96204bSAurelien Jarno 446*9f96204bSAurelien Jarno partition@0 { 447*9f96204bSAurelien Jarno label = "SPL"; 448*9f96204bSAurelien Jarno reg = <0x0 0xe0000>; 449*9f96204bSAurelien Jarno }; 450*9f96204bSAurelien Jarno partition@e0000 { 451*9f96204bSAurelien Jarno label = "U-Boot Env"; 452*9f96204bSAurelien Jarno reg = <0xe0000 0x20000>; 453*9f96204bSAurelien Jarno }; 454*9f96204bSAurelien Jarno partition@100000 { 455*9f96204bSAurelien Jarno label = "U-Boot"; 456*9f96204bSAurelien Jarno reg = <0x100000 0x200000>; 457*9f96204bSAurelien Jarno }; 458*9f96204bSAurelien Jarno partition@300000 { 459*9f96204bSAurelien Jarno label = "splash"; 460*9f96204bSAurelien Jarno reg = <0x300000 0x100000>; 461*9f96204bSAurelien Jarno }; 462*9f96204bSAurelien Jarno partition@400000 { 463*9f96204bSAurelien Jarno label = "Filesystem"; 464*9f96204bSAurelien Jarno reg = <0x400000 0xc00000>; 465*9f96204bSAurelien Jarno }; 466*9f96204bSAurelien Jarno }; 467*9f96204bSAurelien Jarno }; 468*9f96204bSAurelien Jarno}; 469*9f96204bSAurelien Jarno 470f5511bd8SAurelien Jarno&tsadc { 471f5511bd8SAurelien Jarno rockchip,hw-tshut-mode = <1>; 472f5511bd8SAurelien Jarno rockchip,hw-tshut-polarity = <0>; 473f5511bd8SAurelien Jarno status = "okay"; 474f5511bd8SAurelien Jarno}; 475f5511bd8SAurelien Jarno 476fd358326SDongjin Kim&uart2 { 477fd358326SDongjin Kim status = "okay"; 478fd358326SDongjin Kim}; 479