1fd358326SDongjin Kim// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2fd358326SDongjin Kim/* 3fd358326SDongjin Kim * Copyright (c) 2022 Hardkernel Co., Ltd. 4fd358326SDongjin Kim * 5fd358326SDongjin Kim */ 6fd358326SDongjin Kim 7fd358326SDongjin Kim/dts-v1/; 8fd358326SDongjin Kim#include <dt-bindings/gpio/gpio.h> 9fd358326SDongjin Kim#include <dt-bindings/leds/common.h> 10fd358326SDongjin Kim#include <dt-bindings/pinctrl/rockchip.h> 11*913404aaSAurelien Jarno#include <dt-bindings/soc/rockchip,vop2.h> 12fd358326SDongjin Kim#include "rk3568.dtsi" 13fd358326SDongjin Kim 14fd358326SDongjin Kim/ { 15fd358326SDongjin Kim model = "Hardkernel ODROID-M1"; 16fd358326SDongjin Kim compatible = "rockchip,rk3568-odroid-m1", "rockchip,rk3568"; 17fd358326SDongjin Kim 18fd358326SDongjin Kim aliases { 19fd358326SDongjin Kim ethernet0 = &gmac0; 20fd358326SDongjin Kim i2c0 = &i2c3; 21fd358326SDongjin Kim i2c3 = &i2c0; 22fd358326SDongjin Kim mmc0 = &sdhci; 23fd358326SDongjin Kim mmc1 = &sdmmc0; 24fd358326SDongjin Kim serial0 = &uart1; 25fd358326SDongjin Kim serial1 = &uart0; 26fd358326SDongjin Kim }; 27fd358326SDongjin Kim 28fd358326SDongjin Kim chosen { 29fd358326SDongjin Kim stdout-path = "serial2:1500000n8"; 30fd358326SDongjin Kim }; 31fd358326SDongjin Kim 32fd358326SDongjin Kim dc_12v: dc-12v-regulator { 33fd358326SDongjin Kim compatible = "regulator-fixed"; 34fd358326SDongjin Kim regulator-name = "dc_12v"; 35fd358326SDongjin Kim regulator-always-on; 36fd358326SDongjin Kim regulator-boot-on; 37fd358326SDongjin Kim regulator-min-microvolt = <12000000>; 38fd358326SDongjin Kim regulator-max-microvolt = <12000000>; 39fd358326SDongjin Kim }; 40fd358326SDongjin Kim 41*913404aaSAurelien Jarno hdmi-con { 42*913404aaSAurelien Jarno compatible = "hdmi-connector"; 43*913404aaSAurelien Jarno type = "a"; 44*913404aaSAurelien Jarno 45*913404aaSAurelien Jarno port { 46*913404aaSAurelien Jarno hdmi_con_in: endpoint { 47*913404aaSAurelien Jarno remote-endpoint = <&hdmi_out_con>; 48*913404aaSAurelien Jarno }; 49*913404aaSAurelien Jarno }; 50*913404aaSAurelien Jarno }; 51*913404aaSAurelien Jarno 52fd358326SDongjin Kim leds { 53fd358326SDongjin Kim compatible = "gpio-leds"; 54fd358326SDongjin Kim 55fd358326SDongjin Kim led_power: led-0 { 56fd358326SDongjin Kim gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; 57fd358326SDongjin Kim function = LED_FUNCTION_POWER; 58fd358326SDongjin Kim color = <LED_COLOR_ID_RED>; 59fd358326SDongjin Kim default-state = "keep"; 60fd358326SDongjin Kim linux,default-trigger = "default-on"; 61fd358326SDongjin Kim pinctrl-names = "default"; 62fd358326SDongjin Kim pinctrl-0 = <&led_power_pin>; 63fd358326SDongjin Kim }; 64fd358326SDongjin Kim led_work: led-1 { 65fd358326SDongjin Kim gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; 66fd358326SDongjin Kim function = LED_FUNCTION_HEARTBEAT; 67fd358326SDongjin Kim color = <LED_COLOR_ID_BLUE>; 68fd358326SDongjin Kim linux,default-trigger = "heartbeat"; 69fd358326SDongjin Kim pinctrl-names = "default"; 70fd358326SDongjin Kim pinctrl-0 = <&led_work_pin>; 71fd358326SDongjin Kim }; 72fd358326SDongjin Kim }; 73fd358326SDongjin Kim 7478f85844SAurelien Jarno rk809-sound { 7578f85844SAurelien Jarno compatible = "simple-audio-card"; 7678f85844SAurelien Jarno pinctrl-names = "default"; 7778f85844SAurelien Jarno pinctrl-0 = <&hp_det_pin>; 7878f85844SAurelien Jarno simple-audio-card,name = "Analog RK817"; 7978f85844SAurelien Jarno simple-audio-card,format = "i2s"; 8078f85844SAurelien Jarno simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; 8178f85844SAurelien Jarno simple-audio-card,mclk-fs = <256>; 8278f85844SAurelien Jarno simple-audio-card,widgets = 8378f85844SAurelien Jarno "Headphone", "Headphones", 8478f85844SAurelien Jarno "Speaker", "Speaker"; 8578f85844SAurelien Jarno simple-audio-card,routing = 8678f85844SAurelien Jarno "Headphones", "HPOL", 8778f85844SAurelien Jarno "Headphones", "HPOR", 8878f85844SAurelien Jarno "Speaker", "SPKO"; 8978f85844SAurelien Jarno 9078f85844SAurelien Jarno simple-audio-card,cpu { 9178f85844SAurelien Jarno sound-dai = <&i2s1_8ch>; 9278f85844SAurelien Jarno }; 9378f85844SAurelien Jarno 9478f85844SAurelien Jarno simple-audio-card,codec { 9578f85844SAurelien Jarno sound-dai = <&rk809>; 9678f85844SAurelien Jarno }; 9778f85844SAurelien Jarno }; 9878f85844SAurelien Jarno 99fd358326SDongjin Kim vcc3v3_sys: vcc3v3-sys-regulator { 100fd358326SDongjin Kim compatible = "regulator-fixed"; 101fd358326SDongjin Kim regulator-name = "vcc3v3_sys"; 102fd358326SDongjin Kim regulator-always-on; 103fd358326SDongjin Kim regulator-boot-on; 104fd358326SDongjin Kim regulator-min-microvolt = <3300000>; 105fd358326SDongjin Kim regulator-max-microvolt = <3300000>; 106fd358326SDongjin Kim vin-supply = <&dc_12v>; 107fd358326SDongjin Kim }; 108fd358326SDongjin Kim}; 109fd358326SDongjin Kim 110fd358326SDongjin Kim&cpu0 { 111fd358326SDongjin Kim cpu-supply = <&vdd_cpu>; 112fd358326SDongjin Kim}; 113fd358326SDongjin Kim 114fd358326SDongjin Kim&cpu1 { 115fd358326SDongjin Kim cpu-supply = <&vdd_cpu>; 116fd358326SDongjin Kim}; 117fd358326SDongjin Kim 118fd358326SDongjin Kim&cpu2 { 119fd358326SDongjin Kim cpu-supply = <&vdd_cpu>; 120fd358326SDongjin Kim}; 121fd358326SDongjin Kim 122fd358326SDongjin Kim&cpu3 { 123fd358326SDongjin Kim cpu-supply = <&vdd_cpu>; 124fd358326SDongjin Kim}; 125fd358326SDongjin Kim 126fd358326SDongjin Kim&gmac0 { 127fd358326SDongjin Kim assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; 128fd358326SDongjin Kim assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; 129fd358326SDongjin Kim assigned-clock-rates = <0>, <125000000>; 130fd358326SDongjin Kim clock_in_out = "output"; 131fd358326SDongjin Kim phy-handle = <&rgmii_phy0>; 132fd358326SDongjin Kim phy-mode = "rgmii"; 133fd358326SDongjin Kim phy-supply = <&vcc3v3_sys>; 134fd358326SDongjin Kim pinctrl-names = "default"; 135fd358326SDongjin Kim pinctrl-0 = <&gmac0_miim 136fd358326SDongjin Kim &gmac0_tx_bus2 137fd358326SDongjin Kim &gmac0_rx_bus2 138fd358326SDongjin Kim &gmac0_rgmii_clk 139fd358326SDongjin Kim &gmac0_rgmii_bus>; 140fd358326SDongjin Kim status = "okay"; 141fd358326SDongjin Kim 142fd358326SDongjin Kim tx_delay = <0x4f>; 143fd358326SDongjin Kim rx_delay = <0x2d>; 144fd358326SDongjin Kim}; 145fd358326SDongjin Kim 146*913404aaSAurelien Jarno&hdmi { 147*913404aaSAurelien Jarno avdd-0v9-supply = <&vdda0v9_image>; 148*913404aaSAurelien Jarno avdd-1v8-supply = <&vcca1v8_image>; 149*913404aaSAurelien Jarno status = "okay"; 150*913404aaSAurelien Jarno}; 151*913404aaSAurelien Jarno 152*913404aaSAurelien Jarno&hdmi_in { 153*913404aaSAurelien Jarno hdmi_in_vp0: endpoint { 154*913404aaSAurelien Jarno remote-endpoint = <&vp0_out_hdmi>; 155*913404aaSAurelien Jarno }; 156*913404aaSAurelien Jarno}; 157*913404aaSAurelien Jarno 158*913404aaSAurelien Jarno&hdmi_out { 159*913404aaSAurelien Jarno hdmi_out_con: endpoint { 160*913404aaSAurelien Jarno remote-endpoint = <&hdmi_con_in>; 161*913404aaSAurelien Jarno }; 162*913404aaSAurelien Jarno}; 163*913404aaSAurelien Jarno 164fd358326SDongjin Kim&i2c0 { 165fd358326SDongjin Kim status = "okay"; 166fd358326SDongjin Kim 167fd358326SDongjin Kim vdd_cpu: regulator@1c { 168fd358326SDongjin Kim compatible = "tcs,tcs4525"; 169fd358326SDongjin Kim reg = <0x1c>; 170fd358326SDongjin Kim fcs,suspend-voltage-selector = <1>; 171fd358326SDongjin Kim regulator-name = "vdd_cpu"; 172fd358326SDongjin Kim regulator-always-on; 173fd358326SDongjin Kim regulator-boot-on; 174fd358326SDongjin Kim regulator-min-microvolt = <800000>; 175fd358326SDongjin Kim regulator-max-microvolt = <1150000>; 176fd358326SDongjin Kim regulator-ramp-delay = <2300>; 177fd358326SDongjin Kim vin-supply = <&vcc3v3_sys>; 178fd358326SDongjin Kim 179fd358326SDongjin Kim regulator-state-mem { 180fd358326SDongjin Kim regulator-off-in-suspend; 181fd358326SDongjin Kim }; 182fd358326SDongjin Kim }; 183fd358326SDongjin Kim 184fd358326SDongjin Kim rk809: pmic@20 { 185fd358326SDongjin Kim compatible = "rockchip,rk809"; 186fd358326SDongjin Kim reg = <0x20>; 187fd358326SDongjin Kim interrupt-parent = <&gpio0>; 188fd358326SDongjin Kim interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; 18978f85844SAurelien Jarno assigned-clocks = <&cru I2S1_MCLKOUT_TX>; 19078f85844SAurelien Jarno assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; 191fd358326SDongjin Kim #clock-cells = <1>; 19278f85844SAurelien Jarno clock-names = "mclk"; 19378f85844SAurelien Jarno clocks = <&cru I2S1_MCLKOUT_TX>; 194fd358326SDongjin Kim pinctrl-names = "default"; 19578f85844SAurelien Jarno pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; 196fd358326SDongjin Kim rockchip,system-power-controller; 19778f85844SAurelien Jarno #sound-dai-cells = <0>; 198fd358326SDongjin Kim vcc1-supply = <&vcc3v3_sys>; 199fd358326SDongjin Kim vcc2-supply = <&vcc3v3_sys>; 200fd358326SDongjin Kim vcc3-supply = <&vcc3v3_sys>; 201fd358326SDongjin Kim vcc4-supply = <&vcc3v3_sys>; 202fd358326SDongjin Kim vcc5-supply = <&vcc3v3_sys>; 203fd358326SDongjin Kim vcc6-supply = <&vcc3v3_sys>; 204fd358326SDongjin Kim vcc7-supply = <&vcc3v3_sys>; 205fd358326SDongjin Kim vcc8-supply = <&vcc3v3_sys>; 206fd358326SDongjin Kim vcc9-supply = <&vcc3v3_sys>; 207fd358326SDongjin Kim wakeup-source; 208fd358326SDongjin Kim 209fd358326SDongjin Kim regulators { 210fd358326SDongjin Kim vdd_logic: DCDC_REG1 { 211fd358326SDongjin Kim regulator-name = "vdd_logic"; 212fd358326SDongjin Kim regulator-always-on; 213fd358326SDongjin Kim regulator-boot-on; 214fd358326SDongjin Kim regulator-init-microvolt = <900000>; 215fd358326SDongjin Kim regulator-initial-mode = <0x2>; 216fd358326SDongjin Kim regulator-min-microvolt = <500000>; 217fd358326SDongjin Kim regulator-max-microvolt = <1350000>; 218fd358326SDongjin Kim regulator-ramp-delay = <6001>; 219fd358326SDongjin Kim 220fd358326SDongjin Kim regulator-state-mem { 221fd358326SDongjin Kim regulator-off-in-suspend; 222fd358326SDongjin Kim }; 223fd358326SDongjin Kim }; 224fd358326SDongjin Kim 225fd358326SDongjin Kim vdd_gpu: DCDC_REG2 { 226fd358326SDongjin Kim regulator-name = "vdd_gpu"; 227fd358326SDongjin Kim regulator-always-on; 228fd358326SDongjin Kim regulator-init-microvolt = <900000>; 229fd358326SDongjin Kim regulator-initial-mode = <0x2>; 230fd358326SDongjin Kim regulator-min-microvolt = <500000>; 231fd358326SDongjin Kim regulator-max-microvolt = <1350000>; 232fd358326SDongjin Kim regulator-ramp-delay = <6001>; 233fd358326SDongjin Kim 234fd358326SDongjin Kim regulator-state-mem { 235fd358326SDongjin Kim regulator-off-in-suspend; 236fd358326SDongjin Kim }; 237fd358326SDongjin Kim }; 238fd358326SDongjin Kim 239fd358326SDongjin Kim vcc_ddr: DCDC_REG3 { 240fd358326SDongjin Kim regulator-name = "vcc_ddr"; 241fd358326SDongjin Kim regulator-always-on; 242fd358326SDongjin Kim regulator-boot-on; 243fd358326SDongjin Kim regulator-initial-mode = <0x2>; 244fd358326SDongjin Kim 245fd358326SDongjin Kim regulator-state-mem { 246fd358326SDongjin Kim regulator-on-in-suspend; 247fd358326SDongjin Kim }; 248fd358326SDongjin Kim }; 249fd358326SDongjin Kim 250fd358326SDongjin Kim vdd_npu: DCDC_REG4 { 251fd358326SDongjin Kim regulator-name = "vdd_npu"; 252fd358326SDongjin Kim regulator-init-microvolt = <900000>; 253fd358326SDongjin Kim regulator-initial-mode = <0x2>; 254fd358326SDongjin Kim regulator-min-microvolt = <500000>; 255fd358326SDongjin Kim regulator-max-microvolt = <1350000>; 256fd358326SDongjin Kim regulator-ramp-delay = <6001>; 257fd358326SDongjin Kim 258fd358326SDongjin Kim regulator-state-mem { 259fd358326SDongjin Kim regulator-off-in-suspend; 260fd358326SDongjin Kim }; 261fd358326SDongjin Kim }; 262fd358326SDongjin Kim 263fd358326SDongjin Kim vcc_1v8: DCDC_REG5 { 264fd358326SDongjin Kim regulator-name = "vcc_1v8"; 265fd358326SDongjin Kim regulator-always-on; 266fd358326SDongjin Kim regulator-boot-on; 267fd358326SDongjin Kim regulator-min-microvolt = <1800000>; 268fd358326SDongjin Kim regulator-max-microvolt = <1800000>; 269fd358326SDongjin Kim 270fd358326SDongjin Kim regulator-state-mem { 271fd358326SDongjin Kim regulator-off-in-suspend; 272fd358326SDongjin Kim }; 273fd358326SDongjin Kim }; 274fd358326SDongjin Kim 275fd358326SDongjin Kim vdda0v9_image: LDO_REG1 { 276fd358326SDongjin Kim regulator-name = "vdda0v9_image"; 277fd358326SDongjin Kim regulator-always-on; 278fd358326SDongjin Kim regulator-min-microvolt = <900000>; 279fd358326SDongjin Kim regulator-max-microvolt = <900000>; 280fd358326SDongjin Kim 281fd358326SDongjin Kim regulator-state-mem { 282fd358326SDongjin Kim regulator-off-in-suspend; 283fd358326SDongjin Kim }; 284fd358326SDongjin Kim }; 285fd358326SDongjin Kim 286fd358326SDongjin Kim vdda_0v9: LDO_REG2 { 287fd358326SDongjin Kim regulator-name = "vdda_0v9"; 288fd358326SDongjin Kim regulator-always-on; 289fd358326SDongjin Kim regulator-boot-on; 290fd358326SDongjin Kim regulator-min-microvolt = <900000>; 291fd358326SDongjin Kim regulator-max-microvolt = <900000>; 292fd358326SDongjin Kim 293fd358326SDongjin Kim regulator-state-mem { 294fd358326SDongjin Kim regulator-off-in-suspend; 295fd358326SDongjin Kim }; 296fd358326SDongjin Kim }; 297fd358326SDongjin Kim 298fd358326SDongjin Kim vdda0v9_pmu: LDO_REG3 { 299fd358326SDongjin Kim regulator-name = "vdda0v9_pmu"; 300fd358326SDongjin Kim regulator-always-on; 301fd358326SDongjin Kim regulator-boot-on; 302fd358326SDongjin Kim regulator-min-microvolt = <900000>; 303fd358326SDongjin Kim regulator-max-microvolt = <900000>; 304fd358326SDongjin Kim 305fd358326SDongjin Kim regulator-state-mem { 306fd358326SDongjin Kim regulator-on-in-suspend; 307fd358326SDongjin Kim regulator-suspend-microvolt = <900000>; 308fd358326SDongjin Kim }; 309fd358326SDongjin Kim }; 310fd358326SDongjin Kim 311fd358326SDongjin Kim vccio_acodec: LDO_REG4 { 312fd358326SDongjin Kim regulator-name = "vccio_acodec"; 313fd358326SDongjin Kim regulator-always-on; 314fd358326SDongjin Kim regulator-boot-on; 315fd358326SDongjin Kim regulator-min-microvolt = <3300000>; 316fd358326SDongjin Kim regulator-max-microvolt = <3300000>; 317fd358326SDongjin Kim 318fd358326SDongjin Kim regulator-state-mem { 319fd358326SDongjin Kim regulator-off-in-suspend; 320fd358326SDongjin Kim }; 321fd358326SDongjin Kim }; 322fd358326SDongjin Kim 323fd358326SDongjin Kim vccio_sd: LDO_REG5 { 324fd358326SDongjin Kim regulator-name = "vccio_sd"; 325fd358326SDongjin Kim regulator-min-microvolt = <1800000>; 326fd358326SDongjin Kim regulator-max-microvolt = <3300000>; 327fd358326SDongjin Kim 328fd358326SDongjin Kim regulator-state-mem { 329fd358326SDongjin Kim regulator-off-in-suspend; 330fd358326SDongjin Kim }; 331fd358326SDongjin Kim }; 332fd358326SDongjin Kim 333fd358326SDongjin Kim vcc3v3_pmu: LDO_REG6 { 334fd358326SDongjin Kim regulator-name = "vcc3v3_pmu"; 335fd358326SDongjin Kim regulator-always-on; 336fd358326SDongjin Kim regulator-boot-on; 337fd358326SDongjin Kim regulator-min-microvolt = <3300000>; 338fd358326SDongjin Kim regulator-max-microvolt = <3300000>; 339fd358326SDongjin Kim 340fd358326SDongjin Kim regulator-state-mem { 341fd358326SDongjin Kim regulator-on-in-suspend; 342fd358326SDongjin Kim regulator-suspend-microvolt = <3300000>; 343fd358326SDongjin Kim }; 344fd358326SDongjin Kim }; 345fd358326SDongjin Kim 346fd358326SDongjin Kim vcca_1v8: LDO_REG7 { 347fd358326SDongjin Kim regulator-name = "vcca_1v8"; 348fd358326SDongjin Kim regulator-always-on; 349fd358326SDongjin Kim regulator-boot-on; 350fd358326SDongjin Kim regulator-min-microvolt = <1800000>; 351fd358326SDongjin Kim regulator-max-microvolt = <1800000>; 352fd358326SDongjin Kim 353fd358326SDongjin Kim regulator-state-mem { 354fd358326SDongjin Kim regulator-off-in-suspend; 355fd358326SDongjin Kim }; 356fd358326SDongjin Kim }; 357fd358326SDongjin Kim 358fd358326SDongjin Kim vcca1v8_pmu: LDO_REG8 { 359fd358326SDongjin Kim regulator-name = "vcca1v8_pmu"; 360fd358326SDongjin Kim regulator-always-on; 361fd358326SDongjin Kim regulator-boot-on; 362fd358326SDongjin Kim regulator-min-microvolt = <1800000>; 363fd358326SDongjin Kim regulator-max-microvolt = <1800000>; 364fd358326SDongjin Kim 365fd358326SDongjin Kim regulator-state-mem { 366fd358326SDongjin Kim regulator-on-in-suspend; 367fd358326SDongjin Kim regulator-suspend-microvolt = <1800000>; 368fd358326SDongjin Kim }; 369fd358326SDongjin Kim }; 370fd358326SDongjin Kim 371fd358326SDongjin Kim vcca1v8_image: LDO_REG9 { 372fd358326SDongjin Kim regulator-name = "vcca1v8_image"; 373fd358326SDongjin Kim regulator-always-on; 374fd358326SDongjin Kim regulator-min-microvolt = <1800000>; 375fd358326SDongjin Kim regulator-max-microvolt = <1800000>; 376fd358326SDongjin Kim 377fd358326SDongjin Kim regulator-state-mem { 378fd358326SDongjin Kim regulator-off-in-suspend; 379fd358326SDongjin Kim }; 380fd358326SDongjin Kim }; 381fd358326SDongjin Kim 382fd358326SDongjin Kim vcc_3v3: SWITCH_REG1 { 383fd358326SDongjin Kim regulator-name = "vcc_3v3"; 384fd358326SDongjin Kim regulator-always-on; 385fd358326SDongjin Kim regulator-boot-on; 386fd358326SDongjin Kim 387fd358326SDongjin Kim regulator-state-mem { 388fd358326SDongjin Kim regulator-off-in-suspend; 389fd358326SDongjin Kim }; 390fd358326SDongjin Kim }; 391fd358326SDongjin Kim 392fd358326SDongjin Kim vcc3v3_sd: SWITCH_REG2 { 393fd358326SDongjin Kim regulator-name = "vcc3v3_sd"; 394fd358326SDongjin Kim 395fd358326SDongjin Kim regulator-state-mem { 396fd358326SDongjin Kim regulator-off-in-suspend; 397fd358326SDongjin Kim }; 398fd358326SDongjin Kim }; 399fd358326SDongjin Kim }; 400fd358326SDongjin Kim }; 401fd358326SDongjin Kim}; 402fd358326SDongjin Kim 40378f85844SAurelien Jarno&i2s1_8ch { 40478f85844SAurelien Jarno rockchip,trcm-sync-tx-only; 40578f85844SAurelien Jarno status = "okay"; 40678f85844SAurelien Jarno}; 40778f85844SAurelien Jarno 408fd358326SDongjin Kim&mdio0 { 409fd358326SDongjin Kim rgmii_phy0: ethernet-phy@0 { 410fd358326SDongjin Kim compatible = "ethernet-phy-ieee802.3-c22"; 411fd358326SDongjin Kim reg = <0x0>; 412fd358326SDongjin Kim reset-assert-us = <20000>; 413fd358326SDongjin Kim reset-deassert-us = <100000>; 414fd358326SDongjin Kim reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; 415fd358326SDongjin Kim }; 416fd358326SDongjin Kim}; 417fd358326SDongjin Kim 418fd358326SDongjin Kim&pinctrl { 4199f96204bSAurelien Jarno fspi { 4209f96204bSAurelien Jarno fspi_dual_io_pins: fspi-dual-io-pins { 4219f96204bSAurelien Jarno rockchip,pins = 4229f96204bSAurelien Jarno /* fspi_clk */ 4239f96204bSAurelien Jarno <1 RK_PD0 1 &pcfg_pull_none>, 4249f96204bSAurelien Jarno /* fspi_cs0n */ 4259f96204bSAurelien Jarno <1 RK_PD3 1 &pcfg_pull_none>, 4269f96204bSAurelien Jarno /* fspi_d0 */ 4279f96204bSAurelien Jarno <1 RK_PD1 1 &pcfg_pull_none>, 4289f96204bSAurelien Jarno /* fspi_d1 */ 4299f96204bSAurelien Jarno <1 RK_PD2 1 &pcfg_pull_none>; 4309f96204bSAurelien Jarno }; 4319f96204bSAurelien Jarno }; 4329f96204bSAurelien Jarno 433fd358326SDongjin Kim leds { 434fd358326SDongjin Kim led_power_pin: led-power-pin { 435fd358326SDongjin Kim rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 436fd358326SDongjin Kim }; 437fd358326SDongjin Kim led_work_pin: led-work-pin { 438fd358326SDongjin Kim rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; 439fd358326SDongjin Kim }; 440fd358326SDongjin Kim }; 441fd358326SDongjin Kim 442fd358326SDongjin Kim pmic { 443fd358326SDongjin Kim pmic_int_l: pmic-int-l { 444fd358326SDongjin Kim rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; 445fd358326SDongjin Kim }; 446fd358326SDongjin Kim }; 44778f85844SAurelien Jarno 44878f85844SAurelien Jarno rk809 { 44978f85844SAurelien Jarno hp_det_pin: hp-det-pin { 45078f85844SAurelien Jarno rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 45178f85844SAurelien Jarno }; 45278f85844SAurelien Jarno }; 453fd358326SDongjin Kim}; 454fd358326SDongjin Kim 455fd358326SDongjin Kim&pmu_io_domains { 456fd358326SDongjin Kim pmuio1-supply = <&vcc3v3_pmu>; 457fd358326SDongjin Kim pmuio2-supply = <&vcc3v3_pmu>; 458fd358326SDongjin Kim vccio1-supply = <&vccio_acodec>; 459fd358326SDongjin Kim vccio2-supply = <&vcc_1v8>; 460fd358326SDongjin Kim vccio3-supply = <&vccio_sd>; 461fd358326SDongjin Kim vccio4-supply = <&vcc_1v8>; 462fd358326SDongjin Kim vccio5-supply = <&vcc_3v3>; 463fd358326SDongjin Kim vccio6-supply = <&vcc_3v3>; 464fd358326SDongjin Kim vccio7-supply = <&vcc_3v3>; 465fd358326SDongjin Kim status = "okay"; 466fd358326SDongjin Kim}; 467fd358326SDongjin Kim 468fd358326SDongjin Kim&saradc { 469fd358326SDongjin Kim vref-supply = <&vcca_1v8>; 470fd358326SDongjin Kim status = "okay"; 471fd358326SDongjin Kim}; 472fd358326SDongjin Kim 473fd358326SDongjin Kim&sdhci { 474fd358326SDongjin Kim bus-width = <8>; 475fd358326SDongjin Kim max-frequency = <200000000>; 476fd358326SDongjin Kim non-removable; 477fd358326SDongjin Kim pinctrl-names = "default"; 478fd358326SDongjin Kim pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>; 479fd358326SDongjin Kim vmmc-supply = <&vcc_3v3>; 480fd358326SDongjin Kim vqmmc-supply = <&vcc_1v8>; 481fd358326SDongjin Kim status = "okay"; 482fd358326SDongjin Kim}; 483fd358326SDongjin Kim 484fd358326SDongjin Kim&sdmmc0 { 485fd358326SDongjin Kim bus-width = <4>; 486fd358326SDongjin Kim cap-sd-highspeed; 487fd358326SDongjin Kim cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; 488fd358326SDongjin Kim disable-wp; 489fd358326SDongjin Kim pinctrl-names = "default"; 490fd358326SDongjin Kim pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; 491fd358326SDongjin Kim sd-uhs-sdr50; 492fd358326SDongjin Kim vmmc-supply = <&vcc3v3_sd>; 493fd358326SDongjin Kim vqmmc-supply = <&vccio_sd>; 494fd358326SDongjin Kim status = "okay"; 495fd358326SDongjin Kim}; 496fd358326SDongjin Kim 4979f96204bSAurelien Jarno&sfc { 4989f96204bSAurelien Jarno /* Dual I/O mode as the D2 pin conflicts with the eMMC */ 4999f96204bSAurelien Jarno pinctrl-0 = <&fspi_dual_io_pins>; 5009f96204bSAurelien Jarno pinctrl-names = "default"; 5019f96204bSAurelien Jarno #address-cells = <1>; 5029f96204bSAurelien Jarno #size-cells = <0>; 5039f96204bSAurelien Jarno status = "okay"; 5049f96204bSAurelien Jarno 5059f96204bSAurelien Jarno flash@0 { 5069f96204bSAurelien Jarno compatible = "jedec,spi-nor"; 5079f96204bSAurelien Jarno reg = <0>; 5089f96204bSAurelien Jarno spi-max-frequency = <100000000>; 5099f96204bSAurelien Jarno spi-rx-bus-width = <2>; 5109f96204bSAurelien Jarno spi-tx-bus-width = <1>; 5119f96204bSAurelien Jarno 5129f96204bSAurelien Jarno partitions { 5139f96204bSAurelien Jarno compatible = "fixed-partitions"; 5149f96204bSAurelien Jarno #address-cells = <1>; 5159f96204bSAurelien Jarno #size-cells = <1>; 5169f96204bSAurelien Jarno 5179f96204bSAurelien Jarno partition@0 { 5189f96204bSAurelien Jarno label = "SPL"; 5199f96204bSAurelien Jarno reg = <0x0 0xe0000>; 5209f96204bSAurelien Jarno }; 5219f96204bSAurelien Jarno partition@e0000 { 5229f96204bSAurelien Jarno label = "U-Boot Env"; 5239f96204bSAurelien Jarno reg = <0xe0000 0x20000>; 5249f96204bSAurelien Jarno }; 5259f96204bSAurelien Jarno partition@100000 { 5269f96204bSAurelien Jarno label = "U-Boot"; 5279f96204bSAurelien Jarno reg = <0x100000 0x200000>; 5289f96204bSAurelien Jarno }; 5299f96204bSAurelien Jarno partition@300000 { 5309f96204bSAurelien Jarno label = "splash"; 5319f96204bSAurelien Jarno reg = <0x300000 0x100000>; 5329f96204bSAurelien Jarno }; 5339f96204bSAurelien Jarno partition@400000 { 5349f96204bSAurelien Jarno label = "Filesystem"; 5359f96204bSAurelien Jarno reg = <0x400000 0xc00000>; 5369f96204bSAurelien Jarno }; 5379f96204bSAurelien Jarno }; 5389f96204bSAurelien Jarno }; 5399f96204bSAurelien Jarno}; 5409f96204bSAurelien Jarno 541f5511bd8SAurelien Jarno&tsadc { 542f5511bd8SAurelien Jarno rockchip,hw-tshut-mode = <1>; 543f5511bd8SAurelien Jarno rockchip,hw-tshut-polarity = <0>; 544f5511bd8SAurelien Jarno status = "okay"; 545f5511bd8SAurelien Jarno}; 546f5511bd8SAurelien Jarno 547fd358326SDongjin Kim&uart2 { 548fd358326SDongjin Kim status = "okay"; 549fd358326SDongjin Kim}; 550*913404aaSAurelien Jarno 551*913404aaSAurelien Jarno&vop { 552*913404aaSAurelien Jarno assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; 553*913404aaSAurelien Jarno assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; 554*913404aaSAurelien Jarno status = "okay"; 555*913404aaSAurelien Jarno}; 556*913404aaSAurelien Jarno 557*913404aaSAurelien Jarno&vop_mmu { 558*913404aaSAurelien Jarno status = "okay"; 559*913404aaSAurelien Jarno}; 560*913404aaSAurelien Jarno 561*913404aaSAurelien Jarno&vp0 { 562*913404aaSAurelien Jarno vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { 563*913404aaSAurelien Jarno reg = <ROCKCHIP_VOP2_EP_HDMI0>; 564*913404aaSAurelien Jarno remote-endpoint = <&hdmi_in_vp0>; 565*913404aaSAurelien Jarno }; 566*913404aaSAurelien Jarno}; 567