1fd358326SDongjin Kim// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2fd358326SDongjin Kim/* 3fd358326SDongjin Kim * Copyright (c) 2022 Hardkernel Co., Ltd. 4fd358326SDongjin Kim * 5fd358326SDongjin Kim */ 6fd358326SDongjin Kim 7fd358326SDongjin Kim/dts-v1/; 8fd358326SDongjin Kim#include <dt-bindings/gpio/gpio.h> 9fd358326SDongjin Kim#include <dt-bindings/leds/common.h> 10fd358326SDongjin Kim#include <dt-bindings/pinctrl/rockchip.h> 11fd358326SDongjin Kim#include "rk3568.dtsi" 12fd358326SDongjin Kim 13fd358326SDongjin Kim/ { 14fd358326SDongjin Kim model = "Hardkernel ODROID-M1"; 15fd358326SDongjin Kim compatible = "rockchip,rk3568-odroid-m1", "rockchip,rk3568"; 16fd358326SDongjin Kim 17fd358326SDongjin Kim aliases { 18fd358326SDongjin Kim ethernet0 = &gmac0; 19fd358326SDongjin Kim i2c0 = &i2c3; 20fd358326SDongjin Kim i2c3 = &i2c0; 21fd358326SDongjin Kim mmc0 = &sdhci; 22fd358326SDongjin Kim mmc1 = &sdmmc0; 23fd358326SDongjin Kim serial0 = &uart1; 24fd358326SDongjin Kim serial1 = &uart0; 25fd358326SDongjin Kim }; 26fd358326SDongjin Kim 27fd358326SDongjin Kim chosen { 28fd358326SDongjin Kim stdout-path = "serial2:1500000n8"; 29fd358326SDongjin Kim }; 30fd358326SDongjin Kim 31fd358326SDongjin Kim dc_12v: dc-12v-regulator { 32fd358326SDongjin Kim compatible = "regulator-fixed"; 33fd358326SDongjin Kim regulator-name = "dc_12v"; 34fd358326SDongjin Kim regulator-always-on; 35fd358326SDongjin Kim regulator-boot-on; 36fd358326SDongjin Kim regulator-min-microvolt = <12000000>; 37fd358326SDongjin Kim regulator-max-microvolt = <12000000>; 38fd358326SDongjin Kim }; 39fd358326SDongjin Kim 40fd358326SDongjin Kim leds { 41fd358326SDongjin Kim compatible = "gpio-leds"; 42fd358326SDongjin Kim 43fd358326SDongjin Kim led_power: led-0 { 44fd358326SDongjin Kim gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; 45fd358326SDongjin Kim function = LED_FUNCTION_POWER; 46fd358326SDongjin Kim color = <LED_COLOR_ID_RED>; 47fd358326SDongjin Kim default-state = "keep"; 48fd358326SDongjin Kim linux,default-trigger = "default-on"; 49fd358326SDongjin Kim pinctrl-names = "default"; 50fd358326SDongjin Kim pinctrl-0 = <&led_power_pin>; 51fd358326SDongjin Kim }; 52fd358326SDongjin Kim led_work: led-1 { 53fd358326SDongjin Kim gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; 54fd358326SDongjin Kim function = LED_FUNCTION_HEARTBEAT; 55fd358326SDongjin Kim color = <LED_COLOR_ID_BLUE>; 56fd358326SDongjin Kim linux,default-trigger = "heartbeat"; 57fd358326SDongjin Kim pinctrl-names = "default"; 58fd358326SDongjin Kim pinctrl-0 = <&led_work_pin>; 59fd358326SDongjin Kim }; 60fd358326SDongjin Kim }; 61fd358326SDongjin Kim 62*78f85844SAurelien Jarno rk809-sound { 63*78f85844SAurelien Jarno compatible = "simple-audio-card"; 64*78f85844SAurelien Jarno pinctrl-names = "default"; 65*78f85844SAurelien Jarno pinctrl-0 = <&hp_det_pin>; 66*78f85844SAurelien Jarno simple-audio-card,name = "Analog RK817"; 67*78f85844SAurelien Jarno simple-audio-card,format = "i2s"; 68*78f85844SAurelien Jarno simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; 69*78f85844SAurelien Jarno simple-audio-card,mclk-fs = <256>; 70*78f85844SAurelien Jarno simple-audio-card,widgets = 71*78f85844SAurelien Jarno "Headphone", "Headphones", 72*78f85844SAurelien Jarno "Speaker", "Speaker"; 73*78f85844SAurelien Jarno simple-audio-card,routing = 74*78f85844SAurelien Jarno "Headphones", "HPOL", 75*78f85844SAurelien Jarno "Headphones", "HPOR", 76*78f85844SAurelien Jarno "Speaker", "SPKO"; 77*78f85844SAurelien Jarno 78*78f85844SAurelien Jarno simple-audio-card,cpu { 79*78f85844SAurelien Jarno sound-dai = <&i2s1_8ch>; 80*78f85844SAurelien Jarno }; 81*78f85844SAurelien Jarno 82*78f85844SAurelien Jarno simple-audio-card,codec { 83*78f85844SAurelien Jarno sound-dai = <&rk809>; 84*78f85844SAurelien Jarno }; 85*78f85844SAurelien Jarno }; 86*78f85844SAurelien Jarno 87fd358326SDongjin Kim vcc3v3_sys: vcc3v3-sys-regulator { 88fd358326SDongjin Kim compatible = "regulator-fixed"; 89fd358326SDongjin Kim regulator-name = "vcc3v3_sys"; 90fd358326SDongjin Kim regulator-always-on; 91fd358326SDongjin Kim regulator-boot-on; 92fd358326SDongjin Kim regulator-min-microvolt = <3300000>; 93fd358326SDongjin Kim regulator-max-microvolt = <3300000>; 94fd358326SDongjin Kim vin-supply = <&dc_12v>; 95fd358326SDongjin Kim }; 96fd358326SDongjin Kim}; 97fd358326SDongjin Kim 98fd358326SDongjin Kim&cpu0 { 99fd358326SDongjin Kim cpu-supply = <&vdd_cpu>; 100fd358326SDongjin Kim}; 101fd358326SDongjin Kim 102fd358326SDongjin Kim&cpu1 { 103fd358326SDongjin Kim cpu-supply = <&vdd_cpu>; 104fd358326SDongjin Kim}; 105fd358326SDongjin Kim 106fd358326SDongjin Kim&cpu2 { 107fd358326SDongjin Kim cpu-supply = <&vdd_cpu>; 108fd358326SDongjin Kim}; 109fd358326SDongjin Kim 110fd358326SDongjin Kim&cpu3 { 111fd358326SDongjin Kim cpu-supply = <&vdd_cpu>; 112fd358326SDongjin Kim}; 113fd358326SDongjin Kim 114fd358326SDongjin Kim&gmac0 { 115fd358326SDongjin Kim assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; 116fd358326SDongjin Kim assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; 117fd358326SDongjin Kim assigned-clock-rates = <0>, <125000000>; 118fd358326SDongjin Kim clock_in_out = "output"; 119fd358326SDongjin Kim phy-handle = <&rgmii_phy0>; 120fd358326SDongjin Kim phy-mode = "rgmii"; 121fd358326SDongjin Kim phy-supply = <&vcc3v3_sys>; 122fd358326SDongjin Kim pinctrl-names = "default"; 123fd358326SDongjin Kim pinctrl-0 = <&gmac0_miim 124fd358326SDongjin Kim &gmac0_tx_bus2 125fd358326SDongjin Kim &gmac0_rx_bus2 126fd358326SDongjin Kim &gmac0_rgmii_clk 127fd358326SDongjin Kim &gmac0_rgmii_bus>; 128fd358326SDongjin Kim status = "okay"; 129fd358326SDongjin Kim 130fd358326SDongjin Kim tx_delay = <0x4f>; 131fd358326SDongjin Kim rx_delay = <0x2d>; 132fd358326SDongjin Kim}; 133fd358326SDongjin Kim 134fd358326SDongjin Kim&i2c0 { 135fd358326SDongjin Kim status = "okay"; 136fd358326SDongjin Kim 137fd358326SDongjin Kim vdd_cpu: regulator@1c { 138fd358326SDongjin Kim compatible = "tcs,tcs4525"; 139fd358326SDongjin Kim reg = <0x1c>; 140fd358326SDongjin Kim fcs,suspend-voltage-selector = <1>; 141fd358326SDongjin Kim regulator-name = "vdd_cpu"; 142fd358326SDongjin Kim regulator-always-on; 143fd358326SDongjin Kim regulator-boot-on; 144fd358326SDongjin Kim regulator-min-microvolt = <800000>; 145fd358326SDongjin Kim regulator-max-microvolt = <1150000>; 146fd358326SDongjin Kim regulator-ramp-delay = <2300>; 147fd358326SDongjin Kim vin-supply = <&vcc3v3_sys>; 148fd358326SDongjin Kim 149fd358326SDongjin Kim regulator-state-mem { 150fd358326SDongjin Kim regulator-off-in-suspend; 151fd358326SDongjin Kim }; 152fd358326SDongjin Kim }; 153fd358326SDongjin Kim 154fd358326SDongjin Kim rk809: pmic@20 { 155fd358326SDongjin Kim compatible = "rockchip,rk809"; 156fd358326SDongjin Kim reg = <0x20>; 157fd358326SDongjin Kim interrupt-parent = <&gpio0>; 158fd358326SDongjin Kim interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; 159*78f85844SAurelien Jarno assigned-clocks = <&cru I2S1_MCLKOUT_TX>; 160*78f85844SAurelien Jarno assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; 161fd358326SDongjin Kim #clock-cells = <1>; 162*78f85844SAurelien Jarno clock-names = "mclk"; 163*78f85844SAurelien Jarno clocks = <&cru I2S1_MCLKOUT_TX>; 164fd358326SDongjin Kim pinctrl-names = "default"; 165*78f85844SAurelien Jarno pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; 166fd358326SDongjin Kim rockchip,system-power-controller; 167*78f85844SAurelien Jarno #sound-dai-cells = <0>; 168fd358326SDongjin Kim vcc1-supply = <&vcc3v3_sys>; 169fd358326SDongjin Kim vcc2-supply = <&vcc3v3_sys>; 170fd358326SDongjin Kim vcc3-supply = <&vcc3v3_sys>; 171fd358326SDongjin Kim vcc4-supply = <&vcc3v3_sys>; 172fd358326SDongjin Kim vcc5-supply = <&vcc3v3_sys>; 173fd358326SDongjin Kim vcc6-supply = <&vcc3v3_sys>; 174fd358326SDongjin Kim vcc7-supply = <&vcc3v3_sys>; 175fd358326SDongjin Kim vcc8-supply = <&vcc3v3_sys>; 176fd358326SDongjin Kim vcc9-supply = <&vcc3v3_sys>; 177fd358326SDongjin Kim wakeup-source; 178fd358326SDongjin Kim 179fd358326SDongjin Kim regulators { 180fd358326SDongjin Kim vdd_logic: DCDC_REG1 { 181fd358326SDongjin Kim regulator-name = "vdd_logic"; 182fd358326SDongjin Kim regulator-always-on; 183fd358326SDongjin Kim regulator-boot-on; 184fd358326SDongjin Kim regulator-init-microvolt = <900000>; 185fd358326SDongjin Kim regulator-initial-mode = <0x2>; 186fd358326SDongjin Kim regulator-min-microvolt = <500000>; 187fd358326SDongjin Kim regulator-max-microvolt = <1350000>; 188fd358326SDongjin Kim regulator-ramp-delay = <6001>; 189fd358326SDongjin Kim 190fd358326SDongjin Kim regulator-state-mem { 191fd358326SDongjin Kim regulator-off-in-suspend; 192fd358326SDongjin Kim }; 193fd358326SDongjin Kim }; 194fd358326SDongjin Kim 195fd358326SDongjin Kim vdd_gpu: DCDC_REG2 { 196fd358326SDongjin Kim regulator-name = "vdd_gpu"; 197fd358326SDongjin Kim regulator-always-on; 198fd358326SDongjin Kim regulator-init-microvolt = <900000>; 199fd358326SDongjin Kim regulator-initial-mode = <0x2>; 200fd358326SDongjin Kim regulator-min-microvolt = <500000>; 201fd358326SDongjin Kim regulator-max-microvolt = <1350000>; 202fd358326SDongjin Kim regulator-ramp-delay = <6001>; 203fd358326SDongjin Kim 204fd358326SDongjin Kim regulator-state-mem { 205fd358326SDongjin Kim regulator-off-in-suspend; 206fd358326SDongjin Kim }; 207fd358326SDongjin Kim }; 208fd358326SDongjin Kim 209fd358326SDongjin Kim vcc_ddr: DCDC_REG3 { 210fd358326SDongjin Kim regulator-name = "vcc_ddr"; 211fd358326SDongjin Kim regulator-always-on; 212fd358326SDongjin Kim regulator-boot-on; 213fd358326SDongjin Kim regulator-initial-mode = <0x2>; 214fd358326SDongjin Kim 215fd358326SDongjin Kim regulator-state-mem { 216fd358326SDongjin Kim regulator-on-in-suspend; 217fd358326SDongjin Kim }; 218fd358326SDongjin Kim }; 219fd358326SDongjin Kim 220fd358326SDongjin Kim vdd_npu: DCDC_REG4 { 221fd358326SDongjin Kim regulator-name = "vdd_npu"; 222fd358326SDongjin Kim regulator-init-microvolt = <900000>; 223fd358326SDongjin Kim regulator-initial-mode = <0x2>; 224fd358326SDongjin Kim regulator-min-microvolt = <500000>; 225fd358326SDongjin Kim regulator-max-microvolt = <1350000>; 226fd358326SDongjin Kim regulator-ramp-delay = <6001>; 227fd358326SDongjin Kim 228fd358326SDongjin Kim regulator-state-mem { 229fd358326SDongjin Kim regulator-off-in-suspend; 230fd358326SDongjin Kim }; 231fd358326SDongjin Kim }; 232fd358326SDongjin Kim 233fd358326SDongjin Kim vcc_1v8: DCDC_REG5 { 234fd358326SDongjin Kim regulator-name = "vcc_1v8"; 235fd358326SDongjin Kim regulator-always-on; 236fd358326SDongjin Kim regulator-boot-on; 237fd358326SDongjin Kim regulator-min-microvolt = <1800000>; 238fd358326SDongjin Kim regulator-max-microvolt = <1800000>; 239fd358326SDongjin Kim 240fd358326SDongjin Kim regulator-state-mem { 241fd358326SDongjin Kim regulator-off-in-suspend; 242fd358326SDongjin Kim }; 243fd358326SDongjin Kim }; 244fd358326SDongjin Kim 245fd358326SDongjin Kim vdda0v9_image: LDO_REG1 { 246fd358326SDongjin Kim regulator-name = "vdda0v9_image"; 247fd358326SDongjin Kim regulator-always-on; 248fd358326SDongjin Kim regulator-min-microvolt = <900000>; 249fd358326SDongjin Kim regulator-max-microvolt = <900000>; 250fd358326SDongjin Kim 251fd358326SDongjin Kim regulator-state-mem { 252fd358326SDongjin Kim regulator-off-in-suspend; 253fd358326SDongjin Kim }; 254fd358326SDongjin Kim }; 255fd358326SDongjin Kim 256fd358326SDongjin Kim vdda_0v9: LDO_REG2 { 257fd358326SDongjin Kim regulator-name = "vdda_0v9"; 258fd358326SDongjin Kim regulator-always-on; 259fd358326SDongjin Kim regulator-boot-on; 260fd358326SDongjin Kim regulator-min-microvolt = <900000>; 261fd358326SDongjin Kim regulator-max-microvolt = <900000>; 262fd358326SDongjin Kim 263fd358326SDongjin Kim regulator-state-mem { 264fd358326SDongjin Kim regulator-off-in-suspend; 265fd358326SDongjin Kim }; 266fd358326SDongjin Kim }; 267fd358326SDongjin Kim 268fd358326SDongjin Kim vdda0v9_pmu: LDO_REG3 { 269fd358326SDongjin Kim regulator-name = "vdda0v9_pmu"; 270fd358326SDongjin Kim regulator-always-on; 271fd358326SDongjin Kim regulator-boot-on; 272fd358326SDongjin Kim regulator-min-microvolt = <900000>; 273fd358326SDongjin Kim regulator-max-microvolt = <900000>; 274fd358326SDongjin Kim 275fd358326SDongjin Kim regulator-state-mem { 276fd358326SDongjin Kim regulator-on-in-suspend; 277fd358326SDongjin Kim regulator-suspend-microvolt = <900000>; 278fd358326SDongjin Kim }; 279fd358326SDongjin Kim }; 280fd358326SDongjin Kim 281fd358326SDongjin Kim vccio_acodec: LDO_REG4 { 282fd358326SDongjin Kim regulator-name = "vccio_acodec"; 283fd358326SDongjin Kim regulator-always-on; 284fd358326SDongjin Kim regulator-boot-on; 285fd358326SDongjin Kim regulator-min-microvolt = <3300000>; 286fd358326SDongjin Kim regulator-max-microvolt = <3300000>; 287fd358326SDongjin Kim 288fd358326SDongjin Kim regulator-state-mem { 289fd358326SDongjin Kim regulator-off-in-suspend; 290fd358326SDongjin Kim }; 291fd358326SDongjin Kim }; 292fd358326SDongjin Kim 293fd358326SDongjin Kim vccio_sd: LDO_REG5 { 294fd358326SDongjin Kim regulator-name = "vccio_sd"; 295fd358326SDongjin Kim regulator-min-microvolt = <1800000>; 296fd358326SDongjin Kim regulator-max-microvolt = <3300000>; 297fd358326SDongjin Kim 298fd358326SDongjin Kim regulator-state-mem { 299fd358326SDongjin Kim regulator-off-in-suspend; 300fd358326SDongjin Kim }; 301fd358326SDongjin Kim }; 302fd358326SDongjin Kim 303fd358326SDongjin Kim vcc3v3_pmu: LDO_REG6 { 304fd358326SDongjin Kim regulator-name = "vcc3v3_pmu"; 305fd358326SDongjin Kim regulator-always-on; 306fd358326SDongjin Kim regulator-boot-on; 307fd358326SDongjin Kim regulator-min-microvolt = <3300000>; 308fd358326SDongjin Kim regulator-max-microvolt = <3300000>; 309fd358326SDongjin Kim 310fd358326SDongjin Kim regulator-state-mem { 311fd358326SDongjin Kim regulator-on-in-suspend; 312fd358326SDongjin Kim regulator-suspend-microvolt = <3300000>; 313fd358326SDongjin Kim }; 314fd358326SDongjin Kim }; 315fd358326SDongjin Kim 316fd358326SDongjin Kim vcca_1v8: LDO_REG7 { 317fd358326SDongjin Kim regulator-name = "vcca_1v8"; 318fd358326SDongjin Kim regulator-always-on; 319fd358326SDongjin Kim regulator-boot-on; 320fd358326SDongjin Kim regulator-min-microvolt = <1800000>; 321fd358326SDongjin Kim regulator-max-microvolt = <1800000>; 322fd358326SDongjin Kim 323fd358326SDongjin Kim regulator-state-mem { 324fd358326SDongjin Kim regulator-off-in-suspend; 325fd358326SDongjin Kim }; 326fd358326SDongjin Kim }; 327fd358326SDongjin Kim 328fd358326SDongjin Kim vcca1v8_pmu: LDO_REG8 { 329fd358326SDongjin Kim regulator-name = "vcca1v8_pmu"; 330fd358326SDongjin Kim regulator-always-on; 331fd358326SDongjin Kim regulator-boot-on; 332fd358326SDongjin Kim regulator-min-microvolt = <1800000>; 333fd358326SDongjin Kim regulator-max-microvolt = <1800000>; 334fd358326SDongjin Kim 335fd358326SDongjin Kim regulator-state-mem { 336fd358326SDongjin Kim regulator-on-in-suspend; 337fd358326SDongjin Kim regulator-suspend-microvolt = <1800000>; 338fd358326SDongjin Kim }; 339fd358326SDongjin Kim }; 340fd358326SDongjin Kim 341fd358326SDongjin Kim vcca1v8_image: LDO_REG9 { 342fd358326SDongjin Kim regulator-name = "vcca1v8_image"; 343fd358326SDongjin Kim regulator-always-on; 344fd358326SDongjin Kim regulator-min-microvolt = <1800000>; 345fd358326SDongjin Kim regulator-max-microvolt = <1800000>; 346fd358326SDongjin Kim 347fd358326SDongjin Kim regulator-state-mem { 348fd358326SDongjin Kim regulator-off-in-suspend; 349fd358326SDongjin Kim }; 350fd358326SDongjin Kim }; 351fd358326SDongjin Kim 352fd358326SDongjin Kim vcc_3v3: SWITCH_REG1 { 353fd358326SDongjin Kim regulator-name = "vcc_3v3"; 354fd358326SDongjin Kim regulator-always-on; 355fd358326SDongjin Kim regulator-boot-on; 356fd358326SDongjin Kim 357fd358326SDongjin Kim regulator-state-mem { 358fd358326SDongjin Kim regulator-off-in-suspend; 359fd358326SDongjin Kim }; 360fd358326SDongjin Kim }; 361fd358326SDongjin Kim 362fd358326SDongjin Kim vcc3v3_sd: SWITCH_REG2 { 363fd358326SDongjin Kim regulator-name = "vcc3v3_sd"; 364fd358326SDongjin Kim 365fd358326SDongjin Kim regulator-state-mem { 366fd358326SDongjin Kim regulator-off-in-suspend; 367fd358326SDongjin Kim }; 368fd358326SDongjin Kim }; 369fd358326SDongjin Kim }; 370fd358326SDongjin Kim }; 371fd358326SDongjin Kim}; 372fd358326SDongjin Kim 373*78f85844SAurelien Jarno&i2s1_8ch { 374*78f85844SAurelien Jarno rockchip,trcm-sync-tx-only; 375*78f85844SAurelien Jarno status = "okay"; 376*78f85844SAurelien Jarno}; 377*78f85844SAurelien Jarno 378fd358326SDongjin Kim&mdio0 { 379fd358326SDongjin Kim rgmii_phy0: ethernet-phy@0 { 380fd358326SDongjin Kim compatible = "ethernet-phy-ieee802.3-c22"; 381fd358326SDongjin Kim reg = <0x0>; 382fd358326SDongjin Kim reset-assert-us = <20000>; 383fd358326SDongjin Kim reset-deassert-us = <100000>; 384fd358326SDongjin Kim reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; 385fd358326SDongjin Kim }; 386fd358326SDongjin Kim}; 387fd358326SDongjin Kim 388fd358326SDongjin Kim&pinctrl { 3899f96204bSAurelien Jarno fspi { 3909f96204bSAurelien Jarno fspi_dual_io_pins: fspi-dual-io-pins { 3919f96204bSAurelien Jarno rockchip,pins = 3929f96204bSAurelien Jarno /* fspi_clk */ 3939f96204bSAurelien Jarno <1 RK_PD0 1 &pcfg_pull_none>, 3949f96204bSAurelien Jarno /* fspi_cs0n */ 3959f96204bSAurelien Jarno <1 RK_PD3 1 &pcfg_pull_none>, 3969f96204bSAurelien Jarno /* fspi_d0 */ 3979f96204bSAurelien Jarno <1 RK_PD1 1 &pcfg_pull_none>, 3989f96204bSAurelien Jarno /* fspi_d1 */ 3999f96204bSAurelien Jarno <1 RK_PD2 1 &pcfg_pull_none>; 4009f96204bSAurelien Jarno }; 4019f96204bSAurelien Jarno }; 4029f96204bSAurelien Jarno 403fd358326SDongjin Kim leds { 404fd358326SDongjin Kim led_power_pin: led-power-pin { 405fd358326SDongjin Kim rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 406fd358326SDongjin Kim }; 407fd358326SDongjin Kim led_work_pin: led-work-pin { 408fd358326SDongjin Kim rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; 409fd358326SDongjin Kim }; 410fd358326SDongjin Kim }; 411fd358326SDongjin Kim 412fd358326SDongjin Kim pmic { 413fd358326SDongjin Kim pmic_int_l: pmic-int-l { 414fd358326SDongjin Kim rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; 415fd358326SDongjin Kim }; 416fd358326SDongjin Kim }; 417*78f85844SAurelien Jarno 418*78f85844SAurelien Jarno rk809 { 419*78f85844SAurelien Jarno hp_det_pin: hp-det-pin { 420*78f85844SAurelien Jarno rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 421*78f85844SAurelien Jarno }; 422*78f85844SAurelien Jarno }; 423fd358326SDongjin Kim}; 424fd358326SDongjin Kim 425fd358326SDongjin Kim&pmu_io_domains { 426fd358326SDongjin Kim pmuio1-supply = <&vcc3v3_pmu>; 427fd358326SDongjin Kim pmuio2-supply = <&vcc3v3_pmu>; 428fd358326SDongjin Kim vccio1-supply = <&vccio_acodec>; 429fd358326SDongjin Kim vccio2-supply = <&vcc_1v8>; 430fd358326SDongjin Kim vccio3-supply = <&vccio_sd>; 431fd358326SDongjin Kim vccio4-supply = <&vcc_1v8>; 432fd358326SDongjin Kim vccio5-supply = <&vcc_3v3>; 433fd358326SDongjin Kim vccio6-supply = <&vcc_3v3>; 434fd358326SDongjin Kim vccio7-supply = <&vcc_3v3>; 435fd358326SDongjin Kim status = "okay"; 436fd358326SDongjin Kim}; 437fd358326SDongjin Kim 438fd358326SDongjin Kim&saradc { 439fd358326SDongjin Kim vref-supply = <&vcca_1v8>; 440fd358326SDongjin Kim status = "okay"; 441fd358326SDongjin Kim}; 442fd358326SDongjin Kim 443fd358326SDongjin Kim&sdhci { 444fd358326SDongjin Kim bus-width = <8>; 445fd358326SDongjin Kim max-frequency = <200000000>; 446fd358326SDongjin Kim non-removable; 447fd358326SDongjin Kim pinctrl-names = "default"; 448fd358326SDongjin Kim pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>; 449fd358326SDongjin Kim vmmc-supply = <&vcc_3v3>; 450fd358326SDongjin Kim vqmmc-supply = <&vcc_1v8>; 451fd358326SDongjin Kim status = "okay"; 452fd358326SDongjin Kim}; 453fd358326SDongjin Kim 454fd358326SDongjin Kim&sdmmc0 { 455fd358326SDongjin Kim bus-width = <4>; 456fd358326SDongjin Kim cap-sd-highspeed; 457fd358326SDongjin Kim cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; 458fd358326SDongjin Kim disable-wp; 459fd358326SDongjin Kim pinctrl-names = "default"; 460fd358326SDongjin Kim pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; 461fd358326SDongjin Kim sd-uhs-sdr50; 462fd358326SDongjin Kim vmmc-supply = <&vcc3v3_sd>; 463fd358326SDongjin Kim vqmmc-supply = <&vccio_sd>; 464fd358326SDongjin Kim status = "okay"; 465fd358326SDongjin Kim}; 466fd358326SDongjin Kim 4679f96204bSAurelien Jarno&sfc { 4689f96204bSAurelien Jarno /* Dual I/O mode as the D2 pin conflicts with the eMMC */ 4699f96204bSAurelien Jarno pinctrl-0 = <&fspi_dual_io_pins>; 4709f96204bSAurelien Jarno pinctrl-names = "default"; 4719f96204bSAurelien Jarno #address-cells = <1>; 4729f96204bSAurelien Jarno #size-cells = <0>; 4739f96204bSAurelien Jarno status = "okay"; 4749f96204bSAurelien Jarno 4759f96204bSAurelien Jarno flash@0 { 4769f96204bSAurelien Jarno compatible = "jedec,spi-nor"; 4779f96204bSAurelien Jarno reg = <0>; 4789f96204bSAurelien Jarno spi-max-frequency = <100000000>; 4799f96204bSAurelien Jarno spi-rx-bus-width = <2>; 4809f96204bSAurelien Jarno spi-tx-bus-width = <1>; 4819f96204bSAurelien Jarno 4829f96204bSAurelien Jarno partitions { 4839f96204bSAurelien Jarno compatible = "fixed-partitions"; 4849f96204bSAurelien Jarno #address-cells = <1>; 4859f96204bSAurelien Jarno #size-cells = <1>; 4869f96204bSAurelien Jarno 4879f96204bSAurelien Jarno partition@0 { 4889f96204bSAurelien Jarno label = "SPL"; 4899f96204bSAurelien Jarno reg = <0x0 0xe0000>; 4909f96204bSAurelien Jarno }; 4919f96204bSAurelien Jarno partition@e0000 { 4929f96204bSAurelien Jarno label = "U-Boot Env"; 4939f96204bSAurelien Jarno reg = <0xe0000 0x20000>; 4949f96204bSAurelien Jarno }; 4959f96204bSAurelien Jarno partition@100000 { 4969f96204bSAurelien Jarno label = "U-Boot"; 4979f96204bSAurelien Jarno reg = <0x100000 0x200000>; 4989f96204bSAurelien Jarno }; 4999f96204bSAurelien Jarno partition@300000 { 5009f96204bSAurelien Jarno label = "splash"; 5019f96204bSAurelien Jarno reg = <0x300000 0x100000>; 5029f96204bSAurelien Jarno }; 5039f96204bSAurelien Jarno partition@400000 { 5049f96204bSAurelien Jarno label = "Filesystem"; 5059f96204bSAurelien Jarno reg = <0x400000 0xc00000>; 5069f96204bSAurelien Jarno }; 5079f96204bSAurelien Jarno }; 5089f96204bSAurelien Jarno }; 5099f96204bSAurelien Jarno}; 5109f96204bSAurelien Jarno 511f5511bd8SAurelien Jarno&tsadc { 512f5511bd8SAurelien Jarno rockchip,hw-tshut-mode = <1>; 513f5511bd8SAurelien Jarno rockchip,hw-tshut-polarity = <0>; 514f5511bd8SAurelien Jarno status = "okay"; 515f5511bd8SAurelien Jarno}; 516f5511bd8SAurelien Jarno 517fd358326SDongjin Kim&uart2 { 518fd358326SDongjin Kim status = "okay"; 519fd358326SDongjin Kim}; 520