1fd358326SDongjin Kim// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2fd358326SDongjin Kim/*
3fd358326SDongjin Kim * Copyright (c) 2022 Hardkernel Co., Ltd.
4fd358326SDongjin Kim *
5fd358326SDongjin Kim */
6fd358326SDongjin Kim
7fd358326SDongjin Kim/dts-v1/;
8fd358326SDongjin Kim#include <dt-bindings/gpio/gpio.h>
9fd358326SDongjin Kim#include <dt-bindings/leds/common.h>
10fd358326SDongjin Kim#include <dt-bindings/pinctrl/rockchip.h>
11913404aaSAurelien Jarno#include <dt-bindings/soc/rockchip,vop2.h>
12fd358326SDongjin Kim#include "rk3568.dtsi"
13fd358326SDongjin Kim
14fd358326SDongjin Kim/ {
15fd358326SDongjin Kim	model = "Hardkernel ODROID-M1";
16fd358326SDongjin Kim	compatible = "rockchip,rk3568-odroid-m1", "rockchip,rk3568";
17fd358326SDongjin Kim
18fd358326SDongjin Kim	aliases {
19fd358326SDongjin Kim		ethernet0 = &gmac0;
20fd358326SDongjin Kim		i2c0 = &i2c3;
21fd358326SDongjin Kim		i2c3 = &i2c0;
22fd358326SDongjin Kim		mmc0 = &sdhci;
23fd358326SDongjin Kim		mmc1 = &sdmmc0;
24fd358326SDongjin Kim		serial0 = &uart1;
25fd358326SDongjin Kim		serial1 = &uart0;
26fd358326SDongjin Kim	};
27fd358326SDongjin Kim
28fd358326SDongjin Kim	chosen {
29fd358326SDongjin Kim		stdout-path = "serial2:1500000n8";
30fd358326SDongjin Kim	};
31fd358326SDongjin Kim
32fd358326SDongjin Kim	dc_12v: dc-12v-regulator {
33fd358326SDongjin Kim		compatible = "regulator-fixed";
34fd358326SDongjin Kim		regulator-name = "dc_12v";
35fd358326SDongjin Kim		regulator-always-on;
36fd358326SDongjin Kim		regulator-boot-on;
37fd358326SDongjin Kim		regulator-min-microvolt = <12000000>;
38fd358326SDongjin Kim		regulator-max-microvolt = <12000000>;
39fd358326SDongjin Kim	};
40fd358326SDongjin Kim
41913404aaSAurelien Jarno	hdmi-con {
42913404aaSAurelien Jarno		compatible = "hdmi-connector";
43913404aaSAurelien Jarno		type = "a";
44913404aaSAurelien Jarno
45913404aaSAurelien Jarno		port {
46913404aaSAurelien Jarno			hdmi_con_in: endpoint {
47913404aaSAurelien Jarno				remote-endpoint = <&hdmi_out_con>;
48913404aaSAurelien Jarno			};
49913404aaSAurelien Jarno		};
50913404aaSAurelien Jarno	};
51913404aaSAurelien Jarno
52fd358326SDongjin Kim	leds {
53fd358326SDongjin Kim		compatible = "gpio-leds";
54fd358326SDongjin Kim
55fd358326SDongjin Kim		led_power: led-0 {
56fd358326SDongjin Kim			gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
57fd358326SDongjin Kim			function = LED_FUNCTION_POWER;
58fd358326SDongjin Kim			color = <LED_COLOR_ID_RED>;
59fd358326SDongjin Kim			default-state = "keep";
60fd358326SDongjin Kim			linux,default-trigger = "default-on";
61fd358326SDongjin Kim			pinctrl-names = "default";
62fd358326SDongjin Kim			pinctrl-0 = <&led_power_pin>;
63fd358326SDongjin Kim		};
64fd358326SDongjin Kim		led_work: led-1 {
65fd358326SDongjin Kim			gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
66fd358326SDongjin Kim			function = LED_FUNCTION_HEARTBEAT;
67fd358326SDongjin Kim			color = <LED_COLOR_ID_BLUE>;
68fd358326SDongjin Kim			linux,default-trigger = "heartbeat";
69fd358326SDongjin Kim			pinctrl-names = "default";
70fd358326SDongjin Kim			pinctrl-0 = <&led_work_pin>;
71fd358326SDongjin Kim		};
72fd358326SDongjin Kim	};
73fd358326SDongjin Kim
7478f85844SAurelien Jarno	rk809-sound {
7578f85844SAurelien Jarno		compatible = "simple-audio-card";
7678f85844SAurelien Jarno		pinctrl-names = "default";
7778f85844SAurelien Jarno		pinctrl-0 = <&hp_det_pin>;
7878f85844SAurelien Jarno		simple-audio-card,name = "Analog RK817";
7978f85844SAurelien Jarno		simple-audio-card,format = "i2s";
8078f85844SAurelien Jarno		simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
8178f85844SAurelien Jarno		simple-audio-card,mclk-fs = <256>;
8278f85844SAurelien Jarno		simple-audio-card,widgets =
8378f85844SAurelien Jarno			"Headphone", "Headphones",
8478f85844SAurelien Jarno			"Speaker", "Speaker";
8578f85844SAurelien Jarno		simple-audio-card,routing =
8678f85844SAurelien Jarno			"Headphones", "HPOL",
8778f85844SAurelien Jarno			"Headphones", "HPOR",
8878f85844SAurelien Jarno			"Speaker", "SPKO";
8978f85844SAurelien Jarno
9078f85844SAurelien Jarno		simple-audio-card,cpu {
9178f85844SAurelien Jarno			sound-dai = <&i2s1_8ch>;
9278f85844SAurelien Jarno		};
9378f85844SAurelien Jarno
9478f85844SAurelien Jarno		simple-audio-card,codec {
9578f85844SAurelien Jarno			sound-dai = <&rk809>;
9678f85844SAurelien Jarno		};
9778f85844SAurelien Jarno	};
9878f85844SAurelien Jarno
99fd358326SDongjin Kim	vcc3v3_sys: vcc3v3-sys-regulator {
100fd358326SDongjin Kim		compatible = "regulator-fixed";
101fd358326SDongjin Kim		regulator-name = "vcc3v3_sys";
102fd358326SDongjin Kim		regulator-always-on;
103fd358326SDongjin Kim		regulator-boot-on;
104fd358326SDongjin Kim		regulator-min-microvolt = <3300000>;
105fd358326SDongjin Kim		regulator-max-microvolt = <3300000>;
106fd358326SDongjin Kim		vin-supply = <&dc_12v>;
107fd358326SDongjin Kim	};
108*4685d7b6SAurelien Jarno
109*4685d7b6SAurelien Jarno	vcc5v0_sys: vcc5v0-sys-regulator {
110*4685d7b6SAurelien Jarno		compatible = "regulator-fixed";
111*4685d7b6SAurelien Jarno		regulator-name = "vcc5v0_sys";
112*4685d7b6SAurelien Jarno		regulator-always-on;
113*4685d7b6SAurelien Jarno		regulator-boot-on;
114*4685d7b6SAurelien Jarno		regulator-min-microvolt = <5000000>;
115*4685d7b6SAurelien Jarno		regulator-max-microvolt = <5000000>;
116*4685d7b6SAurelien Jarno		vin-supply = <&dc_12v>;
117*4685d7b6SAurelien Jarno	};
118*4685d7b6SAurelien Jarno
119*4685d7b6SAurelien Jarno	vcc5v0_usb_host: vcc5v0-usb-host-regulator {
120*4685d7b6SAurelien Jarno		compatible = "regulator-fixed";
121*4685d7b6SAurelien Jarno		regulator-name = "vcc5v0_usb_host";
122*4685d7b6SAurelien Jarno		enable-active-high;
123*4685d7b6SAurelien Jarno		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
124*4685d7b6SAurelien Jarno		pinctrl-names = "default";
125*4685d7b6SAurelien Jarno		pinctrl-0 = <&vcc5v0_usb_host_en_pin>;
126*4685d7b6SAurelien Jarno		regulator-min-microvolt = <5000000>;
127*4685d7b6SAurelien Jarno		regulator-max-microvolt = <5000000>;
128*4685d7b6SAurelien Jarno		vin-supply = <&vcc5v0_sys>;
129*4685d7b6SAurelien Jarno	};
130fd358326SDongjin Kim};
131fd358326SDongjin Kim
132fd358326SDongjin Kim&cpu0 {
133fd358326SDongjin Kim	cpu-supply = <&vdd_cpu>;
134fd358326SDongjin Kim};
135fd358326SDongjin Kim
136fd358326SDongjin Kim&cpu1 {
137fd358326SDongjin Kim	cpu-supply = <&vdd_cpu>;
138fd358326SDongjin Kim};
139fd358326SDongjin Kim
140fd358326SDongjin Kim&cpu2 {
141fd358326SDongjin Kim	cpu-supply = <&vdd_cpu>;
142fd358326SDongjin Kim};
143fd358326SDongjin Kim
144fd358326SDongjin Kim&cpu3 {
145fd358326SDongjin Kim	cpu-supply = <&vdd_cpu>;
146fd358326SDongjin Kim};
147fd358326SDongjin Kim
148fd358326SDongjin Kim&gmac0 {
149fd358326SDongjin Kim	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
150fd358326SDongjin Kim	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
151fd358326SDongjin Kim	assigned-clock-rates = <0>, <125000000>;
152fd358326SDongjin Kim	clock_in_out = "output";
153fd358326SDongjin Kim	phy-handle = <&rgmii_phy0>;
154fd358326SDongjin Kim	phy-mode = "rgmii";
155fd358326SDongjin Kim	phy-supply = <&vcc3v3_sys>;
156fd358326SDongjin Kim	pinctrl-names = "default";
157fd358326SDongjin Kim	pinctrl-0 = <&gmac0_miim
158fd358326SDongjin Kim		     &gmac0_tx_bus2
159fd358326SDongjin Kim		     &gmac0_rx_bus2
160fd358326SDongjin Kim		     &gmac0_rgmii_clk
161fd358326SDongjin Kim		     &gmac0_rgmii_bus>;
162fd358326SDongjin Kim	status = "okay";
163fd358326SDongjin Kim
164fd358326SDongjin Kim	tx_delay = <0x4f>;
165fd358326SDongjin Kim	rx_delay = <0x2d>;
166fd358326SDongjin Kim};
167fd358326SDongjin Kim
168cb80b345SAurelien Jarno&gpu {
169cb80b345SAurelien Jarno	mali-supply = <&vdd_gpu>;
170cb80b345SAurelien Jarno	status = "okay";
171cb80b345SAurelien Jarno};
172cb80b345SAurelien Jarno
173913404aaSAurelien Jarno&hdmi {
174913404aaSAurelien Jarno	avdd-0v9-supply = <&vdda0v9_image>;
175913404aaSAurelien Jarno	avdd-1v8-supply = <&vcca1v8_image>;
176913404aaSAurelien Jarno	status = "okay";
177913404aaSAurelien Jarno};
178913404aaSAurelien Jarno
179913404aaSAurelien Jarno&hdmi_in {
180913404aaSAurelien Jarno	hdmi_in_vp0: endpoint {
181913404aaSAurelien Jarno		remote-endpoint = <&vp0_out_hdmi>;
182913404aaSAurelien Jarno	};
183913404aaSAurelien Jarno};
184913404aaSAurelien Jarno
185913404aaSAurelien Jarno&hdmi_out {
186913404aaSAurelien Jarno	hdmi_out_con: endpoint {
187913404aaSAurelien Jarno		remote-endpoint = <&hdmi_con_in>;
188913404aaSAurelien Jarno	};
189913404aaSAurelien Jarno};
190913404aaSAurelien Jarno
1911ca7ddddSAurelien Jarno&hdmi_sound {
1921ca7ddddSAurelien Jarno	status = "okay";
1931ca7ddddSAurelien Jarno};
1941ca7ddddSAurelien Jarno
195fd358326SDongjin Kim&i2c0 {
196fd358326SDongjin Kim	status = "okay";
197fd358326SDongjin Kim
198fd358326SDongjin Kim	vdd_cpu: regulator@1c {
199fd358326SDongjin Kim		compatible = "tcs,tcs4525";
200fd358326SDongjin Kim		reg = <0x1c>;
201fd358326SDongjin Kim		fcs,suspend-voltage-selector = <1>;
202fd358326SDongjin Kim		regulator-name = "vdd_cpu";
203fd358326SDongjin Kim		regulator-always-on;
204fd358326SDongjin Kim		regulator-boot-on;
205fd358326SDongjin Kim		regulator-min-microvolt = <800000>;
206fd358326SDongjin Kim		regulator-max-microvolt = <1150000>;
207fd358326SDongjin Kim		regulator-ramp-delay = <2300>;
208fd358326SDongjin Kim		vin-supply = <&vcc3v3_sys>;
209fd358326SDongjin Kim
210fd358326SDongjin Kim		regulator-state-mem {
211fd358326SDongjin Kim			regulator-off-in-suspend;
212fd358326SDongjin Kim		};
213fd358326SDongjin Kim	};
214fd358326SDongjin Kim
215fd358326SDongjin Kim	rk809: pmic@20 {
216fd358326SDongjin Kim		compatible = "rockchip,rk809";
217fd358326SDongjin Kim		reg = <0x20>;
218fd358326SDongjin Kim		interrupt-parent = <&gpio0>;
219fd358326SDongjin Kim		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
22078f85844SAurelien Jarno		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
22178f85844SAurelien Jarno		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
222fd358326SDongjin Kim		#clock-cells = <1>;
22378f85844SAurelien Jarno		clock-names = "mclk";
22478f85844SAurelien Jarno		clocks = <&cru I2S1_MCLKOUT_TX>;
225fd358326SDongjin Kim		pinctrl-names = "default";
22678f85844SAurelien Jarno		pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
227fd358326SDongjin Kim		rockchip,system-power-controller;
22878f85844SAurelien Jarno		#sound-dai-cells = <0>;
229fd358326SDongjin Kim		vcc1-supply = <&vcc3v3_sys>;
230fd358326SDongjin Kim		vcc2-supply = <&vcc3v3_sys>;
231fd358326SDongjin Kim		vcc3-supply = <&vcc3v3_sys>;
232fd358326SDongjin Kim		vcc4-supply = <&vcc3v3_sys>;
233fd358326SDongjin Kim		vcc5-supply = <&vcc3v3_sys>;
234fd358326SDongjin Kim		vcc6-supply = <&vcc3v3_sys>;
235fd358326SDongjin Kim		vcc7-supply = <&vcc3v3_sys>;
236fd358326SDongjin Kim		vcc8-supply = <&vcc3v3_sys>;
237fd358326SDongjin Kim		vcc9-supply = <&vcc3v3_sys>;
238fd358326SDongjin Kim		wakeup-source;
239fd358326SDongjin Kim
240fd358326SDongjin Kim		regulators {
241fd358326SDongjin Kim			vdd_logic: DCDC_REG1 {
242fd358326SDongjin Kim				regulator-name = "vdd_logic";
243fd358326SDongjin Kim				regulator-always-on;
244fd358326SDongjin Kim				regulator-boot-on;
245fd358326SDongjin Kim				regulator-init-microvolt = <900000>;
246fd358326SDongjin Kim				regulator-initial-mode = <0x2>;
247fd358326SDongjin Kim				regulator-min-microvolt = <500000>;
248fd358326SDongjin Kim				regulator-max-microvolt = <1350000>;
249fd358326SDongjin Kim				regulator-ramp-delay = <6001>;
250fd358326SDongjin Kim
251fd358326SDongjin Kim				regulator-state-mem {
252fd358326SDongjin Kim					regulator-off-in-suspend;
253fd358326SDongjin Kim				};
254fd358326SDongjin Kim			};
255fd358326SDongjin Kim
256fd358326SDongjin Kim			vdd_gpu: DCDC_REG2 {
257fd358326SDongjin Kim				regulator-name = "vdd_gpu";
258fd358326SDongjin Kim				regulator-always-on;
259fd358326SDongjin Kim				regulator-init-microvolt = <900000>;
260fd358326SDongjin Kim				regulator-initial-mode = <0x2>;
261fd358326SDongjin Kim				regulator-min-microvolt = <500000>;
262fd358326SDongjin Kim				regulator-max-microvolt = <1350000>;
263fd358326SDongjin Kim				regulator-ramp-delay = <6001>;
264fd358326SDongjin Kim
265fd358326SDongjin Kim				regulator-state-mem {
266fd358326SDongjin Kim					regulator-off-in-suspend;
267fd358326SDongjin Kim				};
268fd358326SDongjin Kim			};
269fd358326SDongjin Kim
270fd358326SDongjin Kim			vcc_ddr: DCDC_REG3 {
271fd358326SDongjin Kim				regulator-name = "vcc_ddr";
272fd358326SDongjin Kim				regulator-always-on;
273fd358326SDongjin Kim				regulator-boot-on;
274fd358326SDongjin Kim				regulator-initial-mode = <0x2>;
275fd358326SDongjin Kim
276fd358326SDongjin Kim				regulator-state-mem {
277fd358326SDongjin Kim					regulator-on-in-suspend;
278fd358326SDongjin Kim				};
279fd358326SDongjin Kim			};
280fd358326SDongjin Kim
281fd358326SDongjin Kim			vdd_npu: DCDC_REG4 {
282fd358326SDongjin Kim				regulator-name = "vdd_npu";
283fd358326SDongjin Kim				regulator-init-microvolt = <900000>;
284fd358326SDongjin Kim				regulator-initial-mode = <0x2>;
285fd358326SDongjin Kim				regulator-min-microvolt = <500000>;
286fd358326SDongjin Kim				regulator-max-microvolt = <1350000>;
287fd358326SDongjin Kim				regulator-ramp-delay = <6001>;
288fd358326SDongjin Kim
289fd358326SDongjin Kim				regulator-state-mem {
290fd358326SDongjin Kim					regulator-off-in-suspend;
291fd358326SDongjin Kim				};
292fd358326SDongjin Kim			};
293fd358326SDongjin Kim
294fd358326SDongjin Kim			vcc_1v8: DCDC_REG5 {
295fd358326SDongjin Kim				regulator-name = "vcc_1v8";
296fd358326SDongjin Kim				regulator-always-on;
297fd358326SDongjin Kim				regulator-boot-on;
298fd358326SDongjin Kim				regulator-min-microvolt = <1800000>;
299fd358326SDongjin Kim				regulator-max-microvolt = <1800000>;
300fd358326SDongjin Kim
301fd358326SDongjin Kim				regulator-state-mem {
302fd358326SDongjin Kim					regulator-off-in-suspend;
303fd358326SDongjin Kim				};
304fd358326SDongjin Kim			};
305fd358326SDongjin Kim
306fd358326SDongjin Kim			vdda0v9_image: LDO_REG1 {
307fd358326SDongjin Kim				regulator-name = "vdda0v9_image";
308fd358326SDongjin Kim				regulator-always-on;
309fd358326SDongjin Kim				regulator-min-microvolt = <900000>;
310fd358326SDongjin Kim				regulator-max-microvolt = <900000>;
311fd358326SDongjin Kim
312fd358326SDongjin Kim				regulator-state-mem {
313fd358326SDongjin Kim					regulator-off-in-suspend;
314fd358326SDongjin Kim				};
315fd358326SDongjin Kim			};
316fd358326SDongjin Kim
317fd358326SDongjin Kim			vdda_0v9: LDO_REG2 {
318fd358326SDongjin Kim				regulator-name = "vdda_0v9";
319fd358326SDongjin Kim				regulator-always-on;
320fd358326SDongjin Kim				regulator-boot-on;
321fd358326SDongjin Kim				regulator-min-microvolt = <900000>;
322fd358326SDongjin Kim				regulator-max-microvolt = <900000>;
323fd358326SDongjin Kim
324fd358326SDongjin Kim				regulator-state-mem {
325fd358326SDongjin Kim					regulator-off-in-suspend;
326fd358326SDongjin Kim				};
327fd358326SDongjin Kim			};
328fd358326SDongjin Kim
329fd358326SDongjin Kim			vdda0v9_pmu: LDO_REG3 {
330fd358326SDongjin Kim				regulator-name = "vdda0v9_pmu";
331fd358326SDongjin Kim				regulator-always-on;
332fd358326SDongjin Kim				regulator-boot-on;
333fd358326SDongjin Kim				regulator-min-microvolt = <900000>;
334fd358326SDongjin Kim				regulator-max-microvolt = <900000>;
335fd358326SDongjin Kim
336fd358326SDongjin Kim				regulator-state-mem {
337fd358326SDongjin Kim					regulator-on-in-suspend;
338fd358326SDongjin Kim					regulator-suspend-microvolt = <900000>;
339fd358326SDongjin Kim				};
340fd358326SDongjin Kim			};
341fd358326SDongjin Kim
342fd358326SDongjin Kim			vccio_acodec: LDO_REG4 {
343fd358326SDongjin Kim				regulator-name = "vccio_acodec";
344fd358326SDongjin Kim				regulator-always-on;
345fd358326SDongjin Kim				regulator-boot-on;
346fd358326SDongjin Kim				regulator-min-microvolt = <3300000>;
347fd358326SDongjin Kim				regulator-max-microvolt = <3300000>;
348fd358326SDongjin Kim
349fd358326SDongjin Kim				regulator-state-mem {
350fd358326SDongjin Kim					regulator-off-in-suspend;
351fd358326SDongjin Kim				};
352fd358326SDongjin Kim			};
353fd358326SDongjin Kim
354fd358326SDongjin Kim			vccio_sd: LDO_REG5 {
355fd358326SDongjin Kim				regulator-name = "vccio_sd";
356fd358326SDongjin Kim				regulator-min-microvolt = <1800000>;
357fd358326SDongjin Kim				regulator-max-microvolt = <3300000>;
358fd358326SDongjin Kim
359fd358326SDongjin Kim				regulator-state-mem {
360fd358326SDongjin Kim					regulator-off-in-suspend;
361fd358326SDongjin Kim				};
362fd358326SDongjin Kim			};
363fd358326SDongjin Kim
364fd358326SDongjin Kim			vcc3v3_pmu: LDO_REG6 {
365fd358326SDongjin Kim				regulator-name = "vcc3v3_pmu";
366fd358326SDongjin Kim				regulator-always-on;
367fd358326SDongjin Kim				regulator-boot-on;
368fd358326SDongjin Kim				regulator-min-microvolt = <3300000>;
369fd358326SDongjin Kim				regulator-max-microvolt = <3300000>;
370fd358326SDongjin Kim
371fd358326SDongjin Kim				regulator-state-mem {
372fd358326SDongjin Kim					regulator-on-in-suspend;
373fd358326SDongjin Kim					regulator-suspend-microvolt = <3300000>;
374fd358326SDongjin Kim				};
375fd358326SDongjin Kim			};
376fd358326SDongjin Kim
377fd358326SDongjin Kim			vcca_1v8: LDO_REG7 {
378fd358326SDongjin Kim				regulator-name = "vcca_1v8";
379fd358326SDongjin Kim				regulator-always-on;
380fd358326SDongjin Kim				regulator-boot-on;
381fd358326SDongjin Kim				regulator-min-microvolt = <1800000>;
382fd358326SDongjin Kim				regulator-max-microvolt = <1800000>;
383fd358326SDongjin Kim
384fd358326SDongjin Kim				regulator-state-mem {
385fd358326SDongjin Kim					regulator-off-in-suspend;
386fd358326SDongjin Kim				};
387fd358326SDongjin Kim			};
388fd358326SDongjin Kim
389fd358326SDongjin Kim			vcca1v8_pmu: LDO_REG8 {
390fd358326SDongjin Kim				regulator-name = "vcca1v8_pmu";
391fd358326SDongjin Kim				regulator-always-on;
392fd358326SDongjin Kim				regulator-boot-on;
393fd358326SDongjin Kim				regulator-min-microvolt = <1800000>;
394fd358326SDongjin Kim				regulator-max-microvolt = <1800000>;
395fd358326SDongjin Kim
396fd358326SDongjin Kim				regulator-state-mem {
397fd358326SDongjin Kim					regulator-on-in-suspend;
398fd358326SDongjin Kim					regulator-suspend-microvolt = <1800000>;
399fd358326SDongjin Kim				};
400fd358326SDongjin Kim			};
401fd358326SDongjin Kim
402fd358326SDongjin Kim			vcca1v8_image: LDO_REG9 {
403fd358326SDongjin Kim				regulator-name = "vcca1v8_image";
404fd358326SDongjin Kim				regulator-always-on;
405fd358326SDongjin Kim				regulator-min-microvolt = <1800000>;
406fd358326SDongjin Kim				regulator-max-microvolt = <1800000>;
407fd358326SDongjin Kim
408fd358326SDongjin Kim				regulator-state-mem {
409fd358326SDongjin Kim					regulator-off-in-suspend;
410fd358326SDongjin Kim				};
411fd358326SDongjin Kim			};
412fd358326SDongjin Kim
413fd358326SDongjin Kim			vcc_3v3: SWITCH_REG1 {
414fd358326SDongjin Kim				regulator-name = "vcc_3v3";
415fd358326SDongjin Kim				regulator-always-on;
416fd358326SDongjin Kim				regulator-boot-on;
417fd358326SDongjin Kim
418fd358326SDongjin Kim				regulator-state-mem {
419fd358326SDongjin Kim					regulator-off-in-suspend;
420fd358326SDongjin Kim				};
421fd358326SDongjin Kim			};
422fd358326SDongjin Kim
423fd358326SDongjin Kim			vcc3v3_sd: SWITCH_REG2 {
424fd358326SDongjin Kim				regulator-name = "vcc3v3_sd";
425fd358326SDongjin Kim
426fd358326SDongjin Kim				regulator-state-mem {
427fd358326SDongjin Kim					regulator-off-in-suspend;
428fd358326SDongjin Kim				};
429fd358326SDongjin Kim			};
430fd358326SDongjin Kim		};
431fd358326SDongjin Kim	};
432fd358326SDongjin Kim};
433fd358326SDongjin Kim
4341ca7ddddSAurelien Jarno&i2s0_8ch {
4351ca7ddddSAurelien Jarno	status = "okay";
4361ca7ddddSAurelien Jarno};
4371ca7ddddSAurelien Jarno
43878f85844SAurelien Jarno&i2s1_8ch {
43978f85844SAurelien Jarno	rockchip,trcm-sync-tx-only;
44078f85844SAurelien Jarno	status = "okay";
44178f85844SAurelien Jarno};
44278f85844SAurelien Jarno
443fd358326SDongjin Kim&mdio0 {
444fd358326SDongjin Kim	rgmii_phy0: ethernet-phy@0 {
445fd358326SDongjin Kim		compatible = "ethernet-phy-ieee802.3-c22";
446fd358326SDongjin Kim		reg = <0x0>;
447fd358326SDongjin Kim		reset-assert-us = <20000>;
448fd358326SDongjin Kim		reset-deassert-us = <100000>;
449fd358326SDongjin Kim		reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
450fd358326SDongjin Kim	};
451fd358326SDongjin Kim};
452fd358326SDongjin Kim
453fd358326SDongjin Kim&pinctrl {
4549f96204bSAurelien Jarno	fspi {
4559f96204bSAurelien Jarno		fspi_dual_io_pins: fspi-dual-io-pins {
4569f96204bSAurelien Jarno			rockchip,pins =
4579f96204bSAurelien Jarno				/* fspi_clk */
4589f96204bSAurelien Jarno				<1 RK_PD0 1 &pcfg_pull_none>,
4599f96204bSAurelien Jarno				/* fspi_cs0n */
4609f96204bSAurelien Jarno				<1 RK_PD3 1 &pcfg_pull_none>,
4619f96204bSAurelien Jarno				/* fspi_d0 */
4629f96204bSAurelien Jarno				<1 RK_PD1 1 &pcfg_pull_none>,
4639f96204bSAurelien Jarno				/* fspi_d1 */
4649f96204bSAurelien Jarno				<1 RK_PD2 1 &pcfg_pull_none>;
4659f96204bSAurelien Jarno		};
4669f96204bSAurelien Jarno	};
4679f96204bSAurelien Jarno
468fd358326SDongjin Kim	leds {
469fd358326SDongjin Kim		led_power_pin: led-power-pin {
470fd358326SDongjin Kim			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
471fd358326SDongjin Kim		};
472fd358326SDongjin Kim		led_work_pin: led-work-pin {
473fd358326SDongjin Kim			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
474fd358326SDongjin Kim		};
475fd358326SDongjin Kim	};
476fd358326SDongjin Kim
477fd358326SDongjin Kim	pmic {
478fd358326SDongjin Kim		pmic_int_l: pmic-int-l {
479fd358326SDongjin Kim			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
480fd358326SDongjin Kim		};
481fd358326SDongjin Kim	};
48278f85844SAurelien Jarno
48378f85844SAurelien Jarno	rk809 {
48478f85844SAurelien Jarno		hp_det_pin: hp-det-pin {
48578f85844SAurelien Jarno			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
48678f85844SAurelien Jarno		};
48778f85844SAurelien Jarno	};
488*4685d7b6SAurelien Jarno
489*4685d7b6SAurelien Jarno	usb {
490*4685d7b6SAurelien Jarno		vcc5v0_usb_host_en_pin: vcc5v0-usb-host-en-pin {
491*4685d7b6SAurelien Jarno			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
492*4685d7b6SAurelien Jarno		};
493*4685d7b6SAurelien Jarno		vcc5v0_usb_otg_en_pin: vcc5v0-usb-otg-en-pin {
494*4685d7b6SAurelien Jarno			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
495*4685d7b6SAurelien Jarno		};
496*4685d7b6SAurelien Jarno	};
497fd358326SDongjin Kim};
498fd358326SDongjin Kim
499fd358326SDongjin Kim&pmu_io_domains {
500fd358326SDongjin Kim	pmuio1-supply = <&vcc3v3_pmu>;
501fd358326SDongjin Kim	pmuio2-supply = <&vcc3v3_pmu>;
502fd358326SDongjin Kim	vccio1-supply = <&vccio_acodec>;
503fd358326SDongjin Kim	vccio2-supply = <&vcc_1v8>;
504fd358326SDongjin Kim	vccio3-supply = <&vccio_sd>;
505fd358326SDongjin Kim	vccio4-supply = <&vcc_1v8>;
506fd358326SDongjin Kim	vccio5-supply = <&vcc_3v3>;
507fd358326SDongjin Kim	vccio6-supply = <&vcc_3v3>;
508fd358326SDongjin Kim	vccio7-supply = <&vcc_3v3>;
509fd358326SDongjin Kim	status = "okay";
510fd358326SDongjin Kim};
511fd358326SDongjin Kim
512fd358326SDongjin Kim&saradc {
513fd358326SDongjin Kim	vref-supply = <&vcca_1v8>;
514fd358326SDongjin Kim	status = "okay";
515fd358326SDongjin Kim};
516fd358326SDongjin Kim
517fd358326SDongjin Kim&sdhci {
518fd358326SDongjin Kim	bus-width = <8>;
519fd358326SDongjin Kim	max-frequency = <200000000>;
520fd358326SDongjin Kim	non-removable;
521fd358326SDongjin Kim	pinctrl-names = "default";
522fd358326SDongjin Kim	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>;
523fd358326SDongjin Kim	vmmc-supply = <&vcc_3v3>;
524fd358326SDongjin Kim	vqmmc-supply = <&vcc_1v8>;
525fd358326SDongjin Kim	status = "okay";
526fd358326SDongjin Kim};
527fd358326SDongjin Kim
528fd358326SDongjin Kim&sdmmc0 {
529fd358326SDongjin Kim	bus-width = <4>;
530fd358326SDongjin Kim	cap-sd-highspeed;
531fd358326SDongjin Kim	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
532fd358326SDongjin Kim	disable-wp;
533fd358326SDongjin Kim	pinctrl-names = "default";
534fd358326SDongjin Kim	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
535fd358326SDongjin Kim	sd-uhs-sdr50;
536fd358326SDongjin Kim	vmmc-supply = <&vcc3v3_sd>;
537fd358326SDongjin Kim	vqmmc-supply = <&vccio_sd>;
538fd358326SDongjin Kim	status = "okay";
539fd358326SDongjin Kim};
540fd358326SDongjin Kim
5419f96204bSAurelien Jarno&sfc {
5429f96204bSAurelien Jarno	/* Dual I/O mode as the D2 pin conflicts with the eMMC */
5439f96204bSAurelien Jarno	pinctrl-0 = <&fspi_dual_io_pins>;
5449f96204bSAurelien Jarno	pinctrl-names = "default";
5459f96204bSAurelien Jarno	#address-cells = <1>;
5469f96204bSAurelien Jarno	#size-cells = <0>;
5479f96204bSAurelien Jarno	status = "okay";
5489f96204bSAurelien Jarno
5499f96204bSAurelien Jarno	flash@0 {
5509f96204bSAurelien Jarno		compatible = "jedec,spi-nor";
5519f96204bSAurelien Jarno		reg = <0>;
5529f96204bSAurelien Jarno		spi-max-frequency = <100000000>;
5539f96204bSAurelien Jarno		spi-rx-bus-width = <2>;
5549f96204bSAurelien Jarno		spi-tx-bus-width = <1>;
5559f96204bSAurelien Jarno
5569f96204bSAurelien Jarno		partitions {
5579f96204bSAurelien Jarno			compatible = "fixed-partitions";
5589f96204bSAurelien Jarno			#address-cells = <1>;
5599f96204bSAurelien Jarno			#size-cells = <1>;
5609f96204bSAurelien Jarno
5619f96204bSAurelien Jarno			partition@0 {
5629f96204bSAurelien Jarno				label = "SPL";
5639f96204bSAurelien Jarno				reg = <0x0 0xe0000>;
5649f96204bSAurelien Jarno			};
5659f96204bSAurelien Jarno			partition@e0000 {
5669f96204bSAurelien Jarno				label = "U-Boot Env";
5679f96204bSAurelien Jarno				reg = <0xe0000 0x20000>;
5689f96204bSAurelien Jarno			};
5699f96204bSAurelien Jarno			partition@100000 {
5709f96204bSAurelien Jarno				label = "U-Boot";
5719f96204bSAurelien Jarno				reg = <0x100000 0x200000>;
5729f96204bSAurelien Jarno			};
5739f96204bSAurelien Jarno			partition@300000 {
5749f96204bSAurelien Jarno				label = "splash";
5759f96204bSAurelien Jarno				reg = <0x300000 0x100000>;
5769f96204bSAurelien Jarno			};
5779f96204bSAurelien Jarno			partition@400000 {
5789f96204bSAurelien Jarno				label = "Filesystem";
5799f96204bSAurelien Jarno				reg = <0x400000 0xc00000>;
5809f96204bSAurelien Jarno			};
5819f96204bSAurelien Jarno		};
5829f96204bSAurelien Jarno	};
5839f96204bSAurelien Jarno};
5849f96204bSAurelien Jarno
585f5511bd8SAurelien Jarno&tsadc {
586f5511bd8SAurelien Jarno	rockchip,hw-tshut-mode = <1>;
587f5511bd8SAurelien Jarno	rockchip,hw-tshut-polarity = <0>;
588f5511bd8SAurelien Jarno	status = "okay";
589f5511bd8SAurelien Jarno};
590f5511bd8SAurelien Jarno
591fd358326SDongjin Kim&uart2 {
592fd358326SDongjin Kim	status = "okay";
593fd358326SDongjin Kim};
594913404aaSAurelien Jarno
595*4685d7b6SAurelien Jarno&usb_host0_ehci {
596*4685d7b6SAurelien Jarno	status = "okay";
597*4685d7b6SAurelien Jarno};
598*4685d7b6SAurelien Jarno
599*4685d7b6SAurelien Jarno&usb_host0_ohci {
600*4685d7b6SAurelien Jarno	status = "okay";
601*4685d7b6SAurelien Jarno};
602*4685d7b6SAurelien Jarno
603*4685d7b6SAurelien Jarno&usb_host1_ehci {
604*4685d7b6SAurelien Jarno	status = "okay";
605*4685d7b6SAurelien Jarno};
606*4685d7b6SAurelien Jarno
607*4685d7b6SAurelien Jarno&usb_host1_ohci {
608*4685d7b6SAurelien Jarno	status = "okay";
609*4685d7b6SAurelien Jarno};
610*4685d7b6SAurelien Jarno
611*4685d7b6SAurelien Jarno&usb2phy1 {
612*4685d7b6SAurelien Jarno	status = "okay";
613*4685d7b6SAurelien Jarno};
614*4685d7b6SAurelien Jarno
615*4685d7b6SAurelien Jarno&usb2phy1_host {
616*4685d7b6SAurelien Jarno	phy-supply = <&vcc5v0_usb_host>;
617*4685d7b6SAurelien Jarno	status = "okay";
618*4685d7b6SAurelien Jarno};
619*4685d7b6SAurelien Jarno
620*4685d7b6SAurelien Jarno&usb2phy1_otg {
621*4685d7b6SAurelien Jarno	phy-supply = <&vcc5v0_usb_host>;
622*4685d7b6SAurelien Jarno	status = "okay";
623*4685d7b6SAurelien Jarno};
624*4685d7b6SAurelien Jarno
625913404aaSAurelien Jarno&vop {
626913404aaSAurelien Jarno	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
627913404aaSAurelien Jarno	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
628913404aaSAurelien Jarno	status = "okay";
629913404aaSAurelien Jarno};
630913404aaSAurelien Jarno
631913404aaSAurelien Jarno&vop_mmu {
632913404aaSAurelien Jarno	status = "okay";
633913404aaSAurelien Jarno};
634913404aaSAurelien Jarno
635913404aaSAurelien Jarno&vp0 {
636913404aaSAurelien Jarno	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
637913404aaSAurelien Jarno		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
638913404aaSAurelien Jarno		remote-endpoint = <&hdmi_in_vp0>;
639913404aaSAurelien Jarno	};
640913404aaSAurelien Jarno};
641