1fd358326SDongjin Kim// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2fd358326SDongjin Kim/*
3fd358326SDongjin Kim * Copyright (c) 2022 Hardkernel Co., Ltd.
4fd358326SDongjin Kim *
5fd358326SDongjin Kim */
6fd358326SDongjin Kim
7fd358326SDongjin Kim/dts-v1/;
8fd358326SDongjin Kim#include <dt-bindings/gpio/gpio.h>
9fd358326SDongjin Kim#include <dt-bindings/leds/common.h>
10fd358326SDongjin Kim#include <dt-bindings/pinctrl/rockchip.h>
11913404aaSAurelien Jarno#include <dt-bindings/soc/rockchip,vop2.h>
12fd358326SDongjin Kim#include "rk3568.dtsi"
13fd358326SDongjin Kim
14fd358326SDongjin Kim/ {
15fd358326SDongjin Kim	model = "Hardkernel ODROID-M1";
16fd358326SDongjin Kim	compatible = "rockchip,rk3568-odroid-m1", "rockchip,rk3568";
17fd358326SDongjin Kim
18fd358326SDongjin Kim	aliases {
19fd358326SDongjin Kim		ethernet0 = &gmac0;
20fd358326SDongjin Kim		i2c0 = &i2c3;
21fd358326SDongjin Kim		i2c3 = &i2c0;
22fd358326SDongjin Kim		mmc0 = &sdhci;
23fd358326SDongjin Kim		mmc1 = &sdmmc0;
24fd358326SDongjin Kim		serial0 = &uart1;
25fd358326SDongjin Kim		serial1 = &uart0;
26fd358326SDongjin Kim	};
27fd358326SDongjin Kim
28fd358326SDongjin Kim	chosen {
29fd358326SDongjin Kim		stdout-path = "serial2:1500000n8";
30fd358326SDongjin Kim	};
31fd358326SDongjin Kim
32fd358326SDongjin Kim	dc_12v: dc-12v-regulator {
33fd358326SDongjin Kim		compatible = "regulator-fixed";
34fd358326SDongjin Kim		regulator-name = "dc_12v";
35fd358326SDongjin Kim		regulator-always-on;
36fd358326SDongjin Kim		regulator-boot-on;
37fd358326SDongjin Kim		regulator-min-microvolt = <12000000>;
38fd358326SDongjin Kim		regulator-max-microvolt = <12000000>;
39fd358326SDongjin Kim	};
40fd358326SDongjin Kim
41913404aaSAurelien Jarno	hdmi-con {
42913404aaSAurelien Jarno		compatible = "hdmi-connector";
43913404aaSAurelien Jarno		type = "a";
44913404aaSAurelien Jarno
45913404aaSAurelien Jarno		port {
46913404aaSAurelien Jarno			hdmi_con_in: endpoint {
47913404aaSAurelien Jarno				remote-endpoint = <&hdmi_out_con>;
48913404aaSAurelien Jarno			};
49913404aaSAurelien Jarno		};
50913404aaSAurelien Jarno	};
51913404aaSAurelien Jarno
52fd358326SDongjin Kim	leds {
53fd358326SDongjin Kim		compatible = "gpio-leds";
54fd358326SDongjin Kim
55fd358326SDongjin Kim		led_power: led-0 {
56fd358326SDongjin Kim			gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
57fd358326SDongjin Kim			function = LED_FUNCTION_POWER;
58fd358326SDongjin Kim			color = <LED_COLOR_ID_RED>;
59fd358326SDongjin Kim			default-state = "keep";
60fd358326SDongjin Kim			linux,default-trigger = "default-on";
61fd358326SDongjin Kim			pinctrl-names = "default";
62fd358326SDongjin Kim			pinctrl-0 = <&led_power_pin>;
63fd358326SDongjin Kim		};
64fd358326SDongjin Kim		led_work: led-1 {
65fd358326SDongjin Kim			gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
66fd358326SDongjin Kim			function = LED_FUNCTION_HEARTBEAT;
67fd358326SDongjin Kim			color = <LED_COLOR_ID_BLUE>;
68fd358326SDongjin Kim			linux,default-trigger = "heartbeat";
69fd358326SDongjin Kim			pinctrl-names = "default";
70fd358326SDongjin Kim			pinctrl-0 = <&led_work_pin>;
71fd358326SDongjin Kim		};
72fd358326SDongjin Kim	};
73fd358326SDongjin Kim
7478f85844SAurelien Jarno	rk809-sound {
7578f85844SAurelien Jarno		compatible = "simple-audio-card";
7678f85844SAurelien Jarno		pinctrl-names = "default";
7778f85844SAurelien Jarno		pinctrl-0 = <&hp_det_pin>;
7878f85844SAurelien Jarno		simple-audio-card,name = "Analog RK817";
7978f85844SAurelien Jarno		simple-audio-card,format = "i2s";
8078f85844SAurelien Jarno		simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
8178f85844SAurelien Jarno		simple-audio-card,mclk-fs = <256>;
8278f85844SAurelien Jarno		simple-audio-card,widgets =
8378f85844SAurelien Jarno			"Headphone", "Headphones",
8478f85844SAurelien Jarno			"Speaker", "Speaker";
8578f85844SAurelien Jarno		simple-audio-card,routing =
8678f85844SAurelien Jarno			"Headphones", "HPOL",
8778f85844SAurelien Jarno			"Headphones", "HPOR",
8878f85844SAurelien Jarno			"Speaker", "SPKO";
8978f85844SAurelien Jarno
9078f85844SAurelien Jarno		simple-audio-card,cpu {
9178f85844SAurelien Jarno			sound-dai = <&i2s1_8ch>;
9278f85844SAurelien Jarno		};
9378f85844SAurelien Jarno
9478f85844SAurelien Jarno		simple-audio-card,codec {
9578f85844SAurelien Jarno			sound-dai = <&rk809>;
9678f85844SAurelien Jarno		};
9778f85844SAurelien Jarno	};
9878f85844SAurelien Jarno
99*35b28582SAurelien Jarno	vcc3v3_pcie: vcc3v3-pcie-regulator {
100*35b28582SAurelien Jarno		compatible = "regulator-fixed";
101*35b28582SAurelien Jarno		regulator-name = "vcc3v3_pcie";
102*35b28582SAurelien Jarno		enable-active-high;
103*35b28582SAurelien Jarno		gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
104*35b28582SAurelien Jarno		pinctrl-names = "default";
105*35b28582SAurelien Jarno		pinctrl-0 = <&vcc3v3_pcie_en_pin>;
106*35b28582SAurelien Jarno		regulator-min-microvolt = <3300000>;
107*35b28582SAurelien Jarno		regulator-max-microvolt = <3300000>;
108*35b28582SAurelien Jarno		startup-delay-us = <5000>;
109*35b28582SAurelien Jarno		vin-supply = <&vcc3v3_sys>;
110*35b28582SAurelien Jarno	};
111*35b28582SAurelien Jarno
112fd358326SDongjin Kim	vcc3v3_sys: vcc3v3-sys-regulator {
113fd358326SDongjin Kim		compatible = "regulator-fixed";
114fd358326SDongjin Kim		regulator-name = "vcc3v3_sys";
115fd358326SDongjin Kim		regulator-always-on;
116fd358326SDongjin Kim		regulator-boot-on;
117fd358326SDongjin Kim		regulator-min-microvolt = <3300000>;
118fd358326SDongjin Kim		regulator-max-microvolt = <3300000>;
119fd358326SDongjin Kim		vin-supply = <&dc_12v>;
120fd358326SDongjin Kim	};
1214685d7b6SAurelien Jarno
1224685d7b6SAurelien Jarno	vcc5v0_sys: vcc5v0-sys-regulator {
1234685d7b6SAurelien Jarno		compatible = "regulator-fixed";
1244685d7b6SAurelien Jarno		regulator-name = "vcc5v0_sys";
1254685d7b6SAurelien Jarno		regulator-always-on;
1264685d7b6SAurelien Jarno		regulator-boot-on;
1274685d7b6SAurelien Jarno		regulator-min-microvolt = <5000000>;
1284685d7b6SAurelien Jarno		regulator-max-microvolt = <5000000>;
1294685d7b6SAurelien Jarno		vin-supply = <&dc_12v>;
1304685d7b6SAurelien Jarno	};
1314685d7b6SAurelien Jarno
1324685d7b6SAurelien Jarno	vcc5v0_usb_host: vcc5v0-usb-host-regulator {
1334685d7b6SAurelien Jarno		compatible = "regulator-fixed";
1344685d7b6SAurelien Jarno		regulator-name = "vcc5v0_usb_host";
1354685d7b6SAurelien Jarno		enable-active-high;
1364685d7b6SAurelien Jarno		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
1374685d7b6SAurelien Jarno		pinctrl-names = "default";
1384685d7b6SAurelien Jarno		pinctrl-0 = <&vcc5v0_usb_host_en_pin>;
1394685d7b6SAurelien Jarno		regulator-min-microvolt = <5000000>;
1404685d7b6SAurelien Jarno		regulator-max-microvolt = <5000000>;
1414685d7b6SAurelien Jarno		vin-supply = <&vcc5v0_sys>;
1424685d7b6SAurelien Jarno	};
1439984ef56SAurelien Jarno
1449984ef56SAurelien Jarno	vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
1459984ef56SAurelien Jarno		compatible = "regulator-fixed";
1469984ef56SAurelien Jarno		regulator-name = "vcc5v0_usb_otg";
1479984ef56SAurelien Jarno		enable-active-high;
1489984ef56SAurelien Jarno		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
1499984ef56SAurelien Jarno		pinctrl-names = "default";
1509984ef56SAurelien Jarno		pinctrl-0 = <&vcc5v0_usb_otg_en_pin>;
1519984ef56SAurelien Jarno		regulator-min-microvolt = <5000000>;
1529984ef56SAurelien Jarno		regulator-max-microvolt = <5000000>;
1539984ef56SAurelien Jarno		vin-supply = <&vcc5v0_sys>;
1549984ef56SAurelien Jarno	};
1559984ef56SAurelien Jarno};
1569984ef56SAurelien Jarno
1579984ef56SAurelien Jarno&combphy0 {
1589984ef56SAurelien Jarno	/* Used for USB3 */
1599984ef56SAurelien Jarno	phy-supply = <&vcc5v0_usb_host>;
1609984ef56SAurelien Jarno	status = "okay";
1619984ef56SAurelien Jarno};
1629984ef56SAurelien Jarno
1639984ef56SAurelien Jarno&combphy1 {
1649984ef56SAurelien Jarno	/* Used for USB3 */
1659984ef56SAurelien Jarno	phy-supply = <&vcc5v0_usb_otg>;
1669984ef56SAurelien Jarno	status = "okay";
167fd358326SDongjin Kim};
168fd358326SDongjin Kim
1696a5a04d5SAurelien Jarno&combphy2 {
1706a5a04d5SAurelien Jarno	/* used for SATA */
1716a5a04d5SAurelien Jarno	status = "okay";
1726a5a04d5SAurelien Jarno};
1736a5a04d5SAurelien Jarno
174fd358326SDongjin Kim&cpu0 {
175fd358326SDongjin Kim	cpu-supply = <&vdd_cpu>;
176fd358326SDongjin Kim};
177fd358326SDongjin Kim
178fd358326SDongjin Kim&cpu1 {
179fd358326SDongjin Kim	cpu-supply = <&vdd_cpu>;
180fd358326SDongjin Kim};
181fd358326SDongjin Kim
182fd358326SDongjin Kim&cpu2 {
183fd358326SDongjin Kim	cpu-supply = <&vdd_cpu>;
184fd358326SDongjin Kim};
185fd358326SDongjin Kim
186fd358326SDongjin Kim&cpu3 {
187fd358326SDongjin Kim	cpu-supply = <&vdd_cpu>;
188fd358326SDongjin Kim};
189fd358326SDongjin Kim
190fd358326SDongjin Kim&gmac0 {
191fd358326SDongjin Kim	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
192fd358326SDongjin Kim	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
193fd358326SDongjin Kim	assigned-clock-rates = <0>, <125000000>;
194fd358326SDongjin Kim	clock_in_out = "output";
195fd358326SDongjin Kim	phy-handle = <&rgmii_phy0>;
196fd358326SDongjin Kim	phy-mode = "rgmii";
197fd358326SDongjin Kim	phy-supply = <&vcc3v3_sys>;
198fd358326SDongjin Kim	pinctrl-names = "default";
199fd358326SDongjin Kim	pinctrl-0 = <&gmac0_miim
200fd358326SDongjin Kim		     &gmac0_tx_bus2
201fd358326SDongjin Kim		     &gmac0_rx_bus2
202fd358326SDongjin Kim		     &gmac0_rgmii_clk
203fd358326SDongjin Kim		     &gmac0_rgmii_bus>;
204fd358326SDongjin Kim	status = "okay";
205fd358326SDongjin Kim
206fd358326SDongjin Kim	tx_delay = <0x4f>;
207fd358326SDongjin Kim	rx_delay = <0x2d>;
208fd358326SDongjin Kim};
209fd358326SDongjin Kim
210cb80b345SAurelien Jarno&gpu {
211cb80b345SAurelien Jarno	mali-supply = <&vdd_gpu>;
212cb80b345SAurelien Jarno	status = "okay";
213cb80b345SAurelien Jarno};
214cb80b345SAurelien Jarno
215913404aaSAurelien Jarno&hdmi {
216913404aaSAurelien Jarno	avdd-0v9-supply = <&vdda0v9_image>;
217913404aaSAurelien Jarno	avdd-1v8-supply = <&vcca1v8_image>;
218913404aaSAurelien Jarno	status = "okay";
219913404aaSAurelien Jarno};
220913404aaSAurelien Jarno
221913404aaSAurelien Jarno&hdmi_in {
222913404aaSAurelien Jarno	hdmi_in_vp0: endpoint {
223913404aaSAurelien Jarno		remote-endpoint = <&vp0_out_hdmi>;
224913404aaSAurelien Jarno	};
225913404aaSAurelien Jarno};
226913404aaSAurelien Jarno
227913404aaSAurelien Jarno&hdmi_out {
228913404aaSAurelien Jarno	hdmi_out_con: endpoint {
229913404aaSAurelien Jarno		remote-endpoint = <&hdmi_con_in>;
230913404aaSAurelien Jarno	};
231913404aaSAurelien Jarno};
232913404aaSAurelien Jarno
2331ca7ddddSAurelien Jarno&hdmi_sound {
2341ca7ddddSAurelien Jarno	status = "okay";
2351ca7ddddSAurelien Jarno};
2361ca7ddddSAurelien Jarno
237fd358326SDongjin Kim&i2c0 {
238fd358326SDongjin Kim	status = "okay";
239fd358326SDongjin Kim
240fd358326SDongjin Kim	vdd_cpu: regulator@1c {
241fd358326SDongjin Kim		compatible = "tcs,tcs4525";
242fd358326SDongjin Kim		reg = <0x1c>;
243fd358326SDongjin Kim		fcs,suspend-voltage-selector = <1>;
244fd358326SDongjin Kim		regulator-name = "vdd_cpu";
245fd358326SDongjin Kim		regulator-always-on;
246fd358326SDongjin Kim		regulator-boot-on;
247fd358326SDongjin Kim		regulator-min-microvolt = <800000>;
248fd358326SDongjin Kim		regulator-max-microvolt = <1150000>;
249fd358326SDongjin Kim		regulator-ramp-delay = <2300>;
250fd358326SDongjin Kim		vin-supply = <&vcc3v3_sys>;
251fd358326SDongjin Kim
252fd358326SDongjin Kim		regulator-state-mem {
253fd358326SDongjin Kim			regulator-off-in-suspend;
254fd358326SDongjin Kim		};
255fd358326SDongjin Kim	};
256fd358326SDongjin Kim
257fd358326SDongjin Kim	rk809: pmic@20 {
258fd358326SDongjin Kim		compatible = "rockchip,rk809";
259fd358326SDongjin Kim		reg = <0x20>;
260fd358326SDongjin Kim		interrupt-parent = <&gpio0>;
261fd358326SDongjin Kim		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
26278f85844SAurelien Jarno		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
26378f85844SAurelien Jarno		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
264fd358326SDongjin Kim		#clock-cells = <1>;
26578f85844SAurelien Jarno		clock-names = "mclk";
26678f85844SAurelien Jarno		clocks = <&cru I2S1_MCLKOUT_TX>;
267fd358326SDongjin Kim		pinctrl-names = "default";
26878f85844SAurelien Jarno		pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
269fd358326SDongjin Kim		rockchip,system-power-controller;
27078f85844SAurelien Jarno		#sound-dai-cells = <0>;
271fd358326SDongjin Kim		vcc1-supply = <&vcc3v3_sys>;
272fd358326SDongjin Kim		vcc2-supply = <&vcc3v3_sys>;
273fd358326SDongjin Kim		vcc3-supply = <&vcc3v3_sys>;
274fd358326SDongjin Kim		vcc4-supply = <&vcc3v3_sys>;
275fd358326SDongjin Kim		vcc5-supply = <&vcc3v3_sys>;
276fd358326SDongjin Kim		vcc6-supply = <&vcc3v3_sys>;
277fd358326SDongjin Kim		vcc7-supply = <&vcc3v3_sys>;
278fd358326SDongjin Kim		vcc8-supply = <&vcc3v3_sys>;
279fd358326SDongjin Kim		vcc9-supply = <&vcc3v3_sys>;
280fd358326SDongjin Kim		wakeup-source;
281fd358326SDongjin Kim
282fd358326SDongjin Kim		regulators {
283fd358326SDongjin Kim			vdd_logic: DCDC_REG1 {
284fd358326SDongjin Kim				regulator-name = "vdd_logic";
285fd358326SDongjin Kim				regulator-always-on;
286fd358326SDongjin Kim				regulator-boot-on;
287fd358326SDongjin Kim				regulator-init-microvolt = <900000>;
288fd358326SDongjin Kim				regulator-initial-mode = <0x2>;
289fd358326SDongjin Kim				regulator-min-microvolt = <500000>;
290fd358326SDongjin Kim				regulator-max-microvolt = <1350000>;
291fd358326SDongjin Kim				regulator-ramp-delay = <6001>;
292fd358326SDongjin Kim
293fd358326SDongjin Kim				regulator-state-mem {
294fd358326SDongjin Kim					regulator-off-in-suspend;
295fd358326SDongjin Kim				};
296fd358326SDongjin Kim			};
297fd358326SDongjin Kim
298fd358326SDongjin Kim			vdd_gpu: DCDC_REG2 {
299fd358326SDongjin Kim				regulator-name = "vdd_gpu";
300fd358326SDongjin Kim				regulator-always-on;
301fd358326SDongjin Kim				regulator-init-microvolt = <900000>;
302fd358326SDongjin Kim				regulator-initial-mode = <0x2>;
303fd358326SDongjin Kim				regulator-min-microvolt = <500000>;
304fd358326SDongjin Kim				regulator-max-microvolt = <1350000>;
305fd358326SDongjin Kim				regulator-ramp-delay = <6001>;
306fd358326SDongjin Kim
307fd358326SDongjin Kim				regulator-state-mem {
308fd358326SDongjin Kim					regulator-off-in-suspend;
309fd358326SDongjin Kim				};
310fd358326SDongjin Kim			};
311fd358326SDongjin Kim
312fd358326SDongjin Kim			vcc_ddr: DCDC_REG3 {
313fd358326SDongjin Kim				regulator-name = "vcc_ddr";
314fd358326SDongjin Kim				regulator-always-on;
315fd358326SDongjin Kim				regulator-boot-on;
316fd358326SDongjin Kim				regulator-initial-mode = <0x2>;
317fd358326SDongjin Kim
318fd358326SDongjin Kim				regulator-state-mem {
319fd358326SDongjin Kim					regulator-on-in-suspend;
320fd358326SDongjin Kim				};
321fd358326SDongjin Kim			};
322fd358326SDongjin Kim
323fd358326SDongjin Kim			vdd_npu: DCDC_REG4 {
324fd358326SDongjin Kim				regulator-name = "vdd_npu";
325fd358326SDongjin Kim				regulator-init-microvolt = <900000>;
326fd358326SDongjin Kim				regulator-initial-mode = <0x2>;
327fd358326SDongjin Kim				regulator-min-microvolt = <500000>;
328fd358326SDongjin Kim				regulator-max-microvolt = <1350000>;
329fd358326SDongjin Kim				regulator-ramp-delay = <6001>;
330fd358326SDongjin Kim
331fd358326SDongjin Kim				regulator-state-mem {
332fd358326SDongjin Kim					regulator-off-in-suspend;
333fd358326SDongjin Kim				};
334fd358326SDongjin Kim			};
335fd358326SDongjin Kim
336fd358326SDongjin Kim			vcc_1v8: DCDC_REG5 {
337fd358326SDongjin Kim				regulator-name = "vcc_1v8";
338fd358326SDongjin Kim				regulator-always-on;
339fd358326SDongjin Kim				regulator-boot-on;
340fd358326SDongjin Kim				regulator-min-microvolt = <1800000>;
341fd358326SDongjin Kim				regulator-max-microvolt = <1800000>;
342fd358326SDongjin Kim
343fd358326SDongjin Kim				regulator-state-mem {
344fd358326SDongjin Kim					regulator-off-in-suspend;
345fd358326SDongjin Kim				};
346fd358326SDongjin Kim			};
347fd358326SDongjin Kim
348fd358326SDongjin Kim			vdda0v9_image: LDO_REG1 {
349fd358326SDongjin Kim				regulator-name = "vdda0v9_image";
350fd358326SDongjin Kim				regulator-always-on;
351fd358326SDongjin Kim				regulator-min-microvolt = <900000>;
352fd358326SDongjin Kim				regulator-max-microvolt = <900000>;
353fd358326SDongjin Kim
354fd358326SDongjin Kim				regulator-state-mem {
355fd358326SDongjin Kim					regulator-off-in-suspend;
356fd358326SDongjin Kim				};
357fd358326SDongjin Kim			};
358fd358326SDongjin Kim
359fd358326SDongjin Kim			vdda_0v9: LDO_REG2 {
360fd358326SDongjin Kim				regulator-name = "vdda_0v9";
361fd358326SDongjin Kim				regulator-always-on;
362fd358326SDongjin Kim				regulator-boot-on;
363fd358326SDongjin Kim				regulator-min-microvolt = <900000>;
364fd358326SDongjin Kim				regulator-max-microvolt = <900000>;
365fd358326SDongjin Kim
366fd358326SDongjin Kim				regulator-state-mem {
367fd358326SDongjin Kim					regulator-off-in-suspend;
368fd358326SDongjin Kim				};
369fd358326SDongjin Kim			};
370fd358326SDongjin Kim
371fd358326SDongjin Kim			vdda0v9_pmu: LDO_REG3 {
372fd358326SDongjin Kim				regulator-name = "vdda0v9_pmu";
373fd358326SDongjin Kim				regulator-always-on;
374fd358326SDongjin Kim				regulator-boot-on;
375fd358326SDongjin Kim				regulator-min-microvolt = <900000>;
376fd358326SDongjin Kim				regulator-max-microvolt = <900000>;
377fd358326SDongjin Kim
378fd358326SDongjin Kim				regulator-state-mem {
379fd358326SDongjin Kim					regulator-on-in-suspend;
380fd358326SDongjin Kim					regulator-suspend-microvolt = <900000>;
381fd358326SDongjin Kim				};
382fd358326SDongjin Kim			};
383fd358326SDongjin Kim
384fd358326SDongjin Kim			vccio_acodec: LDO_REG4 {
385fd358326SDongjin Kim				regulator-name = "vccio_acodec";
386fd358326SDongjin Kim				regulator-always-on;
387fd358326SDongjin Kim				regulator-boot-on;
388fd358326SDongjin Kim				regulator-min-microvolt = <3300000>;
389fd358326SDongjin Kim				regulator-max-microvolt = <3300000>;
390fd358326SDongjin Kim
391fd358326SDongjin Kim				regulator-state-mem {
392fd358326SDongjin Kim					regulator-off-in-suspend;
393fd358326SDongjin Kim				};
394fd358326SDongjin Kim			};
395fd358326SDongjin Kim
396fd358326SDongjin Kim			vccio_sd: LDO_REG5 {
397fd358326SDongjin Kim				regulator-name = "vccio_sd";
398fd358326SDongjin Kim				regulator-min-microvolt = <1800000>;
399fd358326SDongjin Kim				regulator-max-microvolt = <3300000>;
400fd358326SDongjin Kim
401fd358326SDongjin Kim				regulator-state-mem {
402fd358326SDongjin Kim					regulator-off-in-suspend;
403fd358326SDongjin Kim				};
404fd358326SDongjin Kim			};
405fd358326SDongjin Kim
406fd358326SDongjin Kim			vcc3v3_pmu: LDO_REG6 {
407fd358326SDongjin Kim				regulator-name = "vcc3v3_pmu";
408fd358326SDongjin Kim				regulator-always-on;
409fd358326SDongjin Kim				regulator-boot-on;
410fd358326SDongjin Kim				regulator-min-microvolt = <3300000>;
411fd358326SDongjin Kim				regulator-max-microvolt = <3300000>;
412fd358326SDongjin Kim
413fd358326SDongjin Kim				regulator-state-mem {
414fd358326SDongjin Kim					regulator-on-in-suspend;
415fd358326SDongjin Kim					regulator-suspend-microvolt = <3300000>;
416fd358326SDongjin Kim				};
417fd358326SDongjin Kim			};
418fd358326SDongjin Kim
419fd358326SDongjin Kim			vcca_1v8: LDO_REG7 {
420fd358326SDongjin Kim				regulator-name = "vcca_1v8";
421fd358326SDongjin Kim				regulator-always-on;
422fd358326SDongjin Kim				regulator-boot-on;
423fd358326SDongjin Kim				regulator-min-microvolt = <1800000>;
424fd358326SDongjin Kim				regulator-max-microvolt = <1800000>;
425fd358326SDongjin Kim
426fd358326SDongjin Kim				regulator-state-mem {
427fd358326SDongjin Kim					regulator-off-in-suspend;
428fd358326SDongjin Kim				};
429fd358326SDongjin Kim			};
430fd358326SDongjin Kim
431fd358326SDongjin Kim			vcca1v8_pmu: LDO_REG8 {
432fd358326SDongjin Kim				regulator-name = "vcca1v8_pmu";
433fd358326SDongjin Kim				regulator-always-on;
434fd358326SDongjin Kim				regulator-boot-on;
435fd358326SDongjin Kim				regulator-min-microvolt = <1800000>;
436fd358326SDongjin Kim				regulator-max-microvolt = <1800000>;
437fd358326SDongjin Kim
438fd358326SDongjin Kim				regulator-state-mem {
439fd358326SDongjin Kim					regulator-on-in-suspend;
440fd358326SDongjin Kim					regulator-suspend-microvolt = <1800000>;
441fd358326SDongjin Kim				};
442fd358326SDongjin Kim			};
443fd358326SDongjin Kim
444fd358326SDongjin Kim			vcca1v8_image: LDO_REG9 {
445fd358326SDongjin Kim				regulator-name = "vcca1v8_image";
446fd358326SDongjin Kim				regulator-always-on;
447fd358326SDongjin Kim				regulator-min-microvolt = <1800000>;
448fd358326SDongjin Kim				regulator-max-microvolt = <1800000>;
449fd358326SDongjin Kim
450fd358326SDongjin Kim				regulator-state-mem {
451fd358326SDongjin Kim					regulator-off-in-suspend;
452fd358326SDongjin Kim				};
453fd358326SDongjin Kim			};
454fd358326SDongjin Kim
455fd358326SDongjin Kim			vcc_3v3: SWITCH_REG1 {
456fd358326SDongjin Kim				regulator-name = "vcc_3v3";
457fd358326SDongjin Kim				regulator-always-on;
458fd358326SDongjin Kim				regulator-boot-on;
459fd358326SDongjin Kim
460fd358326SDongjin Kim				regulator-state-mem {
461fd358326SDongjin Kim					regulator-off-in-suspend;
462fd358326SDongjin Kim				};
463fd358326SDongjin Kim			};
464fd358326SDongjin Kim
465fd358326SDongjin Kim			vcc3v3_sd: SWITCH_REG2 {
466fd358326SDongjin Kim				regulator-name = "vcc3v3_sd";
467fd358326SDongjin Kim
468fd358326SDongjin Kim				regulator-state-mem {
469fd358326SDongjin Kim					regulator-off-in-suspend;
470fd358326SDongjin Kim				};
471fd358326SDongjin Kim			};
472fd358326SDongjin Kim		};
473fd358326SDongjin Kim	};
474fd358326SDongjin Kim};
475fd358326SDongjin Kim
4761ca7ddddSAurelien Jarno&i2s0_8ch {
4771ca7ddddSAurelien Jarno	status = "okay";
4781ca7ddddSAurelien Jarno};
4791ca7ddddSAurelien Jarno
48078f85844SAurelien Jarno&i2s1_8ch {
48178f85844SAurelien Jarno	rockchip,trcm-sync-tx-only;
48278f85844SAurelien Jarno	status = "okay";
48378f85844SAurelien Jarno};
48478f85844SAurelien Jarno
485fd358326SDongjin Kim&mdio0 {
486fd358326SDongjin Kim	rgmii_phy0: ethernet-phy@0 {
487fd358326SDongjin Kim		compatible = "ethernet-phy-ieee802.3-c22";
488fd358326SDongjin Kim		reg = <0x0>;
489fd358326SDongjin Kim		reset-assert-us = <20000>;
490fd358326SDongjin Kim		reset-deassert-us = <100000>;
491fd358326SDongjin Kim		reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
492fd358326SDongjin Kim	};
493fd358326SDongjin Kim};
494fd358326SDongjin Kim
495*35b28582SAurelien Jarno&pcie30phy {
496*35b28582SAurelien Jarno	status = "okay";
497*35b28582SAurelien Jarno};
498*35b28582SAurelien Jarno
499*35b28582SAurelien Jarno&pcie3x2 {
500*35b28582SAurelien Jarno	pinctrl-names = "default";
501*35b28582SAurelien Jarno	pinctrl-0 = <&pcie_reset_pin>;
502*35b28582SAurelien Jarno	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
503*35b28582SAurelien Jarno	vpcie3v3-supply = <&vcc3v3_pcie>;
504*35b28582SAurelien Jarno	status = "okay";
505*35b28582SAurelien Jarno};
506*35b28582SAurelien Jarno
507fd358326SDongjin Kim&pinctrl {
5089f96204bSAurelien Jarno	fspi {
5099f96204bSAurelien Jarno		fspi_dual_io_pins: fspi-dual-io-pins {
5109f96204bSAurelien Jarno			rockchip,pins =
5119f96204bSAurelien Jarno				/* fspi_clk */
5129f96204bSAurelien Jarno				<1 RK_PD0 1 &pcfg_pull_none>,
5139f96204bSAurelien Jarno				/* fspi_cs0n */
5149f96204bSAurelien Jarno				<1 RK_PD3 1 &pcfg_pull_none>,
5159f96204bSAurelien Jarno				/* fspi_d0 */
5169f96204bSAurelien Jarno				<1 RK_PD1 1 &pcfg_pull_none>,
5179f96204bSAurelien Jarno				/* fspi_d1 */
5189f96204bSAurelien Jarno				<1 RK_PD2 1 &pcfg_pull_none>;
5199f96204bSAurelien Jarno		};
5209f96204bSAurelien Jarno	};
5219f96204bSAurelien Jarno
522fd358326SDongjin Kim	leds {
523fd358326SDongjin Kim		led_power_pin: led-power-pin {
524fd358326SDongjin Kim			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
525fd358326SDongjin Kim		};
526fd358326SDongjin Kim		led_work_pin: led-work-pin {
527fd358326SDongjin Kim			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
528fd358326SDongjin Kim		};
529fd358326SDongjin Kim	};
530fd358326SDongjin Kim
531*35b28582SAurelien Jarno	pcie {
532*35b28582SAurelien Jarno		pcie_reset_pin: pcie-reset-pin {
533*35b28582SAurelien Jarno			rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
534*35b28582SAurelien Jarno		};
535*35b28582SAurelien Jarno		vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin {
536*35b28582SAurelien Jarno			rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
537*35b28582SAurelien Jarno		};
538*35b28582SAurelien Jarno	};
539*35b28582SAurelien Jarno
540fd358326SDongjin Kim	pmic {
541fd358326SDongjin Kim		pmic_int_l: pmic-int-l {
542fd358326SDongjin Kim			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
543fd358326SDongjin Kim		};
544fd358326SDongjin Kim	};
54578f85844SAurelien Jarno
54678f85844SAurelien Jarno	rk809 {
54778f85844SAurelien Jarno		hp_det_pin: hp-det-pin {
54878f85844SAurelien Jarno			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
54978f85844SAurelien Jarno		};
55078f85844SAurelien Jarno	};
5514685d7b6SAurelien Jarno
5524685d7b6SAurelien Jarno	usb {
5534685d7b6SAurelien Jarno		vcc5v0_usb_host_en_pin: vcc5v0-usb-host-en-pin {
5544685d7b6SAurelien Jarno			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
5554685d7b6SAurelien Jarno		};
5569984ef56SAurelien Jarno		vcc5v0_usb_otg_en_pin: vcc5v0-usb-dr-en-pin {
5574685d7b6SAurelien Jarno			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
5584685d7b6SAurelien Jarno		};
5594685d7b6SAurelien Jarno	};
560fd358326SDongjin Kim};
561fd358326SDongjin Kim
562fd358326SDongjin Kim&pmu_io_domains {
563fd358326SDongjin Kim	pmuio1-supply = <&vcc3v3_pmu>;
564fd358326SDongjin Kim	pmuio2-supply = <&vcc3v3_pmu>;
565fd358326SDongjin Kim	vccio1-supply = <&vccio_acodec>;
566fd358326SDongjin Kim	vccio2-supply = <&vcc_1v8>;
567fd358326SDongjin Kim	vccio3-supply = <&vccio_sd>;
568fd358326SDongjin Kim	vccio4-supply = <&vcc_1v8>;
569fd358326SDongjin Kim	vccio5-supply = <&vcc_3v3>;
570fd358326SDongjin Kim	vccio6-supply = <&vcc_3v3>;
571fd358326SDongjin Kim	vccio7-supply = <&vcc_3v3>;
572fd358326SDongjin Kim	status = "okay";
573fd358326SDongjin Kim};
574fd358326SDongjin Kim
575fd358326SDongjin Kim&saradc {
576fd358326SDongjin Kim	vref-supply = <&vcca_1v8>;
577fd358326SDongjin Kim	status = "okay";
578fd358326SDongjin Kim};
579fd358326SDongjin Kim
5806a5a04d5SAurelien Jarno&sata2 {
5816a5a04d5SAurelien Jarno	status = "okay";
5826a5a04d5SAurelien Jarno};
5836a5a04d5SAurelien Jarno
584fd358326SDongjin Kim&sdhci {
585fd358326SDongjin Kim	bus-width = <8>;
586fd358326SDongjin Kim	max-frequency = <200000000>;
587fd358326SDongjin Kim	non-removable;
588fd358326SDongjin Kim	pinctrl-names = "default";
589fd358326SDongjin Kim	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>;
590fd358326SDongjin Kim	vmmc-supply = <&vcc_3v3>;
591fd358326SDongjin Kim	vqmmc-supply = <&vcc_1v8>;
592fd358326SDongjin Kim	status = "okay";
593fd358326SDongjin Kim};
594fd358326SDongjin Kim
595fd358326SDongjin Kim&sdmmc0 {
596fd358326SDongjin Kim	bus-width = <4>;
597fd358326SDongjin Kim	cap-sd-highspeed;
598fd358326SDongjin Kim	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
599fd358326SDongjin Kim	disable-wp;
600fd358326SDongjin Kim	pinctrl-names = "default";
601fd358326SDongjin Kim	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
602fd358326SDongjin Kim	sd-uhs-sdr50;
603fd358326SDongjin Kim	vmmc-supply = <&vcc3v3_sd>;
604fd358326SDongjin Kim	vqmmc-supply = <&vccio_sd>;
605fd358326SDongjin Kim	status = "okay";
606fd358326SDongjin Kim};
607fd358326SDongjin Kim
6089f96204bSAurelien Jarno&sfc {
6099f96204bSAurelien Jarno	/* Dual I/O mode as the D2 pin conflicts with the eMMC */
6109f96204bSAurelien Jarno	pinctrl-0 = <&fspi_dual_io_pins>;
6119f96204bSAurelien Jarno	pinctrl-names = "default";
6129f96204bSAurelien Jarno	#address-cells = <1>;
6139f96204bSAurelien Jarno	#size-cells = <0>;
6149f96204bSAurelien Jarno	status = "okay";
6159f96204bSAurelien Jarno
6169f96204bSAurelien Jarno	flash@0 {
6179f96204bSAurelien Jarno		compatible = "jedec,spi-nor";
6189f96204bSAurelien Jarno		reg = <0>;
6199f96204bSAurelien Jarno		spi-max-frequency = <100000000>;
6209f96204bSAurelien Jarno		spi-rx-bus-width = <2>;
6219f96204bSAurelien Jarno		spi-tx-bus-width = <1>;
6229f96204bSAurelien Jarno
6239f96204bSAurelien Jarno		partitions {
6249f96204bSAurelien Jarno			compatible = "fixed-partitions";
6259f96204bSAurelien Jarno			#address-cells = <1>;
6269f96204bSAurelien Jarno			#size-cells = <1>;
6279f96204bSAurelien Jarno
6289f96204bSAurelien Jarno			partition@0 {
6299f96204bSAurelien Jarno				label = "SPL";
6309f96204bSAurelien Jarno				reg = <0x0 0xe0000>;
6319f96204bSAurelien Jarno			};
6329f96204bSAurelien Jarno			partition@e0000 {
6339f96204bSAurelien Jarno				label = "U-Boot Env";
6349f96204bSAurelien Jarno				reg = <0xe0000 0x20000>;
6359f96204bSAurelien Jarno			};
6369f96204bSAurelien Jarno			partition@100000 {
6379f96204bSAurelien Jarno				label = "U-Boot";
6389f96204bSAurelien Jarno				reg = <0x100000 0x200000>;
6399f96204bSAurelien Jarno			};
6409f96204bSAurelien Jarno			partition@300000 {
6419f96204bSAurelien Jarno				label = "splash";
6429f96204bSAurelien Jarno				reg = <0x300000 0x100000>;
6439f96204bSAurelien Jarno			};
6449f96204bSAurelien Jarno			partition@400000 {
6459f96204bSAurelien Jarno				label = "Filesystem";
6469f96204bSAurelien Jarno				reg = <0x400000 0xc00000>;
6479f96204bSAurelien Jarno			};
6489f96204bSAurelien Jarno		};
6499f96204bSAurelien Jarno	};
6509f96204bSAurelien Jarno};
6519f96204bSAurelien Jarno
652f5511bd8SAurelien Jarno&tsadc {
653f5511bd8SAurelien Jarno	rockchip,hw-tshut-mode = <1>;
654f5511bd8SAurelien Jarno	rockchip,hw-tshut-polarity = <0>;
655f5511bd8SAurelien Jarno	status = "okay";
656f5511bd8SAurelien Jarno};
657f5511bd8SAurelien Jarno
658fd358326SDongjin Kim&uart2 {
659fd358326SDongjin Kim	status = "okay";
660fd358326SDongjin Kim};
661913404aaSAurelien Jarno
6624685d7b6SAurelien Jarno&usb_host0_ehci {
6634685d7b6SAurelien Jarno	status = "okay";
6644685d7b6SAurelien Jarno};
6654685d7b6SAurelien Jarno
6664685d7b6SAurelien Jarno&usb_host0_ohci {
6674685d7b6SAurelien Jarno	status = "okay";
6684685d7b6SAurelien Jarno};
6694685d7b6SAurelien Jarno
6709984ef56SAurelien Jarno&usb_host0_xhci {
6719984ef56SAurelien Jarno	dr_mode = "host";
6729984ef56SAurelien Jarno	status = "okay";
6739984ef56SAurelien Jarno};
6749984ef56SAurelien Jarno
6754685d7b6SAurelien Jarno&usb_host1_ehci {
6764685d7b6SAurelien Jarno	status = "okay";
6774685d7b6SAurelien Jarno};
6784685d7b6SAurelien Jarno
6794685d7b6SAurelien Jarno&usb_host1_ohci {
6804685d7b6SAurelien Jarno	status = "okay";
6814685d7b6SAurelien Jarno};
6824685d7b6SAurelien Jarno
6839984ef56SAurelien Jarno&usb_host1_xhci {
6849984ef56SAurelien Jarno	status = "okay";
6859984ef56SAurelien Jarno};
6869984ef56SAurelien Jarno
6879984ef56SAurelien Jarno&usb2phy0 {
6889984ef56SAurelien Jarno	status = "okay";
6899984ef56SAurelien Jarno};
6909984ef56SAurelien Jarno
6919984ef56SAurelien Jarno&usb2phy0_host {
6929984ef56SAurelien Jarno	phy-supply = <&vcc5v0_usb_host>;
6939984ef56SAurelien Jarno	status = "okay";
6949984ef56SAurelien Jarno};
6959984ef56SAurelien Jarno
6969984ef56SAurelien Jarno&usb2phy0_otg {
6979984ef56SAurelien Jarno	phy-supply = <&vcc5v0_usb_otg>;
6989984ef56SAurelien Jarno	status = "okay";
6999984ef56SAurelien Jarno};
7009984ef56SAurelien Jarno
7014685d7b6SAurelien Jarno&usb2phy1 {
7024685d7b6SAurelien Jarno	status = "okay";
7034685d7b6SAurelien Jarno};
7044685d7b6SAurelien Jarno
7054685d7b6SAurelien Jarno&usb2phy1_host {
7064685d7b6SAurelien Jarno	phy-supply = <&vcc5v0_usb_host>;
7074685d7b6SAurelien Jarno	status = "okay";
7084685d7b6SAurelien Jarno};
7094685d7b6SAurelien Jarno
7104685d7b6SAurelien Jarno&usb2phy1_otg {
7114685d7b6SAurelien Jarno	phy-supply = <&vcc5v0_usb_host>;
7124685d7b6SAurelien Jarno	status = "okay";
7134685d7b6SAurelien Jarno};
7144685d7b6SAurelien Jarno
715913404aaSAurelien Jarno&vop {
716913404aaSAurelien Jarno	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
717913404aaSAurelien Jarno	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
718913404aaSAurelien Jarno	status = "okay";
719913404aaSAurelien Jarno};
720913404aaSAurelien Jarno
721913404aaSAurelien Jarno&vop_mmu {
722913404aaSAurelien Jarno	status = "okay";
723913404aaSAurelien Jarno};
724913404aaSAurelien Jarno
725913404aaSAurelien Jarno&vp0 {
726913404aaSAurelien Jarno	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
727913404aaSAurelien Jarno		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
728913404aaSAurelien Jarno		remote-endpoint = <&hdmi_in_vp0>;
729913404aaSAurelien Jarno	};
730913404aaSAurelien Jarno};
731