1fd358326SDongjin Kim// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2fd358326SDongjin Kim/* 3fd358326SDongjin Kim * Copyright (c) 2022 Hardkernel Co., Ltd. 4fd358326SDongjin Kim * 5fd358326SDongjin Kim */ 6fd358326SDongjin Kim 7fd358326SDongjin Kim/dts-v1/; 8fd358326SDongjin Kim#include <dt-bindings/gpio/gpio.h> 9fd358326SDongjin Kim#include <dt-bindings/leds/common.h> 10fd358326SDongjin Kim#include <dt-bindings/pinctrl/rockchip.h> 11913404aaSAurelien Jarno#include <dt-bindings/soc/rockchip,vop2.h> 12fd358326SDongjin Kim#include "rk3568.dtsi" 13fd358326SDongjin Kim 14fd358326SDongjin Kim/ { 15fd358326SDongjin Kim model = "Hardkernel ODROID-M1"; 16fd358326SDongjin Kim compatible = "rockchip,rk3568-odroid-m1", "rockchip,rk3568"; 17fd358326SDongjin Kim 18fd358326SDongjin Kim aliases { 19fd358326SDongjin Kim ethernet0 = &gmac0; 20fd358326SDongjin Kim i2c0 = &i2c3; 21fd358326SDongjin Kim i2c3 = &i2c0; 22fd358326SDongjin Kim mmc0 = &sdhci; 23fd358326SDongjin Kim mmc1 = &sdmmc0; 24fd358326SDongjin Kim serial0 = &uart1; 25fd358326SDongjin Kim serial1 = &uart0; 26fd358326SDongjin Kim }; 27fd358326SDongjin Kim 28fd358326SDongjin Kim chosen { 29fd358326SDongjin Kim stdout-path = "serial2:1500000n8"; 30fd358326SDongjin Kim }; 31fd358326SDongjin Kim 32fd358326SDongjin Kim dc_12v: dc-12v-regulator { 33fd358326SDongjin Kim compatible = "regulator-fixed"; 34fd358326SDongjin Kim regulator-name = "dc_12v"; 35fd358326SDongjin Kim regulator-always-on; 36fd358326SDongjin Kim regulator-boot-on; 37fd358326SDongjin Kim regulator-min-microvolt = <12000000>; 38fd358326SDongjin Kim regulator-max-microvolt = <12000000>; 39fd358326SDongjin Kim }; 40fd358326SDongjin Kim 41913404aaSAurelien Jarno hdmi-con { 42913404aaSAurelien Jarno compatible = "hdmi-connector"; 43913404aaSAurelien Jarno type = "a"; 44913404aaSAurelien Jarno 45913404aaSAurelien Jarno port { 46913404aaSAurelien Jarno hdmi_con_in: endpoint { 47913404aaSAurelien Jarno remote-endpoint = <&hdmi_out_con>; 48913404aaSAurelien Jarno }; 49913404aaSAurelien Jarno }; 50913404aaSAurelien Jarno }; 51913404aaSAurelien Jarno 52fd358326SDongjin Kim leds { 53fd358326SDongjin Kim compatible = "gpio-leds"; 54fd358326SDongjin Kim 55fd358326SDongjin Kim led_power: led-0 { 56fd358326SDongjin Kim gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; 57fd358326SDongjin Kim function = LED_FUNCTION_POWER; 58fd358326SDongjin Kim color = <LED_COLOR_ID_RED>; 59fd358326SDongjin Kim default-state = "keep"; 60fd358326SDongjin Kim linux,default-trigger = "default-on"; 61fd358326SDongjin Kim pinctrl-names = "default"; 62fd358326SDongjin Kim pinctrl-0 = <&led_power_pin>; 63fd358326SDongjin Kim }; 64fd358326SDongjin Kim led_work: led-1 { 65fd358326SDongjin Kim gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; 66fd358326SDongjin Kim function = LED_FUNCTION_HEARTBEAT; 67fd358326SDongjin Kim color = <LED_COLOR_ID_BLUE>; 68fd358326SDongjin Kim linux,default-trigger = "heartbeat"; 69fd358326SDongjin Kim pinctrl-names = "default"; 70fd358326SDongjin Kim pinctrl-0 = <&led_work_pin>; 71fd358326SDongjin Kim }; 72fd358326SDongjin Kim }; 73fd358326SDongjin Kim 7478f85844SAurelien Jarno rk809-sound { 7578f85844SAurelien Jarno compatible = "simple-audio-card"; 7678f85844SAurelien Jarno pinctrl-names = "default"; 7778f85844SAurelien Jarno pinctrl-0 = <&hp_det_pin>; 7878f85844SAurelien Jarno simple-audio-card,name = "Analog RK817"; 7978f85844SAurelien Jarno simple-audio-card,format = "i2s"; 8078f85844SAurelien Jarno simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; 8178f85844SAurelien Jarno simple-audio-card,mclk-fs = <256>; 8278f85844SAurelien Jarno simple-audio-card,widgets = 8378f85844SAurelien Jarno "Headphone", "Headphones", 8478f85844SAurelien Jarno "Speaker", "Speaker"; 8578f85844SAurelien Jarno simple-audio-card,routing = 8678f85844SAurelien Jarno "Headphones", "HPOL", 8778f85844SAurelien Jarno "Headphones", "HPOR", 8878f85844SAurelien Jarno "Speaker", "SPKO"; 8978f85844SAurelien Jarno 9078f85844SAurelien Jarno simple-audio-card,cpu { 9178f85844SAurelien Jarno sound-dai = <&i2s1_8ch>; 9278f85844SAurelien Jarno }; 9378f85844SAurelien Jarno 9478f85844SAurelien Jarno simple-audio-card,codec { 9578f85844SAurelien Jarno sound-dai = <&rk809>; 9678f85844SAurelien Jarno }; 9778f85844SAurelien Jarno }; 9878f85844SAurelien Jarno 99fd358326SDongjin Kim vcc3v3_sys: vcc3v3-sys-regulator { 100fd358326SDongjin Kim compatible = "regulator-fixed"; 101fd358326SDongjin Kim regulator-name = "vcc3v3_sys"; 102fd358326SDongjin Kim regulator-always-on; 103fd358326SDongjin Kim regulator-boot-on; 104fd358326SDongjin Kim regulator-min-microvolt = <3300000>; 105fd358326SDongjin Kim regulator-max-microvolt = <3300000>; 106fd358326SDongjin Kim vin-supply = <&dc_12v>; 107fd358326SDongjin Kim }; 108fd358326SDongjin Kim}; 109fd358326SDongjin Kim 110fd358326SDongjin Kim&cpu0 { 111fd358326SDongjin Kim cpu-supply = <&vdd_cpu>; 112fd358326SDongjin Kim}; 113fd358326SDongjin Kim 114fd358326SDongjin Kim&cpu1 { 115fd358326SDongjin Kim cpu-supply = <&vdd_cpu>; 116fd358326SDongjin Kim}; 117fd358326SDongjin Kim 118fd358326SDongjin Kim&cpu2 { 119fd358326SDongjin Kim cpu-supply = <&vdd_cpu>; 120fd358326SDongjin Kim}; 121fd358326SDongjin Kim 122fd358326SDongjin Kim&cpu3 { 123fd358326SDongjin Kim cpu-supply = <&vdd_cpu>; 124fd358326SDongjin Kim}; 125fd358326SDongjin Kim 126fd358326SDongjin Kim&gmac0 { 127fd358326SDongjin Kim assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; 128fd358326SDongjin Kim assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; 129fd358326SDongjin Kim assigned-clock-rates = <0>, <125000000>; 130fd358326SDongjin Kim clock_in_out = "output"; 131fd358326SDongjin Kim phy-handle = <&rgmii_phy0>; 132fd358326SDongjin Kim phy-mode = "rgmii"; 133fd358326SDongjin Kim phy-supply = <&vcc3v3_sys>; 134fd358326SDongjin Kim pinctrl-names = "default"; 135fd358326SDongjin Kim pinctrl-0 = <&gmac0_miim 136fd358326SDongjin Kim &gmac0_tx_bus2 137fd358326SDongjin Kim &gmac0_rx_bus2 138fd358326SDongjin Kim &gmac0_rgmii_clk 139fd358326SDongjin Kim &gmac0_rgmii_bus>; 140fd358326SDongjin Kim status = "okay"; 141fd358326SDongjin Kim 142fd358326SDongjin Kim tx_delay = <0x4f>; 143fd358326SDongjin Kim rx_delay = <0x2d>; 144fd358326SDongjin Kim}; 145fd358326SDongjin Kim 146913404aaSAurelien Jarno&hdmi { 147913404aaSAurelien Jarno avdd-0v9-supply = <&vdda0v9_image>; 148913404aaSAurelien Jarno avdd-1v8-supply = <&vcca1v8_image>; 149913404aaSAurelien Jarno status = "okay"; 150913404aaSAurelien Jarno}; 151913404aaSAurelien Jarno 152913404aaSAurelien Jarno&hdmi_in { 153913404aaSAurelien Jarno hdmi_in_vp0: endpoint { 154913404aaSAurelien Jarno remote-endpoint = <&vp0_out_hdmi>; 155913404aaSAurelien Jarno }; 156913404aaSAurelien Jarno}; 157913404aaSAurelien Jarno 158913404aaSAurelien Jarno&hdmi_out { 159913404aaSAurelien Jarno hdmi_out_con: endpoint { 160913404aaSAurelien Jarno remote-endpoint = <&hdmi_con_in>; 161913404aaSAurelien Jarno }; 162913404aaSAurelien Jarno}; 163913404aaSAurelien Jarno 164*1ca7ddddSAurelien Jarno&hdmi_sound { 165*1ca7ddddSAurelien Jarno status = "okay"; 166*1ca7ddddSAurelien Jarno}; 167*1ca7ddddSAurelien Jarno 168fd358326SDongjin Kim&i2c0 { 169fd358326SDongjin Kim status = "okay"; 170fd358326SDongjin Kim 171fd358326SDongjin Kim vdd_cpu: regulator@1c { 172fd358326SDongjin Kim compatible = "tcs,tcs4525"; 173fd358326SDongjin Kim reg = <0x1c>; 174fd358326SDongjin Kim fcs,suspend-voltage-selector = <1>; 175fd358326SDongjin Kim regulator-name = "vdd_cpu"; 176fd358326SDongjin Kim regulator-always-on; 177fd358326SDongjin Kim regulator-boot-on; 178fd358326SDongjin Kim regulator-min-microvolt = <800000>; 179fd358326SDongjin Kim regulator-max-microvolt = <1150000>; 180fd358326SDongjin Kim regulator-ramp-delay = <2300>; 181fd358326SDongjin Kim vin-supply = <&vcc3v3_sys>; 182fd358326SDongjin Kim 183fd358326SDongjin Kim regulator-state-mem { 184fd358326SDongjin Kim regulator-off-in-suspend; 185fd358326SDongjin Kim }; 186fd358326SDongjin Kim }; 187fd358326SDongjin Kim 188fd358326SDongjin Kim rk809: pmic@20 { 189fd358326SDongjin Kim compatible = "rockchip,rk809"; 190fd358326SDongjin Kim reg = <0x20>; 191fd358326SDongjin Kim interrupt-parent = <&gpio0>; 192fd358326SDongjin Kim interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; 19378f85844SAurelien Jarno assigned-clocks = <&cru I2S1_MCLKOUT_TX>; 19478f85844SAurelien Jarno assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; 195fd358326SDongjin Kim #clock-cells = <1>; 19678f85844SAurelien Jarno clock-names = "mclk"; 19778f85844SAurelien Jarno clocks = <&cru I2S1_MCLKOUT_TX>; 198fd358326SDongjin Kim pinctrl-names = "default"; 19978f85844SAurelien Jarno pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; 200fd358326SDongjin Kim rockchip,system-power-controller; 20178f85844SAurelien Jarno #sound-dai-cells = <0>; 202fd358326SDongjin Kim vcc1-supply = <&vcc3v3_sys>; 203fd358326SDongjin Kim vcc2-supply = <&vcc3v3_sys>; 204fd358326SDongjin Kim vcc3-supply = <&vcc3v3_sys>; 205fd358326SDongjin Kim vcc4-supply = <&vcc3v3_sys>; 206fd358326SDongjin Kim vcc5-supply = <&vcc3v3_sys>; 207fd358326SDongjin Kim vcc6-supply = <&vcc3v3_sys>; 208fd358326SDongjin Kim vcc7-supply = <&vcc3v3_sys>; 209fd358326SDongjin Kim vcc8-supply = <&vcc3v3_sys>; 210fd358326SDongjin Kim vcc9-supply = <&vcc3v3_sys>; 211fd358326SDongjin Kim wakeup-source; 212fd358326SDongjin Kim 213fd358326SDongjin Kim regulators { 214fd358326SDongjin Kim vdd_logic: DCDC_REG1 { 215fd358326SDongjin Kim regulator-name = "vdd_logic"; 216fd358326SDongjin Kim regulator-always-on; 217fd358326SDongjin Kim regulator-boot-on; 218fd358326SDongjin Kim regulator-init-microvolt = <900000>; 219fd358326SDongjin Kim regulator-initial-mode = <0x2>; 220fd358326SDongjin Kim regulator-min-microvolt = <500000>; 221fd358326SDongjin Kim regulator-max-microvolt = <1350000>; 222fd358326SDongjin Kim regulator-ramp-delay = <6001>; 223fd358326SDongjin Kim 224fd358326SDongjin Kim regulator-state-mem { 225fd358326SDongjin Kim regulator-off-in-suspend; 226fd358326SDongjin Kim }; 227fd358326SDongjin Kim }; 228fd358326SDongjin Kim 229fd358326SDongjin Kim vdd_gpu: DCDC_REG2 { 230fd358326SDongjin Kim regulator-name = "vdd_gpu"; 231fd358326SDongjin Kim regulator-always-on; 232fd358326SDongjin Kim regulator-init-microvolt = <900000>; 233fd358326SDongjin Kim regulator-initial-mode = <0x2>; 234fd358326SDongjin Kim regulator-min-microvolt = <500000>; 235fd358326SDongjin Kim regulator-max-microvolt = <1350000>; 236fd358326SDongjin Kim regulator-ramp-delay = <6001>; 237fd358326SDongjin Kim 238fd358326SDongjin Kim regulator-state-mem { 239fd358326SDongjin Kim regulator-off-in-suspend; 240fd358326SDongjin Kim }; 241fd358326SDongjin Kim }; 242fd358326SDongjin Kim 243fd358326SDongjin Kim vcc_ddr: DCDC_REG3 { 244fd358326SDongjin Kim regulator-name = "vcc_ddr"; 245fd358326SDongjin Kim regulator-always-on; 246fd358326SDongjin Kim regulator-boot-on; 247fd358326SDongjin Kim regulator-initial-mode = <0x2>; 248fd358326SDongjin Kim 249fd358326SDongjin Kim regulator-state-mem { 250fd358326SDongjin Kim regulator-on-in-suspend; 251fd358326SDongjin Kim }; 252fd358326SDongjin Kim }; 253fd358326SDongjin Kim 254fd358326SDongjin Kim vdd_npu: DCDC_REG4 { 255fd358326SDongjin Kim regulator-name = "vdd_npu"; 256fd358326SDongjin Kim regulator-init-microvolt = <900000>; 257fd358326SDongjin Kim regulator-initial-mode = <0x2>; 258fd358326SDongjin Kim regulator-min-microvolt = <500000>; 259fd358326SDongjin Kim regulator-max-microvolt = <1350000>; 260fd358326SDongjin Kim regulator-ramp-delay = <6001>; 261fd358326SDongjin Kim 262fd358326SDongjin Kim regulator-state-mem { 263fd358326SDongjin Kim regulator-off-in-suspend; 264fd358326SDongjin Kim }; 265fd358326SDongjin Kim }; 266fd358326SDongjin Kim 267fd358326SDongjin Kim vcc_1v8: DCDC_REG5 { 268fd358326SDongjin Kim regulator-name = "vcc_1v8"; 269fd358326SDongjin Kim regulator-always-on; 270fd358326SDongjin Kim regulator-boot-on; 271fd358326SDongjin Kim regulator-min-microvolt = <1800000>; 272fd358326SDongjin Kim regulator-max-microvolt = <1800000>; 273fd358326SDongjin Kim 274fd358326SDongjin Kim regulator-state-mem { 275fd358326SDongjin Kim regulator-off-in-suspend; 276fd358326SDongjin Kim }; 277fd358326SDongjin Kim }; 278fd358326SDongjin Kim 279fd358326SDongjin Kim vdda0v9_image: LDO_REG1 { 280fd358326SDongjin Kim regulator-name = "vdda0v9_image"; 281fd358326SDongjin Kim regulator-always-on; 282fd358326SDongjin Kim regulator-min-microvolt = <900000>; 283fd358326SDongjin Kim regulator-max-microvolt = <900000>; 284fd358326SDongjin Kim 285fd358326SDongjin Kim regulator-state-mem { 286fd358326SDongjin Kim regulator-off-in-suspend; 287fd358326SDongjin Kim }; 288fd358326SDongjin Kim }; 289fd358326SDongjin Kim 290fd358326SDongjin Kim vdda_0v9: LDO_REG2 { 291fd358326SDongjin Kim regulator-name = "vdda_0v9"; 292fd358326SDongjin Kim regulator-always-on; 293fd358326SDongjin Kim regulator-boot-on; 294fd358326SDongjin Kim regulator-min-microvolt = <900000>; 295fd358326SDongjin Kim regulator-max-microvolt = <900000>; 296fd358326SDongjin Kim 297fd358326SDongjin Kim regulator-state-mem { 298fd358326SDongjin Kim regulator-off-in-suspend; 299fd358326SDongjin Kim }; 300fd358326SDongjin Kim }; 301fd358326SDongjin Kim 302fd358326SDongjin Kim vdda0v9_pmu: LDO_REG3 { 303fd358326SDongjin Kim regulator-name = "vdda0v9_pmu"; 304fd358326SDongjin Kim regulator-always-on; 305fd358326SDongjin Kim regulator-boot-on; 306fd358326SDongjin Kim regulator-min-microvolt = <900000>; 307fd358326SDongjin Kim regulator-max-microvolt = <900000>; 308fd358326SDongjin Kim 309fd358326SDongjin Kim regulator-state-mem { 310fd358326SDongjin Kim regulator-on-in-suspend; 311fd358326SDongjin Kim regulator-suspend-microvolt = <900000>; 312fd358326SDongjin Kim }; 313fd358326SDongjin Kim }; 314fd358326SDongjin Kim 315fd358326SDongjin Kim vccio_acodec: LDO_REG4 { 316fd358326SDongjin Kim regulator-name = "vccio_acodec"; 317fd358326SDongjin Kim regulator-always-on; 318fd358326SDongjin Kim regulator-boot-on; 319fd358326SDongjin Kim regulator-min-microvolt = <3300000>; 320fd358326SDongjin Kim regulator-max-microvolt = <3300000>; 321fd358326SDongjin Kim 322fd358326SDongjin Kim regulator-state-mem { 323fd358326SDongjin Kim regulator-off-in-suspend; 324fd358326SDongjin Kim }; 325fd358326SDongjin Kim }; 326fd358326SDongjin Kim 327fd358326SDongjin Kim vccio_sd: LDO_REG5 { 328fd358326SDongjin Kim regulator-name = "vccio_sd"; 329fd358326SDongjin Kim regulator-min-microvolt = <1800000>; 330fd358326SDongjin Kim regulator-max-microvolt = <3300000>; 331fd358326SDongjin Kim 332fd358326SDongjin Kim regulator-state-mem { 333fd358326SDongjin Kim regulator-off-in-suspend; 334fd358326SDongjin Kim }; 335fd358326SDongjin Kim }; 336fd358326SDongjin Kim 337fd358326SDongjin Kim vcc3v3_pmu: LDO_REG6 { 338fd358326SDongjin Kim regulator-name = "vcc3v3_pmu"; 339fd358326SDongjin Kim regulator-always-on; 340fd358326SDongjin Kim regulator-boot-on; 341fd358326SDongjin Kim regulator-min-microvolt = <3300000>; 342fd358326SDongjin Kim regulator-max-microvolt = <3300000>; 343fd358326SDongjin Kim 344fd358326SDongjin Kim regulator-state-mem { 345fd358326SDongjin Kim regulator-on-in-suspend; 346fd358326SDongjin Kim regulator-suspend-microvolt = <3300000>; 347fd358326SDongjin Kim }; 348fd358326SDongjin Kim }; 349fd358326SDongjin Kim 350fd358326SDongjin Kim vcca_1v8: LDO_REG7 { 351fd358326SDongjin Kim regulator-name = "vcca_1v8"; 352fd358326SDongjin Kim regulator-always-on; 353fd358326SDongjin Kim regulator-boot-on; 354fd358326SDongjin Kim regulator-min-microvolt = <1800000>; 355fd358326SDongjin Kim regulator-max-microvolt = <1800000>; 356fd358326SDongjin Kim 357fd358326SDongjin Kim regulator-state-mem { 358fd358326SDongjin Kim regulator-off-in-suspend; 359fd358326SDongjin Kim }; 360fd358326SDongjin Kim }; 361fd358326SDongjin Kim 362fd358326SDongjin Kim vcca1v8_pmu: LDO_REG8 { 363fd358326SDongjin Kim regulator-name = "vcca1v8_pmu"; 364fd358326SDongjin Kim regulator-always-on; 365fd358326SDongjin Kim regulator-boot-on; 366fd358326SDongjin Kim regulator-min-microvolt = <1800000>; 367fd358326SDongjin Kim regulator-max-microvolt = <1800000>; 368fd358326SDongjin Kim 369fd358326SDongjin Kim regulator-state-mem { 370fd358326SDongjin Kim regulator-on-in-suspend; 371fd358326SDongjin Kim regulator-suspend-microvolt = <1800000>; 372fd358326SDongjin Kim }; 373fd358326SDongjin Kim }; 374fd358326SDongjin Kim 375fd358326SDongjin Kim vcca1v8_image: LDO_REG9 { 376fd358326SDongjin Kim regulator-name = "vcca1v8_image"; 377fd358326SDongjin Kim regulator-always-on; 378fd358326SDongjin Kim regulator-min-microvolt = <1800000>; 379fd358326SDongjin Kim regulator-max-microvolt = <1800000>; 380fd358326SDongjin Kim 381fd358326SDongjin Kim regulator-state-mem { 382fd358326SDongjin Kim regulator-off-in-suspend; 383fd358326SDongjin Kim }; 384fd358326SDongjin Kim }; 385fd358326SDongjin Kim 386fd358326SDongjin Kim vcc_3v3: SWITCH_REG1 { 387fd358326SDongjin Kim regulator-name = "vcc_3v3"; 388fd358326SDongjin Kim regulator-always-on; 389fd358326SDongjin Kim regulator-boot-on; 390fd358326SDongjin Kim 391fd358326SDongjin Kim regulator-state-mem { 392fd358326SDongjin Kim regulator-off-in-suspend; 393fd358326SDongjin Kim }; 394fd358326SDongjin Kim }; 395fd358326SDongjin Kim 396fd358326SDongjin Kim vcc3v3_sd: SWITCH_REG2 { 397fd358326SDongjin Kim regulator-name = "vcc3v3_sd"; 398fd358326SDongjin Kim 399fd358326SDongjin Kim regulator-state-mem { 400fd358326SDongjin Kim regulator-off-in-suspend; 401fd358326SDongjin Kim }; 402fd358326SDongjin Kim }; 403fd358326SDongjin Kim }; 404fd358326SDongjin Kim }; 405fd358326SDongjin Kim}; 406fd358326SDongjin Kim 407*1ca7ddddSAurelien Jarno&i2s0_8ch { 408*1ca7ddddSAurelien Jarno status = "okay"; 409*1ca7ddddSAurelien Jarno}; 410*1ca7ddddSAurelien Jarno 41178f85844SAurelien Jarno&i2s1_8ch { 41278f85844SAurelien Jarno rockchip,trcm-sync-tx-only; 41378f85844SAurelien Jarno status = "okay"; 41478f85844SAurelien Jarno}; 41578f85844SAurelien Jarno 416fd358326SDongjin Kim&mdio0 { 417fd358326SDongjin Kim rgmii_phy0: ethernet-phy@0 { 418fd358326SDongjin Kim compatible = "ethernet-phy-ieee802.3-c22"; 419fd358326SDongjin Kim reg = <0x0>; 420fd358326SDongjin Kim reset-assert-us = <20000>; 421fd358326SDongjin Kim reset-deassert-us = <100000>; 422fd358326SDongjin Kim reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; 423fd358326SDongjin Kim }; 424fd358326SDongjin Kim}; 425fd358326SDongjin Kim 426fd358326SDongjin Kim&pinctrl { 4279f96204bSAurelien Jarno fspi { 4289f96204bSAurelien Jarno fspi_dual_io_pins: fspi-dual-io-pins { 4299f96204bSAurelien Jarno rockchip,pins = 4309f96204bSAurelien Jarno /* fspi_clk */ 4319f96204bSAurelien Jarno <1 RK_PD0 1 &pcfg_pull_none>, 4329f96204bSAurelien Jarno /* fspi_cs0n */ 4339f96204bSAurelien Jarno <1 RK_PD3 1 &pcfg_pull_none>, 4349f96204bSAurelien Jarno /* fspi_d0 */ 4359f96204bSAurelien Jarno <1 RK_PD1 1 &pcfg_pull_none>, 4369f96204bSAurelien Jarno /* fspi_d1 */ 4379f96204bSAurelien Jarno <1 RK_PD2 1 &pcfg_pull_none>; 4389f96204bSAurelien Jarno }; 4399f96204bSAurelien Jarno }; 4409f96204bSAurelien Jarno 441fd358326SDongjin Kim leds { 442fd358326SDongjin Kim led_power_pin: led-power-pin { 443fd358326SDongjin Kim rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 444fd358326SDongjin Kim }; 445fd358326SDongjin Kim led_work_pin: led-work-pin { 446fd358326SDongjin Kim rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; 447fd358326SDongjin Kim }; 448fd358326SDongjin Kim }; 449fd358326SDongjin Kim 450fd358326SDongjin Kim pmic { 451fd358326SDongjin Kim pmic_int_l: pmic-int-l { 452fd358326SDongjin Kim rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; 453fd358326SDongjin Kim }; 454fd358326SDongjin Kim }; 45578f85844SAurelien Jarno 45678f85844SAurelien Jarno rk809 { 45778f85844SAurelien Jarno hp_det_pin: hp-det-pin { 45878f85844SAurelien Jarno rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 45978f85844SAurelien Jarno }; 46078f85844SAurelien Jarno }; 461fd358326SDongjin Kim}; 462fd358326SDongjin Kim 463fd358326SDongjin Kim&pmu_io_domains { 464fd358326SDongjin Kim pmuio1-supply = <&vcc3v3_pmu>; 465fd358326SDongjin Kim pmuio2-supply = <&vcc3v3_pmu>; 466fd358326SDongjin Kim vccio1-supply = <&vccio_acodec>; 467fd358326SDongjin Kim vccio2-supply = <&vcc_1v8>; 468fd358326SDongjin Kim vccio3-supply = <&vccio_sd>; 469fd358326SDongjin Kim vccio4-supply = <&vcc_1v8>; 470fd358326SDongjin Kim vccio5-supply = <&vcc_3v3>; 471fd358326SDongjin Kim vccio6-supply = <&vcc_3v3>; 472fd358326SDongjin Kim vccio7-supply = <&vcc_3v3>; 473fd358326SDongjin Kim status = "okay"; 474fd358326SDongjin Kim}; 475fd358326SDongjin Kim 476fd358326SDongjin Kim&saradc { 477fd358326SDongjin Kim vref-supply = <&vcca_1v8>; 478fd358326SDongjin Kim status = "okay"; 479fd358326SDongjin Kim}; 480fd358326SDongjin Kim 481fd358326SDongjin Kim&sdhci { 482fd358326SDongjin Kim bus-width = <8>; 483fd358326SDongjin Kim max-frequency = <200000000>; 484fd358326SDongjin Kim non-removable; 485fd358326SDongjin Kim pinctrl-names = "default"; 486fd358326SDongjin Kim pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>; 487fd358326SDongjin Kim vmmc-supply = <&vcc_3v3>; 488fd358326SDongjin Kim vqmmc-supply = <&vcc_1v8>; 489fd358326SDongjin Kim status = "okay"; 490fd358326SDongjin Kim}; 491fd358326SDongjin Kim 492fd358326SDongjin Kim&sdmmc0 { 493fd358326SDongjin Kim bus-width = <4>; 494fd358326SDongjin Kim cap-sd-highspeed; 495fd358326SDongjin Kim cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; 496fd358326SDongjin Kim disable-wp; 497fd358326SDongjin Kim pinctrl-names = "default"; 498fd358326SDongjin Kim pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; 499fd358326SDongjin Kim sd-uhs-sdr50; 500fd358326SDongjin Kim vmmc-supply = <&vcc3v3_sd>; 501fd358326SDongjin Kim vqmmc-supply = <&vccio_sd>; 502fd358326SDongjin Kim status = "okay"; 503fd358326SDongjin Kim}; 504fd358326SDongjin Kim 5059f96204bSAurelien Jarno&sfc { 5069f96204bSAurelien Jarno /* Dual I/O mode as the D2 pin conflicts with the eMMC */ 5079f96204bSAurelien Jarno pinctrl-0 = <&fspi_dual_io_pins>; 5089f96204bSAurelien Jarno pinctrl-names = "default"; 5099f96204bSAurelien Jarno #address-cells = <1>; 5109f96204bSAurelien Jarno #size-cells = <0>; 5119f96204bSAurelien Jarno status = "okay"; 5129f96204bSAurelien Jarno 5139f96204bSAurelien Jarno flash@0 { 5149f96204bSAurelien Jarno compatible = "jedec,spi-nor"; 5159f96204bSAurelien Jarno reg = <0>; 5169f96204bSAurelien Jarno spi-max-frequency = <100000000>; 5179f96204bSAurelien Jarno spi-rx-bus-width = <2>; 5189f96204bSAurelien Jarno spi-tx-bus-width = <1>; 5199f96204bSAurelien Jarno 5209f96204bSAurelien Jarno partitions { 5219f96204bSAurelien Jarno compatible = "fixed-partitions"; 5229f96204bSAurelien Jarno #address-cells = <1>; 5239f96204bSAurelien Jarno #size-cells = <1>; 5249f96204bSAurelien Jarno 5259f96204bSAurelien Jarno partition@0 { 5269f96204bSAurelien Jarno label = "SPL"; 5279f96204bSAurelien Jarno reg = <0x0 0xe0000>; 5289f96204bSAurelien Jarno }; 5299f96204bSAurelien Jarno partition@e0000 { 5309f96204bSAurelien Jarno label = "U-Boot Env"; 5319f96204bSAurelien Jarno reg = <0xe0000 0x20000>; 5329f96204bSAurelien Jarno }; 5339f96204bSAurelien Jarno partition@100000 { 5349f96204bSAurelien Jarno label = "U-Boot"; 5359f96204bSAurelien Jarno reg = <0x100000 0x200000>; 5369f96204bSAurelien Jarno }; 5379f96204bSAurelien Jarno partition@300000 { 5389f96204bSAurelien Jarno label = "splash"; 5399f96204bSAurelien Jarno reg = <0x300000 0x100000>; 5409f96204bSAurelien Jarno }; 5419f96204bSAurelien Jarno partition@400000 { 5429f96204bSAurelien Jarno label = "Filesystem"; 5439f96204bSAurelien Jarno reg = <0x400000 0xc00000>; 5449f96204bSAurelien Jarno }; 5459f96204bSAurelien Jarno }; 5469f96204bSAurelien Jarno }; 5479f96204bSAurelien Jarno}; 5489f96204bSAurelien Jarno 549f5511bd8SAurelien Jarno&tsadc { 550f5511bd8SAurelien Jarno rockchip,hw-tshut-mode = <1>; 551f5511bd8SAurelien Jarno rockchip,hw-tshut-polarity = <0>; 552f5511bd8SAurelien Jarno status = "okay"; 553f5511bd8SAurelien Jarno}; 554f5511bd8SAurelien Jarno 555fd358326SDongjin Kim&uart2 { 556fd358326SDongjin Kim status = "okay"; 557fd358326SDongjin Kim}; 558913404aaSAurelien Jarno 559913404aaSAurelien Jarno&vop { 560913404aaSAurelien Jarno assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; 561913404aaSAurelien Jarno assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; 562913404aaSAurelien Jarno status = "okay"; 563913404aaSAurelien Jarno}; 564913404aaSAurelien Jarno 565913404aaSAurelien Jarno&vop_mmu { 566913404aaSAurelien Jarno status = "okay"; 567913404aaSAurelien Jarno}; 568913404aaSAurelien Jarno 569913404aaSAurelien Jarno&vp0 { 570913404aaSAurelien Jarno vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { 571913404aaSAurelien Jarno reg = <ROCKCHIP_VOP2_EP_HDMI0>; 572913404aaSAurelien Jarno remote-endpoint = <&hdmi_in_vp0>; 573913404aaSAurelien Jarno }; 574913404aaSAurelien Jarno}; 575