1/* 2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include <dt-bindings/clock/rk3399-cru.h> 44#include <dt-bindings/gpio/gpio.h> 45#include <dt-bindings/interrupt-controller/arm-gic.h> 46#include <dt-bindings/interrupt-controller/irq.h> 47#include <dt-bindings/pinctrl/rockchip.h> 48#include <dt-bindings/power/rk3399-power.h> 49#include <dt-bindings/thermal/thermal.h> 50 51/ { 52 compatible = "rockchip,rk3399"; 53 54 interrupt-parent = <&gic>; 55 #address-cells = <2>; 56 #size-cells = <2>; 57 58 aliases { 59 ethernet0 = &gmac; 60 i2c0 = &i2c0; 61 i2c1 = &i2c1; 62 i2c2 = &i2c2; 63 i2c3 = &i2c3; 64 i2c4 = &i2c4; 65 i2c5 = &i2c5; 66 i2c6 = &i2c6; 67 i2c7 = &i2c7; 68 i2c8 = &i2c8; 69 serial0 = &uart0; 70 serial1 = &uart1; 71 serial2 = &uart2; 72 serial3 = &uart3; 73 serial4 = &uart4; 74 }; 75 76 cpus { 77 #address-cells = <2>; 78 #size-cells = <0>; 79 80 cpu-map { 81 cluster0 { 82 core0 { 83 cpu = <&cpu_l0>; 84 }; 85 core1 { 86 cpu = <&cpu_l1>; 87 }; 88 core2 { 89 cpu = <&cpu_l2>; 90 }; 91 core3 { 92 cpu = <&cpu_l3>; 93 }; 94 }; 95 96 cluster1 { 97 core0 { 98 cpu = <&cpu_b0>; 99 }; 100 core1 { 101 cpu = <&cpu_b1>; 102 }; 103 }; 104 }; 105 106 cpu_l0: cpu@0 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a53", "arm,armv8"; 109 reg = <0x0 0x0>; 110 enable-method = "psci"; 111 #cooling-cells = <2>; /* min followed by max */ 112 clocks = <&cru ARMCLKL>; 113 dynamic-power-coefficient = <100>; 114 }; 115 116 cpu_l1: cpu@1 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a53", "arm,armv8"; 119 reg = <0x0 0x1>; 120 enable-method = "psci"; 121 clocks = <&cru ARMCLKL>; 122 dynamic-power-coefficient = <100>; 123 }; 124 125 cpu_l2: cpu@2 { 126 device_type = "cpu"; 127 compatible = "arm,cortex-a53", "arm,armv8"; 128 reg = <0x0 0x2>; 129 enable-method = "psci"; 130 clocks = <&cru ARMCLKL>; 131 dynamic-power-coefficient = <100>; 132 }; 133 134 cpu_l3: cpu@3 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a53", "arm,armv8"; 137 reg = <0x0 0x3>; 138 enable-method = "psci"; 139 clocks = <&cru ARMCLKL>; 140 dynamic-power-coefficient = <100>; 141 }; 142 143 cpu_b0: cpu@100 { 144 device_type = "cpu"; 145 compatible = "arm,cortex-a72", "arm,armv8"; 146 reg = <0x0 0x100>; 147 enable-method = "psci"; 148 #cooling-cells = <2>; /* min followed by max */ 149 clocks = <&cru ARMCLKB>; 150 dynamic-power-coefficient = <436>; 151 }; 152 153 cpu_b1: cpu@101 { 154 device_type = "cpu"; 155 compatible = "arm,cortex-a72", "arm,armv8"; 156 reg = <0x0 0x101>; 157 enable-method = "psci"; 158 clocks = <&cru ARMCLKB>; 159 dynamic-power-coefficient = <436>; 160 }; 161 }; 162 163 display-subsystem { 164 compatible = "rockchip,display-subsystem"; 165 ports = <&vopl_out>, <&vopb_out>; 166 }; 167 168 pmu_a53 { 169 compatible = "arm,cortex-a53-pmu"; 170 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 171 }; 172 173 pmu_a72 { 174 compatible = "arm,cortex-a72-pmu"; 175 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 176 }; 177 178 psci { 179 compatible = "arm,psci-1.0"; 180 method = "smc"; 181 }; 182 183 timer { 184 compatible = "arm,armv8-timer"; 185 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 186 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 187 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 188 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 189 arm,no-tick-in-suspend; 190 }; 191 192 xin24m: xin24m { 193 compatible = "fixed-clock"; 194 clock-frequency = <24000000>; 195 clock-output-names = "xin24m"; 196 #clock-cells = <0>; 197 }; 198 199 amba { 200 compatible = "simple-bus"; 201 #address-cells = <2>; 202 #size-cells = <2>; 203 ranges; 204 205 dmac_bus: dma-controller@ff6d0000 { 206 compatible = "arm,pl330", "arm,primecell"; 207 reg = <0x0 0xff6d0000 0x0 0x4000>; 208 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 209 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 210 #dma-cells = <1>; 211 clocks = <&cru ACLK_DMAC0_PERILP>; 212 clock-names = "apb_pclk"; 213 }; 214 215 dmac_peri: dma-controller@ff6e0000 { 216 compatible = "arm,pl330", "arm,primecell"; 217 reg = <0x0 0xff6e0000 0x0 0x4000>; 218 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 219 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 220 #dma-cells = <1>; 221 clocks = <&cru ACLK_DMAC1_PERILP>; 222 clock-names = "apb_pclk"; 223 }; 224 }; 225 226 pcie0: pcie@f8000000 { 227 compatible = "rockchip,rk3399-pcie"; 228 reg = <0x0 0xf8000000 0x0 0x2000000>, 229 <0x0 0xfd000000 0x0 0x1000000>; 230 reg-names = "axi-base", "apb-base"; 231 #address-cells = <3>; 232 #size-cells = <2>; 233 #interrupt-cells = <1>; 234 aspm-no-l0s; 235 bus-range = <0x0 0x1f>; 236 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 237 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 238 clock-names = "aclk", "aclk-perf", 239 "hclk", "pm"; 240 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 241 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 242 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 243 interrupt-names = "sys", "legacy", "client"; 244 interrupt-map-mask = <0 0 0 7>; 245 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 246 <0 0 0 2 &pcie0_intc 1>, 247 <0 0 0 3 &pcie0_intc 2>, 248 <0 0 0 4 &pcie0_intc 3>; 249 linux,pci-domain = <0>; 250 max-link-speed = <1>; 251 msi-map = <0x0 &its 0x0 0x1000>; 252 phys = <&pcie_phy 0>, <&pcie_phy 1>, 253 <&pcie_phy 2>, <&pcie_phy 3>; 254 phy-names = "pcie-phy-0", "pcie-phy-1", 255 "pcie-phy-2", "pcie-phy-3"; 256 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000 257 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; 258 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 259 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 260 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 261 <&cru SRST_A_PCIE>; 262 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 263 "pm", "pclk", "aclk"; 264 status = "disabled"; 265 266 pcie0_intc: interrupt-controller { 267 interrupt-controller; 268 #address-cells = <0>; 269 #interrupt-cells = <1>; 270 }; 271 }; 272 273 gmac: ethernet@fe300000 { 274 compatible = "rockchip,rk3399-gmac"; 275 reg = <0x0 0xfe300000 0x0 0x10000>; 276 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 277 interrupt-names = "macirq"; 278 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 279 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 280 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 281 <&cru PCLK_GMAC>; 282 clock-names = "stmmaceth", "mac_clk_rx", 283 "mac_clk_tx", "clk_mac_ref", 284 "clk_mac_refout", "aclk_mac", 285 "pclk_mac"; 286 power-domains = <&power RK3399_PD_GMAC>; 287 resets = <&cru SRST_A_GMAC>; 288 reset-names = "stmmaceth"; 289 rockchip,grf = <&grf>; 290 status = "disabled"; 291 }; 292 293 sdio0: dwmmc@fe310000 { 294 compatible = "rockchip,rk3399-dw-mshc", 295 "rockchip,rk3288-dw-mshc"; 296 reg = <0x0 0xfe310000 0x0 0x4000>; 297 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 298 max-frequency = <150000000>; 299 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 300 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 301 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 302 fifo-depth = <0x100>; 303 power-domains = <&power RK3399_PD_SDIOAUDIO>; 304 resets = <&cru SRST_SDIO0>; 305 reset-names = "reset"; 306 status = "disabled"; 307 }; 308 309 sdmmc: dwmmc@fe320000 { 310 compatible = "rockchip,rk3399-dw-mshc", 311 "rockchip,rk3288-dw-mshc"; 312 reg = <0x0 0xfe320000 0x0 0x4000>; 313 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 314 max-frequency = <150000000>; 315 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 316 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 317 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 318 fifo-depth = <0x100>; 319 power-domains = <&power RK3399_PD_SD>; 320 resets = <&cru SRST_SDMMC>; 321 reset-names = "reset"; 322 status = "disabled"; 323 }; 324 325 sdhci: sdhci@fe330000 { 326 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 327 reg = <0x0 0xfe330000 0x0 0x10000>; 328 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 329 arasan,soc-ctl-syscon = <&grf>; 330 assigned-clocks = <&cru SCLK_EMMC>; 331 assigned-clock-rates = <200000000>; 332 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 333 clock-names = "clk_xin", "clk_ahb"; 334 clock-output-names = "emmc_cardclock"; 335 #clock-cells = <0>; 336 phys = <&emmc_phy>; 337 phy-names = "phy_arasan"; 338 power-domains = <&power RK3399_PD_EMMC>; 339 status = "disabled"; 340 }; 341 342 usb_host0_ehci: usb@fe380000 { 343 compatible = "generic-ehci"; 344 reg = <0x0 0xfe380000 0x0 0x20000>; 345 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 346 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 347 <&u2phy0>; 348 clock-names = "usbhost", "arbiter", 349 "utmi"; 350 phys = <&u2phy0_host>; 351 phy-names = "usb"; 352 status = "disabled"; 353 }; 354 355 usb_host0_ohci: usb@fe3a0000 { 356 compatible = "generic-ohci"; 357 reg = <0x0 0xfe3a0000 0x0 0x20000>; 358 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 359 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 360 <&u2phy0>; 361 clock-names = "usbhost", "arbiter", 362 "utmi"; 363 phys = <&u2phy0_host>; 364 phy-names = "usb"; 365 status = "disabled"; 366 }; 367 368 usb_host1_ehci: usb@fe3c0000 { 369 compatible = "generic-ehci"; 370 reg = <0x0 0xfe3c0000 0x0 0x20000>; 371 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 372 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 373 <&u2phy1>; 374 clock-names = "usbhost", "arbiter", 375 "utmi"; 376 phys = <&u2phy1_host>; 377 phy-names = "usb"; 378 status = "disabled"; 379 }; 380 381 usb_host1_ohci: usb@fe3e0000 { 382 compatible = "generic-ohci"; 383 reg = <0x0 0xfe3e0000 0x0 0x20000>; 384 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 385 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 386 <&u2phy1>; 387 clock-names = "usbhost", "arbiter", 388 "utmi"; 389 phys = <&u2phy1_host>; 390 phy-names = "usb"; 391 status = "disabled"; 392 }; 393 394 usbdrd3_0: usb@fe800000 { 395 compatible = "rockchip,rk3399-dwc3"; 396 #address-cells = <2>; 397 #size-cells = <2>; 398 ranges; 399 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 400 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>; 401 clock-names = "ref_clk", "suspend_clk", 402 "bus_clk", "grf_clk"; 403 status = "disabled"; 404 405 usbdrd_dwc3_0: dwc3 { 406 compatible = "snps,dwc3"; 407 reg = <0x0 0xfe800000 0x0 0x100000>; 408 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 409 dr_mode = "otg"; 410 phys = <&u2phy0_otg>; 411 phy-names = "usb2-phy"; 412 phy_type = "utmi_wide"; 413 snps,dis_enblslpm_quirk; 414 snps,dis-u2-freeclk-exists-quirk; 415 snps,dis_u2_susphy_quirk; 416 snps,dis-del-phy-power-chg-quirk; 417 snps,dis-tx-ipgap-linecheck-quirk; 418 status = "disabled"; 419 }; 420 }; 421 422 usbdrd3_1: usb@fe900000 { 423 compatible = "rockchip,rk3399-dwc3"; 424 #address-cells = <2>; 425 #size-cells = <2>; 426 ranges; 427 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, 428 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>; 429 clock-names = "ref_clk", "suspend_clk", 430 "bus_clk", "grf_clk"; 431 status = "disabled"; 432 433 usbdrd_dwc3_1: dwc3 { 434 compatible = "snps,dwc3"; 435 reg = <0x0 0xfe900000 0x0 0x100000>; 436 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 437 dr_mode = "otg"; 438 phys = <&u2phy1_otg>; 439 phy-names = "usb2-phy"; 440 phy_type = "utmi_wide"; 441 snps,dis_enblslpm_quirk; 442 snps,dis-u2-freeclk-exists-quirk; 443 snps,dis_u2_susphy_quirk; 444 snps,dis-del-phy-power-chg-quirk; 445 snps,dis-tx-ipgap-linecheck-quirk; 446 status = "disabled"; 447 }; 448 }; 449 450 gic: interrupt-controller@fee00000 { 451 compatible = "arm,gic-v3"; 452 #interrupt-cells = <4>; 453 #address-cells = <2>; 454 #size-cells = <2>; 455 ranges; 456 interrupt-controller; 457 458 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 459 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 460 <0x0 0xfff00000 0 0x10000>, /* GICC */ 461 <0x0 0xfff10000 0 0x10000>, /* GICH */ 462 <0x0 0xfff20000 0 0x10000>; /* GICV */ 463 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 464 its: interrupt-controller@fee20000 { 465 compatible = "arm,gic-v3-its"; 466 msi-controller; 467 reg = <0x0 0xfee20000 0x0 0x20000>; 468 }; 469 470 ppi-partitions { 471 ppi_cluster0: interrupt-partition-0 { 472 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 473 }; 474 475 ppi_cluster1: interrupt-partition-1 { 476 affinity = <&cpu_b0 &cpu_b1>; 477 }; 478 }; 479 }; 480 481 saradc: saradc@ff100000 { 482 compatible = "rockchip,rk3399-saradc"; 483 reg = <0x0 0xff100000 0x0 0x100>; 484 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 485 #io-channel-cells = <1>; 486 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 487 clock-names = "saradc", "apb_pclk"; 488 resets = <&cru SRST_P_SARADC>; 489 reset-names = "saradc-apb"; 490 status = "disabled"; 491 }; 492 493 i2c1: i2c@ff110000 { 494 compatible = "rockchip,rk3399-i2c"; 495 reg = <0x0 0xff110000 0x0 0x1000>; 496 assigned-clocks = <&cru SCLK_I2C1>; 497 assigned-clock-rates = <200000000>; 498 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 499 clock-names = "i2c", "pclk"; 500 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 501 pinctrl-names = "default"; 502 pinctrl-0 = <&i2c1_xfer>; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 status = "disabled"; 506 }; 507 508 i2c2: i2c@ff120000 { 509 compatible = "rockchip,rk3399-i2c"; 510 reg = <0x0 0xff120000 0x0 0x1000>; 511 assigned-clocks = <&cru SCLK_I2C2>; 512 assigned-clock-rates = <200000000>; 513 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 514 clock-names = "i2c", "pclk"; 515 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 516 pinctrl-names = "default"; 517 pinctrl-0 = <&i2c2_xfer>; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 status = "disabled"; 521 }; 522 523 i2c3: i2c@ff130000 { 524 compatible = "rockchip,rk3399-i2c"; 525 reg = <0x0 0xff130000 0x0 0x1000>; 526 assigned-clocks = <&cru SCLK_I2C3>; 527 assigned-clock-rates = <200000000>; 528 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 529 clock-names = "i2c", "pclk"; 530 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 531 pinctrl-names = "default"; 532 pinctrl-0 = <&i2c3_xfer>; 533 #address-cells = <1>; 534 #size-cells = <0>; 535 status = "disabled"; 536 }; 537 538 i2c5: i2c@ff140000 { 539 compatible = "rockchip,rk3399-i2c"; 540 reg = <0x0 0xff140000 0x0 0x1000>; 541 assigned-clocks = <&cru SCLK_I2C5>; 542 assigned-clock-rates = <200000000>; 543 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 544 clock-names = "i2c", "pclk"; 545 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 546 pinctrl-names = "default"; 547 pinctrl-0 = <&i2c5_xfer>; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 status = "disabled"; 551 }; 552 553 i2c6: i2c@ff150000 { 554 compatible = "rockchip,rk3399-i2c"; 555 reg = <0x0 0xff150000 0x0 0x1000>; 556 assigned-clocks = <&cru SCLK_I2C6>; 557 assigned-clock-rates = <200000000>; 558 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 559 clock-names = "i2c", "pclk"; 560 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 561 pinctrl-names = "default"; 562 pinctrl-0 = <&i2c6_xfer>; 563 #address-cells = <1>; 564 #size-cells = <0>; 565 status = "disabled"; 566 }; 567 568 i2c7: i2c@ff160000 { 569 compatible = "rockchip,rk3399-i2c"; 570 reg = <0x0 0xff160000 0x0 0x1000>; 571 assigned-clocks = <&cru SCLK_I2C7>; 572 assigned-clock-rates = <200000000>; 573 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 574 clock-names = "i2c", "pclk"; 575 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 576 pinctrl-names = "default"; 577 pinctrl-0 = <&i2c7_xfer>; 578 #address-cells = <1>; 579 #size-cells = <0>; 580 status = "disabled"; 581 }; 582 583 uart0: serial@ff180000 { 584 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 585 reg = <0x0 0xff180000 0x0 0x100>; 586 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 587 clock-names = "baudclk", "apb_pclk"; 588 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 589 reg-shift = <2>; 590 reg-io-width = <4>; 591 pinctrl-names = "default"; 592 pinctrl-0 = <&uart0_xfer>; 593 status = "disabled"; 594 }; 595 596 uart1: serial@ff190000 { 597 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 598 reg = <0x0 0xff190000 0x0 0x100>; 599 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 600 clock-names = "baudclk", "apb_pclk"; 601 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 602 reg-shift = <2>; 603 reg-io-width = <4>; 604 pinctrl-names = "default"; 605 pinctrl-0 = <&uart1_xfer>; 606 status = "disabled"; 607 }; 608 609 uart2: serial@ff1a0000 { 610 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 611 reg = <0x0 0xff1a0000 0x0 0x100>; 612 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 613 clock-names = "baudclk", "apb_pclk"; 614 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 615 reg-shift = <2>; 616 reg-io-width = <4>; 617 pinctrl-names = "default"; 618 pinctrl-0 = <&uart2c_xfer>; 619 status = "disabled"; 620 }; 621 622 uart3: serial@ff1b0000 { 623 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 624 reg = <0x0 0xff1b0000 0x0 0x100>; 625 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 626 clock-names = "baudclk", "apb_pclk"; 627 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 628 reg-shift = <2>; 629 reg-io-width = <4>; 630 pinctrl-names = "default"; 631 pinctrl-0 = <&uart3_xfer>; 632 status = "disabled"; 633 }; 634 635 spi0: spi@ff1c0000 { 636 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 637 reg = <0x0 0xff1c0000 0x0 0x1000>; 638 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 639 clock-names = "spiclk", "apb_pclk"; 640 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 641 pinctrl-names = "default"; 642 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 643 #address-cells = <1>; 644 #size-cells = <0>; 645 status = "disabled"; 646 }; 647 648 spi1: spi@ff1d0000 { 649 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 650 reg = <0x0 0xff1d0000 0x0 0x1000>; 651 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 652 clock-names = "spiclk", "apb_pclk"; 653 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 654 pinctrl-names = "default"; 655 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 656 #address-cells = <1>; 657 #size-cells = <0>; 658 status = "disabled"; 659 }; 660 661 spi2: spi@ff1e0000 { 662 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 663 reg = <0x0 0xff1e0000 0x0 0x1000>; 664 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 665 clock-names = "spiclk", "apb_pclk"; 666 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 667 pinctrl-names = "default"; 668 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 669 #address-cells = <1>; 670 #size-cells = <0>; 671 status = "disabled"; 672 }; 673 674 spi4: spi@ff1f0000 { 675 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 676 reg = <0x0 0xff1f0000 0x0 0x1000>; 677 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 678 clock-names = "spiclk", "apb_pclk"; 679 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 680 pinctrl-names = "default"; 681 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 682 #address-cells = <1>; 683 #size-cells = <0>; 684 status = "disabled"; 685 }; 686 687 spi5: spi@ff200000 { 688 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 689 reg = <0x0 0xff200000 0x0 0x1000>; 690 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 691 clock-names = "spiclk", "apb_pclk"; 692 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 693 pinctrl-names = "default"; 694 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 695 power-domains = <&power RK3399_PD_SDIOAUDIO>; 696 #address-cells = <1>; 697 #size-cells = <0>; 698 status = "disabled"; 699 }; 700 701 thermal_zones: thermal-zones { 702 cpu_thermal: cpu { 703 polling-delay-passive = <100>; 704 polling-delay = <1000>; 705 706 thermal-sensors = <&tsadc 0>; 707 708 trips { 709 cpu_alert0: cpu_alert0 { 710 temperature = <70000>; 711 hysteresis = <2000>; 712 type = "passive"; 713 }; 714 cpu_alert1: cpu_alert1 { 715 temperature = <75000>; 716 hysteresis = <2000>; 717 type = "passive"; 718 }; 719 cpu_crit: cpu_crit { 720 temperature = <95000>; 721 hysteresis = <2000>; 722 type = "critical"; 723 }; 724 }; 725 726 cooling-maps { 727 map0 { 728 trip = <&cpu_alert0>; 729 cooling-device = 730 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 731 }; 732 map1 { 733 trip = <&cpu_alert1>; 734 cooling-device = 735 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 736 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 737 }; 738 }; 739 }; 740 741 gpu_thermal: gpu { 742 polling-delay-passive = <100>; 743 polling-delay = <1000>; 744 745 thermal-sensors = <&tsadc 1>; 746 747 trips { 748 gpu_alert0: gpu_alert0 { 749 temperature = <75000>; 750 hysteresis = <2000>; 751 type = "passive"; 752 }; 753 gpu_crit: gpu_crit { 754 temperature = <95000>; 755 hysteresis = <2000>; 756 type = "critical"; 757 }; 758 }; 759 760 cooling-maps { 761 map0 { 762 trip = <&gpu_alert0>; 763 cooling-device = 764 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 765 }; 766 }; 767 }; 768 }; 769 770 tsadc: tsadc@ff260000 { 771 compatible = "rockchip,rk3399-tsadc"; 772 reg = <0x0 0xff260000 0x0 0x100>; 773 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 774 assigned-clocks = <&cru SCLK_TSADC>; 775 assigned-clock-rates = <750000>; 776 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 777 clock-names = "tsadc", "apb_pclk"; 778 resets = <&cru SRST_TSADC>; 779 reset-names = "tsadc-apb"; 780 rockchip,grf = <&grf>; 781 rockchip,hw-tshut-temp = <95000>; 782 pinctrl-names = "init", "default", "sleep"; 783 pinctrl-0 = <&otp_gpio>; 784 pinctrl-1 = <&otp_out>; 785 pinctrl-2 = <&otp_gpio>; 786 #thermal-sensor-cells = <1>; 787 status = "disabled"; 788 }; 789 790 qos_emmc: qos@ffa58000 { 791 compatible = "syscon"; 792 reg = <0x0 0xffa58000 0x0 0x20>; 793 }; 794 795 qos_gmac: qos@ffa5c000 { 796 compatible = "syscon"; 797 reg = <0x0 0xffa5c000 0x0 0x20>; 798 }; 799 800 qos_pcie: qos@ffa60080 { 801 compatible = "syscon"; 802 reg = <0x0 0xffa60080 0x0 0x20>; 803 }; 804 805 qos_usb_host0: qos@ffa60100 { 806 compatible = "syscon"; 807 reg = <0x0 0xffa60100 0x0 0x20>; 808 }; 809 810 qos_usb_host1: qos@ffa60180 { 811 compatible = "syscon"; 812 reg = <0x0 0xffa60180 0x0 0x20>; 813 }; 814 815 qos_usb_otg0: qos@ffa70000 { 816 compatible = "syscon"; 817 reg = <0x0 0xffa70000 0x0 0x20>; 818 }; 819 820 qos_usb_otg1: qos@ffa70080 { 821 compatible = "syscon"; 822 reg = <0x0 0xffa70080 0x0 0x20>; 823 }; 824 825 qos_sd: qos@ffa74000 { 826 compatible = "syscon"; 827 reg = <0x0 0xffa74000 0x0 0x20>; 828 }; 829 830 qos_sdioaudio: qos@ffa76000 { 831 compatible = "syscon"; 832 reg = <0x0 0xffa76000 0x0 0x20>; 833 }; 834 835 qos_hdcp: qos@ffa90000 { 836 compatible = "syscon"; 837 reg = <0x0 0xffa90000 0x0 0x20>; 838 }; 839 840 qos_iep: qos@ffa98000 { 841 compatible = "syscon"; 842 reg = <0x0 0xffa98000 0x0 0x20>; 843 }; 844 845 qos_isp0_m0: qos@ffaa0000 { 846 compatible = "syscon"; 847 reg = <0x0 0xffaa0000 0x0 0x20>; 848 }; 849 850 qos_isp0_m1: qos@ffaa0080 { 851 compatible = "syscon"; 852 reg = <0x0 0xffaa0080 0x0 0x20>; 853 }; 854 855 qos_isp1_m0: qos@ffaa8000 { 856 compatible = "syscon"; 857 reg = <0x0 0xffaa8000 0x0 0x20>; 858 }; 859 860 qos_isp1_m1: qos@ffaa8080 { 861 compatible = "syscon"; 862 reg = <0x0 0xffaa8080 0x0 0x20>; 863 }; 864 865 qos_rga_r: qos@ffab0000 { 866 compatible = "syscon"; 867 reg = <0x0 0xffab0000 0x0 0x20>; 868 }; 869 870 qos_rga_w: qos@ffab0080 { 871 compatible = "syscon"; 872 reg = <0x0 0xffab0080 0x0 0x20>; 873 }; 874 875 qos_video_m0: qos@ffab8000 { 876 compatible = "syscon"; 877 reg = <0x0 0xffab8000 0x0 0x20>; 878 }; 879 880 qos_video_m1_r: qos@ffac0000 { 881 compatible = "syscon"; 882 reg = <0x0 0xffac0000 0x0 0x20>; 883 }; 884 885 qos_video_m1_w: qos@ffac0080 { 886 compatible = "syscon"; 887 reg = <0x0 0xffac0080 0x0 0x20>; 888 }; 889 890 qos_vop_big_r: qos@ffac8000 { 891 compatible = "syscon"; 892 reg = <0x0 0xffac8000 0x0 0x20>; 893 }; 894 895 qos_vop_big_w: qos@ffac8080 { 896 compatible = "syscon"; 897 reg = <0x0 0xffac8080 0x0 0x20>; 898 }; 899 900 qos_vop_little: qos@ffad0000 { 901 compatible = "syscon"; 902 reg = <0x0 0xffad0000 0x0 0x20>; 903 }; 904 905 qos_perihp: qos@ffad8080 { 906 compatible = "syscon"; 907 reg = <0x0 0xffad8080 0x0 0x20>; 908 }; 909 910 qos_gpu: qos@ffae0000 { 911 compatible = "syscon"; 912 reg = <0x0 0xffae0000 0x0 0x20>; 913 }; 914 915 pmu: power-management@ff310000 { 916 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 917 reg = <0x0 0xff310000 0x0 0x1000>; 918 919 /* 920 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 921 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 922 * Some of the power domains are grouped together for every 923 * voltage domain. 924 * The detail contents as below. 925 */ 926 power: power-controller { 927 compatible = "rockchip,rk3399-power-controller"; 928 #power-domain-cells = <1>; 929 #address-cells = <1>; 930 #size-cells = <0>; 931 932 /* These power domains are grouped by VD_CENTER */ 933 pd_iep@RK3399_PD_IEP { 934 reg = <RK3399_PD_IEP>; 935 clocks = <&cru ACLK_IEP>, 936 <&cru HCLK_IEP>; 937 pm_qos = <&qos_iep>; 938 }; 939 pd_rga@RK3399_PD_RGA { 940 reg = <RK3399_PD_RGA>; 941 clocks = <&cru ACLK_RGA>, 942 <&cru HCLK_RGA>; 943 pm_qos = <&qos_rga_r>, 944 <&qos_rga_w>; 945 }; 946 pd_vcodec@RK3399_PD_VCODEC { 947 reg = <RK3399_PD_VCODEC>; 948 clocks = <&cru ACLK_VCODEC>, 949 <&cru HCLK_VCODEC>; 950 pm_qos = <&qos_video_m0>; 951 }; 952 pd_vdu@RK3399_PD_VDU { 953 reg = <RK3399_PD_VDU>; 954 clocks = <&cru ACLK_VDU>, 955 <&cru HCLK_VDU>; 956 pm_qos = <&qos_video_m1_r>, 957 <&qos_video_m1_w>; 958 }; 959 960 /* These power domains are grouped by VD_GPU */ 961 pd_gpu@RK3399_PD_GPU { 962 reg = <RK3399_PD_GPU>; 963 clocks = <&cru ACLK_GPU>; 964 pm_qos = <&qos_gpu>; 965 }; 966 967 /* These power domains are grouped by VD_LOGIC */ 968 pd_edp@RK3399_PD_EDP { 969 reg = <RK3399_PD_EDP>; 970 clocks = <&cru PCLK_EDP_CTRL>; 971 }; 972 pd_emmc@RK3399_PD_EMMC { 973 reg = <RK3399_PD_EMMC>; 974 clocks = <&cru ACLK_EMMC>; 975 pm_qos = <&qos_emmc>; 976 }; 977 pd_gmac@RK3399_PD_GMAC { 978 reg = <RK3399_PD_GMAC>; 979 clocks = <&cru ACLK_GMAC>, 980 <&cru PCLK_GMAC>; 981 pm_qos = <&qos_gmac>; 982 }; 983 pd_sd@RK3399_PD_SD { 984 reg = <RK3399_PD_SD>; 985 clocks = <&cru HCLK_SDMMC>, 986 <&cru SCLK_SDMMC>; 987 pm_qos = <&qos_sd>; 988 }; 989 pd_sdioaudio@RK3399_PD_SDIOAUDIO { 990 reg = <RK3399_PD_SDIOAUDIO>; 991 clocks = <&cru HCLK_SDIO>; 992 pm_qos = <&qos_sdioaudio>; 993 }; 994 pd_vio@RK3399_PD_VIO { 995 reg = <RK3399_PD_VIO>; 996 #address-cells = <1>; 997 #size-cells = <0>; 998 999 pd_hdcp@RK3399_PD_HDCP { 1000 reg = <RK3399_PD_HDCP>; 1001 clocks = <&cru ACLK_HDCP>, 1002 <&cru HCLK_HDCP>, 1003 <&cru PCLK_HDCP>; 1004 pm_qos = <&qos_hdcp>; 1005 }; 1006 pd_isp0@RK3399_PD_ISP0 { 1007 reg = <RK3399_PD_ISP0>; 1008 clocks = <&cru ACLK_ISP0>, 1009 <&cru HCLK_ISP0>; 1010 pm_qos = <&qos_isp0_m0>, 1011 <&qos_isp0_m1>; 1012 }; 1013 pd_isp1@RK3399_PD_ISP1 { 1014 reg = <RK3399_PD_ISP1>; 1015 clocks = <&cru ACLK_ISP1>, 1016 <&cru HCLK_ISP1>; 1017 pm_qos = <&qos_isp1_m0>, 1018 <&qos_isp1_m1>; 1019 }; 1020 pd_tcpc0@RK3399_PD_TCPC0 { 1021 reg = <RK3399_PD_TCPD0>; 1022 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1023 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1024 }; 1025 pd_tcpc1@RK3399_PD_TCPC1 { 1026 reg = <RK3399_PD_TCPD1>; 1027 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1028 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1029 }; 1030 pd_vo@RK3399_PD_VO { 1031 reg = <RK3399_PD_VO>; 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 1035 pd_vopb@RK3399_PD_VOPB { 1036 reg = <RK3399_PD_VOPB>; 1037 clocks = <&cru ACLK_VOP0>, 1038 <&cru HCLK_VOP0>; 1039 pm_qos = <&qos_vop_big_r>, 1040 <&qos_vop_big_w>; 1041 }; 1042 pd_vopl@RK3399_PD_VOPL { 1043 reg = <RK3399_PD_VOPL>; 1044 clocks = <&cru ACLK_VOP1>, 1045 <&cru HCLK_VOP1>; 1046 pm_qos = <&qos_vop_little>; 1047 }; 1048 }; 1049 }; 1050 }; 1051 }; 1052 1053 pmugrf: syscon@ff320000 { 1054 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1055 reg = <0x0 0xff320000 0x0 0x1000>; 1056 #address-cells = <1>; 1057 #size-cells = <1>; 1058 1059 pmu_io_domains: io-domains { 1060 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1061 status = "disabled"; 1062 }; 1063 }; 1064 1065 spi3: spi@ff350000 { 1066 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1067 reg = <0x0 0xff350000 0x0 0x1000>; 1068 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1069 clock-names = "spiclk", "apb_pclk"; 1070 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1071 pinctrl-names = "default"; 1072 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 status = "disabled"; 1076 }; 1077 1078 uart4: serial@ff370000 { 1079 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1080 reg = <0x0 0xff370000 0x0 0x100>; 1081 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1082 clock-names = "baudclk", "apb_pclk"; 1083 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1084 reg-shift = <2>; 1085 reg-io-width = <4>; 1086 pinctrl-names = "default"; 1087 pinctrl-0 = <&uart4_xfer>; 1088 status = "disabled"; 1089 }; 1090 1091 i2c0: i2c@ff3c0000 { 1092 compatible = "rockchip,rk3399-i2c"; 1093 reg = <0x0 0xff3c0000 0x0 0x1000>; 1094 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1095 assigned-clock-rates = <200000000>; 1096 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1097 clock-names = "i2c", "pclk"; 1098 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1099 pinctrl-names = "default"; 1100 pinctrl-0 = <&i2c0_xfer>; 1101 #address-cells = <1>; 1102 #size-cells = <0>; 1103 status = "disabled"; 1104 }; 1105 1106 i2c4: i2c@ff3d0000 { 1107 compatible = "rockchip,rk3399-i2c"; 1108 reg = <0x0 0xff3d0000 0x0 0x1000>; 1109 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1110 assigned-clock-rates = <200000000>; 1111 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1112 clock-names = "i2c", "pclk"; 1113 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1114 pinctrl-names = "default"; 1115 pinctrl-0 = <&i2c4_xfer>; 1116 #address-cells = <1>; 1117 #size-cells = <0>; 1118 status = "disabled"; 1119 }; 1120 1121 i2c8: i2c@ff3e0000 { 1122 compatible = "rockchip,rk3399-i2c"; 1123 reg = <0x0 0xff3e0000 0x0 0x1000>; 1124 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1125 assigned-clock-rates = <200000000>; 1126 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1127 clock-names = "i2c", "pclk"; 1128 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1129 pinctrl-names = "default"; 1130 pinctrl-0 = <&i2c8_xfer>; 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 status = "disabled"; 1134 }; 1135 1136 pwm0: pwm@ff420000 { 1137 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1138 reg = <0x0 0xff420000 0x0 0x10>; 1139 #pwm-cells = <3>; 1140 pinctrl-names = "default"; 1141 pinctrl-0 = <&pwm0_pin>; 1142 clocks = <&pmucru PCLK_RKPWM_PMU>; 1143 clock-names = "pwm"; 1144 status = "disabled"; 1145 }; 1146 1147 pwm1: pwm@ff420010 { 1148 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1149 reg = <0x0 0xff420010 0x0 0x10>; 1150 #pwm-cells = <3>; 1151 pinctrl-names = "default"; 1152 pinctrl-0 = <&pwm1_pin>; 1153 clocks = <&pmucru PCLK_RKPWM_PMU>; 1154 clock-names = "pwm"; 1155 status = "disabled"; 1156 }; 1157 1158 pwm2: pwm@ff420020 { 1159 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1160 reg = <0x0 0xff420020 0x0 0x10>; 1161 #pwm-cells = <3>; 1162 pinctrl-names = "default"; 1163 pinctrl-0 = <&pwm2_pin>; 1164 clocks = <&pmucru PCLK_RKPWM_PMU>; 1165 clock-names = "pwm"; 1166 status = "disabled"; 1167 }; 1168 1169 pwm3: pwm@ff420030 { 1170 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1171 reg = <0x0 0xff420030 0x0 0x10>; 1172 #pwm-cells = <3>; 1173 pinctrl-names = "default"; 1174 pinctrl-0 = <&pwm3a_pin>; 1175 clocks = <&pmucru PCLK_RKPWM_PMU>; 1176 clock-names = "pwm"; 1177 status = "disabled"; 1178 }; 1179 1180 vpu_mmu: iommu@ff650800 { 1181 compatible = "rockchip,iommu"; 1182 reg = <0x0 0xff650800 0x0 0x40>; 1183 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 1184 interrupt-names = "vpu_mmu"; 1185 #iommu-cells = <0>; 1186 status = "disabled"; 1187 }; 1188 1189 vdec_mmu: iommu@ff660480 { 1190 compatible = "rockchip,iommu"; 1191 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; 1192 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1193 interrupt-names = "vdec_mmu"; 1194 #iommu-cells = <0>; 1195 status = "disabled"; 1196 }; 1197 1198 iep_mmu: iommu@ff670800 { 1199 compatible = "rockchip,iommu"; 1200 reg = <0x0 0xff670800 0x0 0x40>; 1201 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>; 1202 interrupt-names = "iep_mmu"; 1203 #iommu-cells = <0>; 1204 status = "disabled"; 1205 }; 1206 1207 rga: rga@ff680000 { 1208 compatible = "rockchip,rk3399-rga"; 1209 reg = <0x0 0xff680000 0x0 0x10000>; 1210 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>; 1211 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; 1212 clock-names = "aclk", "hclk", "sclk"; 1213 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 1214 reset-names = "core", "axi", "ahb"; 1215 power-domains = <&power RK3399_PD_RGA>; 1216 }; 1217 1218 efuse0: efuse@ff690000 { 1219 compatible = "rockchip,rk3399-efuse"; 1220 reg = <0x0 0xff690000 0x0 0x80>; 1221 #address-cells = <1>; 1222 #size-cells = <1>; 1223 clocks = <&cru PCLK_EFUSE1024NS>; 1224 clock-names = "pclk_efuse"; 1225 1226 /* Data cells */ 1227 cpu_id: cpu-id@7 { 1228 reg = <0x07 0x10>; 1229 }; 1230 cpub_leakage: cpu-leakage@17 { 1231 reg = <0x17 0x1>; 1232 }; 1233 gpu_leakage: gpu-leakage@18 { 1234 reg = <0x18 0x1>; 1235 }; 1236 center_leakage: center-leakage@19 { 1237 reg = <0x19 0x1>; 1238 }; 1239 cpul_leakage: cpu-leakage@1a { 1240 reg = <0x1a 0x1>; 1241 }; 1242 logic_leakage: logic-leakage@1b { 1243 reg = <0x1b 0x1>; 1244 }; 1245 wafer_info: wafer-info@1c { 1246 reg = <0x1c 0x1>; 1247 }; 1248 }; 1249 1250 pmucru: pmu-clock-controller@ff750000 { 1251 compatible = "rockchip,rk3399-pmucru"; 1252 reg = <0x0 0xff750000 0x0 0x1000>; 1253 rockchip,grf = <&pmugrf>; 1254 #clock-cells = <1>; 1255 #reset-cells = <1>; 1256 assigned-clocks = <&pmucru PLL_PPLL>; 1257 assigned-clock-rates = <676000000>; 1258 }; 1259 1260 cru: clock-controller@ff760000 { 1261 compatible = "rockchip,rk3399-cru"; 1262 reg = <0x0 0xff760000 0x0 0x1000>; 1263 rockchip,grf = <&grf>; 1264 #clock-cells = <1>; 1265 #reset-cells = <1>; 1266 assigned-clocks = 1267 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1268 <&cru PLL_NPLL>, 1269 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1270 <&cru PCLK_PERIHP>, 1271 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1272 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1273 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; 1274 assigned-clock-rates = 1275 <594000000>, <800000000>, 1276 <1000000000>, 1277 <150000000>, <75000000>, 1278 <37500000>, 1279 <100000000>, <100000000>, 1280 <50000000>, <600000000>, 1281 <100000000>, <50000000>; 1282 }; 1283 1284 grf: syscon@ff770000 { 1285 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1286 reg = <0x0 0xff770000 0x0 0x10000>; 1287 #address-cells = <1>; 1288 #size-cells = <1>; 1289 1290 io_domains: io-domains { 1291 compatible = "rockchip,rk3399-io-voltage-domain"; 1292 status = "disabled"; 1293 }; 1294 1295 u2phy0: usb2-phy@e450 { 1296 compatible = "rockchip,rk3399-usb2phy"; 1297 reg = <0xe450 0x10>; 1298 clocks = <&cru SCLK_USB2PHY0_REF>; 1299 clock-names = "phyclk"; 1300 #clock-cells = <0>; 1301 clock-output-names = "clk_usbphy0_480m"; 1302 status = "disabled"; 1303 1304 u2phy0_host: host-port { 1305 #phy-cells = <0>; 1306 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1307 interrupt-names = "linestate"; 1308 status = "disabled"; 1309 }; 1310 1311 u2phy0_otg: otg-port { 1312 #phy-cells = <0>; 1313 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1314 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1315 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1316 interrupt-names = "otg-bvalid", "otg-id", 1317 "linestate"; 1318 status = "disabled"; 1319 }; 1320 }; 1321 1322 u2phy1: usb2-phy@e460 { 1323 compatible = "rockchip,rk3399-usb2phy"; 1324 reg = <0xe460 0x10>; 1325 clocks = <&cru SCLK_USB2PHY1_REF>; 1326 clock-names = "phyclk"; 1327 #clock-cells = <0>; 1328 clock-output-names = "clk_usbphy1_480m"; 1329 status = "disabled"; 1330 1331 u2phy1_host: host-port { 1332 #phy-cells = <0>; 1333 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1334 interrupt-names = "linestate"; 1335 status = "disabled"; 1336 }; 1337 1338 u2phy1_otg: otg-port { 1339 #phy-cells = <0>; 1340 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1341 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1342 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1343 interrupt-names = "otg-bvalid", "otg-id", 1344 "linestate"; 1345 status = "disabled"; 1346 }; 1347 }; 1348 1349 emmc_phy: phy@f780 { 1350 compatible = "rockchip,rk3399-emmc-phy"; 1351 reg = <0xf780 0x24>; 1352 clocks = <&sdhci>; 1353 clock-names = "emmcclk"; 1354 #phy-cells = <0>; 1355 status = "disabled"; 1356 }; 1357 1358 pcie_phy: pcie-phy { 1359 compatible = "rockchip,rk3399-pcie-phy"; 1360 clocks = <&cru SCLK_PCIEPHY_REF>; 1361 clock-names = "refclk"; 1362 #phy-cells = <1>; 1363 resets = <&cru SRST_PCIEPHY>; 1364 reset-names = "phy"; 1365 status = "disabled"; 1366 }; 1367 }; 1368 1369 tcphy0: phy@ff7c0000 { 1370 compatible = "rockchip,rk3399-typec-phy"; 1371 reg = <0x0 0xff7c0000 0x0 0x40000>; 1372 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1373 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1374 clock-names = "tcpdcore", "tcpdphy-ref"; 1375 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1376 assigned-clock-rates = <50000000>; 1377 power-domains = <&power RK3399_PD_TCPD0>; 1378 resets = <&cru SRST_UPHY0>, 1379 <&cru SRST_UPHY0_PIPE_L00>, 1380 <&cru SRST_P_UPHY0_TCPHY>; 1381 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1382 rockchip,grf = <&grf>; 1383 rockchip,typec-conn-dir = <0xe580 0 16>; 1384 rockchip,usb3tousb2-en = <0xe580 3 19>; 1385 rockchip,external-psm = <0xe588 14 30>; 1386 rockchip,pipe-status = <0xe5c0 0 0>; 1387 status = "disabled"; 1388 1389 tcphy0_dp: dp-port { 1390 #phy-cells = <0>; 1391 }; 1392 1393 tcphy0_usb3: usb3-port { 1394 #phy-cells = <0>; 1395 }; 1396 }; 1397 1398 tcphy1: phy@ff800000 { 1399 compatible = "rockchip,rk3399-typec-phy"; 1400 reg = <0x0 0xff800000 0x0 0x40000>; 1401 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1402 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1403 clock-names = "tcpdcore", "tcpdphy-ref"; 1404 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1405 assigned-clock-rates = <50000000>; 1406 power-domains = <&power RK3399_PD_TCPD1>; 1407 resets = <&cru SRST_UPHY1>, 1408 <&cru SRST_UPHY1_PIPE_L00>, 1409 <&cru SRST_P_UPHY1_TCPHY>; 1410 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1411 rockchip,grf = <&grf>; 1412 rockchip,typec-conn-dir = <0xe58c 0 16>; 1413 rockchip,usb3tousb2-en = <0xe58c 3 19>; 1414 rockchip,external-psm = <0xe594 14 30>; 1415 rockchip,pipe-status = <0xe5c0 16 16>; 1416 status = "disabled"; 1417 1418 tcphy1_dp: dp-port { 1419 #phy-cells = <0>; 1420 }; 1421 1422 tcphy1_usb3: usb3-port { 1423 #phy-cells = <0>; 1424 }; 1425 }; 1426 1427 watchdog@ff848000 { 1428 compatible = "snps,dw-wdt"; 1429 reg = <0x0 0xff848000 0x0 0x100>; 1430 clocks = <&cru PCLK_WDT>; 1431 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1432 }; 1433 1434 rktimer: rktimer@ff850000 { 1435 compatible = "rockchip,rk3399-timer"; 1436 reg = <0x0 0xff850000 0x0 0x1000>; 1437 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1438 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1439 clock-names = "pclk", "timer"; 1440 }; 1441 1442 spdif: spdif@ff870000 { 1443 compatible = "rockchip,rk3399-spdif"; 1444 reg = <0x0 0xff870000 0x0 0x1000>; 1445 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1446 dmas = <&dmac_bus 7>; 1447 dma-names = "tx"; 1448 clock-names = "mclk", "hclk"; 1449 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1450 pinctrl-names = "default"; 1451 pinctrl-0 = <&spdif_bus>; 1452 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1453 status = "disabled"; 1454 }; 1455 1456 i2s0: i2s@ff880000 { 1457 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1458 reg = <0x0 0xff880000 0x0 0x1000>; 1459 rockchip,grf = <&grf>; 1460 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1461 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1462 dma-names = "tx", "rx"; 1463 clock-names = "i2s_clk", "i2s_hclk"; 1464 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1465 pinctrl-names = "default"; 1466 pinctrl-0 = <&i2s0_8ch_bus>; 1467 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1468 status = "disabled"; 1469 }; 1470 1471 i2s1: i2s@ff890000 { 1472 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1473 reg = <0x0 0xff890000 0x0 0x1000>; 1474 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1475 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1476 dma-names = "tx", "rx"; 1477 clock-names = "i2s_clk", "i2s_hclk"; 1478 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1479 pinctrl-names = "default"; 1480 pinctrl-0 = <&i2s1_2ch_bus>; 1481 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1482 status = "disabled"; 1483 }; 1484 1485 i2s2: i2s@ff8a0000 { 1486 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1487 reg = <0x0 0xff8a0000 0x0 0x1000>; 1488 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1489 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1490 dma-names = "tx", "rx"; 1491 clock-names = "i2s_clk", "i2s_hclk"; 1492 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1493 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1494 status = "disabled"; 1495 }; 1496 1497 vopl: vop@ff8f0000 { 1498 compatible = "rockchip,rk3399-vop-lit"; 1499 reg = <0x0 0xff8f0000 0x0 0x3efc>; 1500 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1501 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1502 assigned-clock-rates = <400000000>, <100000000>; 1503 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1504 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1505 iommus = <&vopl_mmu>; 1506 power-domains = <&power RK3399_PD_VOPL>; 1507 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1508 reset-names = "axi", "ahb", "dclk"; 1509 status = "disabled"; 1510 1511 vopl_out: port { 1512 #address-cells = <1>; 1513 #size-cells = <0>; 1514 1515 vopl_out_mipi: endpoint@0 { 1516 reg = <0>; 1517 remote-endpoint = <&mipi_in_vopl>; 1518 }; 1519 1520 vopl_out_edp: endpoint@1 { 1521 reg = <1>; 1522 remote-endpoint = <&edp_in_vopl>; 1523 }; 1524 1525 vopl_out_hdmi: endpoint@2 { 1526 reg = <2>; 1527 remote-endpoint = <&hdmi_in_vopl>; 1528 }; 1529 }; 1530 }; 1531 1532 vopl_mmu: iommu@ff8f3f00 { 1533 compatible = "rockchip,iommu"; 1534 reg = <0x0 0xff8f3f00 0x0 0x100>; 1535 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1536 interrupt-names = "vopl_mmu"; 1537 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1538 clock-names = "aclk", "hclk"; 1539 power-domains = <&power RK3399_PD_VOPL>; 1540 #iommu-cells = <0>; 1541 status = "disabled"; 1542 }; 1543 1544 vopb: vop@ff900000 { 1545 compatible = "rockchip,rk3399-vop-big"; 1546 reg = <0x0 0xff900000 0x0 0x3efc>; 1547 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1548 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1549 assigned-clock-rates = <400000000>, <100000000>; 1550 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1551 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1552 iommus = <&vopb_mmu>; 1553 power-domains = <&power RK3399_PD_VOPB>; 1554 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1555 reset-names = "axi", "ahb", "dclk"; 1556 status = "disabled"; 1557 1558 vopb_out: port { 1559 #address-cells = <1>; 1560 #size-cells = <0>; 1561 1562 vopb_out_edp: endpoint@0 { 1563 reg = <0>; 1564 remote-endpoint = <&edp_in_vopb>; 1565 }; 1566 1567 vopb_out_mipi: endpoint@1 { 1568 reg = <1>; 1569 remote-endpoint = <&mipi_in_vopb>; 1570 }; 1571 1572 vopb_out_hdmi: endpoint@2 { 1573 reg = <2>; 1574 remote-endpoint = <&hdmi_in_vopb>; 1575 }; 1576 }; 1577 }; 1578 1579 vopb_mmu: iommu@ff903f00 { 1580 compatible = "rockchip,iommu"; 1581 reg = <0x0 0xff903f00 0x0 0x100>; 1582 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1583 interrupt-names = "vopb_mmu"; 1584 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1585 clock-names = "aclk", "hclk"; 1586 power-domains = <&power RK3399_PD_VOPB>; 1587 #iommu-cells = <0>; 1588 status = "disabled"; 1589 }; 1590 1591 isp0_mmu: iommu@ff914000 { 1592 compatible = "rockchip,iommu"; 1593 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1594 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1595 interrupt-names = "isp0_mmu"; 1596 #iommu-cells = <0>; 1597 rockchip,disable-mmu-reset; 1598 status = "disabled"; 1599 }; 1600 1601 isp1_mmu: iommu@ff924000 { 1602 compatible = "rockchip,iommu"; 1603 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; 1604 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 1605 interrupt-names = "isp1_mmu"; 1606 #iommu-cells = <0>; 1607 rockchip,disable-mmu-reset; 1608 status = "disabled"; 1609 }; 1610 1611 hdmi: hdmi@ff940000 { 1612 compatible = "rockchip,rk3399-dw-hdmi"; 1613 reg = <0x0 0xff940000 0x0 0x20000>; 1614 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 1615 clocks = <&cru PCLK_HDMI_CTRL>, 1616 <&cru SCLK_HDMI_SFR>, 1617 <&cru PLL_VPLL>, 1618 <&cru PCLK_VIO_GRF>, 1619 <&cru SCLK_HDMI_CEC>; 1620 clock-names = "iahb", "isfr", "vpll", "grf", "cec"; 1621 power-domains = <&power RK3399_PD_HDCP>; 1622 reg-io-width = <4>; 1623 rockchip,grf = <&grf>; 1624 status = "disabled"; 1625 1626 ports { 1627 hdmi_in: port { 1628 #address-cells = <1>; 1629 #size-cells = <0>; 1630 1631 hdmi_in_vopb: endpoint@0 { 1632 reg = <0>; 1633 remote-endpoint = <&vopb_out_hdmi>; 1634 }; 1635 hdmi_in_vopl: endpoint@1 { 1636 reg = <1>; 1637 remote-endpoint = <&vopl_out_hdmi>; 1638 }; 1639 }; 1640 }; 1641 }; 1642 1643 mipi_dsi: mipi@ff960000 { 1644 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1645 reg = <0x0 0xff960000 0x0 0x8000>; 1646 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 1647 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, 1648 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; 1649 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1650 power-domains = <&power RK3399_PD_VIO>; 1651 rockchip,grf = <&grf>; 1652 status = "disabled"; 1653 1654 ports { 1655 mipi_in: port { 1656 #address-cells = <1>; 1657 #size-cells = <0>; 1658 1659 mipi_in_vopb: endpoint@0 { 1660 reg = <0>; 1661 remote-endpoint = <&vopb_out_mipi>; 1662 }; 1663 mipi_in_vopl: endpoint@1 { 1664 reg = <1>; 1665 remote-endpoint = <&vopl_out_mipi>; 1666 }; 1667 }; 1668 }; 1669 }; 1670 1671 edp: edp@ff970000 { 1672 compatible = "rockchip,rk3399-edp"; 1673 reg = <0x0 0xff970000 0x0 0x8000>; 1674 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 1675 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>; 1676 clock-names = "dp", "pclk"; 1677 pinctrl-names = "default"; 1678 pinctrl-0 = <&edp_hpd>; 1679 power-domains = <&power RK3399_PD_EDP>; 1680 resets = <&cru SRST_P_EDP_CTRL>; 1681 reset-names = "dp"; 1682 rockchip,grf = <&grf>; 1683 status = "disabled"; 1684 1685 ports { 1686 #address-cells = <1>; 1687 #size-cells = <0>; 1688 edp_in: port@0 { 1689 reg = <0>; 1690 #address-cells = <1>; 1691 #size-cells = <0>; 1692 1693 edp_in_vopb: endpoint@0 { 1694 reg = <0>; 1695 remote-endpoint = <&vopb_out_edp>; 1696 }; 1697 1698 edp_in_vopl: endpoint@1 { 1699 reg = <1>; 1700 remote-endpoint = <&vopl_out_edp>; 1701 }; 1702 }; 1703 }; 1704 }; 1705 1706 gpu: gpu@ff9a0000 { 1707 compatible = "rockchip,rk3399-mali", "arm,mali-t860"; 1708 reg = <0x0 0xff9a0000 0x0 0x10000>; 1709 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>, 1710 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, 1711 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>; 1712 interrupt-names = "gpu", "job", "mmu"; 1713 clocks = <&cru ACLK_GPU>; 1714 power-domains = <&power RK3399_PD_GPU>; 1715 status = "disabled"; 1716 }; 1717 1718 pinctrl: pinctrl { 1719 compatible = "rockchip,rk3399-pinctrl"; 1720 rockchip,grf = <&grf>; 1721 rockchip,pmu = <&pmugrf>; 1722 #address-cells = <2>; 1723 #size-cells = <2>; 1724 ranges; 1725 1726 gpio0: gpio0@ff720000 { 1727 compatible = "rockchip,gpio-bank"; 1728 reg = <0x0 0xff720000 0x0 0x100>; 1729 clocks = <&pmucru PCLK_GPIO0_PMU>; 1730 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 1731 1732 gpio-controller; 1733 #gpio-cells = <0x2>; 1734 1735 interrupt-controller; 1736 #interrupt-cells = <0x2>; 1737 }; 1738 1739 gpio1: gpio1@ff730000 { 1740 compatible = "rockchip,gpio-bank"; 1741 reg = <0x0 0xff730000 0x0 0x100>; 1742 clocks = <&pmucru PCLK_GPIO1_PMU>; 1743 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 1744 1745 gpio-controller; 1746 #gpio-cells = <0x2>; 1747 1748 interrupt-controller; 1749 #interrupt-cells = <0x2>; 1750 }; 1751 1752 gpio2: gpio2@ff780000 { 1753 compatible = "rockchip,gpio-bank"; 1754 reg = <0x0 0xff780000 0x0 0x100>; 1755 clocks = <&cru PCLK_GPIO2>; 1756 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 1757 1758 gpio-controller; 1759 #gpio-cells = <0x2>; 1760 1761 interrupt-controller; 1762 #interrupt-cells = <0x2>; 1763 }; 1764 1765 gpio3: gpio3@ff788000 { 1766 compatible = "rockchip,gpio-bank"; 1767 reg = <0x0 0xff788000 0x0 0x100>; 1768 clocks = <&cru PCLK_GPIO3>; 1769 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 1770 1771 gpio-controller; 1772 #gpio-cells = <0x2>; 1773 1774 interrupt-controller; 1775 #interrupt-cells = <0x2>; 1776 }; 1777 1778 gpio4: gpio4@ff790000 { 1779 compatible = "rockchip,gpio-bank"; 1780 reg = <0x0 0xff790000 0x0 0x100>; 1781 clocks = <&cru PCLK_GPIO4>; 1782 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 1783 1784 gpio-controller; 1785 #gpio-cells = <0x2>; 1786 1787 interrupt-controller; 1788 #interrupt-cells = <0x2>; 1789 }; 1790 1791 pcfg_pull_up: pcfg-pull-up { 1792 bias-pull-up; 1793 }; 1794 1795 pcfg_pull_down: pcfg-pull-down { 1796 bias-pull-down; 1797 }; 1798 1799 pcfg_pull_none: pcfg-pull-none { 1800 bias-disable; 1801 }; 1802 1803 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1804 bias-disable; 1805 drive-strength = <12>; 1806 }; 1807 1808 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1809 bias-pull-up; 1810 drive-strength = <8>; 1811 }; 1812 1813 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1814 bias-pull-down; 1815 drive-strength = <4>; 1816 }; 1817 1818 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1819 bias-pull-up; 1820 drive-strength = <2>; 1821 }; 1822 1823 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 1824 bias-pull-down; 1825 drive-strength = <12>; 1826 }; 1827 1828 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 1829 bias-disable; 1830 drive-strength = <13>; 1831 }; 1832 1833 clock { 1834 clk_32k: clk-32k { 1835 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; 1836 }; 1837 }; 1838 1839 edp { 1840 edp_hpd: edp-hpd { 1841 rockchip,pins = 1842 <4 23 RK_FUNC_2 &pcfg_pull_none>; 1843 }; 1844 }; 1845 1846 gmac { 1847 rgmii_pins: rgmii-pins { 1848 rockchip,pins = 1849 /* mac_txclk */ 1850 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>, 1851 /* mac_rxclk */ 1852 <3 14 RK_FUNC_1 &pcfg_pull_none>, 1853 /* mac_mdio */ 1854 <3 13 RK_FUNC_1 &pcfg_pull_none>, 1855 /* mac_txen */ 1856 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>, 1857 /* mac_clk */ 1858 <3 11 RK_FUNC_1 &pcfg_pull_none>, 1859 /* mac_rxdv */ 1860 <3 9 RK_FUNC_1 &pcfg_pull_none>, 1861 /* mac_mdc */ 1862 <3 8 RK_FUNC_1 &pcfg_pull_none>, 1863 /* mac_rxd1 */ 1864 <3 7 RK_FUNC_1 &pcfg_pull_none>, 1865 /* mac_rxd0 */ 1866 <3 6 RK_FUNC_1 &pcfg_pull_none>, 1867 /* mac_txd1 */ 1868 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>, 1869 /* mac_txd0 */ 1870 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>, 1871 /* mac_rxd3 */ 1872 <3 3 RK_FUNC_1 &pcfg_pull_none>, 1873 /* mac_rxd2 */ 1874 <3 2 RK_FUNC_1 &pcfg_pull_none>, 1875 /* mac_txd3 */ 1876 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>, 1877 /* mac_txd2 */ 1878 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>; 1879 }; 1880 1881 rmii_pins: rmii-pins { 1882 rockchip,pins = 1883 /* mac_mdio */ 1884 <3 13 RK_FUNC_1 &pcfg_pull_none>, 1885 /* mac_txen */ 1886 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>, 1887 /* mac_clk */ 1888 <3 11 RK_FUNC_1 &pcfg_pull_none>, 1889 /* mac_rxer */ 1890 <3 10 RK_FUNC_1 &pcfg_pull_none>, 1891 /* mac_rxdv */ 1892 <3 9 RK_FUNC_1 &pcfg_pull_none>, 1893 /* mac_mdc */ 1894 <3 8 RK_FUNC_1 &pcfg_pull_none>, 1895 /* mac_rxd1 */ 1896 <3 7 RK_FUNC_1 &pcfg_pull_none>, 1897 /* mac_rxd0 */ 1898 <3 6 RK_FUNC_1 &pcfg_pull_none>, 1899 /* mac_txd1 */ 1900 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>, 1901 /* mac_txd0 */ 1902 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>; 1903 }; 1904 }; 1905 1906 i2c0 { 1907 i2c0_xfer: i2c0-xfer { 1908 rockchip,pins = 1909 <1 15 RK_FUNC_2 &pcfg_pull_none>, 1910 <1 16 RK_FUNC_2 &pcfg_pull_none>; 1911 }; 1912 }; 1913 1914 i2c1 { 1915 i2c1_xfer: i2c1-xfer { 1916 rockchip,pins = 1917 <4 2 RK_FUNC_1 &pcfg_pull_none>, 1918 <4 1 RK_FUNC_1 &pcfg_pull_none>; 1919 }; 1920 }; 1921 1922 i2c2 { 1923 i2c2_xfer: i2c2-xfer { 1924 rockchip,pins = 1925 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>, 1926 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>; 1927 }; 1928 }; 1929 1930 i2c3 { 1931 i2c3_xfer: i2c3-xfer { 1932 rockchip,pins = 1933 <4 17 RK_FUNC_1 &pcfg_pull_none>, 1934 <4 16 RK_FUNC_1 &pcfg_pull_none>; 1935 }; 1936 }; 1937 1938 i2c4 { 1939 i2c4_xfer: i2c4-xfer { 1940 rockchip,pins = 1941 <1 12 RK_FUNC_1 &pcfg_pull_none>, 1942 <1 11 RK_FUNC_1 &pcfg_pull_none>; 1943 }; 1944 }; 1945 1946 i2c5 { 1947 i2c5_xfer: i2c5-xfer { 1948 rockchip,pins = 1949 <3 11 RK_FUNC_2 &pcfg_pull_none>, 1950 <3 10 RK_FUNC_2 &pcfg_pull_none>; 1951 }; 1952 }; 1953 1954 i2c6 { 1955 i2c6_xfer: i2c6-xfer { 1956 rockchip,pins = 1957 <2 10 RK_FUNC_2 &pcfg_pull_none>, 1958 <2 9 RK_FUNC_2 &pcfg_pull_none>; 1959 }; 1960 }; 1961 1962 i2c7 { 1963 i2c7_xfer: i2c7-xfer { 1964 rockchip,pins = 1965 <2 8 RK_FUNC_2 &pcfg_pull_none>, 1966 <2 7 RK_FUNC_2 &pcfg_pull_none>; 1967 }; 1968 }; 1969 1970 i2c8 { 1971 i2c8_xfer: i2c8-xfer { 1972 rockchip,pins = 1973 <1 21 RK_FUNC_1 &pcfg_pull_none>, 1974 <1 20 RK_FUNC_1 &pcfg_pull_none>; 1975 }; 1976 }; 1977 1978 i2s0 { 1979 i2s0_8ch_bus: i2s0-8ch-bus { 1980 rockchip,pins = 1981 <3 24 RK_FUNC_1 &pcfg_pull_none>, 1982 <3 25 RK_FUNC_1 &pcfg_pull_none>, 1983 <3 26 RK_FUNC_1 &pcfg_pull_none>, 1984 <3 27 RK_FUNC_1 &pcfg_pull_none>, 1985 <3 28 RK_FUNC_1 &pcfg_pull_none>, 1986 <3 29 RK_FUNC_1 &pcfg_pull_none>, 1987 <3 30 RK_FUNC_1 &pcfg_pull_none>, 1988 <3 31 RK_FUNC_1 &pcfg_pull_none>, 1989 <4 0 RK_FUNC_1 &pcfg_pull_none>; 1990 }; 1991 }; 1992 1993 i2s1 { 1994 i2s1_2ch_bus: i2s1-2ch-bus { 1995 rockchip,pins = 1996 <4 3 RK_FUNC_1 &pcfg_pull_none>, 1997 <4 4 RK_FUNC_1 &pcfg_pull_none>, 1998 <4 5 RK_FUNC_1 &pcfg_pull_none>, 1999 <4 6 RK_FUNC_1 &pcfg_pull_none>, 2000 <4 7 RK_FUNC_1 &pcfg_pull_none>; 2001 }; 2002 }; 2003 2004 sdio0 { 2005 sdio0_bus1: sdio0-bus1 { 2006 rockchip,pins = 2007 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>; 2008 }; 2009 2010 sdio0_bus4: sdio0-bus4 { 2011 rockchip,pins = 2012 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>, 2013 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>, 2014 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>, 2015 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>; 2016 }; 2017 2018 sdio0_cmd: sdio0-cmd { 2019 rockchip,pins = 2020 <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>; 2021 }; 2022 2023 sdio0_clk: sdio0-clk { 2024 rockchip,pins = 2025 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 2026 }; 2027 2028 sdio0_cd: sdio0-cd { 2029 rockchip,pins = 2030 <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>; 2031 }; 2032 2033 sdio0_pwr: sdio0-pwr { 2034 rockchip,pins = 2035 <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>; 2036 }; 2037 2038 sdio0_bkpwr: sdio0-bkpwr { 2039 rockchip,pins = 2040 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; 2041 }; 2042 2043 sdio0_wp: sdio0-wp { 2044 rockchip,pins = 2045 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>; 2046 }; 2047 2048 sdio0_int: sdio0-int { 2049 rockchip,pins = 2050 <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>; 2051 }; 2052 }; 2053 2054 sdmmc { 2055 sdmmc_bus1: sdmmc-bus1 { 2056 rockchip,pins = 2057 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; 2058 }; 2059 2060 sdmmc_bus4: sdmmc-bus4 { 2061 rockchip,pins = 2062 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>, 2063 <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>, 2064 <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>, 2065 <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>; 2066 }; 2067 2068 sdmmc_clk: sdmmc-clk { 2069 rockchip,pins = 2070 <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 2071 }; 2072 2073 sdmmc_cmd: sdmmc-cmd { 2074 rockchip,pins = 2075 <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>; 2076 }; 2077 2078 sdmmc_cd: sdmmc-cd { 2079 rockchip,pins = 2080 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>; 2081 }; 2082 2083 sdmmc_wp: sdmmc-wp { 2084 rockchip,pins = 2085 <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; 2086 }; 2087 }; 2088 2089 sleep { 2090 ap_pwroff: ap-pwroff { 2091 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>; 2092 }; 2093 2094 ddrio_pwroff: ddrio-pwroff { 2095 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; 2096 }; 2097 }; 2098 2099 spdif { 2100 spdif_bus: spdif-bus { 2101 rockchip,pins = 2102 <4 21 RK_FUNC_1 &pcfg_pull_none>; 2103 }; 2104 2105 spdif_bus_1: spdif-bus-1 { 2106 rockchip,pins = 2107 <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; 2108 }; 2109 }; 2110 2111 spi0 { 2112 spi0_clk: spi0-clk { 2113 rockchip,pins = 2114 <3 6 RK_FUNC_2 &pcfg_pull_up>; 2115 }; 2116 spi0_cs0: spi0-cs0 { 2117 rockchip,pins = 2118 <3 7 RK_FUNC_2 &pcfg_pull_up>; 2119 }; 2120 spi0_cs1: spi0-cs1 { 2121 rockchip,pins = 2122 <3 8 RK_FUNC_2 &pcfg_pull_up>; 2123 }; 2124 spi0_tx: spi0-tx { 2125 rockchip,pins = 2126 <3 5 RK_FUNC_2 &pcfg_pull_up>; 2127 }; 2128 spi0_rx: spi0-rx { 2129 rockchip,pins = 2130 <3 4 RK_FUNC_2 &pcfg_pull_up>; 2131 }; 2132 }; 2133 2134 spi1 { 2135 spi1_clk: spi1-clk { 2136 rockchip,pins = 2137 <1 9 RK_FUNC_2 &pcfg_pull_up>; 2138 }; 2139 spi1_cs0: spi1-cs0 { 2140 rockchip,pins = 2141 <1 10 RK_FUNC_2 &pcfg_pull_up>; 2142 }; 2143 spi1_rx: spi1-rx { 2144 rockchip,pins = 2145 <1 7 RK_FUNC_2 &pcfg_pull_up>; 2146 }; 2147 spi1_tx: spi1-tx { 2148 rockchip,pins = 2149 <1 8 RK_FUNC_2 &pcfg_pull_up>; 2150 }; 2151 }; 2152 2153 spi2 { 2154 spi2_clk: spi2-clk { 2155 rockchip,pins = 2156 <2 11 RK_FUNC_1 &pcfg_pull_up>; 2157 }; 2158 spi2_cs0: spi2-cs0 { 2159 rockchip,pins = 2160 <2 12 RK_FUNC_1 &pcfg_pull_up>; 2161 }; 2162 spi2_rx: spi2-rx { 2163 rockchip,pins = 2164 <2 9 RK_FUNC_1 &pcfg_pull_up>; 2165 }; 2166 spi2_tx: spi2-tx { 2167 rockchip,pins = 2168 <2 10 RK_FUNC_1 &pcfg_pull_up>; 2169 }; 2170 }; 2171 2172 spi3 { 2173 spi3_clk: spi3-clk { 2174 rockchip,pins = 2175 <1 17 RK_FUNC_1 &pcfg_pull_up>; 2176 }; 2177 spi3_cs0: spi3-cs0 { 2178 rockchip,pins = 2179 <1 18 RK_FUNC_1 &pcfg_pull_up>; 2180 }; 2181 spi3_rx: spi3-rx { 2182 rockchip,pins = 2183 <1 15 RK_FUNC_1 &pcfg_pull_up>; 2184 }; 2185 spi3_tx: spi3-tx { 2186 rockchip,pins = 2187 <1 16 RK_FUNC_1 &pcfg_pull_up>; 2188 }; 2189 }; 2190 2191 spi4 { 2192 spi4_clk: spi4-clk { 2193 rockchip,pins = 2194 <3 2 RK_FUNC_2 &pcfg_pull_up>; 2195 }; 2196 spi4_cs0: spi4-cs0 { 2197 rockchip,pins = 2198 <3 3 RK_FUNC_2 &pcfg_pull_up>; 2199 }; 2200 spi4_rx: spi4-rx { 2201 rockchip,pins = 2202 <3 0 RK_FUNC_2 &pcfg_pull_up>; 2203 }; 2204 spi4_tx: spi4-tx { 2205 rockchip,pins = 2206 <3 1 RK_FUNC_2 &pcfg_pull_up>; 2207 }; 2208 }; 2209 2210 spi5 { 2211 spi5_clk: spi5-clk { 2212 rockchip,pins = 2213 <2 22 RK_FUNC_2 &pcfg_pull_up>; 2214 }; 2215 spi5_cs0: spi5-cs0 { 2216 rockchip,pins = 2217 <2 23 RK_FUNC_2 &pcfg_pull_up>; 2218 }; 2219 spi5_rx: spi5-rx { 2220 rockchip,pins = 2221 <2 20 RK_FUNC_2 &pcfg_pull_up>; 2222 }; 2223 spi5_tx: spi5-tx { 2224 rockchip,pins = 2225 <2 21 RK_FUNC_2 &pcfg_pull_up>; 2226 }; 2227 }; 2228 2229 tsadc { 2230 otp_gpio: otp-gpio { 2231 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>; 2232 }; 2233 2234 otp_out: otp-out { 2235 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>; 2236 }; 2237 }; 2238 2239 uart0 { 2240 uart0_xfer: uart0-xfer { 2241 rockchip,pins = 2242 <2 16 RK_FUNC_1 &pcfg_pull_up>, 2243 <2 17 RK_FUNC_1 &pcfg_pull_none>; 2244 }; 2245 2246 uart0_cts: uart0-cts { 2247 rockchip,pins = 2248 <2 18 RK_FUNC_1 &pcfg_pull_none>; 2249 }; 2250 2251 uart0_rts: uart0-rts { 2252 rockchip,pins = 2253 <2 19 RK_FUNC_1 &pcfg_pull_none>; 2254 }; 2255 }; 2256 2257 uart1 { 2258 uart1_xfer: uart1-xfer { 2259 rockchip,pins = 2260 <3 12 RK_FUNC_2 &pcfg_pull_up>, 2261 <3 13 RK_FUNC_2 &pcfg_pull_none>; 2262 }; 2263 }; 2264 2265 uart2a { 2266 uart2a_xfer: uart2a-xfer { 2267 rockchip,pins = 2268 <4 8 RK_FUNC_2 &pcfg_pull_up>, 2269 <4 9 RK_FUNC_2 &pcfg_pull_none>; 2270 }; 2271 }; 2272 2273 uart2b { 2274 uart2b_xfer: uart2b-xfer { 2275 rockchip,pins = 2276 <4 16 RK_FUNC_2 &pcfg_pull_up>, 2277 <4 17 RK_FUNC_2 &pcfg_pull_none>; 2278 }; 2279 }; 2280 2281 uart2c { 2282 uart2c_xfer: uart2c-xfer { 2283 rockchip,pins = 2284 <4 19 RK_FUNC_1 &pcfg_pull_up>, 2285 <4 20 RK_FUNC_1 &pcfg_pull_none>; 2286 }; 2287 }; 2288 2289 uart3 { 2290 uart3_xfer: uart3-xfer { 2291 rockchip,pins = 2292 <3 14 RK_FUNC_2 &pcfg_pull_up>, 2293 <3 15 RK_FUNC_2 &pcfg_pull_none>; 2294 }; 2295 2296 uart3_cts: uart3-cts { 2297 rockchip,pins = 2298 <3 18 RK_FUNC_2 &pcfg_pull_none>; 2299 }; 2300 2301 uart3_rts: uart3-rts { 2302 rockchip,pins = 2303 <3 19 RK_FUNC_2 &pcfg_pull_none>; 2304 }; 2305 }; 2306 2307 uart4 { 2308 uart4_xfer: uart4-xfer { 2309 rockchip,pins = 2310 <1 7 RK_FUNC_1 &pcfg_pull_up>, 2311 <1 8 RK_FUNC_1 &pcfg_pull_none>; 2312 }; 2313 }; 2314 2315 uarthdcp { 2316 uarthdcp_xfer: uarthdcp-xfer { 2317 rockchip,pins = 2318 <4 21 RK_FUNC_2 &pcfg_pull_up>, 2319 <4 22 RK_FUNC_2 &pcfg_pull_none>; 2320 }; 2321 }; 2322 2323 pwm0 { 2324 pwm0_pin: pwm0-pin { 2325 rockchip,pins = 2326 <4 18 RK_FUNC_1 &pcfg_pull_none>; 2327 }; 2328 2329 vop0_pwm_pin: vop0-pwm-pin { 2330 rockchip,pins = 2331 <4 18 RK_FUNC_2 &pcfg_pull_none>; 2332 }; 2333 }; 2334 2335 pwm1 { 2336 pwm1_pin: pwm1-pin { 2337 rockchip,pins = 2338 <4 22 RK_FUNC_1 &pcfg_pull_none>; 2339 }; 2340 2341 vop1_pwm_pin: vop1-pwm-pin { 2342 rockchip,pins = 2343 <4 18 RK_FUNC_3 &pcfg_pull_none>; 2344 }; 2345 }; 2346 2347 pwm2 { 2348 pwm2_pin: pwm2-pin { 2349 rockchip,pins = 2350 <1 19 RK_FUNC_1 &pcfg_pull_none>; 2351 }; 2352 }; 2353 2354 pwm3a { 2355 pwm3a_pin: pwm3a-pin { 2356 rockchip,pins = 2357 <0 6 RK_FUNC_1 &pcfg_pull_none>; 2358 }; 2359 }; 2360 2361 pwm3b { 2362 pwm3b_pin: pwm3b-pin { 2363 rockchip,pins = 2364 <1 14 RK_FUNC_1 &pcfg_pull_none>; 2365 }; 2366 }; 2367 2368 hdmi { 2369 hdmi_i2c_xfer: hdmi-i2c-xfer { 2370 rockchip,pins = 2371 <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>, 2372 <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; 2373 }; 2374 2375 hdmi_cec: hdmi-cec { 2376 rockchip,pins = 2377 <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>; 2378 }; 2379 }; 2380 2381 pcie { 2382 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2383 rockchip,pins = 2384 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2385 }; 2386 2387 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2388 rockchip,pins = 2389 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2390 }; 2391 }; 2392 2393 }; 2394}; 2395