1/* 2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include <dt-bindings/clock/rk3399-cru.h> 44#include <dt-bindings/gpio/gpio.h> 45#include <dt-bindings/interrupt-controller/arm-gic.h> 46#include <dt-bindings/interrupt-controller/irq.h> 47#include <dt-bindings/pinctrl/rockchip.h> 48#include <dt-bindings/power/rk3399-power.h> 49#include <dt-bindings/thermal/thermal.h> 50 51/ { 52 compatible = "rockchip,rk3399"; 53 54 interrupt-parent = <&gic>; 55 #address-cells = <2>; 56 #size-cells = <2>; 57 58 aliases { 59 ethernet0 = &gmac; 60 i2c0 = &i2c0; 61 i2c1 = &i2c1; 62 i2c2 = &i2c2; 63 i2c3 = &i2c3; 64 i2c4 = &i2c4; 65 i2c5 = &i2c5; 66 i2c6 = &i2c6; 67 i2c7 = &i2c7; 68 i2c8 = &i2c8; 69 serial0 = &uart0; 70 serial1 = &uart1; 71 serial2 = &uart2; 72 serial3 = &uart3; 73 serial4 = &uart4; 74 }; 75 76 cpus { 77 #address-cells = <2>; 78 #size-cells = <0>; 79 80 cpu-map { 81 cluster0 { 82 core0 { 83 cpu = <&cpu_l0>; 84 }; 85 core1 { 86 cpu = <&cpu_l1>; 87 }; 88 core2 { 89 cpu = <&cpu_l2>; 90 }; 91 core3 { 92 cpu = <&cpu_l3>; 93 }; 94 }; 95 96 cluster1 { 97 core0 { 98 cpu = <&cpu_b0>; 99 }; 100 core1 { 101 cpu = <&cpu_b1>; 102 }; 103 }; 104 }; 105 106 cpu_l0: cpu@0 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a53", "arm,armv8"; 109 reg = <0x0 0x0>; 110 enable-method = "psci"; 111 #cooling-cells = <2>; /* min followed by max */ 112 clocks = <&cru ARMCLKL>; 113 dynamic-power-coefficient = <100>; 114 }; 115 116 cpu_l1: cpu@1 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a53", "arm,armv8"; 119 reg = <0x0 0x1>; 120 enable-method = "psci"; 121 clocks = <&cru ARMCLKL>; 122 dynamic-power-coefficient = <100>; 123 }; 124 125 cpu_l2: cpu@2 { 126 device_type = "cpu"; 127 compatible = "arm,cortex-a53", "arm,armv8"; 128 reg = <0x0 0x2>; 129 enable-method = "psci"; 130 clocks = <&cru ARMCLKL>; 131 dynamic-power-coefficient = <100>; 132 }; 133 134 cpu_l3: cpu@3 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a53", "arm,armv8"; 137 reg = <0x0 0x3>; 138 enable-method = "psci"; 139 clocks = <&cru ARMCLKL>; 140 dynamic-power-coefficient = <100>; 141 }; 142 143 cpu_b0: cpu@100 { 144 device_type = "cpu"; 145 compatible = "arm,cortex-a72", "arm,armv8"; 146 reg = <0x0 0x100>; 147 enable-method = "psci"; 148 #cooling-cells = <2>; /* min followed by max */ 149 clocks = <&cru ARMCLKB>; 150 dynamic-power-coefficient = <436>; 151 }; 152 153 cpu_b1: cpu@101 { 154 device_type = "cpu"; 155 compatible = "arm,cortex-a72", "arm,armv8"; 156 reg = <0x0 0x101>; 157 enable-method = "psci"; 158 clocks = <&cru ARMCLKB>; 159 dynamic-power-coefficient = <436>; 160 }; 161 }; 162 163 display-subsystem { 164 compatible = "rockchip,display-subsystem"; 165 ports = <&vopl_out>, <&vopb_out>; 166 }; 167 168 pmu_a53 { 169 compatible = "arm,cortex-a53-pmu"; 170 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 171 }; 172 173 pmu_a72 { 174 compatible = "arm,cortex-a72-pmu"; 175 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 176 }; 177 178 psci { 179 compatible = "arm,psci-1.0"; 180 method = "smc"; 181 }; 182 183 timer { 184 compatible = "arm,armv8-timer"; 185 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 186 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 187 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 188 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 189 arm,no-tick-in-suspend; 190 }; 191 192 xin24m: xin24m { 193 compatible = "fixed-clock"; 194 clock-frequency = <24000000>; 195 clock-output-names = "xin24m"; 196 #clock-cells = <0>; 197 }; 198 199 amba { 200 compatible = "simple-bus"; 201 #address-cells = <2>; 202 #size-cells = <2>; 203 ranges; 204 205 dmac_bus: dma-controller@ff6d0000 { 206 compatible = "arm,pl330", "arm,primecell"; 207 reg = <0x0 0xff6d0000 0x0 0x4000>; 208 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 209 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 210 #dma-cells = <1>; 211 clocks = <&cru ACLK_DMAC0_PERILP>; 212 clock-names = "apb_pclk"; 213 }; 214 215 dmac_peri: dma-controller@ff6e0000 { 216 compatible = "arm,pl330", "arm,primecell"; 217 reg = <0x0 0xff6e0000 0x0 0x4000>; 218 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 219 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 220 #dma-cells = <1>; 221 clocks = <&cru ACLK_DMAC1_PERILP>; 222 clock-names = "apb_pclk"; 223 }; 224 }; 225 226 pcie0: pcie@f8000000 { 227 compatible = "rockchip,rk3399-pcie"; 228 reg = <0x0 0xf8000000 0x0 0x2000000>, 229 <0x0 0xfd000000 0x0 0x1000000>; 230 reg-names = "axi-base", "apb-base"; 231 #address-cells = <3>; 232 #size-cells = <2>; 233 #interrupt-cells = <1>; 234 aspm-no-l0s; 235 bus-range = <0x0 0x1f>; 236 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 237 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 238 clock-names = "aclk", "aclk-perf", 239 "hclk", "pm"; 240 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 241 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 242 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 243 interrupt-names = "sys", "legacy", "client"; 244 interrupt-map-mask = <0 0 0 7>; 245 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 246 <0 0 0 2 &pcie0_intc 1>, 247 <0 0 0 3 &pcie0_intc 2>, 248 <0 0 0 4 &pcie0_intc 3>; 249 linux,pci-domain = <0>; 250 max-link-speed = <1>; 251 msi-map = <0x0 &its 0x0 0x1000>; 252 phys = <&pcie_phy 0>, <&pcie_phy 1>, 253 <&pcie_phy 2>, <&pcie_phy 3>; 254 phy-names = "pcie-phy-0", "pcie-phy-1", 255 "pcie-phy-2", "pcie-phy-3"; 256 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000 257 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; 258 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 259 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 260 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 261 <&cru SRST_A_PCIE>; 262 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 263 "pm", "pclk", "aclk"; 264 status = "disabled"; 265 266 pcie0_intc: interrupt-controller { 267 interrupt-controller; 268 #address-cells = <0>; 269 #interrupt-cells = <1>; 270 }; 271 }; 272 273 gmac: ethernet@fe300000 { 274 compatible = "rockchip,rk3399-gmac"; 275 reg = <0x0 0xfe300000 0x0 0x10000>; 276 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 277 interrupt-names = "macirq"; 278 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 279 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 280 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 281 <&cru PCLK_GMAC>; 282 clock-names = "stmmaceth", "mac_clk_rx", 283 "mac_clk_tx", "clk_mac_ref", 284 "clk_mac_refout", "aclk_mac", 285 "pclk_mac"; 286 power-domains = <&power RK3399_PD_GMAC>; 287 resets = <&cru SRST_A_GMAC>; 288 reset-names = "stmmaceth"; 289 rockchip,grf = <&grf>; 290 status = "disabled"; 291 }; 292 293 sdio0: dwmmc@fe310000 { 294 compatible = "rockchip,rk3399-dw-mshc", 295 "rockchip,rk3288-dw-mshc"; 296 reg = <0x0 0xfe310000 0x0 0x4000>; 297 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 298 max-frequency = <150000000>; 299 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 300 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 301 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 302 fifo-depth = <0x100>; 303 power-domains = <&power RK3399_PD_SDIOAUDIO>; 304 resets = <&cru SRST_SDIO0>; 305 reset-names = "reset"; 306 status = "disabled"; 307 }; 308 309 sdmmc: dwmmc@fe320000 { 310 compatible = "rockchip,rk3399-dw-mshc", 311 "rockchip,rk3288-dw-mshc"; 312 reg = <0x0 0xfe320000 0x0 0x4000>; 313 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 314 max-frequency = <150000000>; 315 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 316 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 317 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 318 fifo-depth = <0x100>; 319 power-domains = <&power RK3399_PD_SD>; 320 resets = <&cru SRST_SDMMC>; 321 reset-names = "reset"; 322 status = "disabled"; 323 }; 324 325 sdhci: sdhci@fe330000 { 326 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 327 reg = <0x0 0xfe330000 0x0 0x10000>; 328 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 329 arasan,soc-ctl-syscon = <&grf>; 330 assigned-clocks = <&cru SCLK_EMMC>; 331 assigned-clock-rates = <200000000>; 332 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 333 clock-names = "clk_xin", "clk_ahb"; 334 clock-output-names = "emmc_cardclock"; 335 #clock-cells = <0>; 336 phys = <&emmc_phy>; 337 phy-names = "phy_arasan"; 338 power-domains = <&power RK3399_PD_EMMC>; 339 status = "disabled"; 340 }; 341 342 usb_host0_ehci: usb@fe380000 { 343 compatible = "generic-ehci"; 344 reg = <0x0 0xfe380000 0x0 0x20000>; 345 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 346 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 347 <&u2phy0>; 348 clock-names = "usbhost", "arbiter", 349 "utmi"; 350 phys = <&u2phy0_host>; 351 phy-names = "usb"; 352 status = "disabled"; 353 }; 354 355 usb_host0_ohci: usb@fe3a0000 { 356 compatible = "generic-ohci"; 357 reg = <0x0 0xfe3a0000 0x0 0x20000>; 358 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 359 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 360 <&u2phy0>; 361 clock-names = "usbhost", "arbiter", 362 "utmi"; 363 phys = <&u2phy0_host>; 364 phy-names = "usb"; 365 status = "disabled"; 366 }; 367 368 usb_host1_ehci: usb@fe3c0000 { 369 compatible = "generic-ehci"; 370 reg = <0x0 0xfe3c0000 0x0 0x20000>; 371 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 372 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 373 <&u2phy1>; 374 clock-names = "usbhost", "arbiter", 375 "utmi"; 376 phys = <&u2phy1_host>; 377 phy-names = "usb"; 378 status = "disabled"; 379 }; 380 381 usb_host1_ohci: usb@fe3e0000 { 382 compatible = "generic-ohci"; 383 reg = <0x0 0xfe3e0000 0x0 0x20000>; 384 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 385 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 386 <&u2phy1>; 387 clock-names = "usbhost", "arbiter", 388 "utmi"; 389 phys = <&u2phy1_host>; 390 phy-names = "usb"; 391 status = "disabled"; 392 }; 393 394 usbdrd3_0: usb@fe800000 { 395 compatible = "rockchip,rk3399-dwc3"; 396 #address-cells = <2>; 397 #size-cells = <2>; 398 ranges; 399 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 400 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 401 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 402 clock-names = "ref_clk", "suspend_clk", 403 "bus_clk", "aclk_usb3_rksoc_axi_perf", 404 "aclk_usb3", "grf_clk"; 405 resets = <&cru SRST_A_USB3_OTG0>; 406 reset-names = "usb3-otg"; 407 status = "disabled"; 408 409 usbdrd_dwc3_0: dwc3 { 410 compatible = "snps,dwc3"; 411 reg = <0x0 0xfe800000 0x0 0x100000>; 412 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 413 dr_mode = "otg"; 414 phys = <&u2phy0_otg>, <&tcphy0_usb3>; 415 phy-names = "usb2-phy", "usb3-phy"; 416 phy_type = "utmi_wide"; 417 snps,dis_enblslpm_quirk; 418 snps,dis-u2-freeclk-exists-quirk; 419 snps,dis_u2_susphy_quirk; 420 snps,dis-del-phy-power-chg-quirk; 421 snps,dis-tx-ipgap-linecheck-quirk; 422 power-domains = <&power RK3399_PD_USB3>; 423 status = "disabled"; 424 }; 425 }; 426 427 usbdrd3_1: usb@fe900000 { 428 compatible = "rockchip,rk3399-dwc3"; 429 #address-cells = <2>; 430 #size-cells = <2>; 431 ranges; 432 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, 433 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 434 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 435 clock-names = "ref_clk", "suspend_clk", 436 "bus_clk", "aclk_usb3_rksoc_axi_perf", 437 "aclk_usb3", "grf_clk"; 438 resets = <&cru SRST_A_USB3_OTG1>; 439 reset-names = "usb3-otg"; 440 status = "disabled"; 441 442 usbdrd_dwc3_1: dwc3 { 443 compatible = "snps,dwc3"; 444 reg = <0x0 0xfe900000 0x0 0x100000>; 445 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 446 dr_mode = "otg"; 447 phys = <&u2phy1_otg>, <&tcphy1_usb3>; 448 phy-names = "usb2-phy", "usb3-phy"; 449 phy_type = "utmi_wide"; 450 snps,dis_enblslpm_quirk; 451 snps,dis-u2-freeclk-exists-quirk; 452 snps,dis_u2_susphy_quirk; 453 snps,dis-del-phy-power-chg-quirk; 454 snps,dis-tx-ipgap-linecheck-quirk; 455 power-domains = <&power RK3399_PD_USB3>; 456 status = "disabled"; 457 }; 458 }; 459 460 gic: interrupt-controller@fee00000 { 461 compatible = "arm,gic-v3"; 462 #interrupt-cells = <4>; 463 #address-cells = <2>; 464 #size-cells = <2>; 465 ranges; 466 interrupt-controller; 467 468 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 469 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 470 <0x0 0xfff00000 0 0x10000>, /* GICC */ 471 <0x0 0xfff10000 0 0x10000>, /* GICH */ 472 <0x0 0xfff20000 0 0x10000>; /* GICV */ 473 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 474 its: interrupt-controller@fee20000 { 475 compatible = "arm,gic-v3-its"; 476 msi-controller; 477 reg = <0x0 0xfee20000 0x0 0x20000>; 478 }; 479 480 ppi-partitions { 481 ppi_cluster0: interrupt-partition-0 { 482 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 483 }; 484 485 ppi_cluster1: interrupt-partition-1 { 486 affinity = <&cpu_b0 &cpu_b1>; 487 }; 488 }; 489 }; 490 491 saradc: saradc@ff100000 { 492 compatible = "rockchip,rk3399-saradc"; 493 reg = <0x0 0xff100000 0x0 0x100>; 494 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 495 #io-channel-cells = <1>; 496 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 497 clock-names = "saradc", "apb_pclk"; 498 resets = <&cru SRST_P_SARADC>; 499 reset-names = "saradc-apb"; 500 status = "disabled"; 501 }; 502 503 i2c1: i2c@ff110000 { 504 compatible = "rockchip,rk3399-i2c"; 505 reg = <0x0 0xff110000 0x0 0x1000>; 506 assigned-clocks = <&cru SCLK_I2C1>; 507 assigned-clock-rates = <200000000>; 508 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 509 clock-names = "i2c", "pclk"; 510 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 511 pinctrl-names = "default"; 512 pinctrl-0 = <&i2c1_xfer>; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 status = "disabled"; 516 }; 517 518 i2c2: i2c@ff120000 { 519 compatible = "rockchip,rk3399-i2c"; 520 reg = <0x0 0xff120000 0x0 0x1000>; 521 assigned-clocks = <&cru SCLK_I2C2>; 522 assigned-clock-rates = <200000000>; 523 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 524 clock-names = "i2c", "pclk"; 525 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 526 pinctrl-names = "default"; 527 pinctrl-0 = <&i2c2_xfer>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 status = "disabled"; 531 }; 532 533 i2c3: i2c@ff130000 { 534 compatible = "rockchip,rk3399-i2c"; 535 reg = <0x0 0xff130000 0x0 0x1000>; 536 assigned-clocks = <&cru SCLK_I2C3>; 537 assigned-clock-rates = <200000000>; 538 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 539 clock-names = "i2c", "pclk"; 540 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 541 pinctrl-names = "default"; 542 pinctrl-0 = <&i2c3_xfer>; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 status = "disabled"; 546 }; 547 548 i2c5: i2c@ff140000 { 549 compatible = "rockchip,rk3399-i2c"; 550 reg = <0x0 0xff140000 0x0 0x1000>; 551 assigned-clocks = <&cru SCLK_I2C5>; 552 assigned-clock-rates = <200000000>; 553 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 554 clock-names = "i2c", "pclk"; 555 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 556 pinctrl-names = "default"; 557 pinctrl-0 = <&i2c5_xfer>; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 status = "disabled"; 561 }; 562 563 i2c6: i2c@ff150000 { 564 compatible = "rockchip,rk3399-i2c"; 565 reg = <0x0 0xff150000 0x0 0x1000>; 566 assigned-clocks = <&cru SCLK_I2C6>; 567 assigned-clock-rates = <200000000>; 568 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 569 clock-names = "i2c", "pclk"; 570 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 571 pinctrl-names = "default"; 572 pinctrl-0 = <&i2c6_xfer>; 573 #address-cells = <1>; 574 #size-cells = <0>; 575 status = "disabled"; 576 }; 577 578 i2c7: i2c@ff160000 { 579 compatible = "rockchip,rk3399-i2c"; 580 reg = <0x0 0xff160000 0x0 0x1000>; 581 assigned-clocks = <&cru SCLK_I2C7>; 582 assigned-clock-rates = <200000000>; 583 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 584 clock-names = "i2c", "pclk"; 585 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 586 pinctrl-names = "default"; 587 pinctrl-0 = <&i2c7_xfer>; 588 #address-cells = <1>; 589 #size-cells = <0>; 590 status = "disabled"; 591 }; 592 593 uart0: serial@ff180000 { 594 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 595 reg = <0x0 0xff180000 0x0 0x100>; 596 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 597 clock-names = "baudclk", "apb_pclk"; 598 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 599 reg-shift = <2>; 600 reg-io-width = <4>; 601 pinctrl-names = "default"; 602 pinctrl-0 = <&uart0_xfer>; 603 status = "disabled"; 604 }; 605 606 uart1: serial@ff190000 { 607 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 608 reg = <0x0 0xff190000 0x0 0x100>; 609 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 610 clock-names = "baudclk", "apb_pclk"; 611 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 612 reg-shift = <2>; 613 reg-io-width = <4>; 614 pinctrl-names = "default"; 615 pinctrl-0 = <&uart1_xfer>; 616 status = "disabled"; 617 }; 618 619 uart2: serial@ff1a0000 { 620 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 621 reg = <0x0 0xff1a0000 0x0 0x100>; 622 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 623 clock-names = "baudclk", "apb_pclk"; 624 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 625 reg-shift = <2>; 626 reg-io-width = <4>; 627 pinctrl-names = "default"; 628 pinctrl-0 = <&uart2c_xfer>; 629 status = "disabled"; 630 }; 631 632 uart3: serial@ff1b0000 { 633 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 634 reg = <0x0 0xff1b0000 0x0 0x100>; 635 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 636 clock-names = "baudclk", "apb_pclk"; 637 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 638 reg-shift = <2>; 639 reg-io-width = <4>; 640 pinctrl-names = "default"; 641 pinctrl-0 = <&uart3_xfer>; 642 status = "disabled"; 643 }; 644 645 spi0: spi@ff1c0000 { 646 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 647 reg = <0x0 0xff1c0000 0x0 0x1000>; 648 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 649 clock-names = "spiclk", "apb_pclk"; 650 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 651 pinctrl-names = "default"; 652 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 653 #address-cells = <1>; 654 #size-cells = <0>; 655 status = "disabled"; 656 }; 657 658 spi1: spi@ff1d0000 { 659 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 660 reg = <0x0 0xff1d0000 0x0 0x1000>; 661 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 662 clock-names = "spiclk", "apb_pclk"; 663 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 664 pinctrl-names = "default"; 665 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 666 #address-cells = <1>; 667 #size-cells = <0>; 668 status = "disabled"; 669 }; 670 671 spi2: spi@ff1e0000 { 672 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 673 reg = <0x0 0xff1e0000 0x0 0x1000>; 674 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 675 clock-names = "spiclk", "apb_pclk"; 676 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 677 pinctrl-names = "default"; 678 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 679 #address-cells = <1>; 680 #size-cells = <0>; 681 status = "disabled"; 682 }; 683 684 spi4: spi@ff1f0000 { 685 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 686 reg = <0x0 0xff1f0000 0x0 0x1000>; 687 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 688 clock-names = "spiclk", "apb_pclk"; 689 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 690 pinctrl-names = "default"; 691 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 692 #address-cells = <1>; 693 #size-cells = <0>; 694 status = "disabled"; 695 }; 696 697 spi5: spi@ff200000 { 698 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 699 reg = <0x0 0xff200000 0x0 0x1000>; 700 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 701 clock-names = "spiclk", "apb_pclk"; 702 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 703 pinctrl-names = "default"; 704 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 705 power-domains = <&power RK3399_PD_SDIOAUDIO>; 706 #address-cells = <1>; 707 #size-cells = <0>; 708 status = "disabled"; 709 }; 710 711 thermal_zones: thermal-zones { 712 cpu_thermal: cpu { 713 polling-delay-passive = <100>; 714 polling-delay = <1000>; 715 716 thermal-sensors = <&tsadc 0>; 717 718 trips { 719 cpu_alert0: cpu_alert0 { 720 temperature = <70000>; 721 hysteresis = <2000>; 722 type = "passive"; 723 }; 724 cpu_alert1: cpu_alert1 { 725 temperature = <75000>; 726 hysteresis = <2000>; 727 type = "passive"; 728 }; 729 cpu_crit: cpu_crit { 730 temperature = <95000>; 731 hysteresis = <2000>; 732 type = "critical"; 733 }; 734 }; 735 736 cooling-maps { 737 map0 { 738 trip = <&cpu_alert0>; 739 cooling-device = 740 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 741 }; 742 map1 { 743 trip = <&cpu_alert1>; 744 cooling-device = 745 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 746 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 747 }; 748 }; 749 }; 750 751 gpu_thermal: gpu { 752 polling-delay-passive = <100>; 753 polling-delay = <1000>; 754 755 thermal-sensors = <&tsadc 1>; 756 757 trips { 758 gpu_alert0: gpu_alert0 { 759 temperature = <75000>; 760 hysteresis = <2000>; 761 type = "passive"; 762 }; 763 gpu_crit: gpu_crit { 764 temperature = <95000>; 765 hysteresis = <2000>; 766 type = "critical"; 767 }; 768 }; 769 770 cooling-maps { 771 map0 { 772 trip = <&gpu_alert0>; 773 cooling-device = 774 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 775 }; 776 }; 777 }; 778 }; 779 780 tsadc: tsadc@ff260000 { 781 compatible = "rockchip,rk3399-tsadc"; 782 reg = <0x0 0xff260000 0x0 0x100>; 783 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 784 assigned-clocks = <&cru SCLK_TSADC>; 785 assigned-clock-rates = <750000>; 786 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 787 clock-names = "tsadc", "apb_pclk"; 788 resets = <&cru SRST_TSADC>; 789 reset-names = "tsadc-apb"; 790 rockchip,grf = <&grf>; 791 rockchip,hw-tshut-temp = <95000>; 792 pinctrl-names = "init", "default", "sleep"; 793 pinctrl-0 = <&otp_gpio>; 794 pinctrl-1 = <&otp_out>; 795 pinctrl-2 = <&otp_gpio>; 796 #thermal-sensor-cells = <1>; 797 status = "disabled"; 798 }; 799 800 qos_emmc: qos@ffa58000 { 801 compatible = "syscon"; 802 reg = <0x0 0xffa58000 0x0 0x20>; 803 }; 804 805 qos_gmac: qos@ffa5c000 { 806 compatible = "syscon"; 807 reg = <0x0 0xffa5c000 0x0 0x20>; 808 }; 809 810 qos_pcie: qos@ffa60080 { 811 compatible = "syscon"; 812 reg = <0x0 0xffa60080 0x0 0x20>; 813 }; 814 815 qos_usb_host0: qos@ffa60100 { 816 compatible = "syscon"; 817 reg = <0x0 0xffa60100 0x0 0x20>; 818 }; 819 820 qos_usb_host1: qos@ffa60180 { 821 compatible = "syscon"; 822 reg = <0x0 0xffa60180 0x0 0x20>; 823 }; 824 825 qos_usb_otg0: qos@ffa70000 { 826 compatible = "syscon"; 827 reg = <0x0 0xffa70000 0x0 0x20>; 828 }; 829 830 qos_usb_otg1: qos@ffa70080 { 831 compatible = "syscon"; 832 reg = <0x0 0xffa70080 0x0 0x20>; 833 }; 834 835 qos_sd: qos@ffa74000 { 836 compatible = "syscon"; 837 reg = <0x0 0xffa74000 0x0 0x20>; 838 }; 839 840 qos_sdioaudio: qos@ffa76000 { 841 compatible = "syscon"; 842 reg = <0x0 0xffa76000 0x0 0x20>; 843 }; 844 845 qos_hdcp: qos@ffa90000 { 846 compatible = "syscon"; 847 reg = <0x0 0xffa90000 0x0 0x20>; 848 }; 849 850 qos_iep: qos@ffa98000 { 851 compatible = "syscon"; 852 reg = <0x0 0xffa98000 0x0 0x20>; 853 }; 854 855 qos_isp0_m0: qos@ffaa0000 { 856 compatible = "syscon"; 857 reg = <0x0 0xffaa0000 0x0 0x20>; 858 }; 859 860 qos_isp0_m1: qos@ffaa0080 { 861 compatible = "syscon"; 862 reg = <0x0 0xffaa0080 0x0 0x20>; 863 }; 864 865 qos_isp1_m0: qos@ffaa8000 { 866 compatible = "syscon"; 867 reg = <0x0 0xffaa8000 0x0 0x20>; 868 }; 869 870 qos_isp1_m1: qos@ffaa8080 { 871 compatible = "syscon"; 872 reg = <0x0 0xffaa8080 0x0 0x20>; 873 }; 874 875 qos_rga_r: qos@ffab0000 { 876 compatible = "syscon"; 877 reg = <0x0 0xffab0000 0x0 0x20>; 878 }; 879 880 qos_rga_w: qos@ffab0080 { 881 compatible = "syscon"; 882 reg = <0x0 0xffab0080 0x0 0x20>; 883 }; 884 885 qos_video_m0: qos@ffab8000 { 886 compatible = "syscon"; 887 reg = <0x0 0xffab8000 0x0 0x20>; 888 }; 889 890 qos_video_m1_r: qos@ffac0000 { 891 compatible = "syscon"; 892 reg = <0x0 0xffac0000 0x0 0x20>; 893 }; 894 895 qos_video_m1_w: qos@ffac0080 { 896 compatible = "syscon"; 897 reg = <0x0 0xffac0080 0x0 0x20>; 898 }; 899 900 qos_vop_big_r: qos@ffac8000 { 901 compatible = "syscon"; 902 reg = <0x0 0xffac8000 0x0 0x20>; 903 }; 904 905 qos_vop_big_w: qos@ffac8080 { 906 compatible = "syscon"; 907 reg = <0x0 0xffac8080 0x0 0x20>; 908 }; 909 910 qos_vop_little: qos@ffad0000 { 911 compatible = "syscon"; 912 reg = <0x0 0xffad0000 0x0 0x20>; 913 }; 914 915 qos_perihp: qos@ffad8080 { 916 compatible = "syscon"; 917 reg = <0x0 0xffad8080 0x0 0x20>; 918 }; 919 920 qos_gpu: qos@ffae0000 { 921 compatible = "syscon"; 922 reg = <0x0 0xffae0000 0x0 0x20>; 923 }; 924 925 pmu: power-management@ff310000 { 926 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 927 reg = <0x0 0xff310000 0x0 0x1000>; 928 929 /* 930 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 931 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 932 * Some of the power domains are grouped together for every 933 * voltage domain. 934 * The detail contents as below. 935 */ 936 power: power-controller { 937 compatible = "rockchip,rk3399-power-controller"; 938 #power-domain-cells = <1>; 939 #address-cells = <1>; 940 #size-cells = <0>; 941 942 /* These power domains are grouped by VD_CENTER */ 943 pd_iep@RK3399_PD_IEP { 944 reg = <RK3399_PD_IEP>; 945 clocks = <&cru ACLK_IEP>, 946 <&cru HCLK_IEP>; 947 pm_qos = <&qos_iep>; 948 }; 949 pd_rga@RK3399_PD_RGA { 950 reg = <RK3399_PD_RGA>; 951 clocks = <&cru ACLK_RGA>, 952 <&cru HCLK_RGA>; 953 pm_qos = <&qos_rga_r>, 954 <&qos_rga_w>; 955 }; 956 pd_vcodec@RK3399_PD_VCODEC { 957 reg = <RK3399_PD_VCODEC>; 958 clocks = <&cru ACLK_VCODEC>, 959 <&cru HCLK_VCODEC>; 960 pm_qos = <&qos_video_m0>; 961 }; 962 pd_vdu@RK3399_PD_VDU { 963 reg = <RK3399_PD_VDU>; 964 clocks = <&cru ACLK_VDU>, 965 <&cru HCLK_VDU>; 966 pm_qos = <&qos_video_m1_r>, 967 <&qos_video_m1_w>; 968 }; 969 970 /* These power domains are grouped by VD_GPU */ 971 pd_gpu@RK3399_PD_GPU { 972 reg = <RK3399_PD_GPU>; 973 clocks = <&cru ACLK_GPU>; 974 pm_qos = <&qos_gpu>; 975 }; 976 977 /* These power domains are grouped by VD_LOGIC */ 978 pd_edp@RK3399_PD_EDP { 979 reg = <RK3399_PD_EDP>; 980 clocks = <&cru PCLK_EDP_CTRL>; 981 }; 982 pd_emmc@RK3399_PD_EMMC { 983 reg = <RK3399_PD_EMMC>; 984 clocks = <&cru ACLK_EMMC>; 985 pm_qos = <&qos_emmc>; 986 }; 987 pd_gmac@RK3399_PD_GMAC { 988 reg = <RK3399_PD_GMAC>; 989 clocks = <&cru ACLK_GMAC>, 990 <&cru PCLK_GMAC>; 991 pm_qos = <&qos_gmac>; 992 }; 993 pd_sd@RK3399_PD_SD { 994 reg = <RK3399_PD_SD>; 995 clocks = <&cru HCLK_SDMMC>, 996 <&cru SCLK_SDMMC>; 997 pm_qos = <&qos_sd>; 998 }; 999 pd_sdioaudio@RK3399_PD_SDIOAUDIO { 1000 reg = <RK3399_PD_SDIOAUDIO>; 1001 clocks = <&cru HCLK_SDIO>; 1002 pm_qos = <&qos_sdioaudio>; 1003 }; 1004 pd_usb3@RK3399_PD_USB3 { 1005 reg = <RK3399_PD_USB3>; 1006 clocks = <&cru ACLK_USB3>; 1007 pm_qos = <&qos_usb_otg0>, 1008 <&qos_usb_otg1>; 1009 }; 1010 pd_vio@RK3399_PD_VIO { 1011 reg = <RK3399_PD_VIO>; 1012 #address-cells = <1>; 1013 #size-cells = <0>; 1014 1015 pd_hdcp@RK3399_PD_HDCP { 1016 reg = <RK3399_PD_HDCP>; 1017 clocks = <&cru ACLK_HDCP>, 1018 <&cru HCLK_HDCP>, 1019 <&cru PCLK_HDCP>; 1020 pm_qos = <&qos_hdcp>; 1021 }; 1022 pd_isp0@RK3399_PD_ISP0 { 1023 reg = <RK3399_PD_ISP0>; 1024 clocks = <&cru ACLK_ISP0>, 1025 <&cru HCLK_ISP0>; 1026 pm_qos = <&qos_isp0_m0>, 1027 <&qos_isp0_m1>; 1028 }; 1029 pd_isp1@RK3399_PD_ISP1 { 1030 reg = <RK3399_PD_ISP1>; 1031 clocks = <&cru ACLK_ISP1>, 1032 <&cru HCLK_ISP1>; 1033 pm_qos = <&qos_isp1_m0>, 1034 <&qos_isp1_m1>; 1035 }; 1036 pd_tcpc0@RK3399_PD_TCPC0 { 1037 reg = <RK3399_PD_TCPD0>; 1038 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1039 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1040 }; 1041 pd_tcpc1@RK3399_PD_TCPC1 { 1042 reg = <RK3399_PD_TCPD1>; 1043 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1044 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1045 }; 1046 pd_vo@RK3399_PD_VO { 1047 reg = <RK3399_PD_VO>; 1048 #address-cells = <1>; 1049 #size-cells = <0>; 1050 1051 pd_vopb@RK3399_PD_VOPB { 1052 reg = <RK3399_PD_VOPB>; 1053 clocks = <&cru ACLK_VOP0>, 1054 <&cru HCLK_VOP0>; 1055 pm_qos = <&qos_vop_big_r>, 1056 <&qos_vop_big_w>; 1057 }; 1058 pd_vopl@RK3399_PD_VOPL { 1059 reg = <RK3399_PD_VOPL>; 1060 clocks = <&cru ACLK_VOP1>, 1061 <&cru HCLK_VOP1>; 1062 pm_qos = <&qos_vop_little>; 1063 }; 1064 }; 1065 }; 1066 }; 1067 }; 1068 1069 pmugrf: syscon@ff320000 { 1070 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1071 reg = <0x0 0xff320000 0x0 0x1000>; 1072 #address-cells = <1>; 1073 #size-cells = <1>; 1074 1075 pmu_io_domains: io-domains { 1076 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1077 status = "disabled"; 1078 }; 1079 }; 1080 1081 spi3: spi@ff350000 { 1082 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1083 reg = <0x0 0xff350000 0x0 0x1000>; 1084 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1085 clock-names = "spiclk", "apb_pclk"; 1086 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1087 pinctrl-names = "default"; 1088 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1089 #address-cells = <1>; 1090 #size-cells = <0>; 1091 status = "disabled"; 1092 }; 1093 1094 uart4: serial@ff370000 { 1095 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1096 reg = <0x0 0xff370000 0x0 0x100>; 1097 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1098 clock-names = "baudclk", "apb_pclk"; 1099 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1100 reg-shift = <2>; 1101 reg-io-width = <4>; 1102 pinctrl-names = "default"; 1103 pinctrl-0 = <&uart4_xfer>; 1104 status = "disabled"; 1105 }; 1106 1107 i2c0: i2c@ff3c0000 { 1108 compatible = "rockchip,rk3399-i2c"; 1109 reg = <0x0 0xff3c0000 0x0 0x1000>; 1110 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1111 assigned-clock-rates = <200000000>; 1112 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1113 clock-names = "i2c", "pclk"; 1114 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1115 pinctrl-names = "default"; 1116 pinctrl-0 = <&i2c0_xfer>; 1117 #address-cells = <1>; 1118 #size-cells = <0>; 1119 status = "disabled"; 1120 }; 1121 1122 i2c4: i2c@ff3d0000 { 1123 compatible = "rockchip,rk3399-i2c"; 1124 reg = <0x0 0xff3d0000 0x0 0x1000>; 1125 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1126 assigned-clock-rates = <200000000>; 1127 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1128 clock-names = "i2c", "pclk"; 1129 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1130 pinctrl-names = "default"; 1131 pinctrl-0 = <&i2c4_xfer>; 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 status = "disabled"; 1135 }; 1136 1137 i2c8: i2c@ff3e0000 { 1138 compatible = "rockchip,rk3399-i2c"; 1139 reg = <0x0 0xff3e0000 0x0 0x1000>; 1140 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1141 assigned-clock-rates = <200000000>; 1142 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1143 clock-names = "i2c", "pclk"; 1144 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1145 pinctrl-names = "default"; 1146 pinctrl-0 = <&i2c8_xfer>; 1147 #address-cells = <1>; 1148 #size-cells = <0>; 1149 status = "disabled"; 1150 }; 1151 1152 pwm0: pwm@ff420000 { 1153 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1154 reg = <0x0 0xff420000 0x0 0x10>; 1155 #pwm-cells = <3>; 1156 pinctrl-names = "default"; 1157 pinctrl-0 = <&pwm0_pin>; 1158 clocks = <&pmucru PCLK_RKPWM_PMU>; 1159 clock-names = "pwm"; 1160 status = "disabled"; 1161 }; 1162 1163 pwm1: pwm@ff420010 { 1164 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1165 reg = <0x0 0xff420010 0x0 0x10>; 1166 #pwm-cells = <3>; 1167 pinctrl-names = "default"; 1168 pinctrl-0 = <&pwm1_pin>; 1169 clocks = <&pmucru PCLK_RKPWM_PMU>; 1170 clock-names = "pwm"; 1171 status = "disabled"; 1172 }; 1173 1174 pwm2: pwm@ff420020 { 1175 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1176 reg = <0x0 0xff420020 0x0 0x10>; 1177 #pwm-cells = <3>; 1178 pinctrl-names = "default"; 1179 pinctrl-0 = <&pwm2_pin>; 1180 clocks = <&pmucru PCLK_RKPWM_PMU>; 1181 clock-names = "pwm"; 1182 status = "disabled"; 1183 }; 1184 1185 pwm3: pwm@ff420030 { 1186 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1187 reg = <0x0 0xff420030 0x0 0x10>; 1188 #pwm-cells = <3>; 1189 pinctrl-names = "default"; 1190 pinctrl-0 = <&pwm3a_pin>; 1191 clocks = <&pmucru PCLK_RKPWM_PMU>; 1192 clock-names = "pwm"; 1193 status = "disabled"; 1194 }; 1195 1196 vpu_mmu: iommu@ff650800 { 1197 compatible = "rockchip,iommu"; 1198 reg = <0x0 0xff650800 0x0 0x40>; 1199 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 1200 interrupt-names = "vpu_mmu"; 1201 #iommu-cells = <0>; 1202 status = "disabled"; 1203 }; 1204 1205 vdec_mmu: iommu@ff660480 { 1206 compatible = "rockchip,iommu"; 1207 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; 1208 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1209 interrupt-names = "vdec_mmu"; 1210 #iommu-cells = <0>; 1211 status = "disabled"; 1212 }; 1213 1214 iep_mmu: iommu@ff670800 { 1215 compatible = "rockchip,iommu"; 1216 reg = <0x0 0xff670800 0x0 0x40>; 1217 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>; 1218 interrupt-names = "iep_mmu"; 1219 #iommu-cells = <0>; 1220 status = "disabled"; 1221 }; 1222 1223 rga: rga@ff680000 { 1224 compatible = "rockchip,rk3399-rga"; 1225 reg = <0x0 0xff680000 0x0 0x10000>; 1226 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>; 1227 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; 1228 clock-names = "aclk", "hclk", "sclk"; 1229 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 1230 reset-names = "core", "axi", "ahb"; 1231 power-domains = <&power RK3399_PD_RGA>; 1232 }; 1233 1234 efuse0: efuse@ff690000 { 1235 compatible = "rockchip,rk3399-efuse"; 1236 reg = <0x0 0xff690000 0x0 0x80>; 1237 #address-cells = <1>; 1238 #size-cells = <1>; 1239 clocks = <&cru PCLK_EFUSE1024NS>; 1240 clock-names = "pclk_efuse"; 1241 1242 /* Data cells */ 1243 cpu_id: cpu-id@7 { 1244 reg = <0x07 0x10>; 1245 }; 1246 cpub_leakage: cpu-leakage@17 { 1247 reg = <0x17 0x1>; 1248 }; 1249 gpu_leakage: gpu-leakage@18 { 1250 reg = <0x18 0x1>; 1251 }; 1252 center_leakage: center-leakage@19 { 1253 reg = <0x19 0x1>; 1254 }; 1255 cpul_leakage: cpu-leakage@1a { 1256 reg = <0x1a 0x1>; 1257 }; 1258 logic_leakage: logic-leakage@1b { 1259 reg = <0x1b 0x1>; 1260 }; 1261 wafer_info: wafer-info@1c { 1262 reg = <0x1c 0x1>; 1263 }; 1264 }; 1265 1266 pmucru: pmu-clock-controller@ff750000 { 1267 compatible = "rockchip,rk3399-pmucru"; 1268 reg = <0x0 0xff750000 0x0 0x1000>; 1269 rockchip,grf = <&pmugrf>; 1270 #clock-cells = <1>; 1271 #reset-cells = <1>; 1272 assigned-clocks = <&pmucru PLL_PPLL>; 1273 assigned-clock-rates = <676000000>; 1274 }; 1275 1276 cru: clock-controller@ff760000 { 1277 compatible = "rockchip,rk3399-cru"; 1278 reg = <0x0 0xff760000 0x0 0x1000>; 1279 rockchip,grf = <&grf>; 1280 #clock-cells = <1>; 1281 #reset-cells = <1>; 1282 assigned-clocks = 1283 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1284 <&cru PLL_NPLL>, 1285 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1286 <&cru PCLK_PERIHP>, 1287 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1288 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1289 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; 1290 assigned-clock-rates = 1291 <594000000>, <800000000>, 1292 <1000000000>, 1293 <150000000>, <75000000>, 1294 <37500000>, 1295 <100000000>, <100000000>, 1296 <50000000>, <600000000>, 1297 <100000000>, <50000000>; 1298 }; 1299 1300 grf: syscon@ff770000 { 1301 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1302 reg = <0x0 0xff770000 0x0 0x10000>; 1303 #address-cells = <1>; 1304 #size-cells = <1>; 1305 1306 io_domains: io-domains { 1307 compatible = "rockchip,rk3399-io-voltage-domain"; 1308 status = "disabled"; 1309 }; 1310 1311 u2phy0: usb2-phy@e450 { 1312 compatible = "rockchip,rk3399-usb2phy"; 1313 reg = <0xe450 0x10>; 1314 clocks = <&cru SCLK_USB2PHY0_REF>; 1315 clock-names = "phyclk"; 1316 #clock-cells = <0>; 1317 clock-output-names = "clk_usbphy0_480m"; 1318 status = "disabled"; 1319 1320 u2phy0_host: host-port { 1321 #phy-cells = <0>; 1322 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1323 interrupt-names = "linestate"; 1324 status = "disabled"; 1325 }; 1326 1327 u2phy0_otg: otg-port { 1328 #phy-cells = <0>; 1329 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1330 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1331 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1332 interrupt-names = "otg-bvalid", "otg-id", 1333 "linestate"; 1334 status = "disabled"; 1335 }; 1336 }; 1337 1338 u2phy1: usb2-phy@e460 { 1339 compatible = "rockchip,rk3399-usb2phy"; 1340 reg = <0xe460 0x10>; 1341 clocks = <&cru SCLK_USB2PHY1_REF>; 1342 clock-names = "phyclk"; 1343 #clock-cells = <0>; 1344 clock-output-names = "clk_usbphy1_480m"; 1345 status = "disabled"; 1346 1347 u2phy1_host: host-port { 1348 #phy-cells = <0>; 1349 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1350 interrupt-names = "linestate"; 1351 status = "disabled"; 1352 }; 1353 1354 u2phy1_otg: otg-port { 1355 #phy-cells = <0>; 1356 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1357 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1358 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1359 interrupt-names = "otg-bvalid", "otg-id", 1360 "linestate"; 1361 status = "disabled"; 1362 }; 1363 }; 1364 1365 emmc_phy: phy@f780 { 1366 compatible = "rockchip,rk3399-emmc-phy"; 1367 reg = <0xf780 0x24>; 1368 clocks = <&sdhci>; 1369 clock-names = "emmcclk"; 1370 #phy-cells = <0>; 1371 status = "disabled"; 1372 }; 1373 1374 pcie_phy: pcie-phy { 1375 compatible = "rockchip,rk3399-pcie-phy"; 1376 clocks = <&cru SCLK_PCIEPHY_REF>; 1377 clock-names = "refclk"; 1378 #phy-cells = <1>; 1379 resets = <&cru SRST_PCIEPHY>; 1380 reset-names = "phy"; 1381 status = "disabled"; 1382 }; 1383 }; 1384 1385 tcphy0: phy@ff7c0000 { 1386 compatible = "rockchip,rk3399-typec-phy"; 1387 reg = <0x0 0xff7c0000 0x0 0x40000>; 1388 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1389 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1390 clock-names = "tcpdcore", "tcpdphy-ref"; 1391 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1392 assigned-clock-rates = <50000000>; 1393 power-domains = <&power RK3399_PD_TCPD0>; 1394 resets = <&cru SRST_UPHY0>, 1395 <&cru SRST_UPHY0_PIPE_L00>, 1396 <&cru SRST_P_UPHY0_TCPHY>; 1397 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1398 rockchip,grf = <&grf>; 1399 rockchip,typec-conn-dir = <0xe580 0 16>; 1400 rockchip,usb3tousb2-en = <0xe580 3 19>; 1401 rockchip,external-psm = <0xe588 14 30>; 1402 rockchip,pipe-status = <0xe5c0 0 0>; 1403 status = "disabled"; 1404 1405 tcphy0_dp: dp-port { 1406 #phy-cells = <0>; 1407 }; 1408 1409 tcphy0_usb3: usb3-port { 1410 #phy-cells = <0>; 1411 }; 1412 }; 1413 1414 tcphy1: phy@ff800000 { 1415 compatible = "rockchip,rk3399-typec-phy"; 1416 reg = <0x0 0xff800000 0x0 0x40000>; 1417 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1418 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1419 clock-names = "tcpdcore", "tcpdphy-ref"; 1420 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1421 assigned-clock-rates = <50000000>; 1422 power-domains = <&power RK3399_PD_TCPD1>; 1423 resets = <&cru SRST_UPHY1>, 1424 <&cru SRST_UPHY1_PIPE_L00>, 1425 <&cru SRST_P_UPHY1_TCPHY>; 1426 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1427 rockchip,grf = <&grf>; 1428 rockchip,typec-conn-dir = <0xe58c 0 16>; 1429 rockchip,usb3tousb2-en = <0xe58c 3 19>; 1430 rockchip,external-psm = <0xe594 14 30>; 1431 rockchip,pipe-status = <0xe5c0 16 16>; 1432 status = "disabled"; 1433 1434 tcphy1_dp: dp-port { 1435 #phy-cells = <0>; 1436 }; 1437 1438 tcphy1_usb3: usb3-port { 1439 #phy-cells = <0>; 1440 }; 1441 }; 1442 1443 watchdog@ff848000 { 1444 compatible = "snps,dw-wdt"; 1445 reg = <0x0 0xff848000 0x0 0x100>; 1446 clocks = <&cru PCLK_WDT>; 1447 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1448 }; 1449 1450 rktimer: rktimer@ff850000 { 1451 compatible = "rockchip,rk3399-timer"; 1452 reg = <0x0 0xff850000 0x0 0x1000>; 1453 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1454 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1455 clock-names = "pclk", "timer"; 1456 }; 1457 1458 spdif: spdif@ff870000 { 1459 compatible = "rockchip,rk3399-spdif"; 1460 reg = <0x0 0xff870000 0x0 0x1000>; 1461 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1462 dmas = <&dmac_bus 7>; 1463 dma-names = "tx"; 1464 clock-names = "mclk", "hclk"; 1465 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1466 pinctrl-names = "default"; 1467 pinctrl-0 = <&spdif_bus>; 1468 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1469 status = "disabled"; 1470 }; 1471 1472 i2s0: i2s@ff880000 { 1473 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1474 reg = <0x0 0xff880000 0x0 0x1000>; 1475 rockchip,grf = <&grf>; 1476 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1477 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1478 dma-names = "tx", "rx"; 1479 clock-names = "i2s_clk", "i2s_hclk"; 1480 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1481 pinctrl-names = "default"; 1482 pinctrl-0 = <&i2s0_8ch_bus>; 1483 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1484 status = "disabled"; 1485 }; 1486 1487 i2s1: i2s@ff890000 { 1488 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1489 reg = <0x0 0xff890000 0x0 0x1000>; 1490 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1491 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1492 dma-names = "tx", "rx"; 1493 clock-names = "i2s_clk", "i2s_hclk"; 1494 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1495 pinctrl-names = "default"; 1496 pinctrl-0 = <&i2s1_2ch_bus>; 1497 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1498 status = "disabled"; 1499 }; 1500 1501 i2s2: i2s@ff8a0000 { 1502 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1503 reg = <0x0 0xff8a0000 0x0 0x1000>; 1504 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1505 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1506 dma-names = "tx", "rx"; 1507 clock-names = "i2s_clk", "i2s_hclk"; 1508 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1509 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1510 status = "disabled"; 1511 }; 1512 1513 vopl: vop@ff8f0000 { 1514 compatible = "rockchip,rk3399-vop-lit"; 1515 reg = <0x0 0xff8f0000 0x0 0x3efc>; 1516 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1517 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1518 assigned-clock-rates = <400000000>, <100000000>; 1519 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1520 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1521 iommus = <&vopl_mmu>; 1522 power-domains = <&power RK3399_PD_VOPL>; 1523 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1524 reset-names = "axi", "ahb", "dclk"; 1525 status = "disabled"; 1526 1527 vopl_out: port { 1528 #address-cells = <1>; 1529 #size-cells = <0>; 1530 1531 vopl_out_mipi: endpoint@0 { 1532 reg = <0>; 1533 remote-endpoint = <&mipi_in_vopl>; 1534 }; 1535 1536 vopl_out_edp: endpoint@1 { 1537 reg = <1>; 1538 remote-endpoint = <&edp_in_vopl>; 1539 }; 1540 1541 vopl_out_hdmi: endpoint@2 { 1542 reg = <2>; 1543 remote-endpoint = <&hdmi_in_vopl>; 1544 }; 1545 1546 vopl_out_mipi1: endpoint@3 { 1547 reg = <3>; 1548 remote-endpoint = <&mipi1_in_vopl>; 1549 }; 1550 }; 1551 }; 1552 1553 vopl_mmu: iommu@ff8f3f00 { 1554 compatible = "rockchip,iommu"; 1555 reg = <0x0 0xff8f3f00 0x0 0x100>; 1556 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1557 interrupt-names = "vopl_mmu"; 1558 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1559 clock-names = "aclk", "hclk"; 1560 power-domains = <&power RK3399_PD_VOPL>; 1561 #iommu-cells = <0>; 1562 status = "disabled"; 1563 }; 1564 1565 vopb: vop@ff900000 { 1566 compatible = "rockchip,rk3399-vop-big"; 1567 reg = <0x0 0xff900000 0x0 0x3efc>; 1568 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1569 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1570 assigned-clock-rates = <400000000>, <100000000>; 1571 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1572 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1573 iommus = <&vopb_mmu>; 1574 power-domains = <&power RK3399_PD_VOPB>; 1575 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1576 reset-names = "axi", "ahb", "dclk"; 1577 status = "disabled"; 1578 1579 vopb_out: port { 1580 #address-cells = <1>; 1581 #size-cells = <0>; 1582 1583 vopb_out_edp: endpoint@0 { 1584 reg = <0>; 1585 remote-endpoint = <&edp_in_vopb>; 1586 }; 1587 1588 vopb_out_mipi: endpoint@1 { 1589 reg = <1>; 1590 remote-endpoint = <&mipi_in_vopb>; 1591 }; 1592 1593 vopb_out_hdmi: endpoint@2 { 1594 reg = <2>; 1595 remote-endpoint = <&hdmi_in_vopb>; 1596 }; 1597 1598 vopb_out_mipi1: endpoint@3 { 1599 reg = <3>; 1600 remote-endpoint = <&mipi1_in_vopb>; 1601 }; 1602 }; 1603 }; 1604 1605 vopb_mmu: iommu@ff903f00 { 1606 compatible = "rockchip,iommu"; 1607 reg = <0x0 0xff903f00 0x0 0x100>; 1608 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1609 interrupt-names = "vopb_mmu"; 1610 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1611 clock-names = "aclk", "hclk"; 1612 power-domains = <&power RK3399_PD_VOPB>; 1613 #iommu-cells = <0>; 1614 status = "disabled"; 1615 }; 1616 1617 isp0_mmu: iommu@ff914000 { 1618 compatible = "rockchip,iommu"; 1619 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1620 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1621 interrupt-names = "isp0_mmu"; 1622 #iommu-cells = <0>; 1623 rockchip,disable-mmu-reset; 1624 status = "disabled"; 1625 }; 1626 1627 isp1_mmu: iommu@ff924000 { 1628 compatible = "rockchip,iommu"; 1629 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; 1630 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 1631 interrupt-names = "isp1_mmu"; 1632 #iommu-cells = <0>; 1633 rockchip,disable-mmu-reset; 1634 status = "disabled"; 1635 }; 1636 1637 hdmi: hdmi@ff940000 { 1638 compatible = "rockchip,rk3399-dw-hdmi"; 1639 reg = <0x0 0xff940000 0x0 0x20000>; 1640 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 1641 clocks = <&cru PCLK_HDMI_CTRL>, 1642 <&cru SCLK_HDMI_SFR>, 1643 <&cru PLL_VPLL>, 1644 <&cru PCLK_VIO_GRF>, 1645 <&cru SCLK_HDMI_CEC>; 1646 clock-names = "iahb", "isfr", "vpll", "grf", "cec"; 1647 power-domains = <&power RK3399_PD_HDCP>; 1648 reg-io-width = <4>; 1649 rockchip,grf = <&grf>; 1650 status = "disabled"; 1651 1652 ports { 1653 hdmi_in: port { 1654 #address-cells = <1>; 1655 #size-cells = <0>; 1656 1657 hdmi_in_vopb: endpoint@0 { 1658 reg = <0>; 1659 remote-endpoint = <&vopb_out_hdmi>; 1660 }; 1661 hdmi_in_vopl: endpoint@1 { 1662 reg = <1>; 1663 remote-endpoint = <&vopl_out_hdmi>; 1664 }; 1665 }; 1666 }; 1667 }; 1668 1669 mipi_dsi: mipi@ff960000 { 1670 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1671 reg = <0x0 0xff960000 0x0 0x8000>; 1672 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 1673 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, 1674 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; 1675 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1676 power-domains = <&power RK3399_PD_VIO>; 1677 resets = <&cru SRST_P_MIPI_DSI0>; 1678 reset-names = "apb"; 1679 rockchip,grf = <&grf>; 1680 status = "disabled"; 1681 1682 ports { 1683 #address-cells = <1>; 1684 #size-cells = <0>; 1685 1686 mipi_in: port@0 { 1687 reg = <0>; 1688 #address-cells = <1>; 1689 #size-cells = <0>; 1690 1691 mipi_in_vopb: endpoint@0 { 1692 reg = <0>; 1693 remote-endpoint = <&vopb_out_mipi>; 1694 }; 1695 mipi_in_vopl: endpoint@1 { 1696 reg = <1>; 1697 remote-endpoint = <&vopl_out_mipi>; 1698 }; 1699 }; 1700 }; 1701 }; 1702 1703 mipi_dsi1: mipi@ff968000 { 1704 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1705 reg = <0x0 0xff968000 0x0 0x8000>; 1706 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>; 1707 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, 1708 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; 1709 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1710 power-domains = <&power RK3399_PD_VIO>; 1711 resets = <&cru SRST_P_MIPI_DSI1>; 1712 reset-names = "apb"; 1713 rockchip,grf = <&grf>; 1714 status = "disabled"; 1715 1716 ports { 1717 #address-cells = <1>; 1718 #size-cells = <0>; 1719 1720 mipi1_in: port@0 { 1721 reg = <0>; 1722 #address-cells = <1>; 1723 #size-cells = <0>; 1724 1725 mipi1_in_vopb: endpoint@0 { 1726 reg = <0>; 1727 remote-endpoint = <&vopb_out_mipi1>; 1728 }; 1729 1730 mipi1_in_vopl: endpoint@1 { 1731 reg = <1>; 1732 remote-endpoint = <&vopl_out_mipi1>; 1733 }; 1734 }; 1735 }; 1736 }; 1737 1738 edp: edp@ff970000 { 1739 compatible = "rockchip,rk3399-edp"; 1740 reg = <0x0 0xff970000 0x0 0x8000>; 1741 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 1742 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; 1743 clock-names = "dp", "pclk", "grf"; 1744 pinctrl-names = "default"; 1745 pinctrl-0 = <&edp_hpd>; 1746 power-domains = <&power RK3399_PD_EDP>; 1747 resets = <&cru SRST_P_EDP_CTRL>; 1748 reset-names = "dp"; 1749 rockchip,grf = <&grf>; 1750 status = "disabled"; 1751 1752 ports { 1753 #address-cells = <1>; 1754 #size-cells = <0>; 1755 edp_in: port@0 { 1756 reg = <0>; 1757 #address-cells = <1>; 1758 #size-cells = <0>; 1759 1760 edp_in_vopb: endpoint@0 { 1761 reg = <0>; 1762 remote-endpoint = <&vopb_out_edp>; 1763 }; 1764 1765 edp_in_vopl: endpoint@1 { 1766 reg = <1>; 1767 remote-endpoint = <&vopl_out_edp>; 1768 }; 1769 }; 1770 }; 1771 }; 1772 1773 gpu: gpu@ff9a0000 { 1774 compatible = "rockchip,rk3399-mali", "arm,mali-t860"; 1775 reg = <0x0 0xff9a0000 0x0 0x10000>; 1776 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>, 1777 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, 1778 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>; 1779 interrupt-names = "gpu", "job", "mmu"; 1780 clocks = <&cru ACLK_GPU>; 1781 power-domains = <&power RK3399_PD_GPU>; 1782 status = "disabled"; 1783 }; 1784 1785 pinctrl: pinctrl { 1786 compatible = "rockchip,rk3399-pinctrl"; 1787 rockchip,grf = <&grf>; 1788 rockchip,pmu = <&pmugrf>; 1789 #address-cells = <2>; 1790 #size-cells = <2>; 1791 ranges; 1792 1793 gpio0: gpio0@ff720000 { 1794 compatible = "rockchip,gpio-bank"; 1795 reg = <0x0 0xff720000 0x0 0x100>; 1796 clocks = <&pmucru PCLK_GPIO0_PMU>; 1797 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 1798 1799 gpio-controller; 1800 #gpio-cells = <0x2>; 1801 1802 interrupt-controller; 1803 #interrupt-cells = <0x2>; 1804 }; 1805 1806 gpio1: gpio1@ff730000 { 1807 compatible = "rockchip,gpio-bank"; 1808 reg = <0x0 0xff730000 0x0 0x100>; 1809 clocks = <&pmucru PCLK_GPIO1_PMU>; 1810 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 1811 1812 gpio-controller; 1813 #gpio-cells = <0x2>; 1814 1815 interrupt-controller; 1816 #interrupt-cells = <0x2>; 1817 }; 1818 1819 gpio2: gpio2@ff780000 { 1820 compatible = "rockchip,gpio-bank"; 1821 reg = <0x0 0xff780000 0x0 0x100>; 1822 clocks = <&cru PCLK_GPIO2>; 1823 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 1824 1825 gpio-controller; 1826 #gpio-cells = <0x2>; 1827 1828 interrupt-controller; 1829 #interrupt-cells = <0x2>; 1830 }; 1831 1832 gpio3: gpio3@ff788000 { 1833 compatible = "rockchip,gpio-bank"; 1834 reg = <0x0 0xff788000 0x0 0x100>; 1835 clocks = <&cru PCLK_GPIO3>; 1836 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 1837 1838 gpio-controller; 1839 #gpio-cells = <0x2>; 1840 1841 interrupt-controller; 1842 #interrupt-cells = <0x2>; 1843 }; 1844 1845 gpio4: gpio4@ff790000 { 1846 compatible = "rockchip,gpio-bank"; 1847 reg = <0x0 0xff790000 0x0 0x100>; 1848 clocks = <&cru PCLK_GPIO4>; 1849 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 1850 1851 gpio-controller; 1852 #gpio-cells = <0x2>; 1853 1854 interrupt-controller; 1855 #interrupt-cells = <0x2>; 1856 }; 1857 1858 pcfg_pull_up: pcfg-pull-up { 1859 bias-pull-up; 1860 }; 1861 1862 pcfg_pull_down: pcfg-pull-down { 1863 bias-pull-down; 1864 }; 1865 1866 pcfg_pull_none: pcfg-pull-none { 1867 bias-disable; 1868 }; 1869 1870 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1871 bias-disable; 1872 drive-strength = <12>; 1873 }; 1874 1875 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1876 bias-pull-up; 1877 drive-strength = <8>; 1878 }; 1879 1880 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1881 bias-pull-down; 1882 drive-strength = <4>; 1883 }; 1884 1885 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1886 bias-pull-up; 1887 drive-strength = <2>; 1888 }; 1889 1890 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 1891 bias-pull-down; 1892 drive-strength = <12>; 1893 }; 1894 1895 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 1896 bias-disable; 1897 drive-strength = <13>; 1898 }; 1899 1900 clock { 1901 clk_32k: clk-32k { 1902 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; 1903 }; 1904 }; 1905 1906 edp { 1907 edp_hpd: edp-hpd { 1908 rockchip,pins = 1909 <4 23 RK_FUNC_2 &pcfg_pull_none>; 1910 }; 1911 }; 1912 1913 gmac { 1914 rgmii_pins: rgmii-pins { 1915 rockchip,pins = 1916 /* mac_txclk */ 1917 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>, 1918 /* mac_rxclk */ 1919 <3 14 RK_FUNC_1 &pcfg_pull_none>, 1920 /* mac_mdio */ 1921 <3 13 RK_FUNC_1 &pcfg_pull_none>, 1922 /* mac_txen */ 1923 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>, 1924 /* mac_clk */ 1925 <3 11 RK_FUNC_1 &pcfg_pull_none>, 1926 /* mac_rxdv */ 1927 <3 9 RK_FUNC_1 &pcfg_pull_none>, 1928 /* mac_mdc */ 1929 <3 8 RK_FUNC_1 &pcfg_pull_none>, 1930 /* mac_rxd1 */ 1931 <3 7 RK_FUNC_1 &pcfg_pull_none>, 1932 /* mac_rxd0 */ 1933 <3 6 RK_FUNC_1 &pcfg_pull_none>, 1934 /* mac_txd1 */ 1935 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>, 1936 /* mac_txd0 */ 1937 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>, 1938 /* mac_rxd3 */ 1939 <3 3 RK_FUNC_1 &pcfg_pull_none>, 1940 /* mac_rxd2 */ 1941 <3 2 RK_FUNC_1 &pcfg_pull_none>, 1942 /* mac_txd3 */ 1943 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>, 1944 /* mac_txd2 */ 1945 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>; 1946 }; 1947 1948 rmii_pins: rmii-pins { 1949 rockchip,pins = 1950 /* mac_mdio */ 1951 <3 13 RK_FUNC_1 &pcfg_pull_none>, 1952 /* mac_txen */ 1953 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>, 1954 /* mac_clk */ 1955 <3 11 RK_FUNC_1 &pcfg_pull_none>, 1956 /* mac_rxer */ 1957 <3 10 RK_FUNC_1 &pcfg_pull_none>, 1958 /* mac_rxdv */ 1959 <3 9 RK_FUNC_1 &pcfg_pull_none>, 1960 /* mac_mdc */ 1961 <3 8 RK_FUNC_1 &pcfg_pull_none>, 1962 /* mac_rxd1 */ 1963 <3 7 RK_FUNC_1 &pcfg_pull_none>, 1964 /* mac_rxd0 */ 1965 <3 6 RK_FUNC_1 &pcfg_pull_none>, 1966 /* mac_txd1 */ 1967 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>, 1968 /* mac_txd0 */ 1969 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>; 1970 }; 1971 }; 1972 1973 i2c0 { 1974 i2c0_xfer: i2c0-xfer { 1975 rockchip,pins = 1976 <1 15 RK_FUNC_2 &pcfg_pull_none>, 1977 <1 16 RK_FUNC_2 &pcfg_pull_none>; 1978 }; 1979 }; 1980 1981 i2c1 { 1982 i2c1_xfer: i2c1-xfer { 1983 rockchip,pins = 1984 <4 2 RK_FUNC_1 &pcfg_pull_none>, 1985 <4 1 RK_FUNC_1 &pcfg_pull_none>; 1986 }; 1987 }; 1988 1989 i2c2 { 1990 i2c2_xfer: i2c2-xfer { 1991 rockchip,pins = 1992 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>, 1993 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>; 1994 }; 1995 }; 1996 1997 i2c3 { 1998 i2c3_xfer: i2c3-xfer { 1999 rockchip,pins = 2000 <4 17 RK_FUNC_1 &pcfg_pull_none>, 2001 <4 16 RK_FUNC_1 &pcfg_pull_none>; 2002 }; 2003 }; 2004 2005 i2c4 { 2006 i2c4_xfer: i2c4-xfer { 2007 rockchip,pins = 2008 <1 12 RK_FUNC_1 &pcfg_pull_none>, 2009 <1 11 RK_FUNC_1 &pcfg_pull_none>; 2010 }; 2011 }; 2012 2013 i2c5 { 2014 i2c5_xfer: i2c5-xfer { 2015 rockchip,pins = 2016 <3 11 RK_FUNC_2 &pcfg_pull_none>, 2017 <3 10 RK_FUNC_2 &pcfg_pull_none>; 2018 }; 2019 }; 2020 2021 i2c6 { 2022 i2c6_xfer: i2c6-xfer { 2023 rockchip,pins = 2024 <2 10 RK_FUNC_2 &pcfg_pull_none>, 2025 <2 9 RK_FUNC_2 &pcfg_pull_none>; 2026 }; 2027 }; 2028 2029 i2c7 { 2030 i2c7_xfer: i2c7-xfer { 2031 rockchip,pins = 2032 <2 8 RK_FUNC_2 &pcfg_pull_none>, 2033 <2 7 RK_FUNC_2 &pcfg_pull_none>; 2034 }; 2035 }; 2036 2037 i2c8 { 2038 i2c8_xfer: i2c8-xfer { 2039 rockchip,pins = 2040 <1 21 RK_FUNC_1 &pcfg_pull_none>, 2041 <1 20 RK_FUNC_1 &pcfg_pull_none>; 2042 }; 2043 }; 2044 2045 i2s0 { 2046 i2s0_8ch_bus: i2s0-8ch-bus { 2047 rockchip,pins = 2048 <3 24 RK_FUNC_1 &pcfg_pull_none>, 2049 <3 25 RK_FUNC_1 &pcfg_pull_none>, 2050 <3 26 RK_FUNC_1 &pcfg_pull_none>, 2051 <3 27 RK_FUNC_1 &pcfg_pull_none>, 2052 <3 28 RK_FUNC_1 &pcfg_pull_none>, 2053 <3 29 RK_FUNC_1 &pcfg_pull_none>, 2054 <3 30 RK_FUNC_1 &pcfg_pull_none>, 2055 <3 31 RK_FUNC_1 &pcfg_pull_none>, 2056 <4 0 RK_FUNC_1 &pcfg_pull_none>; 2057 }; 2058 }; 2059 2060 i2s1 { 2061 i2s1_2ch_bus: i2s1-2ch-bus { 2062 rockchip,pins = 2063 <4 3 RK_FUNC_1 &pcfg_pull_none>, 2064 <4 4 RK_FUNC_1 &pcfg_pull_none>, 2065 <4 5 RK_FUNC_1 &pcfg_pull_none>, 2066 <4 6 RK_FUNC_1 &pcfg_pull_none>, 2067 <4 7 RK_FUNC_1 &pcfg_pull_none>; 2068 }; 2069 }; 2070 2071 sdio0 { 2072 sdio0_bus1: sdio0-bus1 { 2073 rockchip,pins = 2074 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>; 2075 }; 2076 2077 sdio0_bus4: sdio0-bus4 { 2078 rockchip,pins = 2079 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>, 2080 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>, 2081 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>, 2082 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>; 2083 }; 2084 2085 sdio0_cmd: sdio0-cmd { 2086 rockchip,pins = 2087 <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>; 2088 }; 2089 2090 sdio0_clk: sdio0-clk { 2091 rockchip,pins = 2092 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 2093 }; 2094 2095 sdio0_cd: sdio0-cd { 2096 rockchip,pins = 2097 <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>; 2098 }; 2099 2100 sdio0_pwr: sdio0-pwr { 2101 rockchip,pins = 2102 <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>; 2103 }; 2104 2105 sdio0_bkpwr: sdio0-bkpwr { 2106 rockchip,pins = 2107 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; 2108 }; 2109 2110 sdio0_wp: sdio0-wp { 2111 rockchip,pins = 2112 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>; 2113 }; 2114 2115 sdio0_int: sdio0-int { 2116 rockchip,pins = 2117 <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>; 2118 }; 2119 }; 2120 2121 sdmmc { 2122 sdmmc_bus1: sdmmc-bus1 { 2123 rockchip,pins = 2124 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; 2125 }; 2126 2127 sdmmc_bus4: sdmmc-bus4 { 2128 rockchip,pins = 2129 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>, 2130 <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>, 2131 <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>, 2132 <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>; 2133 }; 2134 2135 sdmmc_clk: sdmmc-clk { 2136 rockchip,pins = 2137 <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 2138 }; 2139 2140 sdmmc_cmd: sdmmc-cmd { 2141 rockchip,pins = 2142 <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>; 2143 }; 2144 2145 sdmmc_cd: sdmmc-cd { 2146 rockchip,pins = 2147 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>; 2148 }; 2149 2150 sdmmc_wp: sdmmc-wp { 2151 rockchip,pins = 2152 <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; 2153 }; 2154 }; 2155 2156 sleep { 2157 ap_pwroff: ap-pwroff { 2158 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>; 2159 }; 2160 2161 ddrio_pwroff: ddrio-pwroff { 2162 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; 2163 }; 2164 }; 2165 2166 spdif { 2167 spdif_bus: spdif-bus { 2168 rockchip,pins = 2169 <4 21 RK_FUNC_1 &pcfg_pull_none>; 2170 }; 2171 2172 spdif_bus_1: spdif-bus-1 { 2173 rockchip,pins = 2174 <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; 2175 }; 2176 }; 2177 2178 spi0 { 2179 spi0_clk: spi0-clk { 2180 rockchip,pins = 2181 <3 6 RK_FUNC_2 &pcfg_pull_up>; 2182 }; 2183 spi0_cs0: spi0-cs0 { 2184 rockchip,pins = 2185 <3 7 RK_FUNC_2 &pcfg_pull_up>; 2186 }; 2187 spi0_cs1: spi0-cs1 { 2188 rockchip,pins = 2189 <3 8 RK_FUNC_2 &pcfg_pull_up>; 2190 }; 2191 spi0_tx: spi0-tx { 2192 rockchip,pins = 2193 <3 5 RK_FUNC_2 &pcfg_pull_up>; 2194 }; 2195 spi0_rx: spi0-rx { 2196 rockchip,pins = 2197 <3 4 RK_FUNC_2 &pcfg_pull_up>; 2198 }; 2199 }; 2200 2201 spi1 { 2202 spi1_clk: spi1-clk { 2203 rockchip,pins = 2204 <1 9 RK_FUNC_2 &pcfg_pull_up>; 2205 }; 2206 spi1_cs0: spi1-cs0 { 2207 rockchip,pins = 2208 <1 10 RK_FUNC_2 &pcfg_pull_up>; 2209 }; 2210 spi1_rx: spi1-rx { 2211 rockchip,pins = 2212 <1 7 RK_FUNC_2 &pcfg_pull_up>; 2213 }; 2214 spi1_tx: spi1-tx { 2215 rockchip,pins = 2216 <1 8 RK_FUNC_2 &pcfg_pull_up>; 2217 }; 2218 }; 2219 2220 spi2 { 2221 spi2_clk: spi2-clk { 2222 rockchip,pins = 2223 <2 11 RK_FUNC_1 &pcfg_pull_up>; 2224 }; 2225 spi2_cs0: spi2-cs0 { 2226 rockchip,pins = 2227 <2 12 RK_FUNC_1 &pcfg_pull_up>; 2228 }; 2229 spi2_rx: spi2-rx { 2230 rockchip,pins = 2231 <2 9 RK_FUNC_1 &pcfg_pull_up>; 2232 }; 2233 spi2_tx: spi2-tx { 2234 rockchip,pins = 2235 <2 10 RK_FUNC_1 &pcfg_pull_up>; 2236 }; 2237 }; 2238 2239 spi3 { 2240 spi3_clk: spi3-clk { 2241 rockchip,pins = 2242 <1 17 RK_FUNC_1 &pcfg_pull_up>; 2243 }; 2244 spi3_cs0: spi3-cs0 { 2245 rockchip,pins = 2246 <1 18 RK_FUNC_1 &pcfg_pull_up>; 2247 }; 2248 spi3_rx: spi3-rx { 2249 rockchip,pins = 2250 <1 15 RK_FUNC_1 &pcfg_pull_up>; 2251 }; 2252 spi3_tx: spi3-tx { 2253 rockchip,pins = 2254 <1 16 RK_FUNC_1 &pcfg_pull_up>; 2255 }; 2256 }; 2257 2258 spi4 { 2259 spi4_clk: spi4-clk { 2260 rockchip,pins = 2261 <3 2 RK_FUNC_2 &pcfg_pull_up>; 2262 }; 2263 spi4_cs0: spi4-cs0 { 2264 rockchip,pins = 2265 <3 3 RK_FUNC_2 &pcfg_pull_up>; 2266 }; 2267 spi4_rx: spi4-rx { 2268 rockchip,pins = 2269 <3 0 RK_FUNC_2 &pcfg_pull_up>; 2270 }; 2271 spi4_tx: spi4-tx { 2272 rockchip,pins = 2273 <3 1 RK_FUNC_2 &pcfg_pull_up>; 2274 }; 2275 }; 2276 2277 spi5 { 2278 spi5_clk: spi5-clk { 2279 rockchip,pins = 2280 <2 22 RK_FUNC_2 &pcfg_pull_up>; 2281 }; 2282 spi5_cs0: spi5-cs0 { 2283 rockchip,pins = 2284 <2 23 RK_FUNC_2 &pcfg_pull_up>; 2285 }; 2286 spi5_rx: spi5-rx { 2287 rockchip,pins = 2288 <2 20 RK_FUNC_2 &pcfg_pull_up>; 2289 }; 2290 spi5_tx: spi5-tx { 2291 rockchip,pins = 2292 <2 21 RK_FUNC_2 &pcfg_pull_up>; 2293 }; 2294 }; 2295 2296 tsadc { 2297 otp_gpio: otp-gpio { 2298 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>; 2299 }; 2300 2301 otp_out: otp-out { 2302 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>; 2303 }; 2304 }; 2305 2306 uart0 { 2307 uart0_xfer: uart0-xfer { 2308 rockchip,pins = 2309 <2 16 RK_FUNC_1 &pcfg_pull_up>, 2310 <2 17 RK_FUNC_1 &pcfg_pull_none>; 2311 }; 2312 2313 uart0_cts: uart0-cts { 2314 rockchip,pins = 2315 <2 18 RK_FUNC_1 &pcfg_pull_none>; 2316 }; 2317 2318 uart0_rts: uart0-rts { 2319 rockchip,pins = 2320 <2 19 RK_FUNC_1 &pcfg_pull_none>; 2321 }; 2322 }; 2323 2324 uart1 { 2325 uart1_xfer: uart1-xfer { 2326 rockchip,pins = 2327 <3 12 RK_FUNC_2 &pcfg_pull_up>, 2328 <3 13 RK_FUNC_2 &pcfg_pull_none>; 2329 }; 2330 }; 2331 2332 uart2a { 2333 uart2a_xfer: uart2a-xfer { 2334 rockchip,pins = 2335 <4 8 RK_FUNC_2 &pcfg_pull_up>, 2336 <4 9 RK_FUNC_2 &pcfg_pull_none>; 2337 }; 2338 }; 2339 2340 uart2b { 2341 uart2b_xfer: uart2b-xfer { 2342 rockchip,pins = 2343 <4 16 RK_FUNC_2 &pcfg_pull_up>, 2344 <4 17 RK_FUNC_2 &pcfg_pull_none>; 2345 }; 2346 }; 2347 2348 uart2c { 2349 uart2c_xfer: uart2c-xfer { 2350 rockchip,pins = 2351 <4 19 RK_FUNC_1 &pcfg_pull_up>, 2352 <4 20 RK_FUNC_1 &pcfg_pull_none>; 2353 }; 2354 }; 2355 2356 uart3 { 2357 uart3_xfer: uart3-xfer { 2358 rockchip,pins = 2359 <3 14 RK_FUNC_2 &pcfg_pull_up>, 2360 <3 15 RK_FUNC_2 &pcfg_pull_none>; 2361 }; 2362 2363 uart3_cts: uart3-cts { 2364 rockchip,pins = 2365 <3 18 RK_FUNC_2 &pcfg_pull_none>; 2366 }; 2367 2368 uart3_rts: uart3-rts { 2369 rockchip,pins = 2370 <3 19 RK_FUNC_2 &pcfg_pull_none>; 2371 }; 2372 }; 2373 2374 uart4 { 2375 uart4_xfer: uart4-xfer { 2376 rockchip,pins = 2377 <1 7 RK_FUNC_1 &pcfg_pull_up>, 2378 <1 8 RK_FUNC_1 &pcfg_pull_none>; 2379 }; 2380 }; 2381 2382 uarthdcp { 2383 uarthdcp_xfer: uarthdcp-xfer { 2384 rockchip,pins = 2385 <4 21 RK_FUNC_2 &pcfg_pull_up>, 2386 <4 22 RK_FUNC_2 &pcfg_pull_none>; 2387 }; 2388 }; 2389 2390 pwm0 { 2391 pwm0_pin: pwm0-pin { 2392 rockchip,pins = 2393 <4 18 RK_FUNC_1 &pcfg_pull_none>; 2394 }; 2395 2396 vop0_pwm_pin: vop0-pwm-pin { 2397 rockchip,pins = 2398 <4 18 RK_FUNC_2 &pcfg_pull_none>; 2399 }; 2400 }; 2401 2402 pwm1 { 2403 pwm1_pin: pwm1-pin { 2404 rockchip,pins = 2405 <4 22 RK_FUNC_1 &pcfg_pull_none>; 2406 }; 2407 2408 vop1_pwm_pin: vop1-pwm-pin { 2409 rockchip,pins = 2410 <4 18 RK_FUNC_3 &pcfg_pull_none>; 2411 }; 2412 }; 2413 2414 pwm2 { 2415 pwm2_pin: pwm2-pin { 2416 rockchip,pins = 2417 <1 19 RK_FUNC_1 &pcfg_pull_none>; 2418 }; 2419 }; 2420 2421 pwm3a { 2422 pwm3a_pin: pwm3a-pin { 2423 rockchip,pins = 2424 <0 6 RK_FUNC_1 &pcfg_pull_none>; 2425 }; 2426 }; 2427 2428 pwm3b { 2429 pwm3b_pin: pwm3b-pin { 2430 rockchip,pins = 2431 <1 14 RK_FUNC_1 &pcfg_pull_none>; 2432 }; 2433 }; 2434 2435 hdmi { 2436 hdmi_i2c_xfer: hdmi-i2c-xfer { 2437 rockchip,pins = 2438 <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>, 2439 <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; 2440 }; 2441 2442 hdmi_cec: hdmi-cec { 2443 rockchip,pins = 2444 <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>; 2445 }; 2446 }; 2447 2448 pcie { 2449 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2450 rockchip,pins = 2451 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2452 }; 2453 2454 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2455 rockchip,pins = 2456 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2457 }; 2458 }; 2459 2460 }; 2461}; 2462