1/* 2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include <dt-bindings/clock/rk3399-cru.h> 44#include <dt-bindings/gpio/gpio.h> 45#include <dt-bindings/interrupt-controller/arm-gic.h> 46#include <dt-bindings/interrupt-controller/irq.h> 47#include <dt-bindings/pinctrl/rockchip.h> 48#include <dt-bindings/power/rk3399-power.h> 49#include <dt-bindings/thermal/thermal.h> 50 51/ { 52 compatible = "rockchip,rk3399"; 53 54 interrupt-parent = <&gic>; 55 #address-cells = <2>; 56 #size-cells = <2>; 57 58 aliases { 59 i2c0 = &i2c0; 60 i2c1 = &i2c1; 61 i2c2 = &i2c2; 62 i2c3 = &i2c3; 63 i2c4 = &i2c4; 64 i2c5 = &i2c5; 65 i2c6 = &i2c6; 66 i2c7 = &i2c7; 67 i2c8 = &i2c8; 68 serial0 = &uart0; 69 serial1 = &uart1; 70 serial2 = &uart2; 71 serial3 = &uart3; 72 serial4 = &uart4; 73 }; 74 75 cpus { 76 #address-cells = <2>; 77 #size-cells = <0>; 78 79 cpu-map { 80 cluster0 { 81 core0 { 82 cpu = <&cpu_l0>; 83 }; 84 core1 { 85 cpu = <&cpu_l1>; 86 }; 87 core2 { 88 cpu = <&cpu_l2>; 89 }; 90 core3 { 91 cpu = <&cpu_l3>; 92 }; 93 }; 94 95 cluster1 { 96 core0 { 97 cpu = <&cpu_b0>; 98 }; 99 core1 { 100 cpu = <&cpu_b1>; 101 }; 102 }; 103 }; 104 105 cpu_l0: cpu@0 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53", "arm,armv8"; 108 reg = <0x0 0x0>; 109 enable-method = "psci"; 110 #cooling-cells = <2>; /* min followed by max */ 111 clocks = <&cru ARMCLKL>; 112 }; 113 114 cpu_l1: cpu@1 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a53", "arm,armv8"; 117 reg = <0x0 0x1>; 118 enable-method = "psci"; 119 clocks = <&cru ARMCLKL>; 120 }; 121 122 cpu_l2: cpu@2 { 123 device_type = "cpu"; 124 compatible = "arm,cortex-a53", "arm,armv8"; 125 reg = <0x0 0x2>; 126 enable-method = "psci"; 127 clocks = <&cru ARMCLKL>; 128 }; 129 130 cpu_l3: cpu@3 { 131 device_type = "cpu"; 132 compatible = "arm,cortex-a53", "arm,armv8"; 133 reg = <0x0 0x3>; 134 enable-method = "psci"; 135 clocks = <&cru ARMCLKL>; 136 }; 137 138 cpu_b0: cpu@100 { 139 device_type = "cpu"; 140 compatible = "arm,cortex-a72", "arm,armv8"; 141 reg = <0x0 0x100>; 142 enable-method = "psci"; 143 #cooling-cells = <2>; /* min followed by max */ 144 clocks = <&cru ARMCLKB>; 145 }; 146 147 cpu_b1: cpu@101 { 148 device_type = "cpu"; 149 compatible = "arm,cortex-a72", "arm,armv8"; 150 reg = <0x0 0x101>; 151 enable-method = "psci"; 152 clocks = <&cru ARMCLKB>; 153 }; 154 }; 155 156 pmu_a53 { 157 compatible = "arm,cortex-a53-pmu"; 158 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 159 }; 160 161 pmu_a72 { 162 compatible = "arm,cortex-a72-pmu"; 163 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 164 }; 165 166 psci { 167 compatible = "arm,psci-1.0"; 168 method = "smc"; 169 }; 170 171 timer { 172 compatible = "arm,armv8-timer"; 173 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 174 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 175 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 176 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 177 }; 178 179 xin24m: xin24m { 180 compatible = "fixed-clock"; 181 clock-frequency = <24000000>; 182 clock-output-names = "xin24m"; 183 #clock-cells = <0>; 184 }; 185 186 amba { 187 compatible = "simple-bus"; 188 #address-cells = <2>; 189 #size-cells = <2>; 190 ranges; 191 192 dmac_bus: dma-controller@ff6d0000 { 193 compatible = "arm,pl330", "arm,primecell"; 194 reg = <0x0 0xff6d0000 0x0 0x4000>; 195 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 196 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 197 #dma-cells = <1>; 198 clocks = <&cru ACLK_DMAC0_PERILP>; 199 clock-names = "apb_pclk"; 200 }; 201 202 dmac_peri: dma-controller@ff6e0000 { 203 compatible = "arm,pl330", "arm,primecell"; 204 reg = <0x0 0xff6e0000 0x0 0x4000>; 205 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 206 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 207 #dma-cells = <1>; 208 clocks = <&cru ACLK_DMAC1_PERILP>; 209 clock-names = "apb_pclk"; 210 }; 211 }; 212 213 gmac: ethernet@fe300000 { 214 compatible = "rockchip,rk3399-gmac"; 215 reg = <0x0 0xfe300000 0x0 0x10000>; 216 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 217 interrupt-names = "macirq"; 218 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 219 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 220 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 221 <&cru PCLK_GMAC>; 222 clock-names = "stmmaceth", "mac_clk_rx", 223 "mac_clk_tx", "clk_mac_ref", 224 "clk_mac_refout", "aclk_mac", 225 "pclk_mac"; 226 power-domains = <&power RK3399_PD_GMAC>; 227 resets = <&cru SRST_A_GMAC>; 228 reset-names = "stmmaceth"; 229 rockchip,grf = <&grf>; 230 status = "disabled"; 231 }; 232 233 sdio0: dwmmc@fe310000 { 234 compatible = "rockchip,rk3399-dw-mshc", 235 "rockchip,rk3288-dw-mshc"; 236 reg = <0x0 0xfe310000 0x0 0x4000>; 237 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 238 clock-freq-min-max = <400000 150000000>; 239 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 240 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 241 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 242 fifo-depth = <0x100>; 243 status = "disabled"; 244 }; 245 246 sdmmc: dwmmc@fe320000 { 247 compatible = "rockchip,rk3399-dw-mshc", 248 "rockchip,rk3288-dw-mshc"; 249 reg = <0x0 0xfe320000 0x0 0x4000>; 250 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 251 clock-freq-min-max = <400000 150000000>; 252 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 253 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 254 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 255 fifo-depth = <0x100>; 256 status = "disabled"; 257 }; 258 259 sdhci: sdhci@fe330000 { 260 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 261 reg = <0x0 0xfe330000 0x0 0x10000>; 262 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 263 arasan,soc-ctl-syscon = <&grf>; 264 assigned-clocks = <&cru SCLK_EMMC>; 265 assigned-clock-rates = <200000000>; 266 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 267 clock-names = "clk_xin", "clk_ahb"; 268 clock-output-names = "emmc_cardclock"; 269 #clock-cells = <0>; 270 phys = <&emmc_phy>; 271 phy-names = "phy_arasan"; 272 status = "disabled"; 273 }; 274 275 pcie0: pcie@f8000000 { 276 compatible = "rockchip,rk3399-pcie"; 277 reg = <0x0 0xf8000000 0x0 0x2000000>, 278 <0x0 0xfd000000 0x0 0x1000000>; 279 reg-names = "axi-base", "apb-base"; 280 #address-cells = <3>; 281 #size-cells = <2>; 282 #interrupt-cells = <1>; 283 bus-range = <0x0 0x1>; 284 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 285 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 286 clock-names = "aclk", "aclk-perf", 287 "hclk", "pm"; 288 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 289 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 290 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 291 interrupt-names = "sys", "legacy", "client"; 292 interrupt-map-mask = <0 0 0 7>; 293 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 294 <0 0 0 2 &pcie0_intc 1>, 295 <0 0 0 3 &pcie0_intc 2>, 296 <0 0 0 4 &pcie0_intc 3>; 297 msi-map = <0x0 &its 0x0 0x1000>; 298 phys = <&pcie_phy>; 299 phy-names = "pcie-phy"; 300 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000 301 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>; 302 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 303 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>; 304 reset-names = "core", "mgmt", "mgmt-sticky", "pipe"; 305 status = "disabled"; 306 307 pcie0_intc: interrupt-controller { 308 interrupt-controller; 309 #address-cells = <0>; 310 #interrupt-cells = <1>; 311 }; 312 }; 313 314 usb_host0_ehci: usb@fe380000 { 315 compatible = "generic-ehci"; 316 reg = <0x0 0xfe380000 0x0 0x20000>; 317 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 318 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; 319 clock-names = "hclk_host0", "hclk_host0_arb"; 320 phys = <&u2phy0_host>; 321 phy-names = "usb"; 322 status = "disabled"; 323 }; 324 325 usb_host0_ohci: usb@fe3a0000 { 326 compatible = "generic-ohci"; 327 reg = <0x0 0xfe3a0000 0x0 0x20000>; 328 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 329 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; 330 clock-names = "hclk_host0", "hclk_host0_arb"; 331 status = "disabled"; 332 }; 333 334 usb_host1_ehci: usb@fe3c0000 { 335 compatible = "generic-ehci"; 336 reg = <0x0 0xfe3c0000 0x0 0x20000>; 337 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 338 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; 339 clock-names = "hclk_host1", "hclk_host1_arb"; 340 phys = <&u2phy1_host>; 341 phy-names = "usb"; 342 status = "disabled"; 343 }; 344 345 usb_host1_ohci: usb@fe3e0000 { 346 compatible = "generic-ohci"; 347 reg = <0x0 0xfe3e0000 0x0 0x20000>; 348 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 349 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; 350 clock-names = "hclk_host1", "hclk_host1_arb"; 351 status = "disabled"; 352 }; 353 354 gic: interrupt-controller@fee00000 { 355 compatible = "arm,gic-v3"; 356 #interrupt-cells = <4>; 357 #address-cells = <2>; 358 #size-cells = <2>; 359 ranges; 360 interrupt-controller; 361 362 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 363 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 364 <0x0 0xfff00000 0 0x10000>, /* GICC */ 365 <0x0 0xfff10000 0 0x10000>, /* GICH */ 366 <0x0 0xfff20000 0 0x10000>; /* GICV */ 367 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 368 its: interrupt-controller@fee20000 { 369 compatible = "arm,gic-v3-its"; 370 msi-controller; 371 reg = <0x0 0xfee20000 0x0 0x20000>; 372 }; 373 374 ppi-partitions { 375 ppi_cluster0: interrupt-partition-0 { 376 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 377 }; 378 379 ppi_cluster1: interrupt-partition-1 { 380 affinity = <&cpu_b0 &cpu_b1>; 381 }; 382 }; 383 }; 384 385 saradc: saradc@ff100000 { 386 compatible = "rockchip,rk3399-saradc"; 387 reg = <0x0 0xff100000 0x0 0x100>; 388 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 389 #io-channel-cells = <1>; 390 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 391 clock-names = "saradc", "apb_pclk"; 392 resets = <&cru SRST_P_SARADC>; 393 reset-names = "saradc-apb"; 394 status = "disabled"; 395 }; 396 397 i2c1: i2c@ff110000 { 398 compatible = "rockchip,rk3399-i2c"; 399 reg = <0x0 0xff110000 0x0 0x1000>; 400 assigned-clocks = <&cru SCLK_I2C1>; 401 assigned-clock-rates = <200000000>; 402 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 403 clock-names = "i2c", "pclk"; 404 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 405 pinctrl-names = "default"; 406 pinctrl-0 = <&i2c1_xfer>; 407 #address-cells = <1>; 408 #size-cells = <0>; 409 status = "disabled"; 410 }; 411 412 i2c2: i2c@ff120000 { 413 compatible = "rockchip,rk3399-i2c"; 414 reg = <0x0 0xff120000 0x0 0x1000>; 415 assigned-clocks = <&cru SCLK_I2C2>; 416 assigned-clock-rates = <200000000>; 417 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 418 clock-names = "i2c", "pclk"; 419 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 420 pinctrl-names = "default"; 421 pinctrl-0 = <&i2c2_xfer>; 422 #address-cells = <1>; 423 #size-cells = <0>; 424 status = "disabled"; 425 }; 426 427 i2c3: i2c@ff130000 { 428 compatible = "rockchip,rk3399-i2c"; 429 reg = <0x0 0xff130000 0x0 0x1000>; 430 assigned-clocks = <&cru SCLK_I2C3>; 431 assigned-clock-rates = <200000000>; 432 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 433 clock-names = "i2c", "pclk"; 434 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 435 pinctrl-names = "default"; 436 pinctrl-0 = <&i2c3_xfer>; 437 #address-cells = <1>; 438 #size-cells = <0>; 439 status = "disabled"; 440 }; 441 442 i2c5: i2c@ff140000 { 443 compatible = "rockchip,rk3399-i2c"; 444 reg = <0x0 0xff140000 0x0 0x1000>; 445 assigned-clocks = <&cru SCLK_I2C5>; 446 assigned-clock-rates = <200000000>; 447 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 448 clock-names = "i2c", "pclk"; 449 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 450 pinctrl-names = "default"; 451 pinctrl-0 = <&i2c5_xfer>; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 status = "disabled"; 455 }; 456 457 i2c6: i2c@ff150000 { 458 compatible = "rockchip,rk3399-i2c"; 459 reg = <0x0 0xff150000 0x0 0x1000>; 460 assigned-clocks = <&cru SCLK_I2C6>; 461 assigned-clock-rates = <200000000>; 462 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 463 clock-names = "i2c", "pclk"; 464 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 465 pinctrl-names = "default"; 466 pinctrl-0 = <&i2c6_xfer>; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 status = "disabled"; 470 }; 471 472 i2c7: i2c@ff160000 { 473 compatible = "rockchip,rk3399-i2c"; 474 reg = <0x0 0xff160000 0x0 0x1000>; 475 assigned-clocks = <&cru SCLK_I2C7>; 476 assigned-clock-rates = <200000000>; 477 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 478 clock-names = "i2c", "pclk"; 479 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 480 pinctrl-names = "default"; 481 pinctrl-0 = <&i2c7_xfer>; 482 #address-cells = <1>; 483 #size-cells = <0>; 484 status = "disabled"; 485 }; 486 487 uart0: serial@ff180000 { 488 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 489 reg = <0x0 0xff180000 0x0 0x100>; 490 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 491 clock-names = "baudclk", "apb_pclk"; 492 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 493 reg-shift = <2>; 494 reg-io-width = <4>; 495 pinctrl-names = "default"; 496 pinctrl-0 = <&uart0_xfer>; 497 status = "disabled"; 498 }; 499 500 uart1: serial@ff190000 { 501 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 502 reg = <0x0 0xff190000 0x0 0x100>; 503 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 504 clock-names = "baudclk", "apb_pclk"; 505 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 506 reg-shift = <2>; 507 reg-io-width = <4>; 508 pinctrl-names = "default"; 509 pinctrl-0 = <&uart1_xfer>; 510 status = "disabled"; 511 }; 512 513 uart2: serial@ff1a0000 { 514 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 515 reg = <0x0 0xff1a0000 0x0 0x100>; 516 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 517 clock-names = "baudclk", "apb_pclk"; 518 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 519 reg-shift = <2>; 520 reg-io-width = <4>; 521 pinctrl-names = "default"; 522 pinctrl-0 = <&uart2c_xfer>; 523 status = "disabled"; 524 }; 525 526 uart3: serial@ff1b0000 { 527 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 528 reg = <0x0 0xff1b0000 0x0 0x100>; 529 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 530 clock-names = "baudclk", "apb_pclk"; 531 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 532 reg-shift = <2>; 533 reg-io-width = <4>; 534 pinctrl-names = "default"; 535 pinctrl-0 = <&uart3_xfer>; 536 status = "disabled"; 537 }; 538 539 spi0: spi@ff1c0000 { 540 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 541 reg = <0x0 0xff1c0000 0x0 0x1000>; 542 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 543 clock-names = "spiclk", "apb_pclk"; 544 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 545 pinctrl-names = "default"; 546 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 status = "disabled"; 550 }; 551 552 spi1: spi@ff1d0000 { 553 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 554 reg = <0x0 0xff1d0000 0x0 0x1000>; 555 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 556 clock-names = "spiclk", "apb_pclk"; 557 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 558 pinctrl-names = "default"; 559 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 560 #address-cells = <1>; 561 #size-cells = <0>; 562 status = "disabled"; 563 }; 564 565 spi2: spi@ff1e0000 { 566 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 567 reg = <0x0 0xff1e0000 0x0 0x1000>; 568 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 569 clock-names = "spiclk", "apb_pclk"; 570 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 571 pinctrl-names = "default"; 572 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 573 #address-cells = <1>; 574 #size-cells = <0>; 575 status = "disabled"; 576 }; 577 578 spi4: spi@ff1f0000 { 579 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 580 reg = <0x0 0xff1f0000 0x0 0x1000>; 581 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 582 clock-names = "spiclk", "apb_pclk"; 583 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 584 pinctrl-names = "default"; 585 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 status = "disabled"; 589 }; 590 591 spi5: spi@ff200000 { 592 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 593 reg = <0x0 0xff200000 0x0 0x1000>; 594 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 595 clock-names = "spiclk", "apb_pclk"; 596 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 597 pinctrl-names = "default"; 598 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 status = "disabled"; 602 }; 603 604 thermal-zones { 605 cpu_thermal: cpu { 606 polling-delay-passive = <100>; 607 polling-delay = <1000>; 608 609 thermal-sensors = <&tsadc 0>; 610 611 trips { 612 cpu_alert0: cpu_alert0 { 613 temperature = <70000>; 614 hysteresis = <2000>; 615 type = "passive"; 616 }; 617 cpu_alert1: cpu_alert1 { 618 temperature = <75000>; 619 hysteresis = <2000>; 620 type = "passive"; 621 }; 622 cpu_crit: cpu_crit { 623 temperature = <95000>; 624 hysteresis = <2000>; 625 type = "critical"; 626 }; 627 }; 628 629 cooling-maps { 630 map0 { 631 trip = <&cpu_alert0>; 632 cooling-device = 633 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 634 }; 635 map1 { 636 trip = <&cpu_alert1>; 637 cooling-device = 638 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 639 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 640 }; 641 }; 642 }; 643 644 gpu_thermal: gpu { 645 polling-delay-passive = <100>; 646 polling-delay = <1000>; 647 648 thermal-sensors = <&tsadc 1>; 649 650 trips { 651 gpu_alert0: gpu_alert0 { 652 temperature = <75000>; 653 hysteresis = <2000>; 654 type = "passive"; 655 }; 656 gpu_crit: gpu_crit { 657 temperature = <95000>; 658 hysteresis = <2000>; 659 type = "critical"; 660 }; 661 }; 662 663 cooling-maps { 664 map0 { 665 trip = <&gpu_alert0>; 666 cooling-device = 667 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 668 }; 669 }; 670 }; 671 }; 672 673 tsadc: tsadc@ff260000 { 674 compatible = "rockchip,rk3399-tsadc"; 675 reg = <0x0 0xff260000 0x0 0x100>; 676 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 677 assigned-clocks = <&cru SCLK_TSADC>; 678 assigned-clock-rates = <750000>; 679 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 680 clock-names = "tsadc", "apb_pclk"; 681 resets = <&cru SRST_TSADC>; 682 reset-names = "tsadc-apb"; 683 rockchip,grf = <&grf>; 684 rockchip,hw-tshut-temp = <95000>; 685 pinctrl-names = "init", "default", "sleep"; 686 pinctrl-0 = <&otp_gpio>; 687 pinctrl-1 = <&otp_out>; 688 pinctrl-2 = <&otp_gpio>; 689 #thermal-sensor-cells = <1>; 690 status = "disabled"; 691 }; 692 693 qos_gmac: qos@ffa5c000 { 694 compatible = "syscon"; 695 reg = <0x0 0xffa5c000 0x0 0x20>; 696 }; 697 698 qos_hdcp: qos@ffa90000 { 699 compatible = "syscon"; 700 reg = <0x0 0xffa90000 0x0 0x20>; 701 }; 702 703 qos_iep: qos@ffa98000 { 704 compatible = "syscon"; 705 reg = <0x0 0xffa98000 0x0 0x20>; 706 }; 707 708 qos_isp0_m0: qos@ffaa0000 { 709 compatible = "syscon"; 710 reg = <0x0 0xffaa0000 0x0 0x20>; 711 }; 712 713 qos_isp0_m1: qos@ffaa0080 { 714 compatible = "syscon"; 715 reg = <0x0 0xffaa0080 0x0 0x20>; 716 }; 717 718 qos_isp1_m0: qos@ffaa8000 { 719 compatible = "syscon"; 720 reg = <0x0 0xffaa8000 0x0 0x20>; 721 }; 722 723 qos_isp1_m1: qos@ffaa8080 { 724 compatible = "syscon"; 725 reg = <0x0 0xffaa8080 0x0 0x20>; 726 }; 727 728 qos_rga_r: qos@ffab0000 { 729 compatible = "syscon"; 730 reg = <0x0 0xffab0000 0x0 0x20>; 731 }; 732 733 qos_rga_w: qos@ffab0080 { 734 compatible = "syscon"; 735 reg = <0x0 0xffab0080 0x0 0x20>; 736 }; 737 738 qos_video_m0: qos@ffab8000 { 739 compatible = "syscon"; 740 reg = <0x0 0xffab8000 0x0 0x20>; 741 }; 742 743 qos_video_m1_r: qos@ffac0000 { 744 compatible = "syscon"; 745 reg = <0x0 0xffac0000 0x0 0x20>; 746 }; 747 748 qos_video_m1_w: qos@ffac0080 { 749 compatible = "syscon"; 750 reg = <0x0 0xffac0080 0x0 0x20>; 751 }; 752 753 qos_vop_big_r: qos@ffac8000 { 754 compatible = "syscon"; 755 reg = <0x0 0xffac8000 0x0 0x20>; 756 }; 757 758 qos_vop_big_w: qos@ffac8080 { 759 compatible = "syscon"; 760 reg = <0x0 0xffac8080 0x0 0x20>; 761 }; 762 763 qos_vop_little: qos@ffad0000 { 764 compatible = "syscon"; 765 reg = <0x0 0xffad0000 0x0 0x20>; 766 }; 767 768 qos_gpu: qos@ffae0000 { 769 compatible = "syscon"; 770 reg = <0x0 0xffae0000 0x0 0x20>; 771 }; 772 773 pmu: power-management@ff310000 { 774 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 775 reg = <0x0 0xff310000 0x0 0x1000>; 776 777 /* 778 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 779 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 780 * Some of the power domains are grouped together for every 781 * voltage domain. 782 * The detail contents as below. 783 */ 784 power: power-controller { 785 compatible = "rockchip,rk3399-power-controller"; 786 #power-domain-cells = <1>; 787 #address-cells = <1>; 788 #size-cells = <0>; 789 790 /* These power domains are grouped by VD_CENTER */ 791 pd_iep@RK3399_PD_IEP { 792 reg = <RK3399_PD_IEP>; 793 clocks = <&cru ACLK_IEP>, 794 <&cru HCLK_IEP>; 795 pm_qos = <&qos_iep>; 796 }; 797 pd_rga@RK3399_PD_RGA { 798 reg = <RK3399_PD_RGA>; 799 clocks = <&cru ACLK_RGA>, 800 <&cru HCLK_RGA>; 801 pm_qos = <&qos_rga_r>, 802 <&qos_rga_w>; 803 }; 804 pd_vcodec@RK3399_PD_VCODEC { 805 reg = <RK3399_PD_VCODEC>; 806 clocks = <&cru ACLK_VCODEC>, 807 <&cru HCLK_VCODEC>; 808 pm_qos = <&qos_video_m0>; 809 }; 810 pd_vdu@RK3399_PD_VDU { 811 reg = <RK3399_PD_VDU>; 812 clocks = <&cru ACLK_VDU>, 813 <&cru HCLK_VDU>; 814 pm_qos = <&qos_video_m1_r>, 815 <&qos_video_m1_w>; 816 }; 817 818 /* These power domains are grouped by VD_GPU */ 819 pd_gpu@RK3399_PD_GPU { 820 reg = <RK3399_PD_GPU>; 821 clocks = <&cru ACLK_GPU>; 822 pm_qos = <&qos_gpu>; 823 }; 824 825 /* These power domains are grouped by VD_LOGIC */ 826 pd_gmac@RK3399_PD_GMAC { 827 reg = <RK3399_PD_GMAC>; 828 clocks = <&cru ACLK_GMAC>; 829 pm_qos = <&qos_gmac>; 830 }; 831 pd_vio@RK3399_PD_VIO { 832 reg = <RK3399_PD_VIO>; 833 #address-cells = <1>; 834 #size-cells = <0>; 835 836 pd_hdcp@RK3399_PD_HDCP { 837 reg = <RK3399_PD_HDCP>; 838 clocks = <&cru ACLK_HDCP>, 839 <&cru HCLK_HDCP>, 840 <&cru PCLK_HDCP>; 841 pm_qos = <&qos_hdcp>; 842 }; 843 pd_isp0@RK3399_PD_ISP0 { 844 reg = <RK3399_PD_ISP0>; 845 clocks = <&cru ACLK_ISP0>, 846 <&cru HCLK_ISP0>; 847 pm_qos = <&qos_isp0_m0>, 848 <&qos_isp0_m1>; 849 }; 850 pd_isp1@RK3399_PD_ISP1 { 851 reg = <RK3399_PD_ISP1>; 852 clocks = <&cru ACLK_ISP1>, 853 <&cru HCLK_ISP1>; 854 pm_qos = <&qos_isp1_m0>, 855 <&qos_isp1_m1>; 856 }; 857 pd_tcpc0@RK3399_PD_TCPC0 { 858 reg = <RK3399_PD_TCPD0>; 859 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 860 <&cru SCLK_UPHY0_TCPDPHY_REF>; 861 }; 862 pd_tcpc1@RK3399_PD_TCPC1 { 863 reg = <RK3399_PD_TCPD1>; 864 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 865 <&cru SCLK_UPHY1_TCPDPHY_REF>; 866 }; 867 pd_vo@RK3399_PD_VO { 868 reg = <RK3399_PD_VO>; 869 #address-cells = <1>; 870 #size-cells = <0>; 871 872 pd_vopb@RK3399_PD_VOPB { 873 reg = <RK3399_PD_VOPB>; 874 clocks = <&cru ACLK_VOP0>, 875 <&cru HCLK_VOP0>; 876 pm_qos = <&qos_vop_big_r>, 877 <&qos_vop_big_w>; 878 }; 879 pd_vopl@RK3399_PD_VOPL { 880 reg = <RK3399_PD_VOPL>; 881 clocks = <&cru ACLK_VOP1>, 882 <&cru HCLK_VOP1>; 883 pm_qos = <&qos_vop_little>; 884 }; 885 }; 886 }; 887 }; 888 }; 889 890 pmugrf: syscon@ff320000 { 891 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 892 reg = <0x0 0xff320000 0x0 0x1000>; 893 #address-cells = <1>; 894 #size-cells = <1>; 895 896 pmu_io_domains: io-domains { 897 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 898 status = "disabled"; 899 }; 900 }; 901 902 spi3: spi@ff350000 { 903 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 904 reg = <0x0 0xff350000 0x0 0x1000>; 905 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 906 clock-names = "spiclk", "apb_pclk"; 907 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 908 pinctrl-names = "default"; 909 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 910 #address-cells = <1>; 911 #size-cells = <0>; 912 status = "disabled"; 913 }; 914 915 uart4: serial@ff370000 { 916 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 917 reg = <0x0 0xff370000 0x0 0x100>; 918 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 919 clock-names = "baudclk", "apb_pclk"; 920 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 921 reg-shift = <2>; 922 reg-io-width = <4>; 923 pinctrl-names = "default"; 924 pinctrl-0 = <&uart4_xfer>; 925 status = "disabled"; 926 }; 927 928 i2c0: i2c@ff3c0000 { 929 compatible = "rockchip,rk3399-i2c"; 930 reg = <0x0 0xff3c0000 0x0 0x1000>; 931 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 932 assigned-clock-rates = <200000000>; 933 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 934 clock-names = "i2c", "pclk"; 935 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 936 pinctrl-names = "default"; 937 pinctrl-0 = <&i2c0_xfer>; 938 #address-cells = <1>; 939 #size-cells = <0>; 940 status = "disabled"; 941 }; 942 943 i2c4: i2c@ff3d0000 { 944 compatible = "rockchip,rk3399-i2c"; 945 reg = <0x0 0xff3d0000 0x0 0x1000>; 946 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 947 assigned-clock-rates = <200000000>; 948 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 949 clock-names = "i2c", "pclk"; 950 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 951 pinctrl-names = "default"; 952 pinctrl-0 = <&i2c4_xfer>; 953 #address-cells = <1>; 954 #size-cells = <0>; 955 status = "disabled"; 956 }; 957 958 i2c8: i2c@ff3e0000 { 959 compatible = "rockchip,rk3399-i2c"; 960 reg = <0x0 0xff3e0000 0x0 0x1000>; 961 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 962 assigned-clock-rates = <200000000>; 963 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 964 clock-names = "i2c", "pclk"; 965 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 966 pinctrl-names = "default"; 967 pinctrl-0 = <&i2c8_xfer>; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 status = "disabled"; 971 }; 972 973 pwm0: pwm@ff420000 { 974 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 975 reg = <0x0 0xff420000 0x0 0x10>; 976 #pwm-cells = <3>; 977 pinctrl-names = "default"; 978 pinctrl-0 = <&pwm0_pin>; 979 clocks = <&pmucru PCLK_RKPWM_PMU>; 980 clock-names = "pwm"; 981 status = "disabled"; 982 }; 983 984 pwm1: pwm@ff420010 { 985 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 986 reg = <0x0 0xff420010 0x0 0x10>; 987 #pwm-cells = <3>; 988 pinctrl-names = "default"; 989 pinctrl-0 = <&pwm1_pin>; 990 clocks = <&pmucru PCLK_RKPWM_PMU>; 991 clock-names = "pwm"; 992 status = "disabled"; 993 }; 994 995 pwm2: pwm@ff420020 { 996 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 997 reg = <0x0 0xff420020 0x0 0x10>; 998 #pwm-cells = <3>; 999 pinctrl-names = "default"; 1000 pinctrl-0 = <&pwm2_pin>; 1001 clocks = <&pmucru PCLK_RKPWM_PMU>; 1002 clock-names = "pwm"; 1003 status = "disabled"; 1004 }; 1005 1006 pwm3: pwm@ff420030 { 1007 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1008 reg = <0x0 0xff420030 0x0 0x10>; 1009 #pwm-cells = <3>; 1010 pinctrl-names = "default"; 1011 pinctrl-0 = <&pwm3a_pin>; 1012 clocks = <&pmucru PCLK_RKPWM_PMU>; 1013 clock-names = "pwm"; 1014 status = "disabled"; 1015 }; 1016 1017 efuse0: efuse@ff690000 { 1018 compatible = "rockchip,rk3399-efuse"; 1019 reg = <0x0 0xff690000 0x0 0x80>; 1020 #address-cells = <1>; 1021 #size-cells = <1>; 1022 clocks = <&cru PCLK_EFUSE1024NS>; 1023 clock-names = "pclk_efuse"; 1024 1025 /* Data cells */ 1026 cpub_leakage: cpu-leakage@17 { 1027 reg = <0x17 0x1>; 1028 }; 1029 gpu_leakage: gpu-leakage@18 { 1030 reg = <0x18 0x1>; 1031 }; 1032 center_leakage: center-leakage@19 { 1033 reg = <0x19 0x1>; 1034 }; 1035 cpul_leakage: cpu-leakage@1a { 1036 reg = <0x1a 0x1>; 1037 }; 1038 logic_leakage: logic-leakage@1b { 1039 reg = <0x1b 0x1>; 1040 }; 1041 wafer_info: wafer-info@1c { 1042 reg = <0x1c 0x1>; 1043 }; 1044 }; 1045 1046 pmucru: pmu-clock-controller@ff750000 { 1047 compatible = "rockchip,rk3399-pmucru"; 1048 reg = <0x0 0xff750000 0x0 0x1000>; 1049 #clock-cells = <1>; 1050 #reset-cells = <1>; 1051 assigned-clocks = <&pmucru PLL_PPLL>; 1052 assigned-clock-rates = <676000000>; 1053 }; 1054 1055 cru: clock-controller@ff760000 { 1056 compatible = "rockchip,rk3399-cru"; 1057 reg = <0x0 0xff760000 0x0 0x1000>; 1058 #clock-cells = <1>; 1059 #reset-cells = <1>; 1060 assigned-clocks = 1061 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1062 <&cru PLL_NPLL>, 1063 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1064 <&cru PCLK_PERIHP>, 1065 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1066 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1067 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; 1068 assigned-clock-rates = 1069 <594000000>, <800000000>, 1070 <1000000000>, 1071 <150000000>, <75000000>, 1072 <37500000>, 1073 <100000000>, <100000000>, 1074 <50000000>, <600000000>, 1075 <100000000>, <50000000>; 1076 }; 1077 1078 grf: syscon@ff770000 { 1079 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1080 reg = <0x0 0xff770000 0x0 0x10000>; 1081 #address-cells = <1>; 1082 #size-cells = <1>; 1083 1084 io_domains: io-domains { 1085 compatible = "rockchip,rk3399-io-voltage-domain"; 1086 status = "disabled"; 1087 }; 1088 1089 u2phy0: usb2-phy@e450 { 1090 compatible = "rockchip,rk3399-usb2phy"; 1091 reg = <0xe450 0x10>; 1092 clocks = <&cru SCLK_USB2PHY0_REF>; 1093 clock-names = "phyclk"; 1094 #clock-cells = <0>; 1095 clock-output-names = "clk_usbphy0_480m"; 1096 status = "disabled"; 1097 1098 u2phy0_host: host-port { 1099 #phy-cells = <0>; 1100 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1101 interrupt-names = "linestate"; 1102 status = "disabled"; 1103 }; 1104 }; 1105 1106 u2phy1: usb2-phy@e460 { 1107 compatible = "rockchip,rk3399-usb2phy"; 1108 reg = <0xe460 0x10>; 1109 clocks = <&cru SCLK_USB2PHY1_REF>; 1110 clock-names = "phyclk"; 1111 #clock-cells = <0>; 1112 clock-output-names = "clk_usbphy1_480m"; 1113 status = "disabled"; 1114 1115 u2phy1_host: host-port { 1116 #phy-cells = <0>; 1117 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1118 interrupt-names = "linestate"; 1119 status = "disabled"; 1120 }; 1121 }; 1122 1123 emmc_phy: phy@f780 { 1124 compatible = "rockchip,rk3399-emmc-phy"; 1125 reg = <0xf780 0x24>; 1126 clocks = <&sdhci>; 1127 clock-names = "emmcclk"; 1128 #phy-cells = <0>; 1129 status = "disabled"; 1130 }; 1131 1132 pcie_phy: pcie-phy { 1133 compatible = "rockchip,rk3399-pcie-phy"; 1134 clocks = <&cru SCLK_PCIEPHY_REF>; 1135 clock-names = "refclk"; 1136 #phy-cells = <0>; 1137 resets = <&cru SRST_PCIEPHY>; 1138 reset-names = "phy"; 1139 status = "disabled"; 1140 }; 1141 }; 1142 1143 tcphy0: phy@ff7c0000 { 1144 compatible = "rockchip,rk3399-typec-phy"; 1145 reg = <0x0 0xff7c0000 0x0 0x40000>; 1146 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1147 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1148 clock-names = "tcpdcore", "tcpdphy-ref"; 1149 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1150 assigned-clock-rates = <50000000>; 1151 resets = <&cru SRST_UPHY0>, 1152 <&cru SRST_UPHY0_PIPE_L00>, 1153 <&cru SRST_P_UPHY0_TCPHY>; 1154 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1155 rockchip,grf = <&grf>; 1156 rockchip,typec-conn-dir = <0xe580 0 16>; 1157 rockchip,usb3tousb2-en = <0xe580 3 19>; 1158 rockchip,external-psm = <0xe588 14 30>; 1159 rockchip,pipe-status = <0xe5c0 0 0>; 1160 status = "disabled"; 1161 1162 tcphy0_dp: dp-port { 1163 #phy-cells = <0>; 1164 }; 1165 1166 tcphy0_usb3: usb3-port { 1167 #phy-cells = <0>; 1168 }; 1169 }; 1170 1171 tcphy1: phy@ff800000 { 1172 compatible = "rockchip,rk3399-typec-phy"; 1173 reg = <0x0 0xff800000 0x0 0x40000>; 1174 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1175 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1176 clock-names = "tcpdcore", "tcpdphy-ref"; 1177 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1178 assigned-clock-rates = <50000000>; 1179 resets = <&cru SRST_UPHY1>, 1180 <&cru SRST_UPHY1_PIPE_L00>, 1181 <&cru SRST_P_UPHY1_TCPHY>; 1182 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1183 rockchip,grf = <&grf>; 1184 rockchip,typec-conn-dir = <0xe58c 0 16>; 1185 rockchip,usb3tousb2-en = <0xe58c 3 19>; 1186 rockchip,external-psm = <0xe594 14 30>; 1187 rockchip,pipe-status = <0xe5c0 16 16>; 1188 status = "disabled"; 1189 1190 tcphy1_dp: dp-port { 1191 #phy-cells = <0>; 1192 }; 1193 1194 tcphy1_usb3: usb3-port { 1195 #phy-cells = <0>; 1196 }; 1197 }; 1198 1199 watchdog@ff848000 { 1200 compatible = "snps,dw-wdt"; 1201 reg = <0x0 0xff848000 0x0 0x100>; 1202 clocks = <&cru PCLK_WDT>; 1203 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1204 }; 1205 1206 rktimer: rktimer@ff850000 { 1207 compatible = "rockchip,rk3399-timer"; 1208 reg = <0x0 0xff850000 0x0 0x1000>; 1209 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1210 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1211 clock-names = "pclk", "timer"; 1212 }; 1213 1214 spdif: spdif@ff870000 { 1215 compatible = "rockchip,rk3399-spdif"; 1216 reg = <0x0 0xff870000 0x0 0x1000>; 1217 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1218 dmas = <&dmac_bus 7>; 1219 dma-names = "tx"; 1220 clock-names = "mclk", "hclk"; 1221 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1222 pinctrl-names = "default"; 1223 pinctrl-0 = <&spdif_bus>; 1224 status = "disabled"; 1225 }; 1226 1227 i2s0: i2s@ff880000 { 1228 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1229 reg = <0x0 0xff880000 0x0 0x1000>; 1230 rockchip,grf = <&grf>; 1231 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1232 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1233 dma-names = "tx", "rx"; 1234 clock-names = "i2s_clk", "i2s_hclk"; 1235 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1236 pinctrl-names = "default"; 1237 pinctrl-0 = <&i2s0_8ch_bus>; 1238 status = "disabled"; 1239 }; 1240 1241 i2s1: i2s@ff890000 { 1242 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1243 reg = <0x0 0xff890000 0x0 0x1000>; 1244 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1245 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1246 dma-names = "tx", "rx"; 1247 clock-names = "i2s_clk", "i2s_hclk"; 1248 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1249 pinctrl-names = "default"; 1250 pinctrl-0 = <&i2s1_2ch_bus>; 1251 status = "disabled"; 1252 }; 1253 1254 i2s2: i2s@ff8a0000 { 1255 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1256 reg = <0x0 0xff8a0000 0x0 0x1000>; 1257 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1258 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1259 dma-names = "tx", "rx"; 1260 clock-names = "i2s_clk", "i2s_hclk"; 1261 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1262 status = "disabled"; 1263 }; 1264 1265 pinctrl: pinctrl { 1266 compatible = "rockchip,rk3399-pinctrl"; 1267 rockchip,grf = <&grf>; 1268 rockchip,pmu = <&pmugrf>; 1269 #address-cells = <2>; 1270 #size-cells = <2>; 1271 ranges; 1272 1273 gpio0: gpio0@ff720000 { 1274 compatible = "rockchip,gpio-bank"; 1275 reg = <0x0 0xff720000 0x0 0x100>; 1276 clocks = <&pmucru PCLK_GPIO0_PMU>; 1277 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 1278 1279 gpio-controller; 1280 #gpio-cells = <0x2>; 1281 1282 interrupt-controller; 1283 #interrupt-cells = <0x2>; 1284 }; 1285 1286 gpio1: gpio1@ff730000 { 1287 compatible = "rockchip,gpio-bank"; 1288 reg = <0x0 0xff730000 0x0 0x100>; 1289 clocks = <&pmucru PCLK_GPIO1_PMU>; 1290 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 1291 1292 gpio-controller; 1293 #gpio-cells = <0x2>; 1294 1295 interrupt-controller; 1296 #interrupt-cells = <0x2>; 1297 }; 1298 1299 gpio2: gpio2@ff780000 { 1300 compatible = "rockchip,gpio-bank"; 1301 reg = <0x0 0xff780000 0x0 0x100>; 1302 clocks = <&cru PCLK_GPIO2>; 1303 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 1304 1305 gpio-controller; 1306 #gpio-cells = <0x2>; 1307 1308 interrupt-controller; 1309 #interrupt-cells = <0x2>; 1310 }; 1311 1312 gpio3: gpio3@ff788000 { 1313 compatible = "rockchip,gpio-bank"; 1314 reg = <0x0 0xff788000 0x0 0x100>; 1315 clocks = <&cru PCLK_GPIO3>; 1316 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 1317 1318 gpio-controller; 1319 #gpio-cells = <0x2>; 1320 1321 interrupt-controller; 1322 #interrupt-cells = <0x2>; 1323 }; 1324 1325 gpio4: gpio4@ff790000 { 1326 compatible = "rockchip,gpio-bank"; 1327 reg = <0x0 0xff790000 0x0 0x100>; 1328 clocks = <&cru PCLK_GPIO4>; 1329 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 1330 1331 gpio-controller; 1332 #gpio-cells = <0x2>; 1333 1334 interrupt-controller; 1335 #interrupt-cells = <0x2>; 1336 }; 1337 1338 pcfg_pull_up: pcfg-pull-up { 1339 bias-pull-up; 1340 }; 1341 1342 pcfg_pull_down: pcfg-pull-down { 1343 bias-pull-down; 1344 }; 1345 1346 pcfg_pull_none: pcfg-pull-none { 1347 bias-disable; 1348 }; 1349 1350 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1351 bias-disable; 1352 drive-strength = <12>; 1353 }; 1354 1355 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1356 bias-pull-up; 1357 drive-strength = <8>; 1358 }; 1359 1360 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1361 bias-pull-down; 1362 drive-strength = <4>; 1363 }; 1364 1365 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1366 bias-pull-up; 1367 drive-strength = <2>; 1368 }; 1369 1370 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 1371 bias-pull-down; 1372 drive-strength = <12>; 1373 }; 1374 1375 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 1376 bias-disable; 1377 drive-strength = <13>; 1378 }; 1379 1380 clock { 1381 clk_32k: clk-32k { 1382 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; 1383 }; 1384 }; 1385 1386 gmac { 1387 rgmii_pins: rgmii-pins { 1388 rockchip,pins = 1389 /* mac_txclk */ 1390 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>, 1391 /* mac_rxclk */ 1392 <3 14 RK_FUNC_1 &pcfg_pull_none>, 1393 /* mac_mdio */ 1394 <3 13 RK_FUNC_1 &pcfg_pull_none>, 1395 /* mac_txen */ 1396 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>, 1397 /* mac_clk */ 1398 <3 11 RK_FUNC_1 &pcfg_pull_none>, 1399 /* mac_rxdv */ 1400 <3 9 RK_FUNC_1 &pcfg_pull_none>, 1401 /* mac_mdc */ 1402 <3 8 RK_FUNC_1 &pcfg_pull_none>, 1403 /* mac_rxd1 */ 1404 <3 7 RK_FUNC_1 &pcfg_pull_none>, 1405 /* mac_rxd0 */ 1406 <3 6 RK_FUNC_1 &pcfg_pull_none>, 1407 /* mac_txd1 */ 1408 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>, 1409 /* mac_txd0 */ 1410 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>, 1411 /* mac_rxd3 */ 1412 <3 3 RK_FUNC_1 &pcfg_pull_none>, 1413 /* mac_rxd2 */ 1414 <3 2 RK_FUNC_1 &pcfg_pull_none>, 1415 /* mac_txd3 */ 1416 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>, 1417 /* mac_txd2 */ 1418 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>; 1419 }; 1420 1421 rmii_pins: rmii-pins { 1422 rockchip,pins = 1423 /* mac_mdio */ 1424 <3 13 RK_FUNC_1 &pcfg_pull_none>, 1425 /* mac_txen */ 1426 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>, 1427 /* mac_clk */ 1428 <3 11 RK_FUNC_1 &pcfg_pull_none>, 1429 /* mac_rxer */ 1430 <3 10 RK_FUNC_1 &pcfg_pull_none>, 1431 /* mac_rxdv */ 1432 <3 9 RK_FUNC_1 &pcfg_pull_none>, 1433 /* mac_mdc */ 1434 <3 8 RK_FUNC_1 &pcfg_pull_none>, 1435 /* mac_rxd1 */ 1436 <3 7 RK_FUNC_1 &pcfg_pull_none>, 1437 /* mac_rxd0 */ 1438 <3 6 RK_FUNC_1 &pcfg_pull_none>, 1439 /* mac_txd1 */ 1440 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>, 1441 /* mac_txd0 */ 1442 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>; 1443 }; 1444 }; 1445 1446 i2c0 { 1447 i2c0_xfer: i2c0-xfer { 1448 rockchip,pins = 1449 <1 15 RK_FUNC_2 &pcfg_pull_none>, 1450 <1 16 RK_FUNC_2 &pcfg_pull_none>; 1451 }; 1452 }; 1453 1454 i2c1 { 1455 i2c1_xfer: i2c1-xfer { 1456 rockchip,pins = 1457 <4 2 RK_FUNC_1 &pcfg_pull_none>, 1458 <4 1 RK_FUNC_1 &pcfg_pull_none>; 1459 }; 1460 }; 1461 1462 i2c2 { 1463 i2c2_xfer: i2c2-xfer { 1464 rockchip,pins = 1465 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>, 1466 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>; 1467 }; 1468 }; 1469 1470 i2c3 { 1471 i2c3_xfer: i2c3-xfer { 1472 rockchip,pins = 1473 <4 17 RK_FUNC_1 &pcfg_pull_none>, 1474 <4 16 RK_FUNC_1 &pcfg_pull_none>; 1475 }; 1476 }; 1477 1478 i2c4 { 1479 i2c4_xfer: i2c4-xfer { 1480 rockchip,pins = 1481 <1 12 RK_FUNC_1 &pcfg_pull_none>, 1482 <1 11 RK_FUNC_1 &pcfg_pull_none>; 1483 }; 1484 }; 1485 1486 i2c5 { 1487 i2c5_xfer: i2c5-xfer { 1488 rockchip,pins = 1489 <3 11 RK_FUNC_2 &pcfg_pull_none>, 1490 <3 10 RK_FUNC_2 &pcfg_pull_none>; 1491 }; 1492 }; 1493 1494 i2c6 { 1495 i2c6_xfer: i2c6-xfer { 1496 rockchip,pins = 1497 <2 10 RK_FUNC_2 &pcfg_pull_none>, 1498 <2 9 RK_FUNC_2 &pcfg_pull_none>; 1499 }; 1500 }; 1501 1502 i2c7 { 1503 i2c7_xfer: i2c7-xfer { 1504 rockchip,pins = 1505 <2 8 RK_FUNC_2 &pcfg_pull_none>, 1506 <2 7 RK_FUNC_2 &pcfg_pull_none>; 1507 }; 1508 }; 1509 1510 i2c8 { 1511 i2c8_xfer: i2c8-xfer { 1512 rockchip,pins = 1513 <1 21 RK_FUNC_1 &pcfg_pull_none>, 1514 <1 20 RK_FUNC_1 &pcfg_pull_none>; 1515 }; 1516 }; 1517 1518 i2s0 { 1519 i2s0_8ch_bus: i2s0-8ch-bus { 1520 rockchip,pins = 1521 <3 24 RK_FUNC_1 &pcfg_pull_none>, 1522 <3 25 RK_FUNC_1 &pcfg_pull_none>, 1523 <3 26 RK_FUNC_1 &pcfg_pull_none>, 1524 <3 27 RK_FUNC_1 &pcfg_pull_none>, 1525 <3 28 RK_FUNC_1 &pcfg_pull_none>, 1526 <3 29 RK_FUNC_1 &pcfg_pull_none>, 1527 <3 30 RK_FUNC_1 &pcfg_pull_none>, 1528 <3 31 RK_FUNC_1 &pcfg_pull_none>, 1529 <4 0 RK_FUNC_1 &pcfg_pull_none>; 1530 }; 1531 }; 1532 1533 i2s1 { 1534 i2s1_2ch_bus: i2s1-2ch-bus { 1535 rockchip,pins = 1536 <4 3 RK_FUNC_1 &pcfg_pull_none>, 1537 <4 4 RK_FUNC_1 &pcfg_pull_none>, 1538 <4 5 RK_FUNC_1 &pcfg_pull_none>, 1539 <4 6 RK_FUNC_1 &pcfg_pull_none>, 1540 <4 7 RK_FUNC_1 &pcfg_pull_none>; 1541 }; 1542 }; 1543 1544 sleep { 1545 ap_pwroff: ap-pwroff { 1546 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>; 1547 }; 1548 1549 ddrio_pwroff: ddrio-pwroff { 1550 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; 1551 }; 1552 }; 1553 1554 spdif { 1555 spdif_bus: spdif-bus { 1556 rockchip,pins = 1557 <4 21 RK_FUNC_1 &pcfg_pull_none>; 1558 }; 1559 }; 1560 1561 spi0 { 1562 spi0_clk: spi0-clk { 1563 rockchip,pins = 1564 <3 6 RK_FUNC_2 &pcfg_pull_up>; 1565 }; 1566 spi0_cs0: spi0-cs0 { 1567 rockchip,pins = 1568 <3 7 RK_FUNC_2 &pcfg_pull_up>; 1569 }; 1570 spi0_cs1: spi0-cs1 { 1571 rockchip,pins = 1572 <3 8 RK_FUNC_2 &pcfg_pull_up>; 1573 }; 1574 spi0_tx: spi0-tx { 1575 rockchip,pins = 1576 <3 5 RK_FUNC_2 &pcfg_pull_up>; 1577 }; 1578 spi0_rx: spi0-rx { 1579 rockchip,pins = 1580 <3 4 RK_FUNC_2 &pcfg_pull_up>; 1581 }; 1582 }; 1583 1584 spi1 { 1585 spi1_clk: spi1-clk { 1586 rockchip,pins = 1587 <1 9 RK_FUNC_2 &pcfg_pull_up>; 1588 }; 1589 spi1_cs0: spi1-cs0 { 1590 rockchip,pins = 1591 <1 10 RK_FUNC_2 &pcfg_pull_up>; 1592 }; 1593 spi1_rx: spi1-rx { 1594 rockchip,pins = 1595 <1 7 RK_FUNC_2 &pcfg_pull_up>; 1596 }; 1597 spi1_tx: spi1-tx { 1598 rockchip,pins = 1599 <1 8 RK_FUNC_2 &pcfg_pull_up>; 1600 }; 1601 }; 1602 1603 spi2 { 1604 spi2_clk: spi2-clk { 1605 rockchip,pins = 1606 <2 11 RK_FUNC_1 &pcfg_pull_up>; 1607 }; 1608 spi2_cs0: spi2-cs0 { 1609 rockchip,pins = 1610 <2 12 RK_FUNC_1 &pcfg_pull_up>; 1611 }; 1612 spi2_rx: spi2-rx { 1613 rockchip,pins = 1614 <2 9 RK_FUNC_1 &pcfg_pull_up>; 1615 }; 1616 spi2_tx: spi2-tx { 1617 rockchip,pins = 1618 <2 10 RK_FUNC_1 &pcfg_pull_up>; 1619 }; 1620 }; 1621 1622 spi3 { 1623 spi3_clk: spi3-clk { 1624 rockchip,pins = 1625 <1 17 RK_FUNC_1 &pcfg_pull_up>; 1626 }; 1627 spi3_cs0: spi3-cs0 { 1628 rockchip,pins = 1629 <1 18 RK_FUNC_1 &pcfg_pull_up>; 1630 }; 1631 spi3_rx: spi3-rx { 1632 rockchip,pins = 1633 <1 15 RK_FUNC_1 &pcfg_pull_up>; 1634 }; 1635 spi3_tx: spi3-tx { 1636 rockchip,pins = 1637 <1 16 RK_FUNC_1 &pcfg_pull_up>; 1638 }; 1639 }; 1640 1641 spi4 { 1642 spi4_clk: spi4-clk { 1643 rockchip,pins = 1644 <3 2 RK_FUNC_2 &pcfg_pull_up>; 1645 }; 1646 spi4_cs0: spi4-cs0 { 1647 rockchip,pins = 1648 <3 3 RK_FUNC_2 &pcfg_pull_up>; 1649 }; 1650 spi4_rx: spi4-rx { 1651 rockchip,pins = 1652 <3 0 RK_FUNC_2 &pcfg_pull_up>; 1653 }; 1654 spi4_tx: spi4-tx { 1655 rockchip,pins = 1656 <3 1 RK_FUNC_2 &pcfg_pull_up>; 1657 }; 1658 }; 1659 1660 spi5 { 1661 spi5_clk: spi5-clk { 1662 rockchip,pins = 1663 <2 22 RK_FUNC_2 &pcfg_pull_up>; 1664 }; 1665 spi5_cs0: spi5-cs0 { 1666 rockchip,pins = 1667 <2 23 RK_FUNC_2 &pcfg_pull_up>; 1668 }; 1669 spi5_rx: spi5-rx { 1670 rockchip,pins = 1671 <2 20 RK_FUNC_2 &pcfg_pull_up>; 1672 }; 1673 spi5_tx: spi5-tx { 1674 rockchip,pins = 1675 <2 21 RK_FUNC_2 &pcfg_pull_up>; 1676 }; 1677 }; 1678 1679 tsadc { 1680 otp_gpio: otp-gpio { 1681 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>; 1682 }; 1683 1684 otp_out: otp-out { 1685 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>; 1686 }; 1687 }; 1688 1689 uart0 { 1690 uart0_xfer: uart0-xfer { 1691 rockchip,pins = 1692 <2 16 RK_FUNC_1 &pcfg_pull_up>, 1693 <2 17 RK_FUNC_1 &pcfg_pull_none>; 1694 }; 1695 1696 uart0_cts: uart0-cts { 1697 rockchip,pins = 1698 <2 18 RK_FUNC_1 &pcfg_pull_none>; 1699 }; 1700 1701 uart0_rts: uart0-rts { 1702 rockchip,pins = 1703 <2 19 RK_FUNC_1 &pcfg_pull_none>; 1704 }; 1705 }; 1706 1707 uart1 { 1708 uart1_xfer: uart1-xfer { 1709 rockchip,pins = 1710 <3 12 RK_FUNC_2 &pcfg_pull_up>, 1711 <3 13 RK_FUNC_2 &pcfg_pull_none>; 1712 }; 1713 }; 1714 1715 uart2a { 1716 uart2a_xfer: uart2a-xfer { 1717 rockchip,pins = 1718 <4 8 RK_FUNC_2 &pcfg_pull_up>, 1719 <4 9 RK_FUNC_2 &pcfg_pull_none>; 1720 }; 1721 }; 1722 1723 uart2b { 1724 uart2b_xfer: uart2b-xfer { 1725 rockchip,pins = 1726 <4 16 RK_FUNC_2 &pcfg_pull_up>, 1727 <4 17 RK_FUNC_2 &pcfg_pull_none>; 1728 }; 1729 }; 1730 1731 uart2c { 1732 uart2c_xfer: uart2c-xfer { 1733 rockchip,pins = 1734 <4 19 RK_FUNC_1 &pcfg_pull_up>, 1735 <4 20 RK_FUNC_1 &pcfg_pull_none>; 1736 }; 1737 }; 1738 1739 uart3 { 1740 uart3_xfer: uart3-xfer { 1741 rockchip,pins = 1742 <3 14 RK_FUNC_2 &pcfg_pull_up>, 1743 <3 15 RK_FUNC_2 &pcfg_pull_none>; 1744 }; 1745 1746 uart3_cts: uart3-cts { 1747 rockchip,pins = 1748 <3 18 RK_FUNC_2 &pcfg_pull_none>; 1749 }; 1750 1751 uart3_rts: uart3-rts { 1752 rockchip,pins = 1753 <3 19 RK_FUNC_2 &pcfg_pull_none>; 1754 }; 1755 }; 1756 1757 uart4 { 1758 uart4_xfer: uart4-xfer { 1759 rockchip,pins = 1760 <1 7 RK_FUNC_1 &pcfg_pull_up>, 1761 <1 8 RK_FUNC_1 &pcfg_pull_none>; 1762 }; 1763 }; 1764 1765 uarthdcp { 1766 uarthdcp_xfer: uarthdcp-xfer { 1767 rockchip,pins = 1768 <4 21 RK_FUNC_2 &pcfg_pull_up>, 1769 <4 22 RK_FUNC_2 &pcfg_pull_none>; 1770 }; 1771 }; 1772 1773 pwm0 { 1774 pwm0_pin: pwm0-pin { 1775 rockchip,pins = 1776 <4 18 RK_FUNC_1 &pcfg_pull_none>; 1777 }; 1778 1779 vop0_pwm_pin: vop0-pwm-pin { 1780 rockchip,pins = 1781 <4 18 RK_FUNC_2 &pcfg_pull_none>; 1782 }; 1783 }; 1784 1785 pwm1 { 1786 pwm1_pin: pwm1-pin { 1787 rockchip,pins = 1788 <4 22 RK_FUNC_1 &pcfg_pull_none>; 1789 }; 1790 1791 vop1_pwm_pin: vop1-pwm-pin { 1792 rockchip,pins = 1793 <4 18 RK_FUNC_3 &pcfg_pull_none>; 1794 }; 1795 }; 1796 1797 pwm2 { 1798 pwm2_pin: pwm2-pin { 1799 rockchip,pins = 1800 <1 19 RK_FUNC_1 &pcfg_pull_none>; 1801 }; 1802 }; 1803 1804 pwm3a { 1805 pwm3a_pin: pwm3a-pin { 1806 rockchip,pins = 1807 <0 6 RK_FUNC_1 &pcfg_pull_none>; 1808 }; 1809 }; 1810 1811 pwm3b { 1812 pwm3b_pin: pwm3b-pin { 1813 rockchip,pins = 1814 <1 14 RK_FUNC_1 &pcfg_pull_none>; 1815 }; 1816 }; 1817 1818 pcie { 1819 pcie_clkreqn: pci-clkreqn { 1820 rockchip,pins = 1821 <2 26 RK_FUNC_2 &pcfg_pull_none>; 1822 }; 1823 1824 pcie_clkreqnb: pci-clkreqnb { 1825 rockchip,pins = 1826 <4 24 RK_FUNC_1 &pcfg_pull_none>; 1827 }; 1828 }; 1829 1830 }; 1831}; 1832