1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3399-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3399-power.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "rockchip,rk3399"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &gmac; 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 i2c6 = &i2c6; 30 i2c7 = &i2c7; 31 i2c8 = &i2c8; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 cpu-map { 44 cluster0 { 45 core0 { 46 cpu = <&cpu_l0>; 47 }; 48 core1 { 49 cpu = <&cpu_l1>; 50 }; 51 core2 { 52 cpu = <&cpu_l2>; 53 }; 54 core3 { 55 cpu = <&cpu_l3>; 56 }; 57 }; 58 59 cluster1 { 60 core0 { 61 cpu = <&cpu_b0>; 62 }; 63 core1 { 64 cpu = <&cpu_b1>; 65 }; 66 }; 67 }; 68 69 cpu_l0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <0x0 0x0>; 73 enable-method = "psci"; 74 capacity-dmips-mhz = <485>; 75 clocks = <&cru ARMCLKL>; 76 #cooling-cells = <2>; /* min followed by max */ 77 dynamic-power-coefficient = <100>; 78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 79 }; 80 81 cpu_l1: cpu@1 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x0 0x1>; 85 enable-method = "psci"; 86 capacity-dmips-mhz = <485>; 87 clocks = <&cru ARMCLKL>; 88 #cooling-cells = <2>; /* min followed by max */ 89 dynamic-power-coefficient = <100>; 90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 91 }; 92 93 cpu_l2: cpu@2 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a53"; 96 reg = <0x0 0x2>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <485>; 99 clocks = <&cru ARMCLKL>; 100 #cooling-cells = <2>; /* min followed by max */ 101 dynamic-power-coefficient = <100>; 102 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 103 }; 104 105 cpu_l3: cpu@3 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53"; 108 reg = <0x0 0x3>; 109 enable-method = "psci"; 110 capacity-dmips-mhz = <485>; 111 clocks = <&cru ARMCLKL>; 112 #cooling-cells = <2>; /* min followed by max */ 113 dynamic-power-coefficient = <100>; 114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 115 }; 116 117 cpu_b0: cpu@100 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a72"; 120 reg = <0x0 0x100>; 121 enable-method = "psci"; 122 capacity-dmips-mhz = <1024>; 123 clocks = <&cru ARMCLKB>; 124 #cooling-cells = <2>; /* min followed by max */ 125 dynamic-power-coefficient = <436>; 126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 127 }; 128 129 cpu_b1: cpu@101 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a72"; 132 reg = <0x0 0x101>; 133 enable-method = "psci"; 134 capacity-dmips-mhz = <1024>; 135 clocks = <&cru ARMCLKB>; 136 #cooling-cells = <2>; /* min followed by max */ 137 dynamic-power-coefficient = <436>; 138 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 139 }; 140 141 idle-states { 142 entry-method = "psci"; 143 144 CPU_SLEEP: cpu-sleep { 145 compatible = "arm,idle-state"; 146 local-timer-stop; 147 arm,psci-suspend-param = <0x0010000>; 148 entry-latency-us = <120>; 149 exit-latency-us = <250>; 150 min-residency-us = <900>; 151 }; 152 153 CLUSTER_SLEEP: cluster-sleep { 154 compatible = "arm,idle-state"; 155 local-timer-stop; 156 arm,psci-suspend-param = <0x1010000>; 157 entry-latency-us = <400>; 158 exit-latency-us = <500>; 159 min-residency-us = <2000>; 160 }; 161 }; 162 }; 163 164 display-subsystem { 165 compatible = "rockchip,display-subsystem"; 166 ports = <&vopl_out>, <&vopb_out>; 167 }; 168 169 pmu_a53 { 170 compatible = "arm,cortex-a53-pmu"; 171 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 172 }; 173 174 pmu_a72 { 175 compatible = "arm,cortex-a72-pmu"; 176 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 177 }; 178 179 psci { 180 compatible = "arm,psci-1.0"; 181 method = "smc"; 182 }; 183 184 timer { 185 compatible = "arm,armv8-timer"; 186 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 187 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 188 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 189 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 190 arm,no-tick-in-suspend; 191 }; 192 193 xin24m: xin24m { 194 compatible = "fixed-clock"; 195 clock-frequency = <24000000>; 196 clock-output-names = "xin24m"; 197 #clock-cells = <0>; 198 }; 199 200 amba { 201 compatible = "simple-bus"; 202 #address-cells = <2>; 203 #size-cells = <2>; 204 ranges; 205 206 dmac_bus: dma-controller@ff6d0000 { 207 compatible = "arm,pl330", "arm,primecell"; 208 reg = <0x0 0xff6d0000 0x0 0x4000>; 209 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 210 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 211 #dma-cells = <1>; 212 clocks = <&cru ACLK_DMAC0_PERILP>; 213 clock-names = "apb_pclk"; 214 }; 215 216 dmac_peri: dma-controller@ff6e0000 { 217 compatible = "arm,pl330", "arm,primecell"; 218 reg = <0x0 0xff6e0000 0x0 0x4000>; 219 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 220 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 221 #dma-cells = <1>; 222 clocks = <&cru ACLK_DMAC1_PERILP>; 223 clock-names = "apb_pclk"; 224 }; 225 }; 226 227 pcie0: pcie@f8000000 { 228 compatible = "rockchip,rk3399-pcie"; 229 reg = <0x0 0xf8000000 0x0 0x2000000>, 230 <0x0 0xfd000000 0x0 0x1000000>; 231 reg-names = "axi-base", "apb-base"; 232 #address-cells = <3>; 233 #size-cells = <2>; 234 #interrupt-cells = <1>; 235 aspm-no-l0s; 236 bus-range = <0x0 0x1f>; 237 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 238 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 239 clock-names = "aclk", "aclk-perf", 240 "hclk", "pm"; 241 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 242 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 243 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 244 interrupt-names = "sys", "legacy", "client"; 245 interrupt-map-mask = <0 0 0 7>; 246 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 247 <0 0 0 2 &pcie0_intc 1>, 248 <0 0 0 3 &pcie0_intc 2>, 249 <0 0 0 4 &pcie0_intc 3>; 250 linux,pci-domain = <0>; 251 max-link-speed = <1>; 252 msi-map = <0x0 &its 0x0 0x1000>; 253 phys = <&pcie_phy 0>, <&pcie_phy 1>, 254 <&pcie_phy 2>, <&pcie_phy 3>; 255 phy-names = "pcie-phy-0", "pcie-phy-1", 256 "pcie-phy-2", "pcie-phy-3"; 257 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000 258 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; 259 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 260 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 261 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 262 <&cru SRST_A_PCIE>; 263 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 264 "pm", "pclk", "aclk"; 265 status = "disabled"; 266 267 pcie0_intc: interrupt-controller { 268 interrupt-controller; 269 #address-cells = <0>; 270 #interrupt-cells = <1>; 271 }; 272 }; 273 274 gmac: ethernet@fe300000 { 275 compatible = "rockchip,rk3399-gmac"; 276 reg = <0x0 0xfe300000 0x0 0x10000>; 277 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 278 interrupt-names = "macirq"; 279 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 280 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 281 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 282 <&cru PCLK_GMAC>; 283 clock-names = "stmmaceth", "mac_clk_rx", 284 "mac_clk_tx", "clk_mac_ref", 285 "clk_mac_refout", "aclk_mac", 286 "pclk_mac"; 287 power-domains = <&power RK3399_PD_GMAC>; 288 resets = <&cru SRST_A_GMAC>; 289 reset-names = "stmmaceth"; 290 rockchip,grf = <&grf>; 291 status = "disabled"; 292 }; 293 294 sdio0: dwmmc@fe310000 { 295 compatible = "rockchip,rk3399-dw-mshc", 296 "rockchip,rk3288-dw-mshc"; 297 reg = <0x0 0xfe310000 0x0 0x4000>; 298 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 299 max-frequency = <150000000>; 300 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 301 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 302 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 303 fifo-depth = <0x100>; 304 power-domains = <&power RK3399_PD_SDIOAUDIO>; 305 resets = <&cru SRST_SDIO0>; 306 reset-names = "reset"; 307 status = "disabled"; 308 }; 309 310 sdmmc: dwmmc@fe320000 { 311 compatible = "rockchip,rk3399-dw-mshc", 312 "rockchip,rk3288-dw-mshc"; 313 reg = <0x0 0xfe320000 0x0 0x4000>; 314 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 315 max-frequency = <150000000>; 316 assigned-clocks = <&cru HCLK_SD>; 317 assigned-clock-rates = <200000000>; 318 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 319 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 320 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 321 fifo-depth = <0x100>; 322 power-domains = <&power RK3399_PD_SD>; 323 resets = <&cru SRST_SDMMC>; 324 reset-names = "reset"; 325 status = "disabled"; 326 }; 327 328 sdhci: sdhci@fe330000 { 329 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 330 reg = <0x0 0xfe330000 0x0 0x10000>; 331 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 332 arasan,soc-ctl-syscon = <&grf>; 333 assigned-clocks = <&cru SCLK_EMMC>; 334 assigned-clock-rates = <200000000>; 335 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 336 clock-names = "clk_xin", "clk_ahb"; 337 clock-output-names = "emmc_cardclock"; 338 #clock-cells = <0>; 339 phys = <&emmc_phy>; 340 phy-names = "phy_arasan"; 341 power-domains = <&power RK3399_PD_EMMC>; 342 disable-cqe-dcmd; 343 status = "disabled"; 344 }; 345 346 usb_host0_ehci: usb@fe380000 { 347 compatible = "generic-ehci"; 348 reg = <0x0 0xfe380000 0x0 0x20000>; 349 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 350 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 351 <&u2phy0>; 352 clock-names = "usbhost", "arbiter", 353 "utmi"; 354 phys = <&u2phy0_host>; 355 phy-names = "usb"; 356 status = "disabled"; 357 }; 358 359 usb_host0_ohci: usb@fe3a0000 { 360 compatible = "generic-ohci"; 361 reg = <0x0 0xfe3a0000 0x0 0x20000>; 362 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 363 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 364 <&u2phy0>; 365 clock-names = "usbhost", "arbiter", 366 "utmi"; 367 phys = <&u2phy0_host>; 368 phy-names = "usb"; 369 status = "disabled"; 370 }; 371 372 usb_host1_ehci: usb@fe3c0000 { 373 compatible = "generic-ehci"; 374 reg = <0x0 0xfe3c0000 0x0 0x20000>; 375 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 376 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 377 <&u2phy1>; 378 clock-names = "usbhost", "arbiter", 379 "utmi"; 380 phys = <&u2phy1_host>; 381 phy-names = "usb"; 382 status = "disabled"; 383 }; 384 385 usb_host1_ohci: usb@fe3e0000 { 386 compatible = "generic-ohci"; 387 reg = <0x0 0xfe3e0000 0x0 0x20000>; 388 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 389 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 390 <&u2phy1>; 391 clock-names = "usbhost", "arbiter", 392 "utmi"; 393 phys = <&u2phy1_host>; 394 phy-names = "usb"; 395 status = "disabled"; 396 }; 397 398 usbdrd3_0: usb@fe800000 { 399 compatible = "rockchip,rk3399-dwc3"; 400 #address-cells = <2>; 401 #size-cells = <2>; 402 ranges; 403 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 404 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 405 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 406 clock-names = "ref_clk", "suspend_clk", 407 "bus_clk", "aclk_usb3_rksoc_axi_perf", 408 "aclk_usb3", "grf_clk"; 409 resets = <&cru SRST_A_USB3_OTG0>; 410 reset-names = "usb3-otg"; 411 status = "disabled"; 412 413 usbdrd_dwc3_0: dwc3 { 414 compatible = "snps,dwc3"; 415 reg = <0x0 0xfe800000 0x0 0x100000>; 416 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 417 dr_mode = "otg"; 418 phys = <&u2phy0_otg>, <&tcphy0_usb3>; 419 phy-names = "usb2-phy", "usb3-phy"; 420 phy_type = "utmi_wide"; 421 snps,dis_enblslpm_quirk; 422 snps,dis-u2-freeclk-exists-quirk; 423 snps,dis_u2_susphy_quirk; 424 snps,dis-del-phy-power-chg-quirk; 425 snps,dis-tx-ipgap-linecheck-quirk; 426 power-domains = <&power RK3399_PD_USB3>; 427 status = "disabled"; 428 }; 429 }; 430 431 usbdrd3_1: usb@fe900000 { 432 compatible = "rockchip,rk3399-dwc3"; 433 #address-cells = <2>; 434 #size-cells = <2>; 435 ranges; 436 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, 437 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 438 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 439 clock-names = "ref_clk", "suspend_clk", 440 "bus_clk", "aclk_usb3_rksoc_axi_perf", 441 "aclk_usb3", "grf_clk"; 442 resets = <&cru SRST_A_USB3_OTG1>; 443 reset-names = "usb3-otg"; 444 status = "disabled"; 445 446 usbdrd_dwc3_1: dwc3 { 447 compatible = "snps,dwc3"; 448 reg = <0x0 0xfe900000 0x0 0x100000>; 449 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 450 dr_mode = "otg"; 451 phys = <&u2phy1_otg>, <&tcphy1_usb3>; 452 phy-names = "usb2-phy", "usb3-phy"; 453 phy_type = "utmi_wide"; 454 snps,dis_enblslpm_quirk; 455 snps,dis-u2-freeclk-exists-quirk; 456 snps,dis_u2_susphy_quirk; 457 snps,dis-del-phy-power-chg-quirk; 458 snps,dis-tx-ipgap-linecheck-quirk; 459 power-domains = <&power RK3399_PD_USB3>; 460 status = "disabled"; 461 }; 462 }; 463 464 cdn_dp: dp@fec00000 { 465 compatible = "rockchip,rk3399-cdn-dp"; 466 reg = <0x0 0xfec00000 0x0 0x100000>; 467 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 468 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>; 469 assigned-clock-rates = <100000000>, <200000000>; 470 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, 471 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; 472 clock-names = "core-clk", "pclk", "spdif", "grf"; 473 phys = <&tcphy0_dp>, <&tcphy1_dp>; 474 power-domains = <&power RK3399_PD_HDCP>; 475 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, 476 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; 477 reset-names = "spdif", "dptx", "apb", "core"; 478 rockchip,grf = <&grf>; 479 #sound-dai-cells = <1>; 480 status = "disabled"; 481 482 ports { 483 dp_in: port { 484 #address-cells = <1>; 485 #size-cells = <0>; 486 487 dp_in_vopb: endpoint@0 { 488 reg = <0>; 489 remote-endpoint = <&vopb_out_dp>; 490 }; 491 492 dp_in_vopl: endpoint@1 { 493 reg = <1>; 494 remote-endpoint = <&vopl_out_dp>; 495 }; 496 }; 497 }; 498 }; 499 500 gic: interrupt-controller@fee00000 { 501 compatible = "arm,gic-v3"; 502 #interrupt-cells = <4>; 503 #address-cells = <2>; 504 #size-cells = <2>; 505 ranges; 506 interrupt-controller; 507 508 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 509 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 510 <0x0 0xfff00000 0 0x10000>, /* GICC */ 511 <0x0 0xfff10000 0 0x10000>, /* GICH */ 512 <0x0 0xfff20000 0 0x10000>; /* GICV */ 513 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 514 its: interrupt-controller@fee20000 { 515 compatible = "arm,gic-v3-its"; 516 msi-controller; 517 reg = <0x0 0xfee20000 0x0 0x20000>; 518 }; 519 520 ppi-partitions { 521 ppi_cluster0: interrupt-partition-0 { 522 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 523 }; 524 525 ppi_cluster1: interrupt-partition-1 { 526 affinity = <&cpu_b0 &cpu_b1>; 527 }; 528 }; 529 }; 530 531 saradc: saradc@ff100000 { 532 compatible = "rockchip,rk3399-saradc"; 533 reg = <0x0 0xff100000 0x0 0x100>; 534 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 535 #io-channel-cells = <1>; 536 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 537 clock-names = "saradc", "apb_pclk"; 538 resets = <&cru SRST_P_SARADC>; 539 reset-names = "saradc-apb"; 540 status = "disabled"; 541 }; 542 543 i2c1: i2c@ff110000 { 544 compatible = "rockchip,rk3399-i2c"; 545 reg = <0x0 0xff110000 0x0 0x1000>; 546 assigned-clocks = <&cru SCLK_I2C1>; 547 assigned-clock-rates = <200000000>; 548 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 549 clock-names = "i2c", "pclk"; 550 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 551 pinctrl-names = "default"; 552 pinctrl-0 = <&i2c1_xfer>; 553 #address-cells = <1>; 554 #size-cells = <0>; 555 status = "disabled"; 556 }; 557 558 i2c2: i2c@ff120000 { 559 compatible = "rockchip,rk3399-i2c"; 560 reg = <0x0 0xff120000 0x0 0x1000>; 561 assigned-clocks = <&cru SCLK_I2C2>; 562 assigned-clock-rates = <200000000>; 563 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 564 clock-names = "i2c", "pclk"; 565 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 566 pinctrl-names = "default"; 567 pinctrl-0 = <&i2c2_xfer>; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 status = "disabled"; 571 }; 572 573 i2c3: i2c@ff130000 { 574 compatible = "rockchip,rk3399-i2c"; 575 reg = <0x0 0xff130000 0x0 0x1000>; 576 assigned-clocks = <&cru SCLK_I2C3>; 577 assigned-clock-rates = <200000000>; 578 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 579 clock-names = "i2c", "pclk"; 580 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 581 pinctrl-names = "default"; 582 pinctrl-0 = <&i2c3_xfer>; 583 #address-cells = <1>; 584 #size-cells = <0>; 585 status = "disabled"; 586 }; 587 588 i2c5: i2c@ff140000 { 589 compatible = "rockchip,rk3399-i2c"; 590 reg = <0x0 0xff140000 0x0 0x1000>; 591 assigned-clocks = <&cru SCLK_I2C5>; 592 assigned-clock-rates = <200000000>; 593 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 594 clock-names = "i2c", "pclk"; 595 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 596 pinctrl-names = "default"; 597 pinctrl-0 = <&i2c5_xfer>; 598 #address-cells = <1>; 599 #size-cells = <0>; 600 status = "disabled"; 601 }; 602 603 i2c6: i2c@ff150000 { 604 compatible = "rockchip,rk3399-i2c"; 605 reg = <0x0 0xff150000 0x0 0x1000>; 606 assigned-clocks = <&cru SCLK_I2C6>; 607 assigned-clock-rates = <200000000>; 608 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 609 clock-names = "i2c", "pclk"; 610 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 611 pinctrl-names = "default"; 612 pinctrl-0 = <&i2c6_xfer>; 613 #address-cells = <1>; 614 #size-cells = <0>; 615 status = "disabled"; 616 }; 617 618 i2c7: i2c@ff160000 { 619 compatible = "rockchip,rk3399-i2c"; 620 reg = <0x0 0xff160000 0x0 0x1000>; 621 assigned-clocks = <&cru SCLK_I2C7>; 622 assigned-clock-rates = <200000000>; 623 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 624 clock-names = "i2c", "pclk"; 625 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 626 pinctrl-names = "default"; 627 pinctrl-0 = <&i2c7_xfer>; 628 #address-cells = <1>; 629 #size-cells = <0>; 630 status = "disabled"; 631 }; 632 633 uart0: serial@ff180000 { 634 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 635 reg = <0x0 0xff180000 0x0 0x100>; 636 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 637 clock-names = "baudclk", "apb_pclk"; 638 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 639 reg-shift = <2>; 640 reg-io-width = <4>; 641 pinctrl-names = "default"; 642 pinctrl-0 = <&uart0_xfer>; 643 status = "disabled"; 644 }; 645 646 uart1: serial@ff190000 { 647 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 648 reg = <0x0 0xff190000 0x0 0x100>; 649 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 650 clock-names = "baudclk", "apb_pclk"; 651 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 652 reg-shift = <2>; 653 reg-io-width = <4>; 654 pinctrl-names = "default"; 655 pinctrl-0 = <&uart1_xfer>; 656 status = "disabled"; 657 }; 658 659 uart2: serial@ff1a0000 { 660 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 661 reg = <0x0 0xff1a0000 0x0 0x100>; 662 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 663 clock-names = "baudclk", "apb_pclk"; 664 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 665 reg-shift = <2>; 666 reg-io-width = <4>; 667 pinctrl-names = "default"; 668 pinctrl-0 = <&uart2c_xfer>; 669 status = "disabled"; 670 }; 671 672 uart3: serial@ff1b0000 { 673 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 674 reg = <0x0 0xff1b0000 0x0 0x100>; 675 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 676 clock-names = "baudclk", "apb_pclk"; 677 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 678 reg-shift = <2>; 679 reg-io-width = <4>; 680 pinctrl-names = "default"; 681 pinctrl-0 = <&uart3_xfer>; 682 status = "disabled"; 683 }; 684 685 spi0: spi@ff1c0000 { 686 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 687 reg = <0x0 0xff1c0000 0x0 0x1000>; 688 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 689 clock-names = "spiclk", "apb_pclk"; 690 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 691 dmas = <&dmac_peri 10>, <&dmac_peri 11>; 692 dma-names = "tx", "rx"; 693 pinctrl-names = "default"; 694 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 695 #address-cells = <1>; 696 #size-cells = <0>; 697 status = "disabled"; 698 }; 699 700 spi1: spi@ff1d0000 { 701 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 702 reg = <0x0 0xff1d0000 0x0 0x1000>; 703 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 704 clock-names = "spiclk", "apb_pclk"; 705 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 706 dmas = <&dmac_peri 12>, <&dmac_peri 13>; 707 dma-names = "tx", "rx"; 708 pinctrl-names = "default"; 709 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 710 #address-cells = <1>; 711 #size-cells = <0>; 712 status = "disabled"; 713 }; 714 715 spi2: spi@ff1e0000 { 716 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 717 reg = <0x0 0xff1e0000 0x0 0x1000>; 718 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 719 clock-names = "spiclk", "apb_pclk"; 720 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 721 dmas = <&dmac_peri 14>, <&dmac_peri 15>; 722 dma-names = "tx", "rx"; 723 pinctrl-names = "default"; 724 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 725 #address-cells = <1>; 726 #size-cells = <0>; 727 status = "disabled"; 728 }; 729 730 spi4: spi@ff1f0000 { 731 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 732 reg = <0x0 0xff1f0000 0x0 0x1000>; 733 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 734 clock-names = "spiclk", "apb_pclk"; 735 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 736 dmas = <&dmac_peri 18>, <&dmac_peri 19>; 737 dma-names = "tx", "rx"; 738 pinctrl-names = "default"; 739 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 740 #address-cells = <1>; 741 #size-cells = <0>; 742 status = "disabled"; 743 }; 744 745 spi5: spi@ff200000 { 746 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 747 reg = <0x0 0xff200000 0x0 0x1000>; 748 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 749 clock-names = "spiclk", "apb_pclk"; 750 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 751 dmas = <&dmac_bus 8>, <&dmac_bus 9>; 752 dma-names = "tx", "rx"; 753 pinctrl-names = "default"; 754 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 755 power-domains = <&power RK3399_PD_SDIOAUDIO>; 756 #address-cells = <1>; 757 #size-cells = <0>; 758 status = "disabled"; 759 }; 760 761 thermal_zones: thermal-zones { 762 cpu_thermal: cpu { 763 polling-delay-passive = <100>; 764 polling-delay = <1000>; 765 766 thermal-sensors = <&tsadc 0>; 767 768 trips { 769 cpu_alert0: cpu_alert0 { 770 temperature = <70000>; 771 hysteresis = <2000>; 772 type = "passive"; 773 }; 774 cpu_alert1: cpu_alert1 { 775 temperature = <75000>; 776 hysteresis = <2000>; 777 type = "passive"; 778 }; 779 cpu_crit: cpu_crit { 780 temperature = <95000>; 781 hysteresis = <2000>; 782 type = "critical"; 783 }; 784 }; 785 786 cooling-maps { 787 map0 { 788 trip = <&cpu_alert0>; 789 cooling-device = 790 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 791 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 792 }; 793 map1 { 794 trip = <&cpu_alert1>; 795 cooling-device = 796 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 797 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 798 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 799 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 800 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 801 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 802 }; 803 }; 804 }; 805 806 gpu_thermal: gpu { 807 polling-delay-passive = <100>; 808 polling-delay = <1000>; 809 810 thermal-sensors = <&tsadc 1>; 811 812 trips { 813 gpu_alert0: gpu_alert0 { 814 temperature = <75000>; 815 hysteresis = <2000>; 816 type = "passive"; 817 }; 818 gpu_crit: gpu_crit { 819 temperature = <95000>; 820 hysteresis = <2000>; 821 type = "critical"; 822 }; 823 }; 824 825 cooling-maps { 826 map0 { 827 trip = <&gpu_alert0>; 828 cooling-device = 829 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 830 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 831 }; 832 }; 833 }; 834 }; 835 836 tsadc: tsadc@ff260000 { 837 compatible = "rockchip,rk3399-tsadc"; 838 reg = <0x0 0xff260000 0x0 0x100>; 839 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 840 assigned-clocks = <&cru SCLK_TSADC>; 841 assigned-clock-rates = <750000>; 842 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 843 clock-names = "tsadc", "apb_pclk"; 844 resets = <&cru SRST_TSADC>; 845 reset-names = "tsadc-apb"; 846 rockchip,grf = <&grf>; 847 rockchip,hw-tshut-temp = <95000>; 848 pinctrl-names = "init", "default", "sleep"; 849 pinctrl-0 = <&otp_gpio>; 850 pinctrl-1 = <&otp_out>; 851 pinctrl-2 = <&otp_gpio>; 852 #thermal-sensor-cells = <1>; 853 status = "disabled"; 854 }; 855 856 qos_emmc: qos@ffa58000 { 857 compatible = "syscon"; 858 reg = <0x0 0xffa58000 0x0 0x20>; 859 }; 860 861 qos_gmac: qos@ffa5c000 { 862 compatible = "syscon"; 863 reg = <0x0 0xffa5c000 0x0 0x20>; 864 }; 865 866 qos_pcie: qos@ffa60080 { 867 compatible = "syscon"; 868 reg = <0x0 0xffa60080 0x0 0x20>; 869 }; 870 871 qos_usb_host0: qos@ffa60100 { 872 compatible = "syscon"; 873 reg = <0x0 0xffa60100 0x0 0x20>; 874 }; 875 876 qos_usb_host1: qos@ffa60180 { 877 compatible = "syscon"; 878 reg = <0x0 0xffa60180 0x0 0x20>; 879 }; 880 881 qos_usb_otg0: qos@ffa70000 { 882 compatible = "syscon"; 883 reg = <0x0 0xffa70000 0x0 0x20>; 884 }; 885 886 qos_usb_otg1: qos@ffa70080 { 887 compatible = "syscon"; 888 reg = <0x0 0xffa70080 0x0 0x20>; 889 }; 890 891 qos_sd: qos@ffa74000 { 892 compatible = "syscon"; 893 reg = <0x0 0xffa74000 0x0 0x20>; 894 }; 895 896 qos_sdioaudio: qos@ffa76000 { 897 compatible = "syscon"; 898 reg = <0x0 0xffa76000 0x0 0x20>; 899 }; 900 901 qos_hdcp: qos@ffa90000 { 902 compatible = "syscon"; 903 reg = <0x0 0xffa90000 0x0 0x20>; 904 }; 905 906 qos_iep: qos@ffa98000 { 907 compatible = "syscon"; 908 reg = <0x0 0xffa98000 0x0 0x20>; 909 }; 910 911 qos_isp0_m0: qos@ffaa0000 { 912 compatible = "syscon"; 913 reg = <0x0 0xffaa0000 0x0 0x20>; 914 }; 915 916 qos_isp0_m1: qos@ffaa0080 { 917 compatible = "syscon"; 918 reg = <0x0 0xffaa0080 0x0 0x20>; 919 }; 920 921 qos_isp1_m0: qos@ffaa8000 { 922 compatible = "syscon"; 923 reg = <0x0 0xffaa8000 0x0 0x20>; 924 }; 925 926 qos_isp1_m1: qos@ffaa8080 { 927 compatible = "syscon"; 928 reg = <0x0 0xffaa8080 0x0 0x20>; 929 }; 930 931 qos_rga_r: qos@ffab0000 { 932 compatible = "syscon"; 933 reg = <0x0 0xffab0000 0x0 0x20>; 934 }; 935 936 qos_rga_w: qos@ffab0080 { 937 compatible = "syscon"; 938 reg = <0x0 0xffab0080 0x0 0x20>; 939 }; 940 941 qos_video_m0: qos@ffab8000 { 942 compatible = "syscon"; 943 reg = <0x0 0xffab8000 0x0 0x20>; 944 }; 945 946 qos_video_m1_r: qos@ffac0000 { 947 compatible = "syscon"; 948 reg = <0x0 0xffac0000 0x0 0x20>; 949 }; 950 951 qos_video_m1_w: qos@ffac0080 { 952 compatible = "syscon"; 953 reg = <0x0 0xffac0080 0x0 0x20>; 954 }; 955 956 qos_vop_big_r: qos@ffac8000 { 957 compatible = "syscon"; 958 reg = <0x0 0xffac8000 0x0 0x20>; 959 }; 960 961 qos_vop_big_w: qos@ffac8080 { 962 compatible = "syscon"; 963 reg = <0x0 0xffac8080 0x0 0x20>; 964 }; 965 966 qos_vop_little: qos@ffad0000 { 967 compatible = "syscon"; 968 reg = <0x0 0xffad0000 0x0 0x20>; 969 }; 970 971 qos_perihp: qos@ffad8080 { 972 compatible = "syscon"; 973 reg = <0x0 0xffad8080 0x0 0x20>; 974 }; 975 976 qos_gpu: qos@ffae0000 { 977 compatible = "syscon"; 978 reg = <0x0 0xffae0000 0x0 0x20>; 979 }; 980 981 pmu: power-management@ff310000 { 982 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 983 reg = <0x0 0xff310000 0x0 0x1000>; 984 985 /* 986 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 987 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 988 * Some of the power domains are grouped together for every 989 * voltage domain. 990 * The detail contents as below. 991 */ 992 power: power-controller { 993 compatible = "rockchip,rk3399-power-controller"; 994 #power-domain-cells = <1>; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 998 /* These power domains are grouped by VD_CENTER */ 999 pd_iep@RK3399_PD_IEP { 1000 reg = <RK3399_PD_IEP>; 1001 clocks = <&cru ACLK_IEP>, 1002 <&cru HCLK_IEP>; 1003 pm_qos = <&qos_iep>; 1004 }; 1005 pd_rga@RK3399_PD_RGA { 1006 reg = <RK3399_PD_RGA>; 1007 clocks = <&cru ACLK_RGA>, 1008 <&cru HCLK_RGA>; 1009 pm_qos = <&qos_rga_r>, 1010 <&qos_rga_w>; 1011 }; 1012 pd_vcodec@RK3399_PD_VCODEC { 1013 reg = <RK3399_PD_VCODEC>; 1014 clocks = <&cru ACLK_VCODEC>, 1015 <&cru HCLK_VCODEC>; 1016 pm_qos = <&qos_video_m0>; 1017 }; 1018 pd_vdu@RK3399_PD_VDU { 1019 reg = <RK3399_PD_VDU>; 1020 clocks = <&cru ACLK_VDU>, 1021 <&cru HCLK_VDU>; 1022 pm_qos = <&qos_video_m1_r>, 1023 <&qos_video_m1_w>; 1024 }; 1025 1026 /* These power domains are grouped by VD_GPU */ 1027 pd_gpu@RK3399_PD_GPU { 1028 reg = <RK3399_PD_GPU>; 1029 clocks = <&cru ACLK_GPU>; 1030 pm_qos = <&qos_gpu>; 1031 }; 1032 1033 /* These power domains are grouped by VD_LOGIC */ 1034 pd_edp@RK3399_PD_EDP { 1035 reg = <RK3399_PD_EDP>; 1036 clocks = <&cru PCLK_EDP_CTRL>; 1037 }; 1038 pd_emmc@RK3399_PD_EMMC { 1039 reg = <RK3399_PD_EMMC>; 1040 clocks = <&cru ACLK_EMMC>; 1041 pm_qos = <&qos_emmc>; 1042 }; 1043 pd_gmac@RK3399_PD_GMAC { 1044 reg = <RK3399_PD_GMAC>; 1045 clocks = <&cru ACLK_GMAC>, 1046 <&cru PCLK_GMAC>; 1047 pm_qos = <&qos_gmac>; 1048 }; 1049 pd_sd@RK3399_PD_SD { 1050 reg = <RK3399_PD_SD>; 1051 clocks = <&cru HCLK_SDMMC>, 1052 <&cru SCLK_SDMMC>; 1053 pm_qos = <&qos_sd>; 1054 }; 1055 pd_sdioaudio@RK3399_PD_SDIOAUDIO { 1056 reg = <RK3399_PD_SDIOAUDIO>; 1057 clocks = <&cru HCLK_SDIO>; 1058 pm_qos = <&qos_sdioaudio>; 1059 }; 1060 pd_usb3@RK3399_PD_USB3 { 1061 reg = <RK3399_PD_USB3>; 1062 clocks = <&cru ACLK_USB3>; 1063 pm_qos = <&qos_usb_otg0>, 1064 <&qos_usb_otg1>; 1065 }; 1066 pd_vio@RK3399_PD_VIO { 1067 reg = <RK3399_PD_VIO>; 1068 #address-cells = <1>; 1069 #size-cells = <0>; 1070 1071 pd_hdcp@RK3399_PD_HDCP { 1072 reg = <RK3399_PD_HDCP>; 1073 clocks = <&cru ACLK_HDCP>, 1074 <&cru HCLK_HDCP>, 1075 <&cru PCLK_HDCP>; 1076 pm_qos = <&qos_hdcp>; 1077 }; 1078 pd_isp0@RK3399_PD_ISP0 { 1079 reg = <RK3399_PD_ISP0>; 1080 clocks = <&cru ACLK_ISP0>, 1081 <&cru HCLK_ISP0>; 1082 pm_qos = <&qos_isp0_m0>, 1083 <&qos_isp0_m1>; 1084 }; 1085 pd_isp1@RK3399_PD_ISP1 { 1086 reg = <RK3399_PD_ISP1>; 1087 clocks = <&cru ACLK_ISP1>, 1088 <&cru HCLK_ISP1>; 1089 pm_qos = <&qos_isp1_m0>, 1090 <&qos_isp1_m1>; 1091 }; 1092 pd_tcpc0@RK3399_PD_TCPC0 { 1093 reg = <RK3399_PD_TCPD0>; 1094 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1095 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1096 }; 1097 pd_tcpc1@RK3399_PD_TCPC1 { 1098 reg = <RK3399_PD_TCPD1>; 1099 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1100 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1101 }; 1102 pd_vo@RK3399_PD_VO { 1103 reg = <RK3399_PD_VO>; 1104 #address-cells = <1>; 1105 #size-cells = <0>; 1106 1107 pd_vopb@RK3399_PD_VOPB { 1108 reg = <RK3399_PD_VOPB>; 1109 clocks = <&cru ACLK_VOP0>, 1110 <&cru HCLK_VOP0>; 1111 pm_qos = <&qos_vop_big_r>, 1112 <&qos_vop_big_w>; 1113 }; 1114 pd_vopl@RK3399_PD_VOPL { 1115 reg = <RK3399_PD_VOPL>; 1116 clocks = <&cru ACLK_VOP1>, 1117 <&cru HCLK_VOP1>; 1118 pm_qos = <&qos_vop_little>; 1119 }; 1120 }; 1121 }; 1122 }; 1123 }; 1124 1125 pmugrf: syscon@ff320000 { 1126 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1127 reg = <0x0 0xff320000 0x0 0x1000>; 1128 #address-cells = <1>; 1129 #size-cells = <1>; 1130 1131 pmu_io_domains: io-domains { 1132 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1133 status = "disabled"; 1134 }; 1135 }; 1136 1137 spi3: spi@ff350000 { 1138 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1139 reg = <0x0 0xff350000 0x0 0x1000>; 1140 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1141 clock-names = "spiclk", "apb_pclk"; 1142 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1143 pinctrl-names = "default"; 1144 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1145 #address-cells = <1>; 1146 #size-cells = <0>; 1147 status = "disabled"; 1148 }; 1149 1150 uart4: serial@ff370000 { 1151 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1152 reg = <0x0 0xff370000 0x0 0x100>; 1153 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1154 clock-names = "baudclk", "apb_pclk"; 1155 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1156 reg-shift = <2>; 1157 reg-io-width = <4>; 1158 pinctrl-names = "default"; 1159 pinctrl-0 = <&uart4_xfer>; 1160 status = "disabled"; 1161 }; 1162 1163 i2c0: i2c@ff3c0000 { 1164 compatible = "rockchip,rk3399-i2c"; 1165 reg = <0x0 0xff3c0000 0x0 0x1000>; 1166 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1167 assigned-clock-rates = <200000000>; 1168 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1169 clock-names = "i2c", "pclk"; 1170 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1171 pinctrl-names = "default"; 1172 pinctrl-0 = <&i2c0_xfer>; 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 status = "disabled"; 1176 }; 1177 1178 i2c4: i2c@ff3d0000 { 1179 compatible = "rockchip,rk3399-i2c"; 1180 reg = <0x0 0xff3d0000 0x0 0x1000>; 1181 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1182 assigned-clock-rates = <200000000>; 1183 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1184 clock-names = "i2c", "pclk"; 1185 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1186 pinctrl-names = "default"; 1187 pinctrl-0 = <&i2c4_xfer>; 1188 #address-cells = <1>; 1189 #size-cells = <0>; 1190 status = "disabled"; 1191 }; 1192 1193 i2c8: i2c@ff3e0000 { 1194 compatible = "rockchip,rk3399-i2c"; 1195 reg = <0x0 0xff3e0000 0x0 0x1000>; 1196 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1197 assigned-clock-rates = <200000000>; 1198 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1199 clock-names = "i2c", "pclk"; 1200 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1201 pinctrl-names = "default"; 1202 pinctrl-0 = <&i2c8_xfer>; 1203 #address-cells = <1>; 1204 #size-cells = <0>; 1205 status = "disabled"; 1206 }; 1207 1208 pwm0: pwm@ff420000 { 1209 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1210 reg = <0x0 0xff420000 0x0 0x10>; 1211 #pwm-cells = <3>; 1212 pinctrl-names = "default"; 1213 pinctrl-0 = <&pwm0_pin>; 1214 clocks = <&pmucru PCLK_RKPWM_PMU>; 1215 clock-names = "pwm"; 1216 status = "disabled"; 1217 }; 1218 1219 pwm1: pwm@ff420010 { 1220 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1221 reg = <0x0 0xff420010 0x0 0x10>; 1222 #pwm-cells = <3>; 1223 pinctrl-names = "default"; 1224 pinctrl-0 = <&pwm1_pin>; 1225 clocks = <&pmucru PCLK_RKPWM_PMU>; 1226 clock-names = "pwm"; 1227 status = "disabled"; 1228 }; 1229 1230 pwm2: pwm@ff420020 { 1231 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1232 reg = <0x0 0xff420020 0x0 0x10>; 1233 #pwm-cells = <3>; 1234 pinctrl-names = "default"; 1235 pinctrl-0 = <&pwm2_pin>; 1236 clocks = <&pmucru PCLK_RKPWM_PMU>; 1237 clock-names = "pwm"; 1238 status = "disabled"; 1239 }; 1240 1241 pwm3: pwm@ff420030 { 1242 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1243 reg = <0x0 0xff420030 0x0 0x10>; 1244 #pwm-cells = <3>; 1245 pinctrl-names = "default"; 1246 pinctrl-0 = <&pwm3a_pin>; 1247 clocks = <&pmucru PCLK_RKPWM_PMU>; 1248 clock-names = "pwm"; 1249 status = "disabled"; 1250 }; 1251 1252 vpu: video-codec@ff650000 { 1253 compatible = "rockchip,rk3399-vpu"; 1254 reg = <0x0 0xff650000 0x0 0x800>; 1255 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 1256 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 1257 interrupt-names = "vepu", "vdpu"; 1258 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1259 clock-names = "aclk", "hclk"; 1260 iommus = <&vpu_mmu>; 1261 power-domains = <&power RK3399_PD_VCODEC>; 1262 }; 1263 1264 vpu_mmu: iommu@ff650800 { 1265 compatible = "rockchip,iommu"; 1266 reg = <0x0 0xff650800 0x0 0x40>; 1267 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 1268 interrupt-names = "vpu_mmu"; 1269 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1270 clock-names = "aclk", "iface"; 1271 #iommu-cells = <0>; 1272 power-domains = <&power RK3399_PD_VCODEC>; 1273 }; 1274 1275 vdec_mmu: iommu@ff660480 { 1276 compatible = "rockchip,iommu"; 1277 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; 1278 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1279 interrupt-names = "vdec_mmu"; 1280 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; 1281 clock-names = "aclk", "iface"; 1282 #iommu-cells = <0>; 1283 status = "disabled"; 1284 }; 1285 1286 iep_mmu: iommu@ff670800 { 1287 compatible = "rockchip,iommu"; 1288 reg = <0x0 0xff670800 0x0 0x40>; 1289 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>; 1290 interrupt-names = "iep_mmu"; 1291 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 1292 clock-names = "aclk", "iface"; 1293 #iommu-cells = <0>; 1294 status = "disabled"; 1295 }; 1296 1297 rga: rga@ff680000 { 1298 compatible = "rockchip,rk3399-rga"; 1299 reg = <0x0 0xff680000 0x0 0x10000>; 1300 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>; 1301 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; 1302 clock-names = "aclk", "hclk", "sclk"; 1303 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 1304 reset-names = "core", "axi", "ahb"; 1305 power-domains = <&power RK3399_PD_RGA>; 1306 }; 1307 1308 efuse0: efuse@ff690000 { 1309 compatible = "rockchip,rk3399-efuse"; 1310 reg = <0x0 0xff690000 0x0 0x80>; 1311 #address-cells = <1>; 1312 #size-cells = <1>; 1313 clocks = <&cru PCLK_EFUSE1024NS>; 1314 clock-names = "pclk_efuse"; 1315 1316 /* Data cells */ 1317 cpu_id: cpu-id@7 { 1318 reg = <0x07 0x10>; 1319 }; 1320 cpub_leakage: cpu-leakage@17 { 1321 reg = <0x17 0x1>; 1322 }; 1323 gpu_leakage: gpu-leakage@18 { 1324 reg = <0x18 0x1>; 1325 }; 1326 center_leakage: center-leakage@19 { 1327 reg = <0x19 0x1>; 1328 }; 1329 cpul_leakage: cpu-leakage@1a { 1330 reg = <0x1a 0x1>; 1331 }; 1332 logic_leakage: logic-leakage@1b { 1333 reg = <0x1b 0x1>; 1334 }; 1335 wafer_info: wafer-info@1c { 1336 reg = <0x1c 0x1>; 1337 }; 1338 }; 1339 1340 pmucru: pmu-clock-controller@ff750000 { 1341 compatible = "rockchip,rk3399-pmucru"; 1342 reg = <0x0 0xff750000 0x0 0x1000>; 1343 rockchip,grf = <&pmugrf>; 1344 #clock-cells = <1>; 1345 #reset-cells = <1>; 1346 assigned-clocks = <&pmucru PLL_PPLL>; 1347 assigned-clock-rates = <676000000>; 1348 }; 1349 1350 cru: clock-controller@ff760000 { 1351 compatible = "rockchip,rk3399-cru"; 1352 reg = <0x0 0xff760000 0x0 0x1000>; 1353 rockchip,grf = <&grf>; 1354 #clock-cells = <1>; 1355 #reset-cells = <1>; 1356 assigned-clocks = 1357 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1358 <&cru PLL_NPLL>, 1359 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1360 <&cru PCLK_PERIHP>, 1361 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1362 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1363 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 1364 <&cru ACLK_VIO>, <&cru ACLK_HDCP>, 1365 <&cru ACLK_GIC_PRE>, 1366 <&cru PCLK_DDR>; 1367 assigned-clock-rates = 1368 <594000000>, <800000000>, 1369 <1000000000>, 1370 <150000000>, <75000000>, 1371 <37500000>, 1372 <100000000>, <100000000>, 1373 <50000000>, <600000000>, 1374 <100000000>, <50000000>, 1375 <400000000>, <400000000>, 1376 <200000000>, 1377 <200000000>; 1378 }; 1379 1380 grf: syscon@ff770000 { 1381 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1382 reg = <0x0 0xff770000 0x0 0x10000>; 1383 #address-cells = <1>; 1384 #size-cells = <1>; 1385 1386 io_domains: io-domains { 1387 compatible = "rockchip,rk3399-io-voltage-domain"; 1388 status = "disabled"; 1389 }; 1390 1391 u2phy0: usb2-phy@e450 { 1392 compatible = "rockchip,rk3399-usb2phy"; 1393 reg = <0xe450 0x10>; 1394 clocks = <&cru SCLK_USB2PHY0_REF>; 1395 clock-names = "phyclk"; 1396 #clock-cells = <0>; 1397 clock-output-names = "clk_usbphy0_480m"; 1398 status = "disabled"; 1399 1400 u2phy0_host: host-port { 1401 #phy-cells = <0>; 1402 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1403 interrupt-names = "linestate"; 1404 status = "disabled"; 1405 }; 1406 1407 u2phy0_otg: otg-port { 1408 #phy-cells = <0>; 1409 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1410 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1411 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1412 interrupt-names = "otg-bvalid", "otg-id", 1413 "linestate"; 1414 status = "disabled"; 1415 }; 1416 }; 1417 1418 u2phy1: usb2-phy@e460 { 1419 compatible = "rockchip,rk3399-usb2phy"; 1420 reg = <0xe460 0x10>; 1421 clocks = <&cru SCLK_USB2PHY1_REF>; 1422 clock-names = "phyclk"; 1423 #clock-cells = <0>; 1424 clock-output-names = "clk_usbphy1_480m"; 1425 status = "disabled"; 1426 1427 u2phy1_host: host-port { 1428 #phy-cells = <0>; 1429 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1430 interrupt-names = "linestate"; 1431 status = "disabled"; 1432 }; 1433 1434 u2phy1_otg: otg-port { 1435 #phy-cells = <0>; 1436 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1437 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1438 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1439 interrupt-names = "otg-bvalid", "otg-id", 1440 "linestate"; 1441 status = "disabled"; 1442 }; 1443 }; 1444 1445 emmc_phy: phy@f780 { 1446 compatible = "rockchip,rk3399-emmc-phy"; 1447 reg = <0xf780 0x24>; 1448 clocks = <&sdhci>; 1449 clock-names = "emmcclk"; 1450 #phy-cells = <0>; 1451 status = "disabled"; 1452 }; 1453 1454 pcie_phy: pcie-phy { 1455 compatible = "rockchip,rk3399-pcie-phy"; 1456 clocks = <&cru SCLK_PCIEPHY_REF>; 1457 clock-names = "refclk"; 1458 #phy-cells = <1>; 1459 resets = <&cru SRST_PCIEPHY>; 1460 drive-impedance-ohm = <50>; 1461 reset-names = "phy"; 1462 status = "disabled"; 1463 }; 1464 }; 1465 1466 tcphy0: phy@ff7c0000 { 1467 compatible = "rockchip,rk3399-typec-phy"; 1468 reg = <0x0 0xff7c0000 0x0 0x40000>; 1469 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1470 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1471 clock-names = "tcpdcore", "tcpdphy-ref"; 1472 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1473 assigned-clock-rates = <50000000>; 1474 power-domains = <&power RK3399_PD_TCPD0>; 1475 resets = <&cru SRST_UPHY0>, 1476 <&cru SRST_UPHY0_PIPE_L00>, 1477 <&cru SRST_P_UPHY0_TCPHY>; 1478 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1479 rockchip,grf = <&grf>; 1480 status = "disabled"; 1481 1482 tcphy0_dp: dp-port { 1483 #phy-cells = <0>; 1484 }; 1485 1486 tcphy0_usb3: usb3-port { 1487 #phy-cells = <0>; 1488 }; 1489 }; 1490 1491 tcphy1: phy@ff800000 { 1492 compatible = "rockchip,rk3399-typec-phy"; 1493 reg = <0x0 0xff800000 0x0 0x40000>; 1494 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1495 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1496 clock-names = "tcpdcore", "tcpdphy-ref"; 1497 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1498 assigned-clock-rates = <50000000>; 1499 power-domains = <&power RK3399_PD_TCPD1>; 1500 resets = <&cru SRST_UPHY1>, 1501 <&cru SRST_UPHY1_PIPE_L00>, 1502 <&cru SRST_P_UPHY1_TCPHY>; 1503 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1504 rockchip,grf = <&grf>; 1505 status = "disabled"; 1506 1507 tcphy1_dp: dp-port { 1508 #phy-cells = <0>; 1509 }; 1510 1511 tcphy1_usb3: usb3-port { 1512 #phy-cells = <0>; 1513 }; 1514 }; 1515 1516 watchdog@ff848000 { 1517 compatible = "snps,dw-wdt"; 1518 reg = <0x0 0xff848000 0x0 0x100>; 1519 clocks = <&cru PCLK_WDT>; 1520 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1521 }; 1522 1523 rktimer: rktimer@ff850000 { 1524 compatible = "rockchip,rk3399-timer"; 1525 reg = <0x0 0xff850000 0x0 0x1000>; 1526 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1527 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1528 clock-names = "pclk", "timer"; 1529 }; 1530 1531 spdif: spdif@ff870000 { 1532 compatible = "rockchip,rk3399-spdif"; 1533 reg = <0x0 0xff870000 0x0 0x1000>; 1534 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1535 dmas = <&dmac_bus 7>; 1536 dma-names = "tx"; 1537 clock-names = "mclk", "hclk"; 1538 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1539 pinctrl-names = "default"; 1540 pinctrl-0 = <&spdif_bus>; 1541 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1542 #sound-dai-cells = <0>; 1543 status = "disabled"; 1544 }; 1545 1546 i2s0: i2s@ff880000 { 1547 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1548 reg = <0x0 0xff880000 0x0 0x1000>; 1549 rockchip,grf = <&grf>; 1550 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1551 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1552 dma-names = "tx", "rx"; 1553 clock-names = "i2s_clk", "i2s_hclk"; 1554 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1555 pinctrl-names = "default"; 1556 pinctrl-0 = <&i2s0_8ch_bus>; 1557 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1558 #sound-dai-cells = <0>; 1559 status = "disabled"; 1560 }; 1561 1562 i2s1: i2s@ff890000 { 1563 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1564 reg = <0x0 0xff890000 0x0 0x1000>; 1565 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1566 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1567 dma-names = "tx", "rx"; 1568 clock-names = "i2s_clk", "i2s_hclk"; 1569 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1570 pinctrl-names = "default"; 1571 pinctrl-0 = <&i2s1_2ch_bus>; 1572 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1573 #sound-dai-cells = <0>; 1574 status = "disabled"; 1575 }; 1576 1577 i2s2: i2s@ff8a0000 { 1578 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1579 reg = <0x0 0xff8a0000 0x0 0x1000>; 1580 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1581 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1582 dma-names = "tx", "rx"; 1583 clock-names = "i2s_clk", "i2s_hclk"; 1584 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1585 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1586 #sound-dai-cells = <0>; 1587 status = "disabled"; 1588 }; 1589 1590 vopl: vop@ff8f0000 { 1591 compatible = "rockchip,rk3399-vop-lit"; 1592 reg = <0x0 0xff8f0000 0x0 0x3efc>; 1593 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1594 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1595 assigned-clock-rates = <400000000>, <100000000>; 1596 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1597 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1598 iommus = <&vopl_mmu>; 1599 power-domains = <&power RK3399_PD_VOPL>; 1600 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1601 reset-names = "axi", "ahb", "dclk"; 1602 status = "disabled"; 1603 1604 vopl_out: port { 1605 #address-cells = <1>; 1606 #size-cells = <0>; 1607 1608 vopl_out_mipi: endpoint@0 { 1609 reg = <0>; 1610 remote-endpoint = <&mipi_in_vopl>; 1611 }; 1612 1613 vopl_out_edp: endpoint@1 { 1614 reg = <1>; 1615 remote-endpoint = <&edp_in_vopl>; 1616 }; 1617 1618 vopl_out_hdmi: endpoint@2 { 1619 reg = <2>; 1620 remote-endpoint = <&hdmi_in_vopl>; 1621 }; 1622 1623 vopl_out_mipi1: endpoint@3 { 1624 reg = <3>; 1625 remote-endpoint = <&mipi1_in_vopl>; 1626 }; 1627 1628 vopl_out_dp: endpoint@4 { 1629 reg = <4>; 1630 remote-endpoint = <&dp_in_vopl>; 1631 }; 1632 }; 1633 }; 1634 1635 vopl_mmu: iommu@ff8f3f00 { 1636 compatible = "rockchip,iommu"; 1637 reg = <0x0 0xff8f3f00 0x0 0x100>; 1638 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1639 interrupt-names = "vopl_mmu"; 1640 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1641 clock-names = "aclk", "iface"; 1642 power-domains = <&power RK3399_PD_VOPL>; 1643 #iommu-cells = <0>; 1644 status = "disabled"; 1645 }; 1646 1647 vopb: vop@ff900000 { 1648 compatible = "rockchip,rk3399-vop-big"; 1649 reg = <0x0 0xff900000 0x0 0x3efc>; 1650 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1651 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1652 assigned-clock-rates = <400000000>, <100000000>; 1653 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1654 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1655 iommus = <&vopb_mmu>; 1656 power-domains = <&power RK3399_PD_VOPB>; 1657 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1658 reset-names = "axi", "ahb", "dclk"; 1659 status = "disabled"; 1660 1661 vopb_out: port { 1662 #address-cells = <1>; 1663 #size-cells = <0>; 1664 1665 vopb_out_edp: endpoint@0 { 1666 reg = <0>; 1667 remote-endpoint = <&edp_in_vopb>; 1668 }; 1669 1670 vopb_out_mipi: endpoint@1 { 1671 reg = <1>; 1672 remote-endpoint = <&mipi_in_vopb>; 1673 }; 1674 1675 vopb_out_hdmi: endpoint@2 { 1676 reg = <2>; 1677 remote-endpoint = <&hdmi_in_vopb>; 1678 }; 1679 1680 vopb_out_mipi1: endpoint@3 { 1681 reg = <3>; 1682 remote-endpoint = <&mipi1_in_vopb>; 1683 }; 1684 1685 vopb_out_dp: endpoint@4 { 1686 reg = <4>; 1687 remote-endpoint = <&dp_in_vopb>; 1688 }; 1689 }; 1690 }; 1691 1692 vopb_mmu: iommu@ff903f00 { 1693 compatible = "rockchip,iommu"; 1694 reg = <0x0 0xff903f00 0x0 0x100>; 1695 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1696 interrupt-names = "vopb_mmu"; 1697 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1698 clock-names = "aclk", "iface"; 1699 power-domains = <&power RK3399_PD_VOPB>; 1700 #iommu-cells = <0>; 1701 status = "disabled"; 1702 }; 1703 1704 isp0_mmu: iommu@ff914000 { 1705 compatible = "rockchip,iommu"; 1706 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1707 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1708 interrupt-names = "isp0_mmu"; 1709 clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>; 1710 clock-names = "aclk", "iface"; 1711 #iommu-cells = <0>; 1712 rockchip,disable-mmu-reset; 1713 status = "disabled"; 1714 }; 1715 1716 isp1_mmu: iommu@ff924000 { 1717 compatible = "rockchip,iommu"; 1718 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; 1719 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 1720 interrupt-names = "isp1_mmu"; 1721 clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>; 1722 clock-names = "aclk", "iface"; 1723 #iommu-cells = <0>; 1724 rockchip,disable-mmu-reset; 1725 status = "disabled"; 1726 }; 1727 1728 hdmi_sound: hdmi-sound { 1729 compatible = "simple-audio-card"; 1730 simple-audio-card,format = "i2s"; 1731 simple-audio-card,mclk-fs = <256>; 1732 simple-audio-card,name = "hdmi-sound"; 1733 status = "disabled"; 1734 1735 simple-audio-card,cpu { 1736 sound-dai = <&i2s2>; 1737 }; 1738 simple-audio-card,codec { 1739 sound-dai = <&hdmi>; 1740 }; 1741 }; 1742 1743 hdmi: hdmi@ff940000 { 1744 compatible = "rockchip,rk3399-dw-hdmi"; 1745 reg = <0x0 0xff940000 0x0 0x20000>; 1746 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 1747 clocks = <&cru PCLK_HDMI_CTRL>, 1748 <&cru SCLK_HDMI_SFR>, 1749 <&cru PLL_VPLL>, 1750 <&cru PCLK_VIO_GRF>, 1751 <&cru SCLK_HDMI_CEC>; 1752 clock-names = "iahb", "isfr", "vpll", "grf", "cec"; 1753 power-domains = <&power RK3399_PD_HDCP>; 1754 reg-io-width = <4>; 1755 rockchip,grf = <&grf>; 1756 #sound-dai-cells = <0>; 1757 status = "disabled"; 1758 1759 ports { 1760 hdmi_in: port { 1761 #address-cells = <1>; 1762 #size-cells = <0>; 1763 1764 hdmi_in_vopb: endpoint@0 { 1765 reg = <0>; 1766 remote-endpoint = <&vopb_out_hdmi>; 1767 }; 1768 hdmi_in_vopl: endpoint@1 { 1769 reg = <1>; 1770 remote-endpoint = <&vopl_out_hdmi>; 1771 }; 1772 }; 1773 }; 1774 }; 1775 1776 mipi_dsi: mipi@ff960000 { 1777 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1778 reg = <0x0 0xff960000 0x0 0x8000>; 1779 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 1780 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, 1781 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; 1782 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1783 power-domains = <&power RK3399_PD_VIO>; 1784 resets = <&cru SRST_P_MIPI_DSI0>; 1785 reset-names = "apb"; 1786 rockchip,grf = <&grf>; 1787 #address-cells = <1>; 1788 #size-cells = <0>; 1789 status = "disabled"; 1790 1791 ports { 1792 #address-cells = <1>; 1793 #size-cells = <0>; 1794 1795 mipi_in: port@0 { 1796 reg = <0>; 1797 #address-cells = <1>; 1798 #size-cells = <0>; 1799 1800 mipi_in_vopb: endpoint@0 { 1801 reg = <0>; 1802 remote-endpoint = <&vopb_out_mipi>; 1803 }; 1804 mipi_in_vopl: endpoint@1 { 1805 reg = <1>; 1806 remote-endpoint = <&vopl_out_mipi>; 1807 }; 1808 }; 1809 }; 1810 }; 1811 1812 mipi_dsi1: mipi@ff968000 { 1813 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1814 reg = <0x0 0xff968000 0x0 0x8000>; 1815 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>; 1816 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, 1817 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; 1818 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1819 power-domains = <&power RK3399_PD_VIO>; 1820 resets = <&cru SRST_P_MIPI_DSI1>; 1821 reset-names = "apb"; 1822 rockchip,grf = <&grf>; 1823 #address-cells = <1>; 1824 #size-cells = <0>; 1825 status = "disabled"; 1826 1827 ports { 1828 #address-cells = <1>; 1829 #size-cells = <0>; 1830 1831 mipi1_in: port@0 { 1832 reg = <0>; 1833 #address-cells = <1>; 1834 #size-cells = <0>; 1835 1836 mipi1_in_vopb: endpoint@0 { 1837 reg = <0>; 1838 remote-endpoint = <&vopb_out_mipi1>; 1839 }; 1840 1841 mipi1_in_vopl: endpoint@1 { 1842 reg = <1>; 1843 remote-endpoint = <&vopl_out_mipi1>; 1844 }; 1845 }; 1846 }; 1847 }; 1848 1849 edp: edp@ff970000 { 1850 compatible = "rockchip,rk3399-edp"; 1851 reg = <0x0 0xff970000 0x0 0x8000>; 1852 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 1853 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; 1854 clock-names = "dp", "pclk", "grf"; 1855 pinctrl-names = "default"; 1856 pinctrl-0 = <&edp_hpd>; 1857 power-domains = <&power RK3399_PD_EDP>; 1858 resets = <&cru SRST_P_EDP_CTRL>; 1859 reset-names = "dp"; 1860 rockchip,grf = <&grf>; 1861 status = "disabled"; 1862 1863 ports { 1864 #address-cells = <1>; 1865 #size-cells = <0>; 1866 edp_in: port@0 { 1867 reg = <0>; 1868 #address-cells = <1>; 1869 #size-cells = <0>; 1870 1871 edp_in_vopb: endpoint@0 { 1872 reg = <0>; 1873 remote-endpoint = <&vopb_out_edp>; 1874 }; 1875 1876 edp_in_vopl: endpoint@1 { 1877 reg = <1>; 1878 remote-endpoint = <&vopl_out_edp>; 1879 }; 1880 }; 1881 }; 1882 }; 1883 1884 gpu: gpu@ff9a0000 { 1885 compatible = "rockchip,rk3399-mali", "arm,mali-t860"; 1886 reg = <0x0 0xff9a0000 0x0 0x10000>; 1887 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>, 1888 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, 1889 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>; 1890 interrupt-names = "gpu", "job", "mmu"; 1891 clocks = <&cru ACLK_GPU>; 1892 power-domains = <&power RK3399_PD_GPU>; 1893 status = "disabled"; 1894 }; 1895 1896 pinctrl: pinctrl { 1897 compatible = "rockchip,rk3399-pinctrl"; 1898 rockchip,grf = <&grf>; 1899 rockchip,pmu = <&pmugrf>; 1900 #address-cells = <2>; 1901 #size-cells = <2>; 1902 ranges; 1903 1904 gpio0: gpio0@ff720000 { 1905 compatible = "rockchip,gpio-bank"; 1906 reg = <0x0 0xff720000 0x0 0x100>; 1907 clocks = <&pmucru PCLK_GPIO0_PMU>; 1908 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 1909 1910 gpio-controller; 1911 #gpio-cells = <0x2>; 1912 1913 interrupt-controller; 1914 #interrupt-cells = <0x2>; 1915 }; 1916 1917 gpio1: gpio1@ff730000 { 1918 compatible = "rockchip,gpio-bank"; 1919 reg = <0x0 0xff730000 0x0 0x100>; 1920 clocks = <&pmucru PCLK_GPIO1_PMU>; 1921 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 1922 1923 gpio-controller; 1924 #gpio-cells = <0x2>; 1925 1926 interrupt-controller; 1927 #interrupt-cells = <0x2>; 1928 }; 1929 1930 gpio2: gpio2@ff780000 { 1931 compatible = "rockchip,gpio-bank"; 1932 reg = <0x0 0xff780000 0x0 0x100>; 1933 clocks = <&cru PCLK_GPIO2>; 1934 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 1935 1936 gpio-controller; 1937 #gpio-cells = <0x2>; 1938 1939 interrupt-controller; 1940 #interrupt-cells = <0x2>; 1941 }; 1942 1943 gpio3: gpio3@ff788000 { 1944 compatible = "rockchip,gpio-bank"; 1945 reg = <0x0 0xff788000 0x0 0x100>; 1946 clocks = <&cru PCLK_GPIO3>; 1947 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 1948 1949 gpio-controller; 1950 #gpio-cells = <0x2>; 1951 1952 interrupt-controller; 1953 #interrupt-cells = <0x2>; 1954 }; 1955 1956 gpio4: gpio4@ff790000 { 1957 compatible = "rockchip,gpio-bank"; 1958 reg = <0x0 0xff790000 0x0 0x100>; 1959 clocks = <&cru PCLK_GPIO4>; 1960 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 1961 1962 gpio-controller; 1963 #gpio-cells = <0x2>; 1964 1965 interrupt-controller; 1966 #interrupt-cells = <0x2>; 1967 }; 1968 1969 pcfg_pull_up: pcfg-pull-up { 1970 bias-pull-up; 1971 }; 1972 1973 pcfg_pull_down: pcfg-pull-down { 1974 bias-pull-down; 1975 }; 1976 1977 pcfg_pull_none: pcfg-pull-none { 1978 bias-disable; 1979 }; 1980 1981 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1982 bias-disable; 1983 drive-strength = <12>; 1984 }; 1985 1986 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 1987 bias-disable; 1988 drive-strength = <13>; 1989 }; 1990 1991 pcfg_pull_none_18ma: pcfg-pull-none-18ma { 1992 bias-disable; 1993 drive-strength = <18>; 1994 }; 1995 1996 pcfg_pull_none_20ma: pcfg-pull-none-20ma { 1997 bias-disable; 1998 drive-strength = <20>; 1999 }; 2000 2001 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 2002 bias-pull-up; 2003 drive-strength = <2>; 2004 }; 2005 2006 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 2007 bias-pull-up; 2008 drive-strength = <8>; 2009 }; 2010 2011 pcfg_pull_up_18ma: pcfg-pull-up-18ma { 2012 bias-pull-up; 2013 drive-strength = <18>; 2014 }; 2015 2016 pcfg_pull_up_20ma: pcfg-pull-up-20ma { 2017 bias-pull-up; 2018 drive-strength = <20>; 2019 }; 2020 2021 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 2022 bias-pull-down; 2023 drive-strength = <4>; 2024 }; 2025 2026 pcfg_pull_down_8ma: pcfg-pull-down-8ma { 2027 bias-pull-down; 2028 drive-strength = <8>; 2029 }; 2030 2031 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 2032 bias-pull-down; 2033 drive-strength = <12>; 2034 }; 2035 2036 pcfg_pull_down_18ma: pcfg-pull-down-18ma { 2037 bias-pull-down; 2038 drive-strength = <18>; 2039 }; 2040 2041 pcfg_pull_down_20ma: pcfg-pull-down-20ma { 2042 bias-pull-down; 2043 drive-strength = <20>; 2044 }; 2045 2046 pcfg_output_high: pcfg-output-high { 2047 output-high; 2048 }; 2049 2050 pcfg_output_low: pcfg-output-low { 2051 output-low; 2052 }; 2053 2054 clock { 2055 clk_32k: clk-32k { 2056 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; 2057 }; 2058 }; 2059 2060 edp { 2061 edp_hpd: edp-hpd { 2062 rockchip,pins = 2063 <4 RK_PC7 2 &pcfg_pull_none>; 2064 }; 2065 }; 2066 2067 gmac { 2068 rgmii_pins: rgmii-pins { 2069 rockchip,pins = 2070 /* mac_txclk */ 2071 <3 RK_PC1 1 &pcfg_pull_none_13ma>, 2072 /* mac_rxclk */ 2073 <3 RK_PB6 1 &pcfg_pull_none>, 2074 /* mac_mdio */ 2075 <3 RK_PB5 1 &pcfg_pull_none>, 2076 /* mac_txen */ 2077 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2078 /* mac_clk */ 2079 <3 RK_PB3 1 &pcfg_pull_none>, 2080 /* mac_rxdv */ 2081 <3 RK_PB1 1 &pcfg_pull_none>, 2082 /* mac_mdc */ 2083 <3 RK_PB0 1 &pcfg_pull_none>, 2084 /* mac_rxd1 */ 2085 <3 RK_PA7 1 &pcfg_pull_none>, 2086 /* mac_rxd0 */ 2087 <3 RK_PA6 1 &pcfg_pull_none>, 2088 /* mac_txd1 */ 2089 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2090 /* mac_txd0 */ 2091 <3 RK_PA4 1 &pcfg_pull_none_13ma>, 2092 /* mac_rxd3 */ 2093 <3 RK_PA3 1 &pcfg_pull_none>, 2094 /* mac_rxd2 */ 2095 <3 RK_PA2 1 &pcfg_pull_none>, 2096 /* mac_txd3 */ 2097 <3 RK_PA1 1 &pcfg_pull_none_13ma>, 2098 /* mac_txd2 */ 2099 <3 RK_PA0 1 &pcfg_pull_none_13ma>; 2100 }; 2101 2102 rmii_pins: rmii-pins { 2103 rockchip,pins = 2104 /* mac_mdio */ 2105 <3 RK_PB5 1 &pcfg_pull_none>, 2106 /* mac_txen */ 2107 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2108 /* mac_clk */ 2109 <3 RK_PB3 1 &pcfg_pull_none>, 2110 /* mac_rxer */ 2111 <3 RK_PB2 1 &pcfg_pull_none>, 2112 /* mac_rxdv */ 2113 <3 RK_PB1 1 &pcfg_pull_none>, 2114 /* mac_mdc */ 2115 <3 RK_PB0 1 &pcfg_pull_none>, 2116 /* mac_rxd1 */ 2117 <3 RK_PA7 1 &pcfg_pull_none>, 2118 /* mac_rxd0 */ 2119 <3 RK_PA6 1 &pcfg_pull_none>, 2120 /* mac_txd1 */ 2121 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2122 /* mac_txd0 */ 2123 <3 RK_PA4 1 &pcfg_pull_none_13ma>; 2124 }; 2125 }; 2126 2127 i2c0 { 2128 i2c0_xfer: i2c0-xfer { 2129 rockchip,pins = 2130 <1 RK_PB7 2 &pcfg_pull_none>, 2131 <1 RK_PC0 2 &pcfg_pull_none>; 2132 }; 2133 }; 2134 2135 i2c1 { 2136 i2c1_xfer: i2c1-xfer { 2137 rockchip,pins = 2138 <4 RK_PA2 1 &pcfg_pull_none>, 2139 <4 RK_PA1 1 &pcfg_pull_none>; 2140 }; 2141 }; 2142 2143 i2c2 { 2144 i2c2_xfer: i2c2-xfer { 2145 rockchip,pins = 2146 <2 RK_PA1 2 &pcfg_pull_none_12ma>, 2147 <2 RK_PA0 2 &pcfg_pull_none_12ma>; 2148 }; 2149 }; 2150 2151 i2c3 { 2152 i2c3_xfer: i2c3-xfer { 2153 rockchip,pins = 2154 <4 RK_PC1 1 &pcfg_pull_none>, 2155 <4 RK_PC0 1 &pcfg_pull_none>; 2156 }; 2157 }; 2158 2159 i2c4 { 2160 i2c4_xfer: i2c4-xfer { 2161 rockchip,pins = 2162 <1 RK_PB4 1 &pcfg_pull_none>, 2163 <1 RK_PB3 1 &pcfg_pull_none>; 2164 }; 2165 }; 2166 2167 i2c5 { 2168 i2c5_xfer: i2c5-xfer { 2169 rockchip,pins = 2170 <3 RK_PB3 2 &pcfg_pull_none>, 2171 <3 RK_PB2 2 &pcfg_pull_none>; 2172 }; 2173 }; 2174 2175 i2c6 { 2176 i2c6_xfer: i2c6-xfer { 2177 rockchip,pins = 2178 <2 RK_PB2 2 &pcfg_pull_none>, 2179 <2 RK_PB1 2 &pcfg_pull_none>; 2180 }; 2181 }; 2182 2183 i2c7 { 2184 i2c7_xfer: i2c7-xfer { 2185 rockchip,pins = 2186 <2 RK_PB0 2 &pcfg_pull_none>, 2187 <2 RK_PA7 2 &pcfg_pull_none>; 2188 }; 2189 }; 2190 2191 i2c8 { 2192 i2c8_xfer: i2c8-xfer { 2193 rockchip,pins = 2194 <1 RK_PC5 1 &pcfg_pull_none>, 2195 <1 RK_PC4 1 &pcfg_pull_none>; 2196 }; 2197 }; 2198 2199 i2s0 { 2200 i2s0_2ch_bus: i2s0-2ch-bus { 2201 rockchip,pins = 2202 <3 RK_PD0 1 &pcfg_pull_none>, 2203 <3 RK_PD1 1 &pcfg_pull_none>, 2204 <3 RK_PD2 1 &pcfg_pull_none>, 2205 <3 RK_PD3 1 &pcfg_pull_none>, 2206 <3 RK_PD7 1 &pcfg_pull_none>, 2207 <4 RK_PA0 1 &pcfg_pull_none>; 2208 }; 2209 2210 i2s0_8ch_bus: i2s0-8ch-bus { 2211 rockchip,pins = 2212 <3 RK_PD0 1 &pcfg_pull_none>, 2213 <3 RK_PD1 1 &pcfg_pull_none>, 2214 <3 RK_PD2 1 &pcfg_pull_none>, 2215 <3 RK_PD3 1 &pcfg_pull_none>, 2216 <3 RK_PD4 1 &pcfg_pull_none>, 2217 <3 RK_PD5 1 &pcfg_pull_none>, 2218 <3 RK_PD6 1 &pcfg_pull_none>, 2219 <3 RK_PD7 1 &pcfg_pull_none>, 2220 <4 RK_PA0 1 &pcfg_pull_none>; 2221 }; 2222 }; 2223 2224 i2s1 { 2225 i2s1_2ch_bus: i2s1-2ch-bus { 2226 rockchip,pins = 2227 <4 RK_PA3 1 &pcfg_pull_none>, 2228 <4 RK_PA4 1 &pcfg_pull_none>, 2229 <4 RK_PA5 1 &pcfg_pull_none>, 2230 <4 RK_PA6 1 &pcfg_pull_none>, 2231 <4 RK_PA7 1 &pcfg_pull_none>; 2232 }; 2233 }; 2234 2235 sdio0 { 2236 sdio0_bus1: sdio0-bus1 { 2237 rockchip,pins = 2238 <2 RK_PC4 1 &pcfg_pull_up>; 2239 }; 2240 2241 sdio0_bus4: sdio0-bus4 { 2242 rockchip,pins = 2243 <2 RK_PC4 1 &pcfg_pull_up>, 2244 <2 RK_PC5 1 &pcfg_pull_up>, 2245 <2 RK_PC6 1 &pcfg_pull_up>, 2246 <2 RK_PC7 1 &pcfg_pull_up>; 2247 }; 2248 2249 sdio0_cmd: sdio0-cmd { 2250 rockchip,pins = 2251 <2 RK_PD0 1 &pcfg_pull_up>; 2252 }; 2253 2254 sdio0_clk: sdio0-clk { 2255 rockchip,pins = 2256 <2 RK_PD1 1 &pcfg_pull_none>; 2257 }; 2258 2259 sdio0_cd: sdio0-cd { 2260 rockchip,pins = 2261 <2 RK_PD2 1 &pcfg_pull_up>; 2262 }; 2263 2264 sdio0_pwr: sdio0-pwr { 2265 rockchip,pins = 2266 <2 RK_PD3 1 &pcfg_pull_up>; 2267 }; 2268 2269 sdio0_bkpwr: sdio0-bkpwr { 2270 rockchip,pins = 2271 <2 RK_PD4 1 &pcfg_pull_up>; 2272 }; 2273 2274 sdio0_wp: sdio0-wp { 2275 rockchip,pins = 2276 <0 RK_PA3 1 &pcfg_pull_up>; 2277 }; 2278 2279 sdio0_int: sdio0-int { 2280 rockchip,pins = 2281 <0 RK_PA4 1 &pcfg_pull_up>; 2282 }; 2283 }; 2284 2285 sdmmc { 2286 sdmmc_bus1: sdmmc-bus1 { 2287 rockchip,pins = 2288 <4 RK_PB0 1 &pcfg_pull_up>; 2289 }; 2290 2291 sdmmc_bus4: sdmmc-bus4 { 2292 rockchip,pins = 2293 <4 RK_PB0 1 &pcfg_pull_up>, 2294 <4 RK_PB1 1 &pcfg_pull_up>, 2295 <4 RK_PB2 1 &pcfg_pull_up>, 2296 <4 RK_PB3 1 &pcfg_pull_up>; 2297 }; 2298 2299 sdmmc_clk: sdmmc-clk { 2300 rockchip,pins = 2301 <4 RK_PB4 1 &pcfg_pull_none>; 2302 }; 2303 2304 sdmmc_cmd: sdmmc-cmd { 2305 rockchip,pins = 2306 <4 RK_PB5 1 &pcfg_pull_up>; 2307 }; 2308 2309 sdmmc_cd: sdmmc-cd { 2310 rockchip,pins = 2311 <0 RK_PA7 1 &pcfg_pull_up>; 2312 }; 2313 2314 sdmmc_wp: sdmmc-wp { 2315 rockchip,pins = 2316 <0 RK_PB0 1 &pcfg_pull_up>; 2317 }; 2318 }; 2319 2320 sleep { 2321 ap_pwroff: ap-pwroff { 2322 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>; 2323 }; 2324 2325 ddrio_pwroff: ddrio-pwroff { 2326 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; 2327 }; 2328 }; 2329 2330 spdif { 2331 spdif_bus: spdif-bus { 2332 rockchip,pins = 2333 <4 RK_PC5 1 &pcfg_pull_none>; 2334 }; 2335 2336 spdif_bus_1: spdif-bus-1 { 2337 rockchip,pins = 2338 <3 RK_PC0 3 &pcfg_pull_none>; 2339 }; 2340 }; 2341 2342 spi0 { 2343 spi0_clk: spi0-clk { 2344 rockchip,pins = 2345 <3 RK_PA6 2 &pcfg_pull_up>; 2346 }; 2347 spi0_cs0: spi0-cs0 { 2348 rockchip,pins = 2349 <3 RK_PA7 2 &pcfg_pull_up>; 2350 }; 2351 spi0_cs1: spi0-cs1 { 2352 rockchip,pins = 2353 <3 RK_PB0 2 &pcfg_pull_up>; 2354 }; 2355 spi0_tx: spi0-tx { 2356 rockchip,pins = 2357 <3 RK_PA5 2 &pcfg_pull_up>; 2358 }; 2359 spi0_rx: spi0-rx { 2360 rockchip,pins = 2361 <3 RK_PA4 2 &pcfg_pull_up>; 2362 }; 2363 }; 2364 2365 spi1 { 2366 spi1_clk: spi1-clk { 2367 rockchip,pins = 2368 <1 RK_PB1 2 &pcfg_pull_up>; 2369 }; 2370 spi1_cs0: spi1-cs0 { 2371 rockchip,pins = 2372 <1 RK_PB2 2 &pcfg_pull_up>; 2373 }; 2374 spi1_rx: spi1-rx { 2375 rockchip,pins = 2376 <1 RK_PA7 2 &pcfg_pull_up>; 2377 }; 2378 spi1_tx: spi1-tx { 2379 rockchip,pins = 2380 <1 RK_PB0 2 &pcfg_pull_up>; 2381 }; 2382 }; 2383 2384 spi2 { 2385 spi2_clk: spi2-clk { 2386 rockchip,pins = 2387 <2 RK_PB3 1 &pcfg_pull_up>; 2388 }; 2389 spi2_cs0: spi2-cs0 { 2390 rockchip,pins = 2391 <2 RK_PB4 1 &pcfg_pull_up>; 2392 }; 2393 spi2_rx: spi2-rx { 2394 rockchip,pins = 2395 <2 RK_PB1 1 &pcfg_pull_up>; 2396 }; 2397 spi2_tx: spi2-tx { 2398 rockchip,pins = 2399 <2 RK_PB2 1 &pcfg_pull_up>; 2400 }; 2401 }; 2402 2403 spi3 { 2404 spi3_clk: spi3-clk { 2405 rockchip,pins = 2406 <1 RK_PC1 1 &pcfg_pull_up>; 2407 }; 2408 spi3_cs0: spi3-cs0 { 2409 rockchip,pins = 2410 <1 RK_PC2 1 &pcfg_pull_up>; 2411 }; 2412 spi3_rx: spi3-rx { 2413 rockchip,pins = 2414 <1 RK_PB7 1 &pcfg_pull_up>; 2415 }; 2416 spi3_tx: spi3-tx { 2417 rockchip,pins = 2418 <1 RK_PC0 1 &pcfg_pull_up>; 2419 }; 2420 }; 2421 2422 spi4 { 2423 spi4_clk: spi4-clk { 2424 rockchip,pins = 2425 <3 RK_PA2 2 &pcfg_pull_up>; 2426 }; 2427 spi4_cs0: spi4-cs0 { 2428 rockchip,pins = 2429 <3 RK_PA3 2 &pcfg_pull_up>; 2430 }; 2431 spi4_rx: spi4-rx { 2432 rockchip,pins = 2433 <3 RK_PA0 2 &pcfg_pull_up>; 2434 }; 2435 spi4_tx: spi4-tx { 2436 rockchip,pins = 2437 <3 RK_PA1 2 &pcfg_pull_up>; 2438 }; 2439 }; 2440 2441 spi5 { 2442 spi5_clk: spi5-clk { 2443 rockchip,pins = 2444 <2 RK_PC6 2 &pcfg_pull_up>; 2445 }; 2446 spi5_cs0: spi5-cs0 { 2447 rockchip,pins = 2448 <2 RK_PC7 2 &pcfg_pull_up>; 2449 }; 2450 spi5_rx: spi5-rx { 2451 rockchip,pins = 2452 <2 RK_PC4 2 &pcfg_pull_up>; 2453 }; 2454 spi5_tx: spi5-tx { 2455 rockchip,pins = 2456 <2 RK_PC5 2 &pcfg_pull_up>; 2457 }; 2458 }; 2459 2460 testclk { 2461 test_clkout0: test-clkout0 { 2462 rockchip,pins = 2463 <0 RK_PA0 1 &pcfg_pull_none>; 2464 }; 2465 2466 test_clkout1: test-clkout1 { 2467 rockchip,pins = 2468 <2 RK_PD1 2 &pcfg_pull_none>; 2469 }; 2470 2471 test_clkout2: test-clkout2 { 2472 rockchip,pins = 2473 <0 RK_PB0 3 &pcfg_pull_none>; 2474 }; 2475 }; 2476 2477 tsadc { 2478 otp_gpio: otp-gpio { 2479 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 2480 }; 2481 2482 otp_out: otp-out { 2483 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; 2484 }; 2485 }; 2486 2487 uart0 { 2488 uart0_xfer: uart0-xfer { 2489 rockchip,pins = 2490 <2 RK_PC0 1 &pcfg_pull_up>, 2491 <2 RK_PC1 1 &pcfg_pull_none>; 2492 }; 2493 2494 uart0_cts: uart0-cts { 2495 rockchip,pins = 2496 <2 RK_PC2 1 &pcfg_pull_none>; 2497 }; 2498 2499 uart0_rts: uart0-rts { 2500 rockchip,pins = 2501 <2 RK_PC3 1 &pcfg_pull_none>; 2502 }; 2503 }; 2504 2505 uart1 { 2506 uart1_xfer: uart1-xfer { 2507 rockchip,pins = 2508 <3 RK_PB4 2 &pcfg_pull_up>, 2509 <3 RK_PB5 2 &pcfg_pull_none>; 2510 }; 2511 }; 2512 2513 uart2a { 2514 uart2a_xfer: uart2a-xfer { 2515 rockchip,pins = 2516 <4 RK_PB0 2 &pcfg_pull_up>, 2517 <4 RK_PB1 2 &pcfg_pull_none>; 2518 }; 2519 }; 2520 2521 uart2b { 2522 uart2b_xfer: uart2b-xfer { 2523 rockchip,pins = 2524 <4 RK_PC0 2 &pcfg_pull_up>, 2525 <4 RK_PC1 2 &pcfg_pull_none>; 2526 }; 2527 }; 2528 2529 uart2c { 2530 uart2c_xfer: uart2c-xfer { 2531 rockchip,pins = 2532 <4 RK_PC3 1 &pcfg_pull_up>, 2533 <4 RK_PC4 1 &pcfg_pull_none>; 2534 }; 2535 }; 2536 2537 uart3 { 2538 uart3_xfer: uart3-xfer { 2539 rockchip,pins = 2540 <3 RK_PB6 2 &pcfg_pull_up>, 2541 <3 RK_PB7 2 &pcfg_pull_none>; 2542 }; 2543 2544 uart3_cts: uart3-cts { 2545 rockchip,pins = 2546 <3 RK_PC0 2 &pcfg_pull_none>; 2547 }; 2548 2549 uart3_rts: uart3-rts { 2550 rockchip,pins = 2551 <3 RK_PC1 2 &pcfg_pull_none>; 2552 }; 2553 }; 2554 2555 uart4 { 2556 uart4_xfer: uart4-xfer { 2557 rockchip,pins = 2558 <1 RK_PA7 1 &pcfg_pull_up>, 2559 <1 RK_PB0 1 &pcfg_pull_none>; 2560 }; 2561 }; 2562 2563 uarthdcp { 2564 uarthdcp_xfer: uarthdcp-xfer { 2565 rockchip,pins = 2566 <4 RK_PC5 2 &pcfg_pull_up>, 2567 <4 RK_PC6 2 &pcfg_pull_none>; 2568 }; 2569 }; 2570 2571 pwm0 { 2572 pwm0_pin: pwm0-pin { 2573 rockchip,pins = 2574 <4 RK_PC2 1 &pcfg_pull_none>; 2575 }; 2576 2577 pwm0_pin_pull_down: pwm0-pin-pull-down { 2578 rockchip,pins = 2579 <4 RK_PC2 1 &pcfg_pull_down>; 2580 }; 2581 2582 vop0_pwm_pin: vop0-pwm-pin { 2583 rockchip,pins = 2584 <4 RK_PC2 2 &pcfg_pull_none>; 2585 }; 2586 2587 vop1_pwm_pin: vop1-pwm-pin { 2588 rockchip,pins = 2589 <4 RK_PC2 3 &pcfg_pull_none>; 2590 }; 2591 }; 2592 2593 pwm1 { 2594 pwm1_pin: pwm1-pin { 2595 rockchip,pins = 2596 <4 RK_PC6 1 &pcfg_pull_none>; 2597 }; 2598 2599 pwm1_pin_pull_down: pwm1-pin-pull-down { 2600 rockchip,pins = 2601 <4 RK_PC6 1 &pcfg_pull_down>; 2602 }; 2603 }; 2604 2605 pwm2 { 2606 pwm2_pin: pwm2-pin { 2607 rockchip,pins = 2608 <1 RK_PC3 1 &pcfg_pull_none>; 2609 }; 2610 2611 pwm2_pin_pull_down: pwm2-pin-pull-down { 2612 rockchip,pins = 2613 <1 RK_PC3 1 &pcfg_pull_down>; 2614 }; 2615 }; 2616 2617 pwm3a { 2618 pwm3a_pin: pwm3a-pin { 2619 rockchip,pins = 2620 <0 RK_PA6 1 &pcfg_pull_none>; 2621 }; 2622 }; 2623 2624 pwm3b { 2625 pwm3b_pin: pwm3b-pin { 2626 rockchip,pins = 2627 <1 RK_PB6 1 &pcfg_pull_none>; 2628 }; 2629 }; 2630 2631 hdmi { 2632 hdmi_i2c_xfer: hdmi-i2c-xfer { 2633 rockchip,pins = 2634 <4 RK_PC1 3 &pcfg_pull_none>, 2635 <4 RK_PC0 3 &pcfg_pull_none>; 2636 }; 2637 2638 hdmi_cec: hdmi-cec { 2639 rockchip,pins = 2640 <4 RK_PC7 1 &pcfg_pull_none>; 2641 }; 2642 }; 2643 2644 pcie { 2645 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2646 rockchip,pins = 2647 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2648 }; 2649 2650 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2651 rockchip,pins = 2652 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2653 }; 2654 }; 2655 2656 }; 2657}; 2658