1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3399-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3399-power.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "rockchip,rk3399"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &gmac; 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 i2c6 = &i2c6; 30 i2c7 = &i2c7; 31 i2c8 = &i2c8; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 cpu-map { 44 cluster0 { 45 core0 { 46 cpu = <&cpu_l0>; 47 }; 48 core1 { 49 cpu = <&cpu_l1>; 50 }; 51 core2 { 52 cpu = <&cpu_l2>; 53 }; 54 core3 { 55 cpu = <&cpu_l3>; 56 }; 57 }; 58 59 cluster1 { 60 core0 { 61 cpu = <&cpu_b0>; 62 }; 63 core1 { 64 cpu = <&cpu_b1>; 65 }; 66 }; 67 }; 68 69 cpu_l0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <0x0 0x0>; 73 enable-method = "psci"; 74 capacity-dmips-mhz = <485>; 75 clocks = <&cru ARMCLKL>; 76 #cooling-cells = <2>; /* min followed by max */ 77 dynamic-power-coefficient = <100>; 78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 79 }; 80 81 cpu_l1: cpu@1 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x0 0x1>; 85 enable-method = "psci"; 86 capacity-dmips-mhz = <485>; 87 clocks = <&cru ARMCLKL>; 88 #cooling-cells = <2>; /* min followed by max */ 89 dynamic-power-coefficient = <100>; 90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 91 }; 92 93 cpu_l2: cpu@2 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a53"; 96 reg = <0x0 0x2>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <485>; 99 clocks = <&cru ARMCLKL>; 100 #cooling-cells = <2>; /* min followed by max */ 101 dynamic-power-coefficient = <100>; 102 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 103 }; 104 105 cpu_l3: cpu@3 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53"; 108 reg = <0x0 0x3>; 109 enable-method = "psci"; 110 capacity-dmips-mhz = <485>; 111 clocks = <&cru ARMCLKL>; 112 #cooling-cells = <2>; /* min followed by max */ 113 dynamic-power-coefficient = <100>; 114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 115 }; 116 117 cpu_b0: cpu@100 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a72"; 120 reg = <0x0 0x100>; 121 enable-method = "psci"; 122 capacity-dmips-mhz = <1024>; 123 clocks = <&cru ARMCLKB>; 124 #cooling-cells = <2>; /* min followed by max */ 125 dynamic-power-coefficient = <436>; 126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 127 128 thermal-idle { 129 #cooling-cells = <2>; 130 duration-us = <10000>; 131 exit-latency-us = <500>; 132 }; 133 }; 134 135 cpu_b1: cpu@101 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a72"; 138 reg = <0x0 0x101>; 139 enable-method = "psci"; 140 capacity-dmips-mhz = <1024>; 141 clocks = <&cru ARMCLKB>; 142 #cooling-cells = <2>; /* min followed by max */ 143 dynamic-power-coefficient = <436>; 144 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 145 146 thermal-idle { 147 #cooling-cells = <2>; 148 duration-us = <10000>; 149 exit-latency-us = <500>; 150 }; 151 }; 152 153 idle-states { 154 entry-method = "psci"; 155 156 CPU_SLEEP: cpu-sleep { 157 compatible = "arm,idle-state"; 158 local-timer-stop; 159 arm,psci-suspend-param = <0x0010000>; 160 entry-latency-us = <120>; 161 exit-latency-us = <250>; 162 min-residency-us = <900>; 163 }; 164 165 CLUSTER_SLEEP: cluster-sleep { 166 compatible = "arm,idle-state"; 167 local-timer-stop; 168 arm,psci-suspend-param = <0x1010000>; 169 entry-latency-us = <400>; 170 exit-latency-us = <500>; 171 min-residency-us = <2000>; 172 }; 173 }; 174 }; 175 176 display-subsystem { 177 compatible = "rockchip,display-subsystem"; 178 ports = <&vopl_out>, <&vopb_out>; 179 }; 180 181 dmc: memory-controller { 182 compatible = "rockchip,rk3399-dmc"; 183 rockchip,pmu = <&pmugrf>; 184 devfreq-events = <&dfi>; 185 clocks = <&cru SCLK_DDRC>; 186 clock-names = "dmc_clk"; 187 status = "disabled"; 188 }; 189 190 pmu_a53 { 191 compatible = "arm,cortex-a53-pmu"; 192 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 193 }; 194 195 pmu_a72 { 196 compatible = "arm,cortex-a72-pmu"; 197 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 198 }; 199 200 psci { 201 compatible = "arm,psci-1.0"; 202 method = "smc"; 203 }; 204 205 timer { 206 compatible = "arm,armv8-timer"; 207 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 208 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 209 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 210 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 211 arm,no-tick-in-suspend; 212 }; 213 214 xin24m: xin24m { 215 compatible = "fixed-clock"; 216 clock-frequency = <24000000>; 217 clock-output-names = "xin24m"; 218 #clock-cells = <0>; 219 }; 220 221 pcie0: pcie@f8000000 { 222 compatible = "rockchip,rk3399-pcie"; 223 reg = <0x0 0xf8000000 0x0 0x2000000>, 224 <0x0 0xfd000000 0x0 0x1000000>; 225 reg-names = "axi-base", "apb-base"; 226 device_type = "pci"; 227 #address-cells = <3>; 228 #size-cells = <2>; 229 #interrupt-cells = <1>; 230 aspm-no-l0s; 231 bus-range = <0x0 0x1f>; 232 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 233 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 234 clock-names = "aclk", "aclk-perf", 235 "hclk", "pm"; 236 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 237 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 238 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 239 interrupt-names = "sys", "legacy", "client"; 240 interrupt-map-mask = <0 0 0 7>; 241 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 242 <0 0 0 2 &pcie0_intc 1>, 243 <0 0 0 3 &pcie0_intc 2>, 244 <0 0 0 4 &pcie0_intc 3>; 245 max-link-speed = <1>; 246 msi-map = <0x0 &its 0x0 0x1000>; 247 phys = <&pcie_phy 0>, <&pcie_phy 1>, 248 <&pcie_phy 2>, <&pcie_phy 3>; 249 phy-names = "pcie-phy-0", "pcie-phy-1", 250 "pcie-phy-2", "pcie-phy-3"; 251 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>, 252 <0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; 253 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 254 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 255 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 256 <&cru SRST_A_PCIE>; 257 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 258 "pm", "pclk", "aclk"; 259 status = "disabled"; 260 261 pcie0_intc: interrupt-controller { 262 interrupt-controller; 263 #address-cells = <0>; 264 #interrupt-cells = <1>; 265 }; 266 }; 267 268 pcie0_ep: pcie-ep@f8000000 { 269 compatible = "rockchip,rk3399-pcie-ep"; 270 reg = <0x0 0xfd000000 0x0 0x1000000>, 271 <0x0 0xfa000000 0x0 0x2000000>; 272 reg-names = "apb-base", "mem-base"; 273 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 274 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 275 clock-names = "aclk", "aclk-perf", 276 "hclk", "pm"; 277 max-functions = /bits/ 8 <8>; 278 num-lanes = <4>; 279 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 280 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 281 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 282 <&cru SRST_A_PCIE>; 283 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 284 "pm", "pclk", "aclk"; 285 phys = <&pcie_phy 0>, <&pcie_phy 1>, 286 <&pcie_phy 2>, <&pcie_phy 3>; 287 phy-names = "pcie-phy-0", "pcie-phy-1", 288 "pcie-phy-2", "pcie-phy-3"; 289 rockchip,max-outbound-regions = <32>; 290 pinctrl-names = "default"; 291 pinctrl-0 = <&pcie_clkreqnb_cpm>; 292 status = "disabled"; 293 }; 294 295 gmac: ethernet@fe300000 { 296 compatible = "rockchip,rk3399-gmac"; 297 reg = <0x0 0xfe300000 0x0 0x10000>; 298 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 299 interrupt-names = "macirq"; 300 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 301 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 302 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 303 <&cru PCLK_GMAC>; 304 clock-names = "stmmaceth", "mac_clk_rx", 305 "mac_clk_tx", "clk_mac_ref", 306 "clk_mac_refout", "aclk_mac", 307 "pclk_mac"; 308 power-domains = <&power RK3399_PD_GMAC>; 309 resets = <&cru SRST_A_GMAC>; 310 reset-names = "stmmaceth"; 311 rockchip,grf = <&grf>; 312 snps,txpbl = <0x4>; 313 status = "disabled"; 314 }; 315 316 sdio0: mmc@fe310000 { 317 compatible = "rockchip,rk3399-dw-mshc", 318 "rockchip,rk3288-dw-mshc"; 319 reg = <0x0 0xfe310000 0x0 0x4000>; 320 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 321 max-frequency = <150000000>; 322 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 323 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 324 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 325 fifo-depth = <0x100>; 326 power-domains = <&power RK3399_PD_SDIOAUDIO>; 327 resets = <&cru SRST_SDIO0>; 328 reset-names = "reset"; 329 status = "disabled"; 330 }; 331 332 sdmmc: mmc@fe320000 { 333 compatible = "rockchip,rk3399-dw-mshc", 334 "rockchip,rk3288-dw-mshc"; 335 reg = <0x0 0xfe320000 0x0 0x4000>; 336 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 337 max-frequency = <150000000>; 338 assigned-clocks = <&cru HCLK_SD>; 339 assigned-clock-rates = <200000000>; 340 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 341 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 342 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 343 fifo-depth = <0x100>; 344 power-domains = <&power RK3399_PD_SD>; 345 resets = <&cru SRST_SDMMC>; 346 reset-names = "reset"; 347 status = "disabled"; 348 }; 349 350 sdhci: mmc@fe330000 { 351 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 352 reg = <0x0 0xfe330000 0x0 0x10000>; 353 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 354 arasan,soc-ctl-syscon = <&grf>; 355 assigned-clocks = <&cru SCLK_EMMC>; 356 assigned-clock-rates = <200000000>; 357 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 358 clock-names = "clk_xin", "clk_ahb"; 359 clock-output-names = "emmc_cardclock"; 360 #clock-cells = <0>; 361 phys = <&emmc_phy>; 362 phy-names = "phy_arasan"; 363 power-domains = <&power RK3399_PD_EMMC>; 364 disable-cqe-dcmd; 365 status = "disabled"; 366 }; 367 368 usb_host0_ehci: usb@fe380000 { 369 compatible = "generic-ehci"; 370 reg = <0x0 0xfe380000 0x0 0x20000>; 371 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 372 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 373 <&u2phy0>; 374 phys = <&u2phy0_host>; 375 phy-names = "usb"; 376 status = "disabled"; 377 }; 378 379 usb_host0_ohci: usb@fe3a0000 { 380 compatible = "generic-ohci"; 381 reg = <0x0 0xfe3a0000 0x0 0x20000>; 382 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 383 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 384 <&u2phy0>; 385 phys = <&u2phy0_host>; 386 phy-names = "usb"; 387 status = "disabled"; 388 }; 389 390 usb_host1_ehci: usb@fe3c0000 { 391 compatible = "generic-ehci"; 392 reg = <0x0 0xfe3c0000 0x0 0x20000>; 393 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 394 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 395 <&u2phy1>; 396 phys = <&u2phy1_host>; 397 phy-names = "usb"; 398 status = "disabled"; 399 }; 400 401 usb_host1_ohci: usb@fe3e0000 { 402 compatible = "generic-ohci"; 403 reg = <0x0 0xfe3e0000 0x0 0x20000>; 404 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 405 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 406 <&u2phy1>; 407 phys = <&u2phy1_host>; 408 phy-names = "usb"; 409 status = "disabled"; 410 }; 411 412 debug@fe430000 { 413 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 414 reg = <0 0xfe430000 0 0x1000>; 415 clocks = <&cru PCLK_COREDBG_L>; 416 clock-names = "apb_pclk"; 417 cpu = <&cpu_l0>; 418 }; 419 420 debug@fe432000 { 421 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 422 reg = <0 0xfe432000 0 0x1000>; 423 clocks = <&cru PCLK_COREDBG_L>; 424 clock-names = "apb_pclk"; 425 cpu = <&cpu_l1>; 426 }; 427 428 debug@fe434000 { 429 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 430 reg = <0 0xfe434000 0 0x1000>; 431 clocks = <&cru PCLK_COREDBG_L>; 432 clock-names = "apb_pclk"; 433 cpu = <&cpu_l2>; 434 }; 435 436 debug@fe436000 { 437 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 438 reg = <0 0xfe436000 0 0x1000>; 439 clocks = <&cru PCLK_COREDBG_L>; 440 clock-names = "apb_pclk"; 441 cpu = <&cpu_l3>; 442 }; 443 444 debug@fe610000 { 445 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 446 reg = <0 0xfe610000 0 0x1000>; 447 clocks = <&cru PCLK_COREDBG_B>; 448 clock-names = "apb_pclk"; 449 cpu = <&cpu_b0>; 450 }; 451 452 debug@fe710000 { 453 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 454 reg = <0 0xfe710000 0 0x1000>; 455 clocks = <&cru PCLK_COREDBG_B>; 456 clock-names = "apb_pclk"; 457 cpu = <&cpu_b1>; 458 }; 459 460 usbdrd3_0: usb@fe800000 { 461 compatible = "rockchip,rk3399-dwc3"; 462 #address-cells = <2>; 463 #size-cells = <2>; 464 ranges; 465 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 466 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 467 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 468 clock-names = "ref_clk", "suspend_clk", 469 "bus_clk", "aclk_usb3_rksoc_axi_perf", 470 "aclk_usb3", "grf_clk"; 471 resets = <&cru SRST_A_USB3_OTG0>; 472 reset-names = "usb3-otg"; 473 status = "disabled"; 474 475 usbdrd_dwc3_0: usb@fe800000 { 476 compatible = "snps,dwc3"; 477 reg = <0x0 0xfe800000 0x0 0x100000>; 478 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 479 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, 480 <&cru SCLK_USB3OTG0_SUSPEND>; 481 clock-names = "ref", "bus_early", "suspend"; 482 dr_mode = "otg"; 483 phys = <&u2phy0_otg>, <&tcphy0_usb3>; 484 phy-names = "usb2-phy", "usb3-phy"; 485 phy_type = "utmi_wide"; 486 snps,dis_enblslpm_quirk; 487 snps,dis-u2-freeclk-exists-quirk; 488 snps,dis_u2_susphy_quirk; 489 snps,dis-del-phy-power-chg-quirk; 490 snps,dis-tx-ipgap-linecheck-quirk; 491 power-domains = <&power RK3399_PD_USB3>; 492 status = "disabled"; 493 }; 494 }; 495 496 usbdrd3_1: usb@fe900000 { 497 compatible = "rockchip,rk3399-dwc3"; 498 #address-cells = <2>; 499 #size-cells = <2>; 500 ranges; 501 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, 502 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 503 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 504 clock-names = "ref_clk", "suspend_clk", 505 "bus_clk", "aclk_usb3_rksoc_axi_perf", 506 "aclk_usb3", "grf_clk"; 507 resets = <&cru SRST_A_USB3_OTG1>; 508 reset-names = "usb3-otg"; 509 status = "disabled"; 510 511 usbdrd_dwc3_1: usb@fe900000 { 512 compatible = "snps,dwc3"; 513 reg = <0x0 0xfe900000 0x0 0x100000>; 514 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 515 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>, 516 <&cru SCLK_USB3OTG1_SUSPEND>; 517 clock-names = "ref", "bus_early", "suspend"; 518 dr_mode = "otg"; 519 phys = <&u2phy1_otg>, <&tcphy1_usb3>; 520 phy-names = "usb2-phy", "usb3-phy"; 521 phy_type = "utmi_wide"; 522 snps,dis_enblslpm_quirk; 523 snps,dis-u2-freeclk-exists-quirk; 524 snps,dis_u2_susphy_quirk; 525 snps,dis-del-phy-power-chg-quirk; 526 snps,dis-tx-ipgap-linecheck-quirk; 527 power-domains = <&power RK3399_PD_USB3>; 528 status = "disabled"; 529 }; 530 }; 531 532 cdn_dp: dp@fec00000 { 533 compatible = "rockchip,rk3399-cdn-dp"; 534 reg = <0x0 0xfec00000 0x0 0x100000>; 535 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 536 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>; 537 assigned-clock-rates = <100000000>, <200000000>; 538 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, 539 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; 540 clock-names = "core-clk", "pclk", "spdif", "grf"; 541 phys = <&tcphy0_dp>, <&tcphy1_dp>; 542 power-domains = <&power RK3399_PD_HDCP>; 543 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, 544 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; 545 reset-names = "spdif", "dptx", "apb", "core"; 546 rockchip,grf = <&grf>; 547 #sound-dai-cells = <1>; 548 status = "disabled"; 549 550 ports { 551 dp_in: port { 552 #address-cells = <1>; 553 #size-cells = <0>; 554 555 dp_in_vopb: endpoint@0 { 556 reg = <0>; 557 remote-endpoint = <&vopb_out_dp>; 558 }; 559 560 dp_in_vopl: endpoint@1 { 561 reg = <1>; 562 remote-endpoint = <&vopl_out_dp>; 563 }; 564 }; 565 }; 566 }; 567 568 gic: interrupt-controller@fee00000 { 569 compatible = "arm,gic-v3"; 570 #interrupt-cells = <4>; 571 #address-cells = <2>; 572 #size-cells = <2>; 573 ranges; 574 interrupt-controller; 575 576 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 577 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 578 <0x0 0xfff00000 0 0x10000>, /* GICC */ 579 <0x0 0xfff10000 0 0x10000>, /* GICH */ 580 <0x0 0xfff20000 0 0x10000>; /* GICV */ 581 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 582 its: msi-controller@fee20000 { 583 compatible = "arm,gic-v3-its"; 584 msi-controller; 585 #msi-cells = <1>; 586 reg = <0x0 0xfee20000 0x0 0x20000>; 587 }; 588 589 ppi-partitions { 590 ppi_cluster0: interrupt-partition-0 { 591 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 592 }; 593 594 ppi_cluster1: interrupt-partition-1 { 595 affinity = <&cpu_b0 &cpu_b1>; 596 }; 597 }; 598 }; 599 600 saradc: saradc@ff100000 { 601 compatible = "rockchip,rk3399-saradc"; 602 reg = <0x0 0xff100000 0x0 0x100>; 603 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 604 #io-channel-cells = <1>; 605 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 606 clock-names = "saradc", "apb_pclk"; 607 resets = <&cru SRST_P_SARADC>; 608 reset-names = "saradc-apb"; 609 status = "disabled"; 610 }; 611 612 crypto0: crypto@ff8b0000 { 613 compatible = "rockchip,rk3399-crypto"; 614 reg = <0x0 0xff8b0000 0x0 0x4000>; 615 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>; 616 clocks = <&cru HCLK_M_CRYPTO0>, <&cru HCLK_S_CRYPTO0>, <&cru SCLK_CRYPTO0>; 617 clock-names = "hclk_master", "hclk_slave", "sclk"; 618 resets = <&cru SRST_CRYPTO0>, <&cru SRST_CRYPTO0_S>, <&cru SRST_CRYPTO0_M>; 619 reset-names = "master", "slave", "crypto-rst"; 620 }; 621 622 crypto1: crypto@ff8b8000 { 623 compatible = "rockchip,rk3399-crypto"; 624 reg = <0x0 0xff8b8000 0x0 0x4000>; 625 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 626 clocks = <&cru HCLK_M_CRYPTO1>, <&cru HCLK_S_CRYPTO1>, <&cru SCLK_CRYPTO1>; 627 clock-names = "hclk_master", "hclk_slave", "sclk"; 628 resets = <&cru SRST_CRYPTO1>, <&cru SRST_CRYPTO1_S>, <&cru SRST_CRYPTO1_M>; 629 reset-names = "master", "slave", "crypto-rst"; 630 }; 631 632 i2c1: i2c@ff110000 { 633 compatible = "rockchip,rk3399-i2c"; 634 reg = <0x0 0xff110000 0x0 0x1000>; 635 assigned-clocks = <&cru SCLK_I2C1>; 636 assigned-clock-rates = <200000000>; 637 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 638 clock-names = "i2c", "pclk"; 639 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 640 pinctrl-names = "default"; 641 pinctrl-0 = <&i2c1_xfer>; 642 #address-cells = <1>; 643 #size-cells = <0>; 644 status = "disabled"; 645 }; 646 647 i2c2: i2c@ff120000 { 648 compatible = "rockchip,rk3399-i2c"; 649 reg = <0x0 0xff120000 0x0 0x1000>; 650 assigned-clocks = <&cru SCLK_I2C2>; 651 assigned-clock-rates = <200000000>; 652 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 653 clock-names = "i2c", "pclk"; 654 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 655 pinctrl-names = "default"; 656 pinctrl-0 = <&i2c2_xfer>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 status = "disabled"; 660 }; 661 662 i2c3: i2c@ff130000 { 663 compatible = "rockchip,rk3399-i2c"; 664 reg = <0x0 0xff130000 0x0 0x1000>; 665 assigned-clocks = <&cru SCLK_I2C3>; 666 assigned-clock-rates = <200000000>; 667 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 668 clock-names = "i2c", "pclk"; 669 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 670 pinctrl-names = "default"; 671 pinctrl-0 = <&i2c3_xfer>; 672 #address-cells = <1>; 673 #size-cells = <0>; 674 status = "disabled"; 675 }; 676 677 i2c5: i2c@ff140000 { 678 compatible = "rockchip,rk3399-i2c"; 679 reg = <0x0 0xff140000 0x0 0x1000>; 680 assigned-clocks = <&cru SCLK_I2C5>; 681 assigned-clock-rates = <200000000>; 682 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 683 clock-names = "i2c", "pclk"; 684 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 685 pinctrl-names = "default"; 686 pinctrl-0 = <&i2c5_xfer>; 687 #address-cells = <1>; 688 #size-cells = <0>; 689 status = "disabled"; 690 }; 691 692 i2c6: i2c@ff150000 { 693 compatible = "rockchip,rk3399-i2c"; 694 reg = <0x0 0xff150000 0x0 0x1000>; 695 assigned-clocks = <&cru SCLK_I2C6>; 696 assigned-clock-rates = <200000000>; 697 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 698 clock-names = "i2c", "pclk"; 699 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 700 pinctrl-names = "default"; 701 pinctrl-0 = <&i2c6_xfer>; 702 #address-cells = <1>; 703 #size-cells = <0>; 704 status = "disabled"; 705 }; 706 707 i2c7: i2c@ff160000 { 708 compatible = "rockchip,rk3399-i2c"; 709 reg = <0x0 0xff160000 0x0 0x1000>; 710 assigned-clocks = <&cru SCLK_I2C7>; 711 assigned-clock-rates = <200000000>; 712 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 713 clock-names = "i2c", "pclk"; 714 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 715 pinctrl-names = "default"; 716 pinctrl-0 = <&i2c7_xfer>; 717 #address-cells = <1>; 718 #size-cells = <0>; 719 status = "disabled"; 720 }; 721 722 uart0: serial@ff180000 { 723 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 724 reg = <0x0 0xff180000 0x0 0x100>; 725 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 726 clock-names = "baudclk", "apb_pclk"; 727 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 728 reg-shift = <2>; 729 reg-io-width = <4>; 730 pinctrl-names = "default"; 731 pinctrl-0 = <&uart0_xfer>; 732 status = "disabled"; 733 }; 734 735 uart1: serial@ff190000 { 736 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 737 reg = <0x0 0xff190000 0x0 0x100>; 738 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 739 clock-names = "baudclk", "apb_pclk"; 740 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 741 reg-shift = <2>; 742 reg-io-width = <4>; 743 pinctrl-names = "default"; 744 pinctrl-0 = <&uart1_xfer>; 745 status = "disabled"; 746 }; 747 748 uart2: serial@ff1a0000 { 749 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 750 reg = <0x0 0xff1a0000 0x0 0x100>; 751 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 752 clock-names = "baudclk", "apb_pclk"; 753 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 754 reg-shift = <2>; 755 reg-io-width = <4>; 756 pinctrl-names = "default"; 757 pinctrl-0 = <&uart2c_xfer>; 758 status = "disabled"; 759 }; 760 761 uart3: serial@ff1b0000 { 762 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 763 reg = <0x0 0xff1b0000 0x0 0x100>; 764 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 765 clock-names = "baudclk", "apb_pclk"; 766 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 767 reg-shift = <2>; 768 reg-io-width = <4>; 769 pinctrl-names = "default"; 770 pinctrl-0 = <&uart3_xfer>; 771 status = "disabled"; 772 }; 773 774 spi0: spi@ff1c0000 { 775 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 776 reg = <0x0 0xff1c0000 0x0 0x1000>; 777 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 778 clock-names = "spiclk", "apb_pclk"; 779 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 780 dmas = <&dmac_peri 10>, <&dmac_peri 11>; 781 dma-names = "tx", "rx"; 782 pinctrl-names = "default"; 783 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 784 #address-cells = <1>; 785 #size-cells = <0>; 786 status = "disabled"; 787 }; 788 789 spi1: spi@ff1d0000 { 790 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 791 reg = <0x0 0xff1d0000 0x0 0x1000>; 792 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 793 clock-names = "spiclk", "apb_pclk"; 794 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 795 dmas = <&dmac_peri 12>, <&dmac_peri 13>; 796 dma-names = "tx", "rx"; 797 pinctrl-names = "default"; 798 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 799 #address-cells = <1>; 800 #size-cells = <0>; 801 status = "disabled"; 802 }; 803 804 spi2: spi@ff1e0000 { 805 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 806 reg = <0x0 0xff1e0000 0x0 0x1000>; 807 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 808 clock-names = "spiclk", "apb_pclk"; 809 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 810 dmas = <&dmac_peri 14>, <&dmac_peri 15>; 811 dma-names = "tx", "rx"; 812 pinctrl-names = "default"; 813 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 814 #address-cells = <1>; 815 #size-cells = <0>; 816 status = "disabled"; 817 }; 818 819 spi4: spi@ff1f0000 { 820 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 821 reg = <0x0 0xff1f0000 0x0 0x1000>; 822 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 823 clock-names = "spiclk", "apb_pclk"; 824 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 825 dmas = <&dmac_peri 18>, <&dmac_peri 19>; 826 dma-names = "tx", "rx"; 827 pinctrl-names = "default"; 828 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 829 #address-cells = <1>; 830 #size-cells = <0>; 831 status = "disabled"; 832 }; 833 834 spi5: spi@ff200000 { 835 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 836 reg = <0x0 0xff200000 0x0 0x1000>; 837 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 838 clock-names = "spiclk", "apb_pclk"; 839 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 840 dmas = <&dmac_bus 8>, <&dmac_bus 9>; 841 dma-names = "tx", "rx"; 842 pinctrl-names = "default"; 843 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 844 power-domains = <&power RK3399_PD_SDIOAUDIO>; 845 #address-cells = <1>; 846 #size-cells = <0>; 847 status = "disabled"; 848 }; 849 850 thermal_zones: thermal-zones { 851 cpu_thermal: cpu-thermal { 852 polling-delay-passive = <100>; 853 polling-delay = <1000>; 854 855 thermal-sensors = <&tsadc 0>; 856 857 trips { 858 cpu_alert0: cpu_alert0 { 859 temperature = <70000>; 860 hysteresis = <2000>; 861 type = "passive"; 862 }; 863 cpu_alert1: cpu_alert1 { 864 temperature = <75000>; 865 hysteresis = <2000>; 866 type = "passive"; 867 }; 868 cpu_crit: cpu_crit { 869 temperature = <95000>; 870 hysteresis = <2000>; 871 type = "critical"; 872 }; 873 }; 874 875 cooling-maps { 876 map0 { 877 trip = <&cpu_alert0>; 878 cooling-device = 879 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 880 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 881 }; 882 map1 { 883 trip = <&cpu_alert1>; 884 cooling-device = 885 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 886 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 887 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 888 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 889 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 890 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 891 }; 892 }; 893 }; 894 895 gpu_thermal: gpu-thermal { 896 polling-delay-passive = <100>; 897 polling-delay = <1000>; 898 899 thermal-sensors = <&tsadc 1>; 900 901 trips { 902 gpu_alert0: gpu_alert0 { 903 temperature = <75000>; 904 hysteresis = <2000>; 905 type = "passive"; 906 }; 907 gpu_crit: gpu_crit { 908 temperature = <95000>; 909 hysteresis = <2000>; 910 type = "critical"; 911 }; 912 }; 913 914 cooling-maps { 915 map0 { 916 trip = <&gpu_alert0>; 917 cooling-device = 918 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 919 }; 920 }; 921 }; 922 }; 923 924 tsadc: tsadc@ff260000 { 925 compatible = "rockchip,rk3399-tsadc"; 926 reg = <0x0 0xff260000 0x0 0x100>; 927 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 928 assigned-clocks = <&cru SCLK_TSADC>; 929 assigned-clock-rates = <750000>; 930 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 931 clock-names = "tsadc", "apb_pclk"; 932 resets = <&cru SRST_TSADC>; 933 reset-names = "tsadc-apb"; 934 rockchip,grf = <&grf>; 935 rockchip,hw-tshut-temp = <95000>; 936 pinctrl-names = "init", "default", "sleep"; 937 pinctrl-0 = <&otp_pin>; 938 pinctrl-1 = <&otp_out>; 939 pinctrl-2 = <&otp_pin>; 940 #thermal-sensor-cells = <1>; 941 status = "disabled"; 942 }; 943 944 qos_emmc: qos@ffa58000 { 945 compatible = "rockchip,rk3399-qos", "syscon"; 946 reg = <0x0 0xffa58000 0x0 0x20>; 947 }; 948 949 qos_gmac: qos@ffa5c000 { 950 compatible = "rockchip,rk3399-qos", "syscon"; 951 reg = <0x0 0xffa5c000 0x0 0x20>; 952 }; 953 954 qos_pcie: qos@ffa60080 { 955 compatible = "rockchip,rk3399-qos", "syscon"; 956 reg = <0x0 0xffa60080 0x0 0x20>; 957 }; 958 959 qos_usb_host0: qos@ffa60100 { 960 compatible = "rockchip,rk3399-qos", "syscon"; 961 reg = <0x0 0xffa60100 0x0 0x20>; 962 }; 963 964 qos_usb_host1: qos@ffa60180 { 965 compatible = "rockchip,rk3399-qos", "syscon"; 966 reg = <0x0 0xffa60180 0x0 0x20>; 967 }; 968 969 qos_usb_otg0: qos@ffa70000 { 970 compatible = "rockchip,rk3399-qos", "syscon"; 971 reg = <0x0 0xffa70000 0x0 0x20>; 972 }; 973 974 qos_usb_otg1: qos@ffa70080 { 975 compatible = "rockchip,rk3399-qos", "syscon"; 976 reg = <0x0 0xffa70080 0x0 0x20>; 977 }; 978 979 qos_sd: qos@ffa74000 { 980 compatible = "rockchip,rk3399-qos", "syscon"; 981 reg = <0x0 0xffa74000 0x0 0x20>; 982 }; 983 984 qos_sdioaudio: qos@ffa76000 { 985 compatible = "rockchip,rk3399-qos", "syscon"; 986 reg = <0x0 0xffa76000 0x0 0x20>; 987 }; 988 989 qos_hdcp: qos@ffa90000 { 990 compatible = "rockchip,rk3399-qos", "syscon"; 991 reg = <0x0 0xffa90000 0x0 0x20>; 992 }; 993 994 qos_iep: qos@ffa98000 { 995 compatible = "rockchip,rk3399-qos", "syscon"; 996 reg = <0x0 0xffa98000 0x0 0x20>; 997 }; 998 999 qos_isp0_m0: qos@ffaa0000 { 1000 compatible = "rockchip,rk3399-qos", "syscon"; 1001 reg = <0x0 0xffaa0000 0x0 0x20>; 1002 }; 1003 1004 qos_isp0_m1: qos@ffaa0080 { 1005 compatible = "rockchip,rk3399-qos", "syscon"; 1006 reg = <0x0 0xffaa0080 0x0 0x20>; 1007 }; 1008 1009 qos_isp1_m0: qos@ffaa8000 { 1010 compatible = "rockchip,rk3399-qos", "syscon"; 1011 reg = <0x0 0xffaa8000 0x0 0x20>; 1012 }; 1013 1014 qos_isp1_m1: qos@ffaa8080 { 1015 compatible = "rockchip,rk3399-qos", "syscon"; 1016 reg = <0x0 0xffaa8080 0x0 0x20>; 1017 }; 1018 1019 qos_rga_r: qos@ffab0000 { 1020 compatible = "rockchip,rk3399-qos", "syscon"; 1021 reg = <0x0 0xffab0000 0x0 0x20>; 1022 }; 1023 1024 qos_rga_w: qos@ffab0080 { 1025 compatible = "rockchip,rk3399-qos", "syscon"; 1026 reg = <0x0 0xffab0080 0x0 0x20>; 1027 }; 1028 1029 qos_video_m0: qos@ffab8000 { 1030 compatible = "rockchip,rk3399-qos", "syscon"; 1031 reg = <0x0 0xffab8000 0x0 0x20>; 1032 }; 1033 1034 qos_video_m1_r: qos@ffac0000 { 1035 compatible = "rockchip,rk3399-qos", "syscon"; 1036 reg = <0x0 0xffac0000 0x0 0x20>; 1037 }; 1038 1039 qos_video_m1_w: qos@ffac0080 { 1040 compatible = "rockchip,rk3399-qos", "syscon"; 1041 reg = <0x0 0xffac0080 0x0 0x20>; 1042 }; 1043 1044 qos_vop_big_r: qos@ffac8000 { 1045 compatible = "rockchip,rk3399-qos", "syscon"; 1046 reg = <0x0 0xffac8000 0x0 0x20>; 1047 }; 1048 1049 qos_vop_big_w: qos@ffac8080 { 1050 compatible = "rockchip,rk3399-qos", "syscon"; 1051 reg = <0x0 0xffac8080 0x0 0x20>; 1052 }; 1053 1054 qos_vop_little: qos@ffad0000 { 1055 compatible = "rockchip,rk3399-qos", "syscon"; 1056 reg = <0x0 0xffad0000 0x0 0x20>; 1057 }; 1058 1059 qos_perihp: qos@ffad8080 { 1060 compatible = "rockchip,rk3399-qos", "syscon"; 1061 reg = <0x0 0xffad8080 0x0 0x20>; 1062 }; 1063 1064 qos_gpu: qos@ffae0000 { 1065 compatible = "rockchip,rk3399-qos", "syscon"; 1066 reg = <0x0 0xffae0000 0x0 0x20>; 1067 }; 1068 1069 pmu: power-management@ff310000 { 1070 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 1071 reg = <0x0 0xff310000 0x0 0x1000>; 1072 1073 /* 1074 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 1075 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 1076 * Some of the power domains are grouped together for every 1077 * voltage domain. 1078 * The detail contents as below. 1079 */ 1080 power: power-controller { 1081 compatible = "rockchip,rk3399-power-controller"; 1082 #power-domain-cells = <1>; 1083 #address-cells = <1>; 1084 #size-cells = <0>; 1085 1086 /* These power domains are grouped by VD_CENTER */ 1087 power-domain@RK3399_PD_IEP { 1088 reg = <RK3399_PD_IEP>; 1089 clocks = <&cru ACLK_IEP>, 1090 <&cru HCLK_IEP>; 1091 pm_qos = <&qos_iep>; 1092 #power-domain-cells = <0>; 1093 }; 1094 power-domain@RK3399_PD_RGA { 1095 reg = <RK3399_PD_RGA>; 1096 clocks = <&cru ACLK_RGA>, 1097 <&cru HCLK_RGA>; 1098 pm_qos = <&qos_rga_r>, 1099 <&qos_rga_w>; 1100 #power-domain-cells = <0>; 1101 }; 1102 power-domain@RK3399_PD_VCODEC { 1103 reg = <RK3399_PD_VCODEC>; 1104 clocks = <&cru ACLK_VCODEC>, 1105 <&cru HCLK_VCODEC>; 1106 pm_qos = <&qos_video_m0>; 1107 #power-domain-cells = <0>; 1108 }; 1109 power-domain@RK3399_PD_VDU { 1110 reg = <RK3399_PD_VDU>; 1111 clocks = <&cru ACLK_VDU>, 1112 <&cru HCLK_VDU>, 1113 <&cru SCLK_VDU_CA>, 1114 <&cru SCLK_VDU_CORE>; 1115 pm_qos = <&qos_video_m1_r>, 1116 <&qos_video_m1_w>; 1117 #power-domain-cells = <0>; 1118 }; 1119 1120 /* These power domains are grouped by VD_GPU */ 1121 power-domain@RK3399_PD_GPU { 1122 reg = <RK3399_PD_GPU>; 1123 clocks = <&cru ACLK_GPU>; 1124 pm_qos = <&qos_gpu>; 1125 #power-domain-cells = <0>; 1126 }; 1127 1128 /* These power domains are grouped by VD_LOGIC */ 1129 power-domain@RK3399_PD_EDP { 1130 reg = <RK3399_PD_EDP>; 1131 clocks = <&cru PCLK_EDP_CTRL>; 1132 #power-domain-cells = <0>; 1133 }; 1134 power-domain@RK3399_PD_EMMC { 1135 reg = <RK3399_PD_EMMC>; 1136 clocks = <&cru ACLK_EMMC>; 1137 pm_qos = <&qos_emmc>; 1138 #power-domain-cells = <0>; 1139 }; 1140 power-domain@RK3399_PD_GMAC { 1141 reg = <RK3399_PD_GMAC>; 1142 clocks = <&cru ACLK_GMAC>, 1143 <&cru PCLK_GMAC>; 1144 pm_qos = <&qos_gmac>; 1145 #power-domain-cells = <0>; 1146 }; 1147 power-domain@RK3399_PD_SD { 1148 reg = <RK3399_PD_SD>; 1149 clocks = <&cru HCLK_SDMMC>, 1150 <&cru SCLK_SDMMC>; 1151 pm_qos = <&qos_sd>; 1152 #power-domain-cells = <0>; 1153 }; 1154 power-domain@RK3399_PD_SDIOAUDIO { 1155 reg = <RK3399_PD_SDIOAUDIO>; 1156 clocks = <&cru HCLK_SDIO>; 1157 pm_qos = <&qos_sdioaudio>; 1158 #power-domain-cells = <0>; 1159 }; 1160 power-domain@RK3399_PD_TCPD0 { 1161 reg = <RK3399_PD_TCPD0>; 1162 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1163 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1164 #power-domain-cells = <0>; 1165 }; 1166 power-domain@RK3399_PD_TCPD1 { 1167 reg = <RK3399_PD_TCPD1>; 1168 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1169 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1170 #power-domain-cells = <0>; 1171 }; 1172 power-domain@RK3399_PD_USB3 { 1173 reg = <RK3399_PD_USB3>; 1174 clocks = <&cru ACLK_USB3>; 1175 pm_qos = <&qos_usb_otg0>, 1176 <&qos_usb_otg1>; 1177 #power-domain-cells = <0>; 1178 }; 1179 power-domain@RK3399_PD_VIO { 1180 reg = <RK3399_PD_VIO>; 1181 #power-domain-cells = <1>; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 1185 power-domain@RK3399_PD_HDCP { 1186 reg = <RK3399_PD_HDCP>; 1187 clocks = <&cru ACLK_HDCP>, 1188 <&cru HCLK_HDCP>, 1189 <&cru PCLK_HDCP>; 1190 pm_qos = <&qos_hdcp>; 1191 #power-domain-cells = <0>; 1192 }; 1193 power-domain@RK3399_PD_ISP0 { 1194 reg = <RK3399_PD_ISP0>; 1195 clocks = <&cru ACLK_ISP0>, 1196 <&cru HCLK_ISP0>; 1197 pm_qos = <&qos_isp0_m0>, 1198 <&qos_isp0_m1>; 1199 #power-domain-cells = <0>; 1200 }; 1201 power-domain@RK3399_PD_ISP1 { 1202 reg = <RK3399_PD_ISP1>; 1203 clocks = <&cru ACLK_ISP1>, 1204 <&cru HCLK_ISP1>; 1205 pm_qos = <&qos_isp1_m0>, 1206 <&qos_isp1_m1>; 1207 #power-domain-cells = <0>; 1208 }; 1209 power-domain@RK3399_PD_VO { 1210 reg = <RK3399_PD_VO>; 1211 #power-domain-cells = <1>; 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 1215 power-domain@RK3399_PD_VOPB { 1216 reg = <RK3399_PD_VOPB>; 1217 clocks = <&cru ACLK_VOP0>, 1218 <&cru HCLK_VOP0>; 1219 pm_qos = <&qos_vop_big_r>, 1220 <&qos_vop_big_w>; 1221 #power-domain-cells = <0>; 1222 }; 1223 power-domain@RK3399_PD_VOPL { 1224 reg = <RK3399_PD_VOPL>; 1225 clocks = <&cru ACLK_VOP1>, 1226 <&cru HCLK_VOP1>; 1227 pm_qos = <&qos_vop_little>; 1228 #power-domain-cells = <0>; 1229 }; 1230 }; 1231 }; 1232 }; 1233 }; 1234 1235 pmugrf: syscon@ff320000 { 1236 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1237 reg = <0x0 0xff320000 0x0 0x1000>; 1238 1239 pmu_io_domains: io-domains { 1240 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1241 status = "disabled"; 1242 }; 1243 }; 1244 1245 spi3: spi@ff350000 { 1246 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1247 reg = <0x0 0xff350000 0x0 0x1000>; 1248 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1249 clock-names = "spiclk", "apb_pclk"; 1250 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1251 pinctrl-names = "default"; 1252 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1253 #address-cells = <1>; 1254 #size-cells = <0>; 1255 status = "disabled"; 1256 }; 1257 1258 uart4: serial@ff370000 { 1259 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1260 reg = <0x0 0xff370000 0x0 0x100>; 1261 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1262 clock-names = "baudclk", "apb_pclk"; 1263 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1264 reg-shift = <2>; 1265 reg-io-width = <4>; 1266 pinctrl-names = "default"; 1267 pinctrl-0 = <&uart4_xfer>; 1268 status = "disabled"; 1269 }; 1270 1271 i2c0: i2c@ff3c0000 { 1272 compatible = "rockchip,rk3399-i2c"; 1273 reg = <0x0 0xff3c0000 0x0 0x1000>; 1274 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1275 assigned-clock-rates = <200000000>; 1276 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1277 clock-names = "i2c", "pclk"; 1278 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1279 pinctrl-names = "default"; 1280 pinctrl-0 = <&i2c0_xfer>; 1281 #address-cells = <1>; 1282 #size-cells = <0>; 1283 status = "disabled"; 1284 }; 1285 1286 i2c4: i2c@ff3d0000 { 1287 compatible = "rockchip,rk3399-i2c"; 1288 reg = <0x0 0xff3d0000 0x0 0x1000>; 1289 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1290 assigned-clock-rates = <200000000>; 1291 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1292 clock-names = "i2c", "pclk"; 1293 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1294 pinctrl-names = "default"; 1295 pinctrl-0 = <&i2c4_xfer>; 1296 #address-cells = <1>; 1297 #size-cells = <0>; 1298 status = "disabled"; 1299 }; 1300 1301 i2c8: i2c@ff3e0000 { 1302 compatible = "rockchip,rk3399-i2c"; 1303 reg = <0x0 0xff3e0000 0x0 0x1000>; 1304 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1305 assigned-clock-rates = <200000000>; 1306 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1307 clock-names = "i2c", "pclk"; 1308 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1309 pinctrl-names = "default"; 1310 pinctrl-0 = <&i2c8_xfer>; 1311 #address-cells = <1>; 1312 #size-cells = <0>; 1313 status = "disabled"; 1314 }; 1315 1316 pwm0: pwm@ff420000 { 1317 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1318 reg = <0x0 0xff420000 0x0 0x10>; 1319 #pwm-cells = <3>; 1320 pinctrl-names = "default"; 1321 pinctrl-0 = <&pwm0_pin>; 1322 clocks = <&pmucru PCLK_RKPWM_PMU>; 1323 status = "disabled"; 1324 }; 1325 1326 pwm1: pwm@ff420010 { 1327 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1328 reg = <0x0 0xff420010 0x0 0x10>; 1329 #pwm-cells = <3>; 1330 pinctrl-names = "default"; 1331 pinctrl-0 = <&pwm1_pin>; 1332 clocks = <&pmucru PCLK_RKPWM_PMU>; 1333 status = "disabled"; 1334 }; 1335 1336 pwm2: pwm@ff420020 { 1337 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1338 reg = <0x0 0xff420020 0x0 0x10>; 1339 #pwm-cells = <3>; 1340 pinctrl-names = "default"; 1341 pinctrl-0 = <&pwm2_pin>; 1342 clocks = <&pmucru PCLK_RKPWM_PMU>; 1343 status = "disabled"; 1344 }; 1345 1346 pwm3: pwm@ff420030 { 1347 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1348 reg = <0x0 0xff420030 0x0 0x10>; 1349 #pwm-cells = <3>; 1350 pinctrl-names = "default"; 1351 pinctrl-0 = <&pwm3a_pin>; 1352 clocks = <&pmucru PCLK_RKPWM_PMU>; 1353 status = "disabled"; 1354 }; 1355 1356 dfi: dfi@ff630000 { 1357 reg = <0x00 0xff630000 0x00 0x4000>; 1358 compatible = "rockchip,rk3399-dfi"; 1359 rockchip,pmu = <&pmugrf>; 1360 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1361 clocks = <&cru PCLK_DDR_MON>; 1362 clock-names = "pclk_ddr_mon"; 1363 status = "disabled"; 1364 }; 1365 1366 vpu: video-codec@ff650000 { 1367 compatible = "rockchip,rk3399-vpu"; 1368 reg = <0x0 0xff650000 0x0 0x800>; 1369 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 1370 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 1371 interrupt-names = "vepu", "vdpu"; 1372 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1373 clock-names = "aclk", "hclk"; 1374 iommus = <&vpu_mmu>; 1375 power-domains = <&power RK3399_PD_VCODEC>; 1376 }; 1377 1378 vpu_mmu: iommu@ff650800 { 1379 compatible = "rockchip,iommu"; 1380 reg = <0x0 0xff650800 0x0 0x40>; 1381 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 1382 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1383 clock-names = "aclk", "iface"; 1384 #iommu-cells = <0>; 1385 power-domains = <&power RK3399_PD_VCODEC>; 1386 }; 1387 1388 vdec: video-codec@ff660000 { 1389 compatible = "rockchip,rk3399-vdec"; 1390 reg = <0x0 0xff660000 0x0 0x480>; 1391 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1392 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, 1393 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; 1394 clock-names = "axi", "ahb", "cabac", "core"; 1395 iommus = <&vdec_mmu>; 1396 power-domains = <&power RK3399_PD_VDU>; 1397 }; 1398 1399 vdec_mmu: iommu@ff660480 { 1400 compatible = "rockchip,iommu"; 1401 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; 1402 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1403 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; 1404 clock-names = "aclk", "iface"; 1405 power-domains = <&power RK3399_PD_VDU>; 1406 #iommu-cells = <0>; 1407 }; 1408 1409 iep_mmu: iommu@ff670800 { 1410 compatible = "rockchip,iommu"; 1411 reg = <0x0 0xff670800 0x0 0x40>; 1412 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>; 1413 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 1414 clock-names = "aclk", "iface"; 1415 #iommu-cells = <0>; 1416 status = "disabled"; 1417 }; 1418 1419 rga: rga@ff680000 { 1420 compatible = "rockchip,rk3399-rga"; 1421 reg = <0x0 0xff680000 0x0 0x10000>; 1422 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>; 1423 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; 1424 clock-names = "aclk", "hclk", "sclk"; 1425 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 1426 reset-names = "core", "axi", "ahb"; 1427 power-domains = <&power RK3399_PD_RGA>; 1428 }; 1429 1430 efuse0: efuse@ff690000 { 1431 compatible = "rockchip,rk3399-efuse"; 1432 reg = <0x0 0xff690000 0x0 0x80>; 1433 #address-cells = <1>; 1434 #size-cells = <1>; 1435 clocks = <&cru PCLK_EFUSE1024NS>; 1436 clock-names = "pclk_efuse"; 1437 1438 /* Data cells */ 1439 cpu_id: cpu-id@7 { 1440 reg = <0x07 0x10>; 1441 }; 1442 cpub_leakage: cpu-leakage@17 { 1443 reg = <0x17 0x1>; 1444 }; 1445 gpu_leakage: gpu-leakage@18 { 1446 reg = <0x18 0x1>; 1447 }; 1448 center_leakage: center-leakage@19 { 1449 reg = <0x19 0x1>; 1450 }; 1451 cpul_leakage: cpu-leakage@1a { 1452 reg = <0x1a 0x1>; 1453 }; 1454 logic_leakage: logic-leakage@1b { 1455 reg = <0x1b 0x1>; 1456 }; 1457 wafer_info: wafer-info@1c { 1458 reg = <0x1c 0x1>; 1459 }; 1460 }; 1461 1462 dmac_bus: dma-controller@ff6d0000 { 1463 compatible = "arm,pl330", "arm,primecell"; 1464 reg = <0x0 0xff6d0000 0x0 0x4000>; 1465 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 1466 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 1467 #dma-cells = <1>; 1468 arm,pl330-periph-burst; 1469 clocks = <&cru ACLK_DMAC0_PERILP>; 1470 clock-names = "apb_pclk"; 1471 }; 1472 1473 dmac_peri: dma-controller@ff6e0000 { 1474 compatible = "arm,pl330", "arm,primecell"; 1475 reg = <0x0 0xff6e0000 0x0 0x4000>; 1476 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 1477 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 1478 #dma-cells = <1>; 1479 arm,pl330-periph-burst; 1480 clocks = <&cru ACLK_DMAC1_PERILP>; 1481 clock-names = "apb_pclk"; 1482 }; 1483 1484 pmucru: clock-controller@ff750000 { 1485 compatible = "rockchip,rk3399-pmucru"; 1486 reg = <0x0 0xff750000 0x0 0x1000>; 1487 clocks = <&xin24m>; 1488 clock-names = "xin24m"; 1489 rockchip,grf = <&pmugrf>; 1490 #clock-cells = <1>; 1491 #reset-cells = <1>; 1492 assigned-clocks = <&pmucru PLL_PPLL>; 1493 assigned-clock-rates = <676000000>; 1494 }; 1495 1496 cru: clock-controller@ff760000 { 1497 compatible = "rockchip,rk3399-cru"; 1498 reg = <0x0 0xff760000 0x0 0x1000>; 1499 clocks = <&xin24m>; 1500 clock-names = "xin24m"; 1501 rockchip,grf = <&grf>; 1502 #clock-cells = <1>; 1503 #reset-cells = <1>; 1504 assigned-clocks = 1505 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1506 <&cru PLL_NPLL>, 1507 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1508 <&cru PCLK_PERIHP>, 1509 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1510 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1511 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 1512 <&cru ACLK_VIO>, <&cru ACLK_HDCP>, 1513 <&cru ACLK_GIC_PRE>, 1514 <&cru PCLK_DDR>, 1515 <&cru ACLK_VDU>; 1516 assigned-clock-rates = 1517 <594000000>, <800000000>, 1518 <1000000000>, 1519 <150000000>, <75000000>, 1520 <37500000>, 1521 <100000000>, <100000000>, 1522 <50000000>, <600000000>, 1523 <100000000>, <50000000>, 1524 <400000000>, <400000000>, 1525 <200000000>, 1526 <200000000>, 1527 <400000000>; 1528 }; 1529 1530 grf: syscon@ff770000 { 1531 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1532 reg = <0x0 0xff770000 0x0 0x10000>; 1533 #address-cells = <1>; 1534 #size-cells = <1>; 1535 1536 io_domains: io-domains { 1537 compatible = "rockchip,rk3399-io-voltage-domain"; 1538 status = "disabled"; 1539 }; 1540 1541 mipi_dphy_rx0: mipi-dphy-rx0 { 1542 compatible = "rockchip,rk3399-mipi-dphy-rx0"; 1543 clocks = <&cru SCLK_MIPIDPHY_REF>, 1544 <&cru SCLK_DPHY_RX0_CFG>, 1545 <&cru PCLK_VIO_GRF>; 1546 clock-names = "dphy-ref", "dphy-cfg", "grf"; 1547 power-domains = <&power RK3399_PD_VIO>; 1548 #phy-cells = <0>; 1549 status = "disabled"; 1550 }; 1551 1552 u2phy0: usb2phy@e450 { 1553 compatible = "rockchip,rk3399-usb2phy"; 1554 reg = <0xe450 0x10>; 1555 clocks = <&cru SCLK_USB2PHY0_REF>; 1556 clock-names = "phyclk"; 1557 #clock-cells = <0>; 1558 clock-output-names = "clk_usbphy0_480m"; 1559 status = "disabled"; 1560 1561 u2phy0_host: host-port { 1562 #phy-cells = <0>; 1563 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1564 interrupt-names = "linestate"; 1565 status = "disabled"; 1566 }; 1567 1568 u2phy0_otg: otg-port { 1569 #phy-cells = <0>; 1570 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1571 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1572 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1573 interrupt-names = "otg-bvalid", "otg-id", 1574 "linestate"; 1575 status = "disabled"; 1576 }; 1577 }; 1578 1579 u2phy1: usb2phy@e460 { 1580 compatible = "rockchip,rk3399-usb2phy"; 1581 reg = <0xe460 0x10>; 1582 clocks = <&cru SCLK_USB2PHY1_REF>; 1583 clock-names = "phyclk"; 1584 #clock-cells = <0>; 1585 clock-output-names = "clk_usbphy1_480m"; 1586 status = "disabled"; 1587 1588 u2phy1_host: host-port { 1589 #phy-cells = <0>; 1590 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1591 interrupt-names = "linestate"; 1592 status = "disabled"; 1593 }; 1594 1595 u2phy1_otg: otg-port { 1596 #phy-cells = <0>; 1597 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1598 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1599 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1600 interrupt-names = "otg-bvalid", "otg-id", 1601 "linestate"; 1602 status = "disabled"; 1603 }; 1604 }; 1605 1606 emmc_phy: phy@f780 { 1607 compatible = "rockchip,rk3399-emmc-phy"; 1608 reg = <0xf780 0x24>; 1609 clocks = <&sdhci>; 1610 clock-names = "emmcclk"; 1611 drive-impedance-ohm = <50>; 1612 #phy-cells = <0>; 1613 status = "disabled"; 1614 }; 1615 1616 pcie_phy: pcie-phy { 1617 compatible = "rockchip,rk3399-pcie-phy"; 1618 clocks = <&cru SCLK_PCIEPHY_REF>; 1619 clock-names = "refclk"; 1620 #phy-cells = <1>; 1621 resets = <&cru SRST_PCIEPHY>; 1622 reset-names = "phy"; 1623 status = "disabled"; 1624 }; 1625 }; 1626 1627 tcphy0: phy@ff7c0000 { 1628 compatible = "rockchip,rk3399-typec-phy"; 1629 reg = <0x0 0xff7c0000 0x0 0x40000>; 1630 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1631 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1632 clock-names = "tcpdcore", "tcpdphy-ref"; 1633 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1634 assigned-clock-rates = <50000000>; 1635 power-domains = <&power RK3399_PD_TCPD0>; 1636 resets = <&cru SRST_UPHY0>, 1637 <&cru SRST_UPHY0_PIPE_L00>, 1638 <&cru SRST_P_UPHY0_TCPHY>; 1639 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1640 rockchip,grf = <&grf>; 1641 status = "disabled"; 1642 1643 tcphy0_dp: dp-port { 1644 #phy-cells = <0>; 1645 }; 1646 1647 tcphy0_usb3: usb3-port { 1648 #phy-cells = <0>; 1649 }; 1650 }; 1651 1652 tcphy1: phy@ff800000 { 1653 compatible = "rockchip,rk3399-typec-phy"; 1654 reg = <0x0 0xff800000 0x0 0x40000>; 1655 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1656 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1657 clock-names = "tcpdcore", "tcpdphy-ref"; 1658 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1659 assigned-clock-rates = <50000000>; 1660 power-domains = <&power RK3399_PD_TCPD1>; 1661 resets = <&cru SRST_UPHY1>, 1662 <&cru SRST_UPHY1_PIPE_L00>, 1663 <&cru SRST_P_UPHY1_TCPHY>; 1664 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1665 rockchip,grf = <&grf>; 1666 status = "disabled"; 1667 1668 tcphy1_dp: dp-port { 1669 #phy-cells = <0>; 1670 }; 1671 1672 tcphy1_usb3: usb3-port { 1673 #phy-cells = <0>; 1674 }; 1675 }; 1676 1677 watchdog@ff848000 { 1678 compatible = "rockchip,rk3399-wdt", "snps,dw-wdt"; 1679 reg = <0x0 0xff848000 0x0 0x100>; 1680 clocks = <&cru PCLK_WDT>; 1681 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1682 }; 1683 1684 rktimer: rktimer@ff850000 { 1685 compatible = "rockchip,rk3399-timer"; 1686 reg = <0x0 0xff850000 0x0 0x1000>; 1687 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1688 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1689 clock-names = "pclk", "timer"; 1690 }; 1691 1692 spdif: spdif@ff870000 { 1693 compatible = "rockchip,rk3399-spdif"; 1694 reg = <0x0 0xff870000 0x0 0x1000>; 1695 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1696 dmas = <&dmac_bus 7>; 1697 dma-names = "tx"; 1698 clock-names = "mclk", "hclk"; 1699 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1700 pinctrl-names = "default"; 1701 pinctrl-0 = <&spdif_bus>; 1702 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1703 #sound-dai-cells = <0>; 1704 status = "disabled"; 1705 }; 1706 1707 i2s0: i2s@ff880000 { 1708 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1709 reg = <0x0 0xff880000 0x0 0x1000>; 1710 rockchip,grf = <&grf>; 1711 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1712 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1713 dma-names = "tx", "rx"; 1714 clock-names = "i2s_clk", "i2s_hclk"; 1715 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1716 pinctrl-names = "bclk_on", "bclk_off"; 1717 pinctrl-0 = <&i2s0_8ch_bus>; 1718 pinctrl-1 = <&i2s0_8ch_bus_bclk_off>; 1719 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1720 #sound-dai-cells = <0>; 1721 status = "disabled"; 1722 }; 1723 1724 i2s1: i2s@ff890000 { 1725 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1726 reg = <0x0 0xff890000 0x0 0x1000>; 1727 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1728 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1729 dma-names = "tx", "rx"; 1730 clock-names = "i2s_clk", "i2s_hclk"; 1731 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1732 pinctrl-names = "default"; 1733 pinctrl-0 = <&i2s1_2ch_bus>; 1734 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1735 #sound-dai-cells = <0>; 1736 status = "disabled"; 1737 }; 1738 1739 i2s2: i2s@ff8a0000 { 1740 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1741 reg = <0x0 0xff8a0000 0x0 0x1000>; 1742 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1743 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1744 dma-names = "tx", "rx"; 1745 clock-names = "i2s_clk", "i2s_hclk"; 1746 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1747 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1748 #sound-dai-cells = <0>; 1749 status = "disabled"; 1750 }; 1751 1752 vopl: vop@ff8f0000 { 1753 compatible = "rockchip,rk3399-vop-lit"; 1754 reg = <0x0 0xff8f0000 0x0 0x2000>, <0x0 0xff8f2000 0x0 0x400>; 1755 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1756 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1757 assigned-clock-rates = <400000000>, <100000000>; 1758 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1759 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1760 iommus = <&vopl_mmu>; 1761 power-domains = <&power RK3399_PD_VOPL>; 1762 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1763 reset-names = "axi", "ahb", "dclk"; 1764 status = "disabled"; 1765 1766 vopl_out: port { 1767 #address-cells = <1>; 1768 #size-cells = <0>; 1769 1770 vopl_out_mipi: endpoint@0 { 1771 reg = <0>; 1772 remote-endpoint = <&mipi_in_vopl>; 1773 }; 1774 1775 vopl_out_edp: endpoint@1 { 1776 reg = <1>; 1777 remote-endpoint = <&edp_in_vopl>; 1778 }; 1779 1780 vopl_out_hdmi: endpoint@2 { 1781 reg = <2>; 1782 remote-endpoint = <&hdmi_in_vopl>; 1783 }; 1784 1785 vopl_out_mipi1: endpoint@3 { 1786 reg = <3>; 1787 remote-endpoint = <&mipi1_in_vopl>; 1788 }; 1789 1790 vopl_out_dp: endpoint@4 { 1791 reg = <4>; 1792 remote-endpoint = <&dp_in_vopl>; 1793 }; 1794 }; 1795 }; 1796 1797 vopl_mmu: iommu@ff8f3f00 { 1798 compatible = "rockchip,iommu"; 1799 reg = <0x0 0xff8f3f00 0x0 0x100>; 1800 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1801 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1802 clock-names = "aclk", "iface"; 1803 power-domains = <&power RK3399_PD_VOPL>; 1804 #iommu-cells = <0>; 1805 status = "disabled"; 1806 }; 1807 1808 vopb: vop@ff900000 { 1809 compatible = "rockchip,rk3399-vop-big"; 1810 reg = <0x0 0xff900000 0x0 0x2000>, <0x0 0xff902000 0x0 0x1000>; 1811 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1812 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1813 assigned-clock-rates = <400000000>, <100000000>; 1814 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1815 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1816 iommus = <&vopb_mmu>; 1817 power-domains = <&power RK3399_PD_VOPB>; 1818 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1819 reset-names = "axi", "ahb", "dclk"; 1820 status = "disabled"; 1821 1822 vopb_out: port { 1823 #address-cells = <1>; 1824 #size-cells = <0>; 1825 1826 vopb_out_edp: endpoint@0 { 1827 reg = <0>; 1828 remote-endpoint = <&edp_in_vopb>; 1829 }; 1830 1831 vopb_out_mipi: endpoint@1 { 1832 reg = <1>; 1833 remote-endpoint = <&mipi_in_vopb>; 1834 }; 1835 1836 vopb_out_hdmi: endpoint@2 { 1837 reg = <2>; 1838 remote-endpoint = <&hdmi_in_vopb>; 1839 }; 1840 1841 vopb_out_mipi1: endpoint@3 { 1842 reg = <3>; 1843 remote-endpoint = <&mipi1_in_vopb>; 1844 }; 1845 1846 vopb_out_dp: endpoint@4 { 1847 reg = <4>; 1848 remote-endpoint = <&dp_in_vopb>; 1849 }; 1850 }; 1851 }; 1852 1853 vopb_mmu: iommu@ff903f00 { 1854 compatible = "rockchip,iommu"; 1855 reg = <0x0 0xff903f00 0x0 0x100>; 1856 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1857 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1858 clock-names = "aclk", "iface"; 1859 power-domains = <&power RK3399_PD_VOPB>; 1860 #iommu-cells = <0>; 1861 status = "disabled"; 1862 }; 1863 1864 isp0: isp0@ff910000 { 1865 compatible = "rockchip,rk3399-cif-isp"; 1866 reg = <0x0 0xff910000 0x0 0x4000>; 1867 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1868 clocks = <&cru SCLK_ISP0>, 1869 <&cru ACLK_ISP0_WRAPPER>, 1870 <&cru HCLK_ISP0_WRAPPER>; 1871 clock-names = "isp", "aclk", "hclk"; 1872 iommus = <&isp0_mmu>; 1873 phys = <&mipi_dphy_rx0>; 1874 phy-names = "dphy"; 1875 power-domains = <&power RK3399_PD_ISP0>; 1876 status = "disabled"; 1877 1878 ports { 1879 #address-cells = <1>; 1880 #size-cells = <0>; 1881 1882 port@0 { 1883 reg = <0>; 1884 #address-cells = <1>; 1885 #size-cells = <0>; 1886 }; 1887 }; 1888 }; 1889 1890 isp0_mmu: iommu@ff914000 { 1891 compatible = "rockchip,iommu"; 1892 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1893 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1894 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; 1895 clock-names = "aclk", "iface"; 1896 #iommu-cells = <0>; 1897 power-domains = <&power RK3399_PD_ISP0>; 1898 rockchip,disable-mmu-reset; 1899 }; 1900 1901 isp1: isp1@ff920000 { 1902 compatible = "rockchip,rk3399-cif-isp"; 1903 reg = <0x0 0xff920000 0x0 0x4000>; 1904 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 1905 clocks = <&cru SCLK_ISP1>, 1906 <&cru ACLK_ISP1_WRAPPER>, 1907 <&cru HCLK_ISP1_WRAPPER>; 1908 clock-names = "isp", "aclk", "hclk"; 1909 iommus = <&isp1_mmu>; 1910 phys = <&mipi_dsi1>; 1911 phy-names = "dphy"; 1912 power-domains = <&power RK3399_PD_ISP1>; 1913 status = "disabled"; 1914 1915 ports { 1916 #address-cells = <1>; 1917 #size-cells = <0>; 1918 1919 port@0 { 1920 reg = <0>; 1921 #address-cells = <1>; 1922 #size-cells = <0>; 1923 }; 1924 }; 1925 }; 1926 1927 isp1_mmu: iommu@ff924000 { 1928 compatible = "rockchip,iommu"; 1929 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; 1930 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 1931 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; 1932 clock-names = "aclk", "iface"; 1933 #iommu-cells = <0>; 1934 power-domains = <&power RK3399_PD_ISP1>; 1935 rockchip,disable-mmu-reset; 1936 }; 1937 1938 hdmi_sound: hdmi-sound { 1939 compatible = "simple-audio-card"; 1940 simple-audio-card,format = "i2s"; 1941 simple-audio-card,mclk-fs = <256>; 1942 simple-audio-card,name = "hdmi-sound"; 1943 status = "disabled"; 1944 1945 simple-audio-card,cpu { 1946 sound-dai = <&i2s2>; 1947 }; 1948 simple-audio-card,codec { 1949 sound-dai = <&hdmi>; 1950 }; 1951 }; 1952 1953 hdmi: hdmi@ff940000 { 1954 compatible = "rockchip,rk3399-dw-hdmi"; 1955 reg = <0x0 0xff940000 0x0 0x20000>; 1956 reg-io-width = <4>; 1957 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 1958 clocks = <&cru PCLK_HDMI_CTRL>, 1959 <&cru SCLK_HDMI_SFR>, 1960 <&cru SCLK_HDMI_CEC>, 1961 <&cru PCLK_VIO_GRF>, 1962 <&cru PLL_VPLL>; 1963 clock-names = "iahb", "isfr", "cec", "grf", "ref"; 1964 power-domains = <&power RK3399_PD_HDCP>; 1965 rockchip,grf = <&grf>; 1966 #sound-dai-cells = <0>; 1967 status = "disabled"; 1968 1969 ports { 1970 #address-cells = <1>; 1971 #size-cells = <0>; 1972 1973 hdmi_in: port@0 { 1974 reg = <0>; 1975 #address-cells = <1>; 1976 #size-cells = <0>; 1977 1978 hdmi_in_vopb: endpoint@0 { 1979 reg = <0>; 1980 remote-endpoint = <&vopb_out_hdmi>; 1981 }; 1982 hdmi_in_vopl: endpoint@1 { 1983 reg = <1>; 1984 remote-endpoint = <&vopl_out_hdmi>; 1985 }; 1986 }; 1987 1988 hdmi_out: port@1 { 1989 reg = <1>; 1990 }; 1991 }; 1992 }; 1993 1994 mipi_dsi: dsi@ff960000 { 1995 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1996 reg = <0x0 0xff960000 0x0 0x8000>; 1997 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 1998 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, 1999 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; 2000 clock-names = "ref", "pclk", "phy_cfg", "grf"; 2001 power-domains = <&power RK3399_PD_VIO>; 2002 resets = <&cru SRST_P_MIPI_DSI0>; 2003 reset-names = "apb"; 2004 rockchip,grf = <&grf>; 2005 #address-cells = <1>; 2006 #size-cells = <0>; 2007 status = "disabled"; 2008 2009 ports { 2010 #address-cells = <1>; 2011 #size-cells = <0>; 2012 2013 mipi_in: port@0 { 2014 reg = <0>; 2015 #address-cells = <1>; 2016 #size-cells = <0>; 2017 2018 mipi_in_vopb: endpoint@0 { 2019 reg = <0>; 2020 remote-endpoint = <&vopb_out_mipi>; 2021 }; 2022 2023 mipi_in_vopl: endpoint@1 { 2024 reg = <1>; 2025 remote-endpoint = <&vopl_out_mipi>; 2026 }; 2027 }; 2028 2029 mipi_out: port@1 { 2030 reg = <1>; 2031 }; 2032 }; 2033 }; 2034 2035 mipi_dsi1: dsi@ff968000 { 2036 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 2037 reg = <0x0 0xff968000 0x0 0x8000>; 2038 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>; 2039 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, 2040 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; 2041 clock-names = "ref", "pclk", "phy_cfg", "grf"; 2042 power-domains = <&power RK3399_PD_VIO>; 2043 resets = <&cru SRST_P_MIPI_DSI1>; 2044 reset-names = "apb"; 2045 rockchip,grf = <&grf>; 2046 #address-cells = <1>; 2047 #size-cells = <0>; 2048 #phy-cells = <0>; 2049 status = "disabled"; 2050 2051 ports { 2052 #address-cells = <1>; 2053 #size-cells = <0>; 2054 2055 mipi1_in: port@0 { 2056 reg = <0>; 2057 #address-cells = <1>; 2058 #size-cells = <0>; 2059 2060 mipi1_in_vopb: endpoint@0 { 2061 reg = <0>; 2062 remote-endpoint = <&vopb_out_mipi1>; 2063 }; 2064 2065 mipi1_in_vopl: endpoint@1 { 2066 reg = <1>; 2067 remote-endpoint = <&vopl_out_mipi1>; 2068 }; 2069 }; 2070 2071 mipi1_out: port@1 { 2072 reg = <1>; 2073 }; 2074 }; 2075 }; 2076 2077 edp: dp@ff970000 { 2078 compatible = "rockchip,rk3399-edp"; 2079 reg = <0x0 0xff970000 0x0 0x8000>; 2080 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 2081 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; 2082 clock-names = "dp", "pclk", "grf"; 2083 pinctrl-names = "default"; 2084 pinctrl-0 = <&edp_hpd>; 2085 power-domains = <&power RK3399_PD_EDP>; 2086 resets = <&cru SRST_P_EDP_CTRL>; 2087 reset-names = "dp"; 2088 rockchip,grf = <&grf>; 2089 status = "disabled"; 2090 2091 ports { 2092 #address-cells = <1>; 2093 #size-cells = <0>; 2094 2095 edp_in: port@0 { 2096 reg = <0>; 2097 #address-cells = <1>; 2098 #size-cells = <0>; 2099 2100 edp_in_vopb: endpoint@0 { 2101 reg = <0>; 2102 remote-endpoint = <&vopb_out_edp>; 2103 }; 2104 2105 edp_in_vopl: endpoint@1 { 2106 reg = <1>; 2107 remote-endpoint = <&vopl_out_edp>; 2108 }; 2109 }; 2110 2111 edp_out: port@1 { 2112 reg = <1>; 2113 }; 2114 }; 2115 }; 2116 2117 gpu: gpu@ff9a0000 { 2118 compatible = "rockchip,rk3399-mali", "arm,mali-t860"; 2119 reg = <0x0 0xff9a0000 0x0 0x10000>; 2120 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, 2121 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>, 2122 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>; 2123 interrupt-names = "job", "mmu", "gpu"; 2124 clocks = <&cru ACLK_GPU>; 2125 #cooling-cells = <2>; 2126 power-domains = <&power RK3399_PD_GPU>; 2127 status = "disabled"; 2128 }; 2129 2130 pinctrl: pinctrl { 2131 compatible = "rockchip,rk3399-pinctrl"; 2132 rockchip,grf = <&grf>; 2133 rockchip,pmu = <&pmugrf>; 2134 #address-cells = <2>; 2135 #size-cells = <2>; 2136 ranges; 2137 2138 gpio0: gpio@ff720000 { 2139 compatible = "rockchip,gpio-bank"; 2140 reg = <0x0 0xff720000 0x0 0x100>; 2141 clocks = <&pmucru PCLK_GPIO0_PMU>; 2142 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 2143 2144 gpio-controller; 2145 #gpio-cells = <0x2>; 2146 2147 interrupt-controller; 2148 #interrupt-cells = <0x2>; 2149 }; 2150 2151 gpio1: gpio@ff730000 { 2152 compatible = "rockchip,gpio-bank"; 2153 reg = <0x0 0xff730000 0x0 0x100>; 2154 clocks = <&pmucru PCLK_GPIO1_PMU>; 2155 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 2156 2157 gpio-controller; 2158 #gpio-cells = <0x2>; 2159 2160 interrupt-controller; 2161 #interrupt-cells = <0x2>; 2162 }; 2163 2164 gpio2: gpio@ff780000 { 2165 compatible = "rockchip,gpio-bank"; 2166 reg = <0x0 0xff780000 0x0 0x100>; 2167 clocks = <&cru PCLK_GPIO2>; 2168 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 2169 2170 gpio-controller; 2171 #gpio-cells = <0x2>; 2172 2173 interrupt-controller; 2174 #interrupt-cells = <0x2>; 2175 }; 2176 2177 gpio3: gpio@ff788000 { 2178 compatible = "rockchip,gpio-bank"; 2179 reg = <0x0 0xff788000 0x0 0x100>; 2180 clocks = <&cru PCLK_GPIO3>; 2181 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 2182 2183 gpio-controller; 2184 #gpio-cells = <0x2>; 2185 2186 interrupt-controller; 2187 #interrupt-cells = <0x2>; 2188 }; 2189 2190 gpio4: gpio@ff790000 { 2191 compatible = "rockchip,gpio-bank"; 2192 reg = <0x0 0xff790000 0x0 0x100>; 2193 clocks = <&cru PCLK_GPIO4>; 2194 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 2195 2196 gpio-controller; 2197 #gpio-cells = <0x2>; 2198 2199 interrupt-controller; 2200 #interrupt-cells = <0x2>; 2201 }; 2202 2203 pcfg_pull_up: pcfg-pull-up { 2204 bias-pull-up; 2205 }; 2206 2207 pcfg_pull_down: pcfg-pull-down { 2208 bias-pull-down; 2209 }; 2210 2211 pcfg_pull_none: pcfg-pull-none { 2212 bias-disable; 2213 }; 2214 2215 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 2216 bias-disable; 2217 drive-strength = <12>; 2218 }; 2219 2220 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 2221 bias-disable; 2222 drive-strength = <13>; 2223 }; 2224 2225 pcfg_pull_none_18ma: pcfg-pull-none-18ma { 2226 bias-disable; 2227 drive-strength = <18>; 2228 }; 2229 2230 pcfg_pull_none_20ma: pcfg-pull-none-20ma { 2231 bias-disable; 2232 drive-strength = <20>; 2233 }; 2234 2235 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 2236 bias-pull-up; 2237 drive-strength = <2>; 2238 }; 2239 2240 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 2241 bias-pull-up; 2242 drive-strength = <8>; 2243 }; 2244 2245 pcfg_pull_up_18ma: pcfg-pull-up-18ma { 2246 bias-pull-up; 2247 drive-strength = <18>; 2248 }; 2249 2250 pcfg_pull_up_20ma: pcfg-pull-up-20ma { 2251 bias-pull-up; 2252 drive-strength = <20>; 2253 }; 2254 2255 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 2256 bias-pull-down; 2257 drive-strength = <4>; 2258 }; 2259 2260 pcfg_pull_down_8ma: pcfg-pull-down-8ma { 2261 bias-pull-down; 2262 drive-strength = <8>; 2263 }; 2264 2265 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 2266 bias-pull-down; 2267 drive-strength = <12>; 2268 }; 2269 2270 pcfg_pull_down_18ma: pcfg-pull-down-18ma { 2271 bias-pull-down; 2272 drive-strength = <18>; 2273 }; 2274 2275 pcfg_pull_down_20ma: pcfg-pull-down-20ma { 2276 bias-pull-down; 2277 drive-strength = <20>; 2278 }; 2279 2280 pcfg_output_high: pcfg-output-high { 2281 output-high; 2282 }; 2283 2284 pcfg_output_low: pcfg-output-low { 2285 output-low; 2286 }; 2287 2288 pcfg_input_enable: pcfg-input-enable { 2289 input-enable; 2290 }; 2291 2292 pcfg_input_pull_up: pcfg-input-pull-up { 2293 input-enable; 2294 bias-pull-up; 2295 }; 2296 2297 pcfg_input_pull_down: pcfg-input-pull-down { 2298 input-enable; 2299 bias-pull-down; 2300 }; 2301 2302 clock { 2303 clk_32k: clk-32k { 2304 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; 2305 }; 2306 }; 2307 2308 cif { 2309 cif_clkin: cif-clkin { 2310 rockchip,pins = 2311 <2 RK_PB2 3 &pcfg_pull_none>; 2312 }; 2313 2314 cif_clkouta: cif-clkouta { 2315 rockchip,pins = 2316 <2 RK_PB3 3 &pcfg_pull_none>; 2317 }; 2318 }; 2319 2320 edp { 2321 edp_hpd: edp-hpd { 2322 rockchip,pins = 2323 <4 RK_PC7 2 &pcfg_pull_none>; 2324 }; 2325 }; 2326 2327 gmac { 2328 rgmii_pins: rgmii-pins { 2329 rockchip,pins = 2330 /* mac_txclk */ 2331 <3 RK_PC1 1 &pcfg_pull_none_13ma>, 2332 /* mac_rxclk */ 2333 <3 RK_PB6 1 &pcfg_pull_none>, 2334 /* mac_mdio */ 2335 <3 RK_PB5 1 &pcfg_pull_none>, 2336 /* mac_txen */ 2337 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2338 /* mac_clk */ 2339 <3 RK_PB3 1 &pcfg_pull_none>, 2340 /* mac_rxdv */ 2341 <3 RK_PB1 1 &pcfg_pull_none>, 2342 /* mac_mdc */ 2343 <3 RK_PB0 1 &pcfg_pull_none>, 2344 /* mac_rxd1 */ 2345 <3 RK_PA7 1 &pcfg_pull_none>, 2346 /* mac_rxd0 */ 2347 <3 RK_PA6 1 &pcfg_pull_none>, 2348 /* mac_txd1 */ 2349 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2350 /* mac_txd0 */ 2351 <3 RK_PA4 1 &pcfg_pull_none_13ma>, 2352 /* mac_rxd3 */ 2353 <3 RK_PA3 1 &pcfg_pull_none>, 2354 /* mac_rxd2 */ 2355 <3 RK_PA2 1 &pcfg_pull_none>, 2356 /* mac_txd3 */ 2357 <3 RK_PA1 1 &pcfg_pull_none_13ma>, 2358 /* mac_txd2 */ 2359 <3 RK_PA0 1 &pcfg_pull_none_13ma>; 2360 }; 2361 2362 rmii_pins: rmii-pins { 2363 rockchip,pins = 2364 /* mac_mdio */ 2365 <3 RK_PB5 1 &pcfg_pull_none>, 2366 /* mac_txen */ 2367 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2368 /* mac_clk */ 2369 <3 RK_PB3 1 &pcfg_pull_none>, 2370 /* mac_rxer */ 2371 <3 RK_PB2 1 &pcfg_pull_none>, 2372 /* mac_rxdv */ 2373 <3 RK_PB1 1 &pcfg_pull_none>, 2374 /* mac_mdc */ 2375 <3 RK_PB0 1 &pcfg_pull_none>, 2376 /* mac_rxd1 */ 2377 <3 RK_PA7 1 &pcfg_pull_none>, 2378 /* mac_rxd0 */ 2379 <3 RK_PA6 1 &pcfg_pull_none>, 2380 /* mac_txd1 */ 2381 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2382 /* mac_txd0 */ 2383 <3 RK_PA4 1 &pcfg_pull_none_13ma>; 2384 }; 2385 }; 2386 2387 i2c0 { 2388 i2c0_xfer: i2c0-xfer { 2389 rockchip,pins = 2390 <1 RK_PB7 2 &pcfg_pull_none>, 2391 <1 RK_PC0 2 &pcfg_pull_none>; 2392 }; 2393 }; 2394 2395 i2c1 { 2396 i2c1_xfer: i2c1-xfer { 2397 rockchip,pins = 2398 <4 RK_PA2 1 &pcfg_pull_none>, 2399 <4 RK_PA1 1 &pcfg_pull_none>; 2400 }; 2401 }; 2402 2403 i2c2 { 2404 i2c2_xfer: i2c2-xfer { 2405 rockchip,pins = 2406 <2 RK_PA1 2 &pcfg_pull_none_12ma>, 2407 <2 RK_PA0 2 &pcfg_pull_none_12ma>; 2408 }; 2409 }; 2410 2411 i2c3 { 2412 i2c3_xfer: i2c3-xfer { 2413 rockchip,pins = 2414 <4 RK_PC1 1 &pcfg_pull_none>, 2415 <4 RK_PC0 1 &pcfg_pull_none>; 2416 }; 2417 }; 2418 2419 i2c4 { 2420 i2c4_xfer: i2c4-xfer { 2421 rockchip,pins = 2422 <1 RK_PB4 1 &pcfg_pull_none>, 2423 <1 RK_PB3 1 &pcfg_pull_none>; 2424 }; 2425 }; 2426 2427 i2c5 { 2428 i2c5_xfer: i2c5-xfer { 2429 rockchip,pins = 2430 <3 RK_PB3 2 &pcfg_pull_none>, 2431 <3 RK_PB2 2 &pcfg_pull_none>; 2432 }; 2433 }; 2434 2435 i2c6 { 2436 i2c6_xfer: i2c6-xfer { 2437 rockchip,pins = 2438 <2 RK_PB2 2 &pcfg_pull_none>, 2439 <2 RK_PB1 2 &pcfg_pull_none>; 2440 }; 2441 }; 2442 2443 i2c7 { 2444 i2c7_xfer: i2c7-xfer { 2445 rockchip,pins = 2446 <2 RK_PB0 2 &pcfg_pull_none>, 2447 <2 RK_PA7 2 &pcfg_pull_none>; 2448 }; 2449 }; 2450 2451 i2c8 { 2452 i2c8_xfer: i2c8-xfer { 2453 rockchip,pins = 2454 <1 RK_PC5 1 &pcfg_pull_none>, 2455 <1 RK_PC4 1 &pcfg_pull_none>; 2456 }; 2457 }; 2458 2459 i2s0 { 2460 i2s0_2ch_bus: i2s0-2ch-bus { 2461 rockchip,pins = 2462 <3 RK_PD0 1 &pcfg_pull_none>, 2463 <3 RK_PD1 1 &pcfg_pull_none>, 2464 <3 RK_PD2 1 &pcfg_pull_none>, 2465 <3 RK_PD3 1 &pcfg_pull_none>, 2466 <3 RK_PD7 1 &pcfg_pull_none>, 2467 <4 RK_PA0 1 &pcfg_pull_none>; 2468 }; 2469 2470 i2s0_2ch_bus_bclk_off: i2s0-2ch-bus-bclk-off { 2471 rockchip,pins = 2472 <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, 2473 <3 RK_PD1 1 &pcfg_pull_none>, 2474 <3 RK_PD2 1 &pcfg_pull_none>, 2475 <3 RK_PD3 1 &pcfg_pull_none>, 2476 <3 RK_PD7 1 &pcfg_pull_none>, 2477 <4 RK_PA0 1 &pcfg_pull_none>; 2478 }; 2479 2480 i2s0_8ch_bus: i2s0-8ch-bus { 2481 rockchip,pins = 2482 <3 RK_PD0 1 &pcfg_pull_none>, 2483 <3 RK_PD1 1 &pcfg_pull_none>, 2484 <3 RK_PD2 1 &pcfg_pull_none>, 2485 <3 RK_PD3 1 &pcfg_pull_none>, 2486 <3 RK_PD4 1 &pcfg_pull_none>, 2487 <3 RK_PD5 1 &pcfg_pull_none>, 2488 <3 RK_PD6 1 &pcfg_pull_none>, 2489 <3 RK_PD7 1 &pcfg_pull_none>, 2490 <4 RK_PA0 1 &pcfg_pull_none>; 2491 }; 2492 2493 i2s0_8ch_bus_bclk_off: i2s0-8ch-bus-bclk-off { 2494 rockchip,pins = 2495 <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, 2496 <3 RK_PD1 1 &pcfg_pull_none>, 2497 <3 RK_PD2 1 &pcfg_pull_none>, 2498 <3 RK_PD3 1 &pcfg_pull_none>, 2499 <3 RK_PD4 1 &pcfg_pull_none>, 2500 <3 RK_PD5 1 &pcfg_pull_none>, 2501 <3 RK_PD6 1 &pcfg_pull_none>, 2502 <3 RK_PD7 1 &pcfg_pull_none>, 2503 <4 RK_PA0 1 &pcfg_pull_none>; 2504 }; 2505 }; 2506 2507 i2s1 { 2508 i2s1_2ch_bus: i2s1-2ch-bus { 2509 rockchip,pins = 2510 <4 RK_PA3 1 &pcfg_pull_none>, 2511 <4 RK_PA4 1 &pcfg_pull_none>, 2512 <4 RK_PA5 1 &pcfg_pull_none>, 2513 <4 RK_PA6 1 &pcfg_pull_none>, 2514 <4 RK_PA7 1 &pcfg_pull_none>; 2515 }; 2516 2517 i2s1_2ch_bus_bclk_off: i2s1-2ch-bus-bclk-off { 2518 rockchip,pins = 2519 <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>, 2520 <4 RK_PA4 1 &pcfg_pull_none>, 2521 <4 RK_PA5 1 &pcfg_pull_none>, 2522 <4 RK_PA6 1 &pcfg_pull_none>, 2523 <4 RK_PA7 1 &pcfg_pull_none>; 2524 }; 2525 }; 2526 2527 sdio0 { 2528 sdio0_bus1: sdio0-bus1 { 2529 rockchip,pins = 2530 <2 RK_PC4 1 &pcfg_pull_up>; 2531 }; 2532 2533 sdio0_bus4: sdio0-bus4 { 2534 rockchip,pins = 2535 <2 RK_PC4 1 &pcfg_pull_up>, 2536 <2 RK_PC5 1 &pcfg_pull_up>, 2537 <2 RK_PC6 1 &pcfg_pull_up>, 2538 <2 RK_PC7 1 &pcfg_pull_up>; 2539 }; 2540 2541 sdio0_cmd: sdio0-cmd { 2542 rockchip,pins = 2543 <2 RK_PD0 1 &pcfg_pull_up>; 2544 }; 2545 2546 sdio0_clk: sdio0-clk { 2547 rockchip,pins = 2548 <2 RK_PD1 1 &pcfg_pull_none>; 2549 }; 2550 2551 sdio0_cd: sdio0-cd { 2552 rockchip,pins = 2553 <2 RK_PD2 1 &pcfg_pull_up>; 2554 }; 2555 2556 sdio0_pwr: sdio0-pwr { 2557 rockchip,pins = 2558 <2 RK_PD3 1 &pcfg_pull_up>; 2559 }; 2560 2561 sdio0_bkpwr: sdio0-bkpwr { 2562 rockchip,pins = 2563 <2 RK_PD4 1 &pcfg_pull_up>; 2564 }; 2565 2566 sdio0_wp: sdio0-wp { 2567 rockchip,pins = 2568 <0 RK_PA3 1 &pcfg_pull_up>; 2569 }; 2570 2571 sdio0_int: sdio0-int { 2572 rockchip,pins = 2573 <0 RK_PA4 1 &pcfg_pull_up>; 2574 }; 2575 }; 2576 2577 sdmmc { 2578 sdmmc_bus1: sdmmc-bus1 { 2579 rockchip,pins = 2580 <4 RK_PB0 1 &pcfg_pull_up>; 2581 }; 2582 2583 sdmmc_bus4: sdmmc-bus4 { 2584 rockchip,pins = 2585 <4 RK_PB0 1 &pcfg_pull_up>, 2586 <4 RK_PB1 1 &pcfg_pull_up>, 2587 <4 RK_PB2 1 &pcfg_pull_up>, 2588 <4 RK_PB3 1 &pcfg_pull_up>; 2589 }; 2590 2591 sdmmc_clk: sdmmc-clk { 2592 rockchip,pins = 2593 <4 RK_PB4 1 &pcfg_pull_none>; 2594 }; 2595 2596 sdmmc_cmd: sdmmc-cmd { 2597 rockchip,pins = 2598 <4 RK_PB5 1 &pcfg_pull_up>; 2599 }; 2600 2601 sdmmc_cd: sdmmc-cd { 2602 rockchip,pins = 2603 <0 RK_PA7 1 &pcfg_pull_up>; 2604 }; 2605 2606 sdmmc_wp: sdmmc-wp { 2607 rockchip,pins = 2608 <0 RK_PB0 1 &pcfg_pull_up>; 2609 }; 2610 }; 2611 2612 suspend { 2613 ap_pwroff: ap-pwroff { 2614 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>; 2615 }; 2616 2617 ddrio_pwroff: ddrio-pwroff { 2618 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; 2619 }; 2620 }; 2621 2622 spdif { 2623 spdif_bus: spdif-bus { 2624 rockchip,pins = 2625 <4 RK_PC5 1 &pcfg_pull_none>; 2626 }; 2627 2628 spdif_bus_1: spdif-bus-1 { 2629 rockchip,pins = 2630 <3 RK_PC0 3 &pcfg_pull_none>; 2631 }; 2632 }; 2633 2634 spi0 { 2635 spi0_clk: spi0-clk { 2636 rockchip,pins = 2637 <3 RK_PA6 2 &pcfg_pull_up>; 2638 }; 2639 spi0_cs0: spi0-cs0 { 2640 rockchip,pins = 2641 <3 RK_PA7 2 &pcfg_pull_up>; 2642 }; 2643 spi0_cs1: spi0-cs1 { 2644 rockchip,pins = 2645 <3 RK_PB0 2 &pcfg_pull_up>; 2646 }; 2647 spi0_tx: spi0-tx { 2648 rockchip,pins = 2649 <3 RK_PA5 2 &pcfg_pull_up>; 2650 }; 2651 spi0_rx: spi0-rx { 2652 rockchip,pins = 2653 <3 RK_PA4 2 &pcfg_pull_up>; 2654 }; 2655 }; 2656 2657 spi1 { 2658 spi1_clk: spi1-clk { 2659 rockchip,pins = 2660 <1 RK_PB1 2 &pcfg_pull_up>; 2661 }; 2662 spi1_cs0: spi1-cs0 { 2663 rockchip,pins = 2664 <1 RK_PB2 2 &pcfg_pull_up>; 2665 }; 2666 spi1_rx: spi1-rx { 2667 rockchip,pins = 2668 <1 RK_PA7 2 &pcfg_pull_up>; 2669 }; 2670 spi1_tx: spi1-tx { 2671 rockchip,pins = 2672 <1 RK_PB0 2 &pcfg_pull_up>; 2673 }; 2674 }; 2675 2676 spi2 { 2677 spi2_clk: spi2-clk { 2678 rockchip,pins = 2679 <2 RK_PB3 1 &pcfg_pull_up>; 2680 }; 2681 spi2_cs0: spi2-cs0 { 2682 rockchip,pins = 2683 <2 RK_PB4 1 &pcfg_pull_up>; 2684 }; 2685 spi2_rx: spi2-rx { 2686 rockchip,pins = 2687 <2 RK_PB1 1 &pcfg_pull_up>; 2688 }; 2689 spi2_tx: spi2-tx { 2690 rockchip,pins = 2691 <2 RK_PB2 1 &pcfg_pull_up>; 2692 }; 2693 }; 2694 2695 spi3 { 2696 spi3_clk: spi3-clk { 2697 rockchip,pins = 2698 <1 RK_PC1 1 &pcfg_pull_up>; 2699 }; 2700 spi3_cs0: spi3-cs0 { 2701 rockchip,pins = 2702 <1 RK_PC2 1 &pcfg_pull_up>; 2703 }; 2704 spi3_rx: spi3-rx { 2705 rockchip,pins = 2706 <1 RK_PB7 1 &pcfg_pull_up>; 2707 }; 2708 spi3_tx: spi3-tx { 2709 rockchip,pins = 2710 <1 RK_PC0 1 &pcfg_pull_up>; 2711 }; 2712 }; 2713 2714 spi4 { 2715 spi4_clk: spi4-clk { 2716 rockchip,pins = 2717 <3 RK_PA2 2 &pcfg_pull_up>; 2718 }; 2719 spi4_cs0: spi4-cs0 { 2720 rockchip,pins = 2721 <3 RK_PA3 2 &pcfg_pull_up>; 2722 }; 2723 spi4_rx: spi4-rx { 2724 rockchip,pins = 2725 <3 RK_PA0 2 &pcfg_pull_up>; 2726 }; 2727 spi4_tx: spi4-tx { 2728 rockchip,pins = 2729 <3 RK_PA1 2 &pcfg_pull_up>; 2730 }; 2731 }; 2732 2733 spi5 { 2734 spi5_clk: spi5-clk { 2735 rockchip,pins = 2736 <2 RK_PC6 2 &pcfg_pull_up>; 2737 }; 2738 spi5_cs0: spi5-cs0 { 2739 rockchip,pins = 2740 <2 RK_PC7 2 &pcfg_pull_up>; 2741 }; 2742 spi5_rx: spi5-rx { 2743 rockchip,pins = 2744 <2 RK_PC4 2 &pcfg_pull_up>; 2745 }; 2746 spi5_tx: spi5-tx { 2747 rockchip,pins = 2748 <2 RK_PC5 2 &pcfg_pull_up>; 2749 }; 2750 }; 2751 2752 testclk { 2753 test_clkout0: test-clkout0 { 2754 rockchip,pins = 2755 <0 RK_PA0 1 &pcfg_pull_none>; 2756 }; 2757 2758 test_clkout1: test-clkout1 { 2759 rockchip,pins = 2760 <2 RK_PD1 2 &pcfg_pull_none>; 2761 }; 2762 2763 test_clkout2: test-clkout2 { 2764 rockchip,pins = 2765 <0 RK_PB0 3 &pcfg_pull_none>; 2766 }; 2767 }; 2768 2769 tsadc { 2770 otp_pin: otp-pin { 2771 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 2772 }; 2773 2774 otp_out: otp-out { 2775 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; 2776 }; 2777 }; 2778 2779 uart0 { 2780 uart0_xfer: uart0-xfer { 2781 rockchip,pins = 2782 <2 RK_PC0 1 &pcfg_pull_up>, 2783 <2 RK_PC1 1 &pcfg_pull_none>; 2784 }; 2785 2786 uart0_cts: uart0-cts { 2787 rockchip,pins = 2788 <2 RK_PC2 1 &pcfg_pull_none>; 2789 }; 2790 2791 uart0_rts: uart0-rts { 2792 rockchip,pins = 2793 <2 RK_PC3 1 &pcfg_pull_none>; 2794 }; 2795 }; 2796 2797 uart1 { 2798 uart1_xfer: uart1-xfer { 2799 rockchip,pins = 2800 <3 RK_PB4 2 &pcfg_pull_up>, 2801 <3 RK_PB5 2 &pcfg_pull_none>; 2802 }; 2803 }; 2804 2805 uart2a { 2806 uart2a_xfer: uart2a-xfer { 2807 rockchip,pins = 2808 <4 RK_PB0 2 &pcfg_pull_up>, 2809 <4 RK_PB1 2 &pcfg_pull_none>; 2810 }; 2811 }; 2812 2813 uart2b { 2814 uart2b_xfer: uart2b-xfer { 2815 rockchip,pins = 2816 <4 RK_PC0 2 &pcfg_pull_up>, 2817 <4 RK_PC1 2 &pcfg_pull_none>; 2818 }; 2819 }; 2820 2821 uart2c { 2822 uart2c_xfer: uart2c-xfer { 2823 rockchip,pins = 2824 <4 RK_PC3 1 &pcfg_pull_up>, 2825 <4 RK_PC4 1 &pcfg_pull_none>; 2826 }; 2827 }; 2828 2829 uart3 { 2830 uart3_xfer: uart3-xfer { 2831 rockchip,pins = 2832 <3 RK_PB6 2 &pcfg_pull_up>, 2833 <3 RK_PB7 2 &pcfg_pull_none>; 2834 }; 2835 2836 uart3_cts: uart3-cts { 2837 rockchip,pins = 2838 <3 RK_PC0 2 &pcfg_pull_none>; 2839 }; 2840 2841 uart3_rts: uart3-rts { 2842 rockchip,pins = 2843 <3 RK_PC1 2 &pcfg_pull_none>; 2844 }; 2845 }; 2846 2847 uart4 { 2848 uart4_xfer: uart4-xfer { 2849 rockchip,pins = 2850 <1 RK_PA7 1 &pcfg_pull_up>, 2851 <1 RK_PB0 1 &pcfg_pull_none>; 2852 }; 2853 }; 2854 2855 uarthdcp { 2856 uarthdcp_xfer: uarthdcp-xfer { 2857 rockchip,pins = 2858 <4 RK_PC5 2 &pcfg_pull_up>, 2859 <4 RK_PC6 2 &pcfg_pull_none>; 2860 }; 2861 }; 2862 2863 pwm0 { 2864 pwm0_pin: pwm0-pin { 2865 rockchip,pins = 2866 <4 RK_PC2 1 &pcfg_pull_none>; 2867 }; 2868 2869 pwm0_pin_pull_down: pwm0-pin-pull-down { 2870 rockchip,pins = 2871 <4 RK_PC2 1 &pcfg_pull_down>; 2872 }; 2873 2874 vop0_pwm_pin: vop0-pwm-pin { 2875 rockchip,pins = 2876 <4 RK_PC2 2 &pcfg_pull_none>; 2877 }; 2878 2879 vop1_pwm_pin: vop1-pwm-pin { 2880 rockchip,pins = 2881 <4 RK_PC2 3 &pcfg_pull_none>; 2882 }; 2883 }; 2884 2885 pwm1 { 2886 pwm1_pin: pwm1-pin { 2887 rockchip,pins = 2888 <4 RK_PC6 1 &pcfg_pull_none>; 2889 }; 2890 2891 pwm1_pin_pull_down: pwm1-pin-pull-down { 2892 rockchip,pins = 2893 <4 RK_PC6 1 &pcfg_pull_down>; 2894 }; 2895 }; 2896 2897 pwm2 { 2898 pwm2_pin: pwm2-pin { 2899 rockchip,pins = 2900 <1 RK_PC3 1 &pcfg_pull_none>; 2901 }; 2902 2903 pwm2_pin_pull_down: pwm2-pin-pull-down { 2904 rockchip,pins = 2905 <1 RK_PC3 1 &pcfg_pull_down>; 2906 }; 2907 }; 2908 2909 pwm3a { 2910 pwm3a_pin: pwm3a-pin { 2911 rockchip,pins = 2912 <0 RK_PA6 1 &pcfg_pull_none>; 2913 }; 2914 }; 2915 2916 pwm3b { 2917 pwm3b_pin: pwm3b-pin { 2918 rockchip,pins = 2919 <1 RK_PB6 1 &pcfg_pull_none>; 2920 }; 2921 }; 2922 2923 hdmi { 2924 hdmi_i2c_xfer: hdmi-i2c-xfer { 2925 rockchip,pins = 2926 <4 RK_PC1 3 &pcfg_pull_none>, 2927 <4 RK_PC0 3 &pcfg_pull_none>; 2928 }; 2929 2930 hdmi_cec: hdmi-cec { 2931 rockchip,pins = 2932 <4 RK_PC7 1 &pcfg_pull_none>; 2933 }; 2934 }; 2935 2936 pcie { 2937 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2938 rockchip,pins = 2939 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2940 }; 2941 2942 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2943 rockchip,pins = 2944 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2945 }; 2946 }; 2947 2948 }; 2949}; 2950