1/* 2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include <dt-bindings/clock/rk3399-cru.h> 44#include <dt-bindings/gpio/gpio.h> 45#include <dt-bindings/interrupt-controller/arm-gic.h> 46#include <dt-bindings/interrupt-controller/irq.h> 47#include <dt-bindings/pinctrl/rockchip.h> 48#include <dt-bindings/power/rk3399-power.h> 49#include <dt-bindings/thermal/thermal.h> 50 51/ { 52 compatible = "rockchip,rk3399"; 53 54 interrupt-parent = <&gic>; 55 #address-cells = <2>; 56 #size-cells = <2>; 57 58 aliases { 59 ethernet0 = &gmac; 60 i2c0 = &i2c0; 61 i2c1 = &i2c1; 62 i2c2 = &i2c2; 63 i2c3 = &i2c3; 64 i2c4 = &i2c4; 65 i2c5 = &i2c5; 66 i2c6 = &i2c6; 67 i2c7 = &i2c7; 68 i2c8 = &i2c8; 69 serial0 = &uart0; 70 serial1 = &uart1; 71 serial2 = &uart2; 72 serial3 = &uart3; 73 serial4 = &uart4; 74 }; 75 76 cpus { 77 #address-cells = <2>; 78 #size-cells = <0>; 79 80 cpu-map { 81 cluster0 { 82 core0 { 83 cpu = <&cpu_l0>; 84 }; 85 core1 { 86 cpu = <&cpu_l1>; 87 }; 88 core2 { 89 cpu = <&cpu_l2>; 90 }; 91 core3 { 92 cpu = <&cpu_l3>; 93 }; 94 }; 95 96 cluster1 { 97 core0 { 98 cpu = <&cpu_b0>; 99 }; 100 core1 { 101 cpu = <&cpu_b1>; 102 }; 103 }; 104 }; 105 106 cpu_l0: cpu@0 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a53", "arm,armv8"; 109 reg = <0x0 0x0>; 110 enable-method = "psci"; 111 #cooling-cells = <2>; /* min followed by max */ 112 clocks = <&cru ARMCLKL>; 113 dynamic-power-coefficient = <100>; 114 }; 115 116 cpu_l1: cpu@1 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a53", "arm,armv8"; 119 reg = <0x0 0x1>; 120 enable-method = "psci"; 121 clocks = <&cru ARMCLKL>; 122 dynamic-power-coefficient = <100>; 123 }; 124 125 cpu_l2: cpu@2 { 126 device_type = "cpu"; 127 compatible = "arm,cortex-a53", "arm,armv8"; 128 reg = <0x0 0x2>; 129 enable-method = "psci"; 130 clocks = <&cru ARMCLKL>; 131 dynamic-power-coefficient = <100>; 132 }; 133 134 cpu_l3: cpu@3 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a53", "arm,armv8"; 137 reg = <0x0 0x3>; 138 enable-method = "psci"; 139 clocks = <&cru ARMCLKL>; 140 dynamic-power-coefficient = <100>; 141 }; 142 143 cpu_b0: cpu@100 { 144 device_type = "cpu"; 145 compatible = "arm,cortex-a72", "arm,armv8"; 146 reg = <0x0 0x100>; 147 enable-method = "psci"; 148 #cooling-cells = <2>; /* min followed by max */ 149 clocks = <&cru ARMCLKB>; 150 dynamic-power-coefficient = <436>; 151 }; 152 153 cpu_b1: cpu@101 { 154 device_type = "cpu"; 155 compatible = "arm,cortex-a72", "arm,armv8"; 156 reg = <0x0 0x101>; 157 enable-method = "psci"; 158 clocks = <&cru ARMCLKB>; 159 dynamic-power-coefficient = <436>; 160 }; 161 }; 162 163 display-subsystem { 164 compatible = "rockchip,display-subsystem"; 165 ports = <&vopl_out>, <&vopb_out>; 166 }; 167 168 pmu_a53 { 169 compatible = "arm,cortex-a53-pmu"; 170 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 171 }; 172 173 pmu_a72 { 174 compatible = "arm,cortex-a72-pmu"; 175 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 176 }; 177 178 psci { 179 compatible = "arm,psci-1.0"; 180 method = "smc"; 181 }; 182 183 timer { 184 compatible = "arm,armv8-timer"; 185 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 186 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 187 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 188 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 189 arm,no-tick-in-suspend; 190 }; 191 192 xin24m: xin24m { 193 compatible = "fixed-clock"; 194 clock-frequency = <24000000>; 195 clock-output-names = "xin24m"; 196 #clock-cells = <0>; 197 }; 198 199 amba { 200 compatible = "simple-bus"; 201 #address-cells = <2>; 202 #size-cells = <2>; 203 ranges; 204 205 dmac_bus: dma-controller@ff6d0000 { 206 compatible = "arm,pl330", "arm,primecell"; 207 reg = <0x0 0xff6d0000 0x0 0x4000>; 208 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 209 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 210 #dma-cells = <1>; 211 clocks = <&cru ACLK_DMAC0_PERILP>; 212 clock-names = "apb_pclk"; 213 }; 214 215 dmac_peri: dma-controller@ff6e0000 { 216 compatible = "arm,pl330", "arm,primecell"; 217 reg = <0x0 0xff6e0000 0x0 0x4000>; 218 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 219 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 220 #dma-cells = <1>; 221 clocks = <&cru ACLK_DMAC1_PERILP>; 222 clock-names = "apb_pclk"; 223 }; 224 }; 225 226 pcie0: pcie@f8000000 { 227 compatible = "rockchip,rk3399-pcie"; 228 reg = <0x0 0xf8000000 0x0 0x2000000>, 229 <0x0 0xfd000000 0x0 0x1000000>; 230 reg-names = "axi-base", "apb-base"; 231 #address-cells = <3>; 232 #size-cells = <2>; 233 #interrupt-cells = <1>; 234 aspm-no-l0s; 235 bus-range = <0x0 0x1f>; 236 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 237 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 238 clock-names = "aclk", "aclk-perf", 239 "hclk", "pm"; 240 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 241 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 242 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 243 interrupt-names = "sys", "legacy", "client"; 244 interrupt-map-mask = <0 0 0 7>; 245 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 246 <0 0 0 2 &pcie0_intc 1>, 247 <0 0 0 3 &pcie0_intc 2>, 248 <0 0 0 4 &pcie0_intc 3>; 249 linux,pci-domain = <0>; 250 max-link-speed = <1>; 251 msi-map = <0x0 &its 0x0 0x1000>; 252 phys = <&pcie_phy 0>, <&pcie_phy 1>, 253 <&pcie_phy 2>, <&pcie_phy 3>; 254 phy-names = "pcie-phy-0", "pcie-phy-1", 255 "pcie-phy-2", "pcie-phy-3"; 256 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000 257 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; 258 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 259 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 260 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 261 <&cru SRST_A_PCIE>; 262 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 263 "pm", "pclk", "aclk"; 264 status = "disabled"; 265 266 pcie0_intc: interrupt-controller { 267 interrupt-controller; 268 #address-cells = <0>; 269 #interrupt-cells = <1>; 270 }; 271 }; 272 273 gmac: ethernet@fe300000 { 274 compatible = "rockchip,rk3399-gmac"; 275 reg = <0x0 0xfe300000 0x0 0x10000>; 276 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 277 interrupt-names = "macirq"; 278 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 279 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 280 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 281 <&cru PCLK_GMAC>; 282 clock-names = "stmmaceth", "mac_clk_rx", 283 "mac_clk_tx", "clk_mac_ref", 284 "clk_mac_refout", "aclk_mac", 285 "pclk_mac"; 286 power-domains = <&power RK3399_PD_GMAC>; 287 resets = <&cru SRST_A_GMAC>; 288 reset-names = "stmmaceth"; 289 rockchip,grf = <&grf>; 290 status = "disabled"; 291 }; 292 293 sdio0: dwmmc@fe310000 { 294 compatible = "rockchip,rk3399-dw-mshc", 295 "rockchip,rk3288-dw-mshc"; 296 reg = <0x0 0xfe310000 0x0 0x4000>; 297 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 298 max-frequency = <150000000>; 299 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 300 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 301 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 302 fifo-depth = <0x100>; 303 power-domains = <&power RK3399_PD_SDIOAUDIO>; 304 resets = <&cru SRST_SDIO0>; 305 reset-names = "reset"; 306 status = "disabled"; 307 }; 308 309 sdmmc: dwmmc@fe320000 { 310 compatible = "rockchip,rk3399-dw-mshc", 311 "rockchip,rk3288-dw-mshc"; 312 reg = <0x0 0xfe320000 0x0 0x4000>; 313 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 314 max-frequency = <150000000>; 315 assigned-clocks = <&cru HCLK_SD>; 316 assigned-clock-rates = <200000000>; 317 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 318 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 319 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 320 fifo-depth = <0x100>; 321 power-domains = <&power RK3399_PD_SD>; 322 resets = <&cru SRST_SDMMC>; 323 reset-names = "reset"; 324 status = "disabled"; 325 }; 326 327 sdhci: sdhci@fe330000 { 328 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 329 reg = <0x0 0xfe330000 0x0 0x10000>; 330 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 331 arasan,soc-ctl-syscon = <&grf>; 332 assigned-clocks = <&cru SCLK_EMMC>; 333 assigned-clock-rates = <200000000>; 334 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 335 clock-names = "clk_xin", "clk_ahb"; 336 clock-output-names = "emmc_cardclock"; 337 #clock-cells = <0>; 338 phys = <&emmc_phy>; 339 phy-names = "phy_arasan"; 340 power-domains = <&power RK3399_PD_EMMC>; 341 status = "disabled"; 342 }; 343 344 usb_host0_ehci: usb@fe380000 { 345 compatible = "generic-ehci"; 346 reg = <0x0 0xfe380000 0x0 0x20000>; 347 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 348 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 349 <&u2phy0>; 350 clock-names = "usbhost", "arbiter", 351 "utmi"; 352 phys = <&u2phy0_host>; 353 phy-names = "usb"; 354 status = "disabled"; 355 }; 356 357 usb_host0_ohci: usb@fe3a0000 { 358 compatible = "generic-ohci"; 359 reg = <0x0 0xfe3a0000 0x0 0x20000>; 360 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 361 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 362 <&u2phy0>; 363 clock-names = "usbhost", "arbiter", 364 "utmi"; 365 phys = <&u2phy0_host>; 366 phy-names = "usb"; 367 status = "disabled"; 368 }; 369 370 usb_host1_ehci: usb@fe3c0000 { 371 compatible = "generic-ehci"; 372 reg = <0x0 0xfe3c0000 0x0 0x20000>; 373 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 374 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 375 <&u2phy1>; 376 clock-names = "usbhost", "arbiter", 377 "utmi"; 378 phys = <&u2phy1_host>; 379 phy-names = "usb"; 380 status = "disabled"; 381 }; 382 383 usb_host1_ohci: usb@fe3e0000 { 384 compatible = "generic-ohci"; 385 reg = <0x0 0xfe3e0000 0x0 0x20000>; 386 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 387 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 388 <&u2phy1>; 389 clock-names = "usbhost", "arbiter", 390 "utmi"; 391 phys = <&u2phy1_host>; 392 phy-names = "usb"; 393 status = "disabled"; 394 }; 395 396 usbdrd3_0: usb@fe800000 { 397 compatible = "rockchip,rk3399-dwc3"; 398 #address-cells = <2>; 399 #size-cells = <2>; 400 ranges; 401 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 402 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 403 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 404 clock-names = "ref_clk", "suspend_clk", 405 "bus_clk", "aclk_usb3_rksoc_axi_perf", 406 "aclk_usb3", "grf_clk"; 407 resets = <&cru SRST_A_USB3_OTG0>; 408 reset-names = "usb3-otg"; 409 status = "disabled"; 410 411 usbdrd_dwc3_0: dwc3 { 412 compatible = "snps,dwc3"; 413 reg = <0x0 0xfe800000 0x0 0x100000>; 414 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 415 dr_mode = "otg"; 416 phys = <&u2phy0_otg>, <&tcphy0_usb3>; 417 phy-names = "usb2-phy", "usb3-phy"; 418 phy_type = "utmi_wide"; 419 snps,dis_enblslpm_quirk; 420 snps,dis-u2-freeclk-exists-quirk; 421 snps,dis_u2_susphy_quirk; 422 snps,dis-del-phy-power-chg-quirk; 423 snps,dis-tx-ipgap-linecheck-quirk; 424 power-domains = <&power RK3399_PD_USB3>; 425 status = "disabled"; 426 }; 427 }; 428 429 usbdrd3_1: usb@fe900000 { 430 compatible = "rockchip,rk3399-dwc3"; 431 #address-cells = <2>; 432 #size-cells = <2>; 433 ranges; 434 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, 435 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 436 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 437 clock-names = "ref_clk", "suspend_clk", 438 "bus_clk", "aclk_usb3_rksoc_axi_perf", 439 "aclk_usb3", "grf_clk"; 440 resets = <&cru SRST_A_USB3_OTG1>; 441 reset-names = "usb3-otg"; 442 status = "disabled"; 443 444 usbdrd_dwc3_1: dwc3 { 445 compatible = "snps,dwc3"; 446 reg = <0x0 0xfe900000 0x0 0x100000>; 447 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 448 dr_mode = "otg"; 449 phys = <&u2phy1_otg>, <&tcphy1_usb3>; 450 phy-names = "usb2-phy", "usb3-phy"; 451 phy_type = "utmi_wide"; 452 snps,dis_enblslpm_quirk; 453 snps,dis-u2-freeclk-exists-quirk; 454 snps,dis_u2_susphy_quirk; 455 snps,dis-del-phy-power-chg-quirk; 456 snps,dis-tx-ipgap-linecheck-quirk; 457 power-domains = <&power RK3399_PD_USB3>; 458 status = "disabled"; 459 }; 460 }; 461 462 cdn_dp: dp@fec00000 { 463 compatible = "rockchip,rk3399-cdn-dp"; 464 reg = <0x0 0xfec00000 0x0 0x100000>; 465 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 466 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>; 467 assigned-clock-rates = <100000000>, <200000000>; 468 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, 469 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; 470 clock-names = "core-clk", "pclk", "spdif", "grf"; 471 phys = <&tcphy0_dp>, <&tcphy1_dp>; 472 power-domains = <&power RK3399_PD_HDCP>; 473 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, 474 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; 475 reset-names = "spdif", "dptx", "apb", "core"; 476 rockchip,grf = <&grf>; 477 #sound-dai-cells = <1>; 478 status = "disabled"; 479 480 ports { 481 dp_in: port { 482 #address-cells = <1>; 483 #size-cells = <0>; 484 485 dp_in_vopb: endpoint@0 { 486 reg = <0>; 487 remote-endpoint = <&vopb_out_dp>; 488 }; 489 490 dp_in_vopl: endpoint@1 { 491 reg = <1>; 492 remote-endpoint = <&vopl_out_dp>; 493 }; 494 }; 495 }; 496 }; 497 498 gic: interrupt-controller@fee00000 { 499 compatible = "arm,gic-v3"; 500 #interrupt-cells = <4>; 501 #address-cells = <2>; 502 #size-cells = <2>; 503 ranges; 504 interrupt-controller; 505 506 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 507 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 508 <0x0 0xfff00000 0 0x10000>, /* GICC */ 509 <0x0 0xfff10000 0 0x10000>, /* GICH */ 510 <0x0 0xfff20000 0 0x10000>; /* GICV */ 511 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 512 its: interrupt-controller@fee20000 { 513 compatible = "arm,gic-v3-its"; 514 msi-controller; 515 reg = <0x0 0xfee20000 0x0 0x20000>; 516 }; 517 518 ppi-partitions { 519 ppi_cluster0: interrupt-partition-0 { 520 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 521 }; 522 523 ppi_cluster1: interrupt-partition-1 { 524 affinity = <&cpu_b0 &cpu_b1>; 525 }; 526 }; 527 }; 528 529 saradc: saradc@ff100000 { 530 compatible = "rockchip,rk3399-saradc"; 531 reg = <0x0 0xff100000 0x0 0x100>; 532 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 533 #io-channel-cells = <1>; 534 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 535 clock-names = "saradc", "apb_pclk"; 536 resets = <&cru SRST_P_SARADC>; 537 reset-names = "saradc-apb"; 538 status = "disabled"; 539 }; 540 541 i2c1: i2c@ff110000 { 542 compatible = "rockchip,rk3399-i2c"; 543 reg = <0x0 0xff110000 0x0 0x1000>; 544 assigned-clocks = <&cru SCLK_I2C1>; 545 assigned-clock-rates = <200000000>; 546 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 547 clock-names = "i2c", "pclk"; 548 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 549 pinctrl-names = "default"; 550 pinctrl-0 = <&i2c1_xfer>; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 status = "disabled"; 554 }; 555 556 i2c2: i2c@ff120000 { 557 compatible = "rockchip,rk3399-i2c"; 558 reg = <0x0 0xff120000 0x0 0x1000>; 559 assigned-clocks = <&cru SCLK_I2C2>; 560 assigned-clock-rates = <200000000>; 561 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 562 clock-names = "i2c", "pclk"; 563 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 564 pinctrl-names = "default"; 565 pinctrl-0 = <&i2c2_xfer>; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 status = "disabled"; 569 }; 570 571 i2c3: i2c@ff130000 { 572 compatible = "rockchip,rk3399-i2c"; 573 reg = <0x0 0xff130000 0x0 0x1000>; 574 assigned-clocks = <&cru SCLK_I2C3>; 575 assigned-clock-rates = <200000000>; 576 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 577 clock-names = "i2c", "pclk"; 578 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 579 pinctrl-names = "default"; 580 pinctrl-0 = <&i2c3_xfer>; 581 #address-cells = <1>; 582 #size-cells = <0>; 583 status = "disabled"; 584 }; 585 586 i2c5: i2c@ff140000 { 587 compatible = "rockchip,rk3399-i2c"; 588 reg = <0x0 0xff140000 0x0 0x1000>; 589 assigned-clocks = <&cru SCLK_I2C5>; 590 assigned-clock-rates = <200000000>; 591 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 592 clock-names = "i2c", "pclk"; 593 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 594 pinctrl-names = "default"; 595 pinctrl-0 = <&i2c5_xfer>; 596 #address-cells = <1>; 597 #size-cells = <0>; 598 status = "disabled"; 599 }; 600 601 i2c6: i2c@ff150000 { 602 compatible = "rockchip,rk3399-i2c"; 603 reg = <0x0 0xff150000 0x0 0x1000>; 604 assigned-clocks = <&cru SCLK_I2C6>; 605 assigned-clock-rates = <200000000>; 606 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 607 clock-names = "i2c", "pclk"; 608 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 609 pinctrl-names = "default"; 610 pinctrl-0 = <&i2c6_xfer>; 611 #address-cells = <1>; 612 #size-cells = <0>; 613 status = "disabled"; 614 }; 615 616 i2c7: i2c@ff160000 { 617 compatible = "rockchip,rk3399-i2c"; 618 reg = <0x0 0xff160000 0x0 0x1000>; 619 assigned-clocks = <&cru SCLK_I2C7>; 620 assigned-clock-rates = <200000000>; 621 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 622 clock-names = "i2c", "pclk"; 623 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 624 pinctrl-names = "default"; 625 pinctrl-0 = <&i2c7_xfer>; 626 #address-cells = <1>; 627 #size-cells = <0>; 628 status = "disabled"; 629 }; 630 631 uart0: serial@ff180000 { 632 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 633 reg = <0x0 0xff180000 0x0 0x100>; 634 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 635 clock-names = "baudclk", "apb_pclk"; 636 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 637 reg-shift = <2>; 638 reg-io-width = <4>; 639 pinctrl-names = "default"; 640 pinctrl-0 = <&uart0_xfer>; 641 status = "disabled"; 642 }; 643 644 uart1: serial@ff190000 { 645 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 646 reg = <0x0 0xff190000 0x0 0x100>; 647 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 648 clock-names = "baudclk", "apb_pclk"; 649 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 650 reg-shift = <2>; 651 reg-io-width = <4>; 652 pinctrl-names = "default"; 653 pinctrl-0 = <&uart1_xfer>; 654 status = "disabled"; 655 }; 656 657 uart2: serial@ff1a0000 { 658 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 659 reg = <0x0 0xff1a0000 0x0 0x100>; 660 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 661 clock-names = "baudclk", "apb_pclk"; 662 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 663 reg-shift = <2>; 664 reg-io-width = <4>; 665 pinctrl-names = "default"; 666 pinctrl-0 = <&uart2c_xfer>; 667 status = "disabled"; 668 }; 669 670 uart3: serial@ff1b0000 { 671 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 672 reg = <0x0 0xff1b0000 0x0 0x100>; 673 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 674 clock-names = "baudclk", "apb_pclk"; 675 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 676 reg-shift = <2>; 677 reg-io-width = <4>; 678 pinctrl-names = "default"; 679 pinctrl-0 = <&uart3_xfer>; 680 status = "disabled"; 681 }; 682 683 spi0: spi@ff1c0000 { 684 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 685 reg = <0x0 0xff1c0000 0x0 0x1000>; 686 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 687 clock-names = "spiclk", "apb_pclk"; 688 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 689 pinctrl-names = "default"; 690 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 691 #address-cells = <1>; 692 #size-cells = <0>; 693 status = "disabled"; 694 }; 695 696 spi1: spi@ff1d0000 { 697 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 698 reg = <0x0 0xff1d0000 0x0 0x1000>; 699 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 700 clock-names = "spiclk", "apb_pclk"; 701 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 702 pinctrl-names = "default"; 703 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 704 #address-cells = <1>; 705 #size-cells = <0>; 706 status = "disabled"; 707 }; 708 709 spi2: spi@ff1e0000 { 710 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 711 reg = <0x0 0xff1e0000 0x0 0x1000>; 712 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 713 clock-names = "spiclk", "apb_pclk"; 714 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 715 pinctrl-names = "default"; 716 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 717 #address-cells = <1>; 718 #size-cells = <0>; 719 status = "disabled"; 720 }; 721 722 spi4: spi@ff1f0000 { 723 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 724 reg = <0x0 0xff1f0000 0x0 0x1000>; 725 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 726 clock-names = "spiclk", "apb_pclk"; 727 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 728 pinctrl-names = "default"; 729 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 730 #address-cells = <1>; 731 #size-cells = <0>; 732 status = "disabled"; 733 }; 734 735 spi5: spi@ff200000 { 736 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 737 reg = <0x0 0xff200000 0x0 0x1000>; 738 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 739 clock-names = "spiclk", "apb_pclk"; 740 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 741 pinctrl-names = "default"; 742 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 743 power-domains = <&power RK3399_PD_SDIOAUDIO>; 744 #address-cells = <1>; 745 #size-cells = <0>; 746 status = "disabled"; 747 }; 748 749 thermal_zones: thermal-zones { 750 cpu_thermal: cpu { 751 polling-delay-passive = <100>; 752 polling-delay = <1000>; 753 754 thermal-sensors = <&tsadc 0>; 755 756 trips { 757 cpu_alert0: cpu_alert0 { 758 temperature = <70000>; 759 hysteresis = <2000>; 760 type = "passive"; 761 }; 762 cpu_alert1: cpu_alert1 { 763 temperature = <75000>; 764 hysteresis = <2000>; 765 type = "passive"; 766 }; 767 cpu_crit: cpu_crit { 768 temperature = <95000>; 769 hysteresis = <2000>; 770 type = "critical"; 771 }; 772 }; 773 774 cooling-maps { 775 map0 { 776 trip = <&cpu_alert0>; 777 cooling-device = 778 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 779 }; 780 map1 { 781 trip = <&cpu_alert1>; 782 cooling-device = 783 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 784 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 785 }; 786 }; 787 }; 788 789 gpu_thermal: gpu { 790 polling-delay-passive = <100>; 791 polling-delay = <1000>; 792 793 thermal-sensors = <&tsadc 1>; 794 795 trips { 796 gpu_alert0: gpu_alert0 { 797 temperature = <75000>; 798 hysteresis = <2000>; 799 type = "passive"; 800 }; 801 gpu_crit: gpu_crit { 802 temperature = <95000>; 803 hysteresis = <2000>; 804 type = "critical"; 805 }; 806 }; 807 808 cooling-maps { 809 map0 { 810 trip = <&gpu_alert0>; 811 cooling-device = 812 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 813 }; 814 }; 815 }; 816 }; 817 818 tsadc: tsadc@ff260000 { 819 compatible = "rockchip,rk3399-tsadc"; 820 reg = <0x0 0xff260000 0x0 0x100>; 821 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 822 assigned-clocks = <&cru SCLK_TSADC>; 823 assigned-clock-rates = <750000>; 824 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 825 clock-names = "tsadc", "apb_pclk"; 826 resets = <&cru SRST_TSADC>; 827 reset-names = "tsadc-apb"; 828 rockchip,grf = <&grf>; 829 rockchip,hw-tshut-temp = <95000>; 830 pinctrl-names = "init", "default", "sleep"; 831 pinctrl-0 = <&otp_gpio>; 832 pinctrl-1 = <&otp_out>; 833 pinctrl-2 = <&otp_gpio>; 834 #thermal-sensor-cells = <1>; 835 status = "disabled"; 836 }; 837 838 qos_emmc: qos@ffa58000 { 839 compatible = "syscon"; 840 reg = <0x0 0xffa58000 0x0 0x20>; 841 }; 842 843 qos_gmac: qos@ffa5c000 { 844 compatible = "syscon"; 845 reg = <0x0 0xffa5c000 0x0 0x20>; 846 }; 847 848 qos_pcie: qos@ffa60080 { 849 compatible = "syscon"; 850 reg = <0x0 0xffa60080 0x0 0x20>; 851 }; 852 853 qos_usb_host0: qos@ffa60100 { 854 compatible = "syscon"; 855 reg = <0x0 0xffa60100 0x0 0x20>; 856 }; 857 858 qos_usb_host1: qos@ffa60180 { 859 compatible = "syscon"; 860 reg = <0x0 0xffa60180 0x0 0x20>; 861 }; 862 863 qos_usb_otg0: qos@ffa70000 { 864 compatible = "syscon"; 865 reg = <0x0 0xffa70000 0x0 0x20>; 866 }; 867 868 qos_usb_otg1: qos@ffa70080 { 869 compatible = "syscon"; 870 reg = <0x0 0xffa70080 0x0 0x20>; 871 }; 872 873 qos_sd: qos@ffa74000 { 874 compatible = "syscon"; 875 reg = <0x0 0xffa74000 0x0 0x20>; 876 }; 877 878 qos_sdioaudio: qos@ffa76000 { 879 compatible = "syscon"; 880 reg = <0x0 0xffa76000 0x0 0x20>; 881 }; 882 883 qos_hdcp: qos@ffa90000 { 884 compatible = "syscon"; 885 reg = <0x0 0xffa90000 0x0 0x20>; 886 }; 887 888 qos_iep: qos@ffa98000 { 889 compatible = "syscon"; 890 reg = <0x0 0xffa98000 0x0 0x20>; 891 }; 892 893 qos_isp0_m0: qos@ffaa0000 { 894 compatible = "syscon"; 895 reg = <0x0 0xffaa0000 0x0 0x20>; 896 }; 897 898 qos_isp0_m1: qos@ffaa0080 { 899 compatible = "syscon"; 900 reg = <0x0 0xffaa0080 0x0 0x20>; 901 }; 902 903 qos_isp1_m0: qos@ffaa8000 { 904 compatible = "syscon"; 905 reg = <0x0 0xffaa8000 0x0 0x20>; 906 }; 907 908 qos_isp1_m1: qos@ffaa8080 { 909 compatible = "syscon"; 910 reg = <0x0 0xffaa8080 0x0 0x20>; 911 }; 912 913 qos_rga_r: qos@ffab0000 { 914 compatible = "syscon"; 915 reg = <0x0 0xffab0000 0x0 0x20>; 916 }; 917 918 qos_rga_w: qos@ffab0080 { 919 compatible = "syscon"; 920 reg = <0x0 0xffab0080 0x0 0x20>; 921 }; 922 923 qos_video_m0: qos@ffab8000 { 924 compatible = "syscon"; 925 reg = <0x0 0xffab8000 0x0 0x20>; 926 }; 927 928 qos_video_m1_r: qos@ffac0000 { 929 compatible = "syscon"; 930 reg = <0x0 0xffac0000 0x0 0x20>; 931 }; 932 933 qos_video_m1_w: qos@ffac0080 { 934 compatible = "syscon"; 935 reg = <0x0 0xffac0080 0x0 0x20>; 936 }; 937 938 qos_vop_big_r: qos@ffac8000 { 939 compatible = "syscon"; 940 reg = <0x0 0xffac8000 0x0 0x20>; 941 }; 942 943 qos_vop_big_w: qos@ffac8080 { 944 compatible = "syscon"; 945 reg = <0x0 0xffac8080 0x0 0x20>; 946 }; 947 948 qos_vop_little: qos@ffad0000 { 949 compatible = "syscon"; 950 reg = <0x0 0xffad0000 0x0 0x20>; 951 }; 952 953 qos_perihp: qos@ffad8080 { 954 compatible = "syscon"; 955 reg = <0x0 0xffad8080 0x0 0x20>; 956 }; 957 958 qos_gpu: qos@ffae0000 { 959 compatible = "syscon"; 960 reg = <0x0 0xffae0000 0x0 0x20>; 961 }; 962 963 pmu: power-management@ff310000 { 964 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 965 reg = <0x0 0xff310000 0x0 0x1000>; 966 967 /* 968 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 969 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 970 * Some of the power domains are grouped together for every 971 * voltage domain. 972 * The detail contents as below. 973 */ 974 power: power-controller { 975 compatible = "rockchip,rk3399-power-controller"; 976 #power-domain-cells = <1>; 977 #address-cells = <1>; 978 #size-cells = <0>; 979 980 /* These power domains are grouped by VD_CENTER */ 981 pd_iep@RK3399_PD_IEP { 982 reg = <RK3399_PD_IEP>; 983 clocks = <&cru ACLK_IEP>, 984 <&cru HCLK_IEP>; 985 pm_qos = <&qos_iep>; 986 }; 987 pd_rga@RK3399_PD_RGA { 988 reg = <RK3399_PD_RGA>; 989 clocks = <&cru ACLK_RGA>, 990 <&cru HCLK_RGA>; 991 pm_qos = <&qos_rga_r>, 992 <&qos_rga_w>; 993 }; 994 pd_vcodec@RK3399_PD_VCODEC { 995 reg = <RK3399_PD_VCODEC>; 996 clocks = <&cru ACLK_VCODEC>, 997 <&cru HCLK_VCODEC>; 998 pm_qos = <&qos_video_m0>; 999 }; 1000 pd_vdu@RK3399_PD_VDU { 1001 reg = <RK3399_PD_VDU>; 1002 clocks = <&cru ACLK_VDU>, 1003 <&cru HCLK_VDU>; 1004 pm_qos = <&qos_video_m1_r>, 1005 <&qos_video_m1_w>; 1006 }; 1007 1008 /* These power domains are grouped by VD_GPU */ 1009 pd_gpu@RK3399_PD_GPU { 1010 reg = <RK3399_PD_GPU>; 1011 clocks = <&cru ACLK_GPU>; 1012 pm_qos = <&qos_gpu>; 1013 }; 1014 1015 /* These power domains are grouped by VD_LOGIC */ 1016 pd_edp@RK3399_PD_EDP { 1017 reg = <RK3399_PD_EDP>; 1018 clocks = <&cru PCLK_EDP_CTRL>; 1019 }; 1020 pd_emmc@RK3399_PD_EMMC { 1021 reg = <RK3399_PD_EMMC>; 1022 clocks = <&cru ACLK_EMMC>; 1023 pm_qos = <&qos_emmc>; 1024 }; 1025 pd_gmac@RK3399_PD_GMAC { 1026 reg = <RK3399_PD_GMAC>; 1027 clocks = <&cru ACLK_GMAC>, 1028 <&cru PCLK_GMAC>; 1029 pm_qos = <&qos_gmac>; 1030 }; 1031 pd_sd@RK3399_PD_SD { 1032 reg = <RK3399_PD_SD>; 1033 clocks = <&cru HCLK_SDMMC>, 1034 <&cru SCLK_SDMMC>; 1035 pm_qos = <&qos_sd>; 1036 }; 1037 pd_sdioaudio@RK3399_PD_SDIOAUDIO { 1038 reg = <RK3399_PD_SDIOAUDIO>; 1039 clocks = <&cru HCLK_SDIO>; 1040 pm_qos = <&qos_sdioaudio>; 1041 }; 1042 pd_usb3@RK3399_PD_USB3 { 1043 reg = <RK3399_PD_USB3>; 1044 clocks = <&cru ACLK_USB3>; 1045 pm_qos = <&qos_usb_otg0>, 1046 <&qos_usb_otg1>; 1047 }; 1048 pd_vio@RK3399_PD_VIO { 1049 reg = <RK3399_PD_VIO>; 1050 #address-cells = <1>; 1051 #size-cells = <0>; 1052 1053 pd_hdcp@RK3399_PD_HDCP { 1054 reg = <RK3399_PD_HDCP>; 1055 clocks = <&cru ACLK_HDCP>, 1056 <&cru HCLK_HDCP>, 1057 <&cru PCLK_HDCP>; 1058 pm_qos = <&qos_hdcp>; 1059 }; 1060 pd_isp0@RK3399_PD_ISP0 { 1061 reg = <RK3399_PD_ISP0>; 1062 clocks = <&cru ACLK_ISP0>, 1063 <&cru HCLK_ISP0>; 1064 pm_qos = <&qos_isp0_m0>, 1065 <&qos_isp0_m1>; 1066 }; 1067 pd_isp1@RK3399_PD_ISP1 { 1068 reg = <RK3399_PD_ISP1>; 1069 clocks = <&cru ACLK_ISP1>, 1070 <&cru HCLK_ISP1>; 1071 pm_qos = <&qos_isp1_m0>, 1072 <&qos_isp1_m1>; 1073 }; 1074 pd_tcpc0@RK3399_PD_TCPC0 { 1075 reg = <RK3399_PD_TCPD0>; 1076 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1077 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1078 }; 1079 pd_tcpc1@RK3399_PD_TCPC1 { 1080 reg = <RK3399_PD_TCPD1>; 1081 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1082 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1083 }; 1084 pd_vo@RK3399_PD_VO { 1085 reg = <RK3399_PD_VO>; 1086 #address-cells = <1>; 1087 #size-cells = <0>; 1088 1089 pd_vopb@RK3399_PD_VOPB { 1090 reg = <RK3399_PD_VOPB>; 1091 clocks = <&cru ACLK_VOP0>, 1092 <&cru HCLK_VOP0>; 1093 pm_qos = <&qos_vop_big_r>, 1094 <&qos_vop_big_w>; 1095 }; 1096 pd_vopl@RK3399_PD_VOPL { 1097 reg = <RK3399_PD_VOPL>; 1098 clocks = <&cru ACLK_VOP1>, 1099 <&cru HCLK_VOP1>; 1100 pm_qos = <&qos_vop_little>; 1101 }; 1102 }; 1103 }; 1104 }; 1105 }; 1106 1107 pmugrf: syscon@ff320000 { 1108 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1109 reg = <0x0 0xff320000 0x0 0x1000>; 1110 #address-cells = <1>; 1111 #size-cells = <1>; 1112 1113 pmu_io_domains: io-domains { 1114 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1115 status = "disabled"; 1116 }; 1117 }; 1118 1119 spi3: spi@ff350000 { 1120 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1121 reg = <0x0 0xff350000 0x0 0x1000>; 1122 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1123 clock-names = "spiclk", "apb_pclk"; 1124 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1125 pinctrl-names = "default"; 1126 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 status = "disabled"; 1130 }; 1131 1132 uart4: serial@ff370000 { 1133 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1134 reg = <0x0 0xff370000 0x0 0x100>; 1135 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1136 clock-names = "baudclk", "apb_pclk"; 1137 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1138 reg-shift = <2>; 1139 reg-io-width = <4>; 1140 pinctrl-names = "default"; 1141 pinctrl-0 = <&uart4_xfer>; 1142 status = "disabled"; 1143 }; 1144 1145 i2c0: i2c@ff3c0000 { 1146 compatible = "rockchip,rk3399-i2c"; 1147 reg = <0x0 0xff3c0000 0x0 0x1000>; 1148 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1149 assigned-clock-rates = <200000000>; 1150 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1151 clock-names = "i2c", "pclk"; 1152 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1153 pinctrl-names = "default"; 1154 pinctrl-0 = <&i2c0_xfer>; 1155 #address-cells = <1>; 1156 #size-cells = <0>; 1157 status = "disabled"; 1158 }; 1159 1160 i2c4: i2c@ff3d0000 { 1161 compatible = "rockchip,rk3399-i2c"; 1162 reg = <0x0 0xff3d0000 0x0 0x1000>; 1163 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1164 assigned-clock-rates = <200000000>; 1165 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1166 clock-names = "i2c", "pclk"; 1167 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1168 pinctrl-names = "default"; 1169 pinctrl-0 = <&i2c4_xfer>; 1170 #address-cells = <1>; 1171 #size-cells = <0>; 1172 status = "disabled"; 1173 }; 1174 1175 i2c8: i2c@ff3e0000 { 1176 compatible = "rockchip,rk3399-i2c"; 1177 reg = <0x0 0xff3e0000 0x0 0x1000>; 1178 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1179 assigned-clock-rates = <200000000>; 1180 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1181 clock-names = "i2c", "pclk"; 1182 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1183 pinctrl-names = "default"; 1184 pinctrl-0 = <&i2c8_xfer>; 1185 #address-cells = <1>; 1186 #size-cells = <0>; 1187 status = "disabled"; 1188 }; 1189 1190 pwm0: pwm@ff420000 { 1191 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1192 reg = <0x0 0xff420000 0x0 0x10>; 1193 #pwm-cells = <3>; 1194 pinctrl-names = "default"; 1195 pinctrl-0 = <&pwm0_pin>; 1196 clocks = <&pmucru PCLK_RKPWM_PMU>; 1197 clock-names = "pwm"; 1198 status = "disabled"; 1199 }; 1200 1201 pwm1: pwm@ff420010 { 1202 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1203 reg = <0x0 0xff420010 0x0 0x10>; 1204 #pwm-cells = <3>; 1205 pinctrl-names = "default"; 1206 pinctrl-0 = <&pwm1_pin>; 1207 clocks = <&pmucru PCLK_RKPWM_PMU>; 1208 clock-names = "pwm"; 1209 status = "disabled"; 1210 }; 1211 1212 pwm2: pwm@ff420020 { 1213 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1214 reg = <0x0 0xff420020 0x0 0x10>; 1215 #pwm-cells = <3>; 1216 pinctrl-names = "default"; 1217 pinctrl-0 = <&pwm2_pin>; 1218 clocks = <&pmucru PCLK_RKPWM_PMU>; 1219 clock-names = "pwm"; 1220 status = "disabled"; 1221 }; 1222 1223 pwm3: pwm@ff420030 { 1224 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1225 reg = <0x0 0xff420030 0x0 0x10>; 1226 #pwm-cells = <3>; 1227 pinctrl-names = "default"; 1228 pinctrl-0 = <&pwm3a_pin>; 1229 clocks = <&pmucru PCLK_RKPWM_PMU>; 1230 clock-names = "pwm"; 1231 status = "disabled"; 1232 }; 1233 1234 vpu_mmu: iommu@ff650800 { 1235 compatible = "rockchip,iommu"; 1236 reg = <0x0 0xff650800 0x0 0x40>; 1237 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 1238 interrupt-names = "vpu_mmu"; 1239 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1240 clock-names = "aclk", "iface"; 1241 #iommu-cells = <0>; 1242 status = "disabled"; 1243 }; 1244 1245 vdec_mmu: iommu@ff660480 { 1246 compatible = "rockchip,iommu"; 1247 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; 1248 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1249 interrupt-names = "vdec_mmu"; 1250 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; 1251 clock-names = "aclk", "iface"; 1252 #iommu-cells = <0>; 1253 status = "disabled"; 1254 }; 1255 1256 iep_mmu: iommu@ff670800 { 1257 compatible = "rockchip,iommu"; 1258 reg = <0x0 0xff670800 0x0 0x40>; 1259 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>; 1260 interrupt-names = "iep_mmu"; 1261 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 1262 clock-names = "aclk", "iface"; 1263 #iommu-cells = <0>; 1264 status = "disabled"; 1265 }; 1266 1267 rga: rga@ff680000 { 1268 compatible = "rockchip,rk3399-rga"; 1269 reg = <0x0 0xff680000 0x0 0x10000>; 1270 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>; 1271 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; 1272 clock-names = "aclk", "hclk", "sclk"; 1273 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 1274 reset-names = "core", "axi", "ahb"; 1275 power-domains = <&power RK3399_PD_RGA>; 1276 }; 1277 1278 efuse0: efuse@ff690000 { 1279 compatible = "rockchip,rk3399-efuse"; 1280 reg = <0x0 0xff690000 0x0 0x80>; 1281 #address-cells = <1>; 1282 #size-cells = <1>; 1283 clocks = <&cru PCLK_EFUSE1024NS>; 1284 clock-names = "pclk_efuse"; 1285 1286 /* Data cells */ 1287 cpu_id: cpu-id@7 { 1288 reg = <0x07 0x10>; 1289 }; 1290 cpub_leakage: cpu-leakage@17 { 1291 reg = <0x17 0x1>; 1292 }; 1293 gpu_leakage: gpu-leakage@18 { 1294 reg = <0x18 0x1>; 1295 }; 1296 center_leakage: center-leakage@19 { 1297 reg = <0x19 0x1>; 1298 }; 1299 cpul_leakage: cpu-leakage@1a { 1300 reg = <0x1a 0x1>; 1301 }; 1302 logic_leakage: logic-leakage@1b { 1303 reg = <0x1b 0x1>; 1304 }; 1305 wafer_info: wafer-info@1c { 1306 reg = <0x1c 0x1>; 1307 }; 1308 }; 1309 1310 pmucru: pmu-clock-controller@ff750000 { 1311 compatible = "rockchip,rk3399-pmucru"; 1312 reg = <0x0 0xff750000 0x0 0x1000>; 1313 rockchip,grf = <&pmugrf>; 1314 #clock-cells = <1>; 1315 #reset-cells = <1>; 1316 assigned-clocks = <&pmucru PLL_PPLL>; 1317 assigned-clock-rates = <676000000>; 1318 }; 1319 1320 cru: clock-controller@ff760000 { 1321 compatible = "rockchip,rk3399-cru"; 1322 reg = <0x0 0xff760000 0x0 0x1000>; 1323 rockchip,grf = <&grf>; 1324 #clock-cells = <1>; 1325 #reset-cells = <1>; 1326 assigned-clocks = 1327 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1328 <&cru PLL_NPLL>, 1329 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1330 <&cru PCLK_PERIHP>, 1331 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1332 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1333 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 1334 <&cru ACLK_VIO>, <&cru ACLK_HDCP>, 1335 <&cru ACLK_GIC_PRE>, 1336 <&cru PCLK_DDR>; 1337 assigned-clock-rates = 1338 <594000000>, <800000000>, 1339 <1000000000>, 1340 <150000000>, <75000000>, 1341 <37500000>, 1342 <100000000>, <100000000>, 1343 <50000000>, <600000000>, 1344 <100000000>, <50000000>, 1345 <400000000>, <400000000>, 1346 <200000000>, 1347 <200000000>; 1348 }; 1349 1350 grf: syscon@ff770000 { 1351 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1352 reg = <0x0 0xff770000 0x0 0x10000>; 1353 #address-cells = <1>; 1354 #size-cells = <1>; 1355 1356 io_domains: io-domains { 1357 compatible = "rockchip,rk3399-io-voltage-domain"; 1358 status = "disabled"; 1359 }; 1360 1361 u2phy0: usb2-phy@e450 { 1362 compatible = "rockchip,rk3399-usb2phy"; 1363 reg = <0xe450 0x10>; 1364 clocks = <&cru SCLK_USB2PHY0_REF>; 1365 clock-names = "phyclk"; 1366 #clock-cells = <0>; 1367 clock-output-names = "clk_usbphy0_480m"; 1368 status = "disabled"; 1369 1370 u2phy0_host: host-port { 1371 #phy-cells = <0>; 1372 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1373 interrupt-names = "linestate"; 1374 status = "disabled"; 1375 }; 1376 1377 u2phy0_otg: otg-port { 1378 #phy-cells = <0>; 1379 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1380 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1381 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1382 interrupt-names = "otg-bvalid", "otg-id", 1383 "linestate"; 1384 status = "disabled"; 1385 }; 1386 }; 1387 1388 u2phy1: usb2-phy@e460 { 1389 compatible = "rockchip,rk3399-usb2phy"; 1390 reg = <0xe460 0x10>; 1391 clocks = <&cru SCLK_USB2PHY1_REF>; 1392 clock-names = "phyclk"; 1393 #clock-cells = <0>; 1394 clock-output-names = "clk_usbphy1_480m"; 1395 status = "disabled"; 1396 1397 u2phy1_host: host-port { 1398 #phy-cells = <0>; 1399 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1400 interrupt-names = "linestate"; 1401 status = "disabled"; 1402 }; 1403 1404 u2phy1_otg: otg-port { 1405 #phy-cells = <0>; 1406 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1407 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1408 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1409 interrupt-names = "otg-bvalid", "otg-id", 1410 "linestate"; 1411 status = "disabled"; 1412 }; 1413 }; 1414 1415 emmc_phy: phy@f780 { 1416 compatible = "rockchip,rk3399-emmc-phy"; 1417 reg = <0xf780 0x24>; 1418 clocks = <&sdhci>; 1419 clock-names = "emmcclk"; 1420 #phy-cells = <0>; 1421 status = "disabled"; 1422 }; 1423 1424 pcie_phy: pcie-phy { 1425 compatible = "rockchip,rk3399-pcie-phy"; 1426 clocks = <&cru SCLK_PCIEPHY_REF>; 1427 clock-names = "refclk"; 1428 #phy-cells = <1>; 1429 resets = <&cru SRST_PCIEPHY>; 1430 reset-names = "phy"; 1431 status = "disabled"; 1432 }; 1433 }; 1434 1435 tcphy0: phy@ff7c0000 { 1436 compatible = "rockchip,rk3399-typec-phy"; 1437 reg = <0x0 0xff7c0000 0x0 0x40000>; 1438 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1439 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1440 clock-names = "tcpdcore", "tcpdphy-ref"; 1441 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1442 assigned-clock-rates = <50000000>; 1443 power-domains = <&power RK3399_PD_TCPD0>; 1444 resets = <&cru SRST_UPHY0>, 1445 <&cru SRST_UPHY0_PIPE_L00>, 1446 <&cru SRST_P_UPHY0_TCPHY>; 1447 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1448 rockchip,grf = <&grf>; 1449 rockchip,typec-conn-dir = <0xe580 0 16>; 1450 rockchip,usb3tousb2-en = <0xe580 3 19>; 1451 rockchip,external-psm = <0xe588 14 30>; 1452 rockchip,pipe-status = <0xe5c0 0 0>; 1453 status = "disabled"; 1454 1455 tcphy0_dp: dp-port { 1456 #phy-cells = <0>; 1457 }; 1458 1459 tcphy0_usb3: usb3-port { 1460 #phy-cells = <0>; 1461 }; 1462 }; 1463 1464 tcphy1: phy@ff800000 { 1465 compatible = "rockchip,rk3399-typec-phy"; 1466 reg = <0x0 0xff800000 0x0 0x40000>; 1467 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1468 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1469 clock-names = "tcpdcore", "tcpdphy-ref"; 1470 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1471 assigned-clock-rates = <50000000>; 1472 power-domains = <&power RK3399_PD_TCPD1>; 1473 resets = <&cru SRST_UPHY1>, 1474 <&cru SRST_UPHY1_PIPE_L00>, 1475 <&cru SRST_P_UPHY1_TCPHY>; 1476 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1477 rockchip,grf = <&grf>; 1478 rockchip,typec-conn-dir = <0xe58c 0 16>; 1479 rockchip,usb3tousb2-en = <0xe58c 3 19>; 1480 rockchip,external-psm = <0xe594 14 30>; 1481 rockchip,pipe-status = <0xe5c0 16 16>; 1482 status = "disabled"; 1483 1484 tcphy1_dp: dp-port { 1485 #phy-cells = <0>; 1486 }; 1487 1488 tcphy1_usb3: usb3-port { 1489 #phy-cells = <0>; 1490 }; 1491 }; 1492 1493 watchdog@ff848000 { 1494 compatible = "snps,dw-wdt"; 1495 reg = <0x0 0xff848000 0x0 0x100>; 1496 clocks = <&cru PCLK_WDT>; 1497 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1498 }; 1499 1500 rktimer: rktimer@ff850000 { 1501 compatible = "rockchip,rk3399-timer"; 1502 reg = <0x0 0xff850000 0x0 0x1000>; 1503 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1504 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1505 clock-names = "pclk", "timer"; 1506 }; 1507 1508 spdif: spdif@ff870000 { 1509 compatible = "rockchip,rk3399-spdif"; 1510 reg = <0x0 0xff870000 0x0 0x1000>; 1511 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1512 dmas = <&dmac_bus 7>; 1513 dma-names = "tx"; 1514 clock-names = "mclk", "hclk"; 1515 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1516 pinctrl-names = "default"; 1517 pinctrl-0 = <&spdif_bus>; 1518 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1519 status = "disabled"; 1520 }; 1521 1522 i2s0: i2s@ff880000 { 1523 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1524 reg = <0x0 0xff880000 0x0 0x1000>; 1525 rockchip,grf = <&grf>; 1526 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1527 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1528 dma-names = "tx", "rx"; 1529 clock-names = "i2s_clk", "i2s_hclk"; 1530 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1531 pinctrl-names = "default"; 1532 pinctrl-0 = <&i2s0_8ch_bus>; 1533 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1534 status = "disabled"; 1535 }; 1536 1537 i2s1: i2s@ff890000 { 1538 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1539 reg = <0x0 0xff890000 0x0 0x1000>; 1540 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1541 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1542 dma-names = "tx", "rx"; 1543 clock-names = "i2s_clk", "i2s_hclk"; 1544 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1545 pinctrl-names = "default"; 1546 pinctrl-0 = <&i2s1_2ch_bus>; 1547 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1548 status = "disabled"; 1549 }; 1550 1551 i2s2: i2s@ff8a0000 { 1552 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1553 reg = <0x0 0xff8a0000 0x0 0x1000>; 1554 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1555 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1556 dma-names = "tx", "rx"; 1557 clock-names = "i2s_clk", "i2s_hclk"; 1558 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1559 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1560 status = "disabled"; 1561 }; 1562 1563 vopl: vop@ff8f0000 { 1564 compatible = "rockchip,rk3399-vop-lit"; 1565 reg = <0x0 0xff8f0000 0x0 0x3efc>; 1566 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1567 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1568 assigned-clock-rates = <400000000>, <100000000>; 1569 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1570 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1571 iommus = <&vopl_mmu>; 1572 power-domains = <&power RK3399_PD_VOPL>; 1573 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1574 reset-names = "axi", "ahb", "dclk"; 1575 status = "disabled"; 1576 1577 vopl_out: port { 1578 #address-cells = <1>; 1579 #size-cells = <0>; 1580 1581 vopl_out_mipi: endpoint@0 { 1582 reg = <0>; 1583 remote-endpoint = <&mipi_in_vopl>; 1584 }; 1585 1586 vopl_out_edp: endpoint@1 { 1587 reg = <1>; 1588 remote-endpoint = <&edp_in_vopl>; 1589 }; 1590 1591 vopl_out_hdmi: endpoint@2 { 1592 reg = <2>; 1593 remote-endpoint = <&hdmi_in_vopl>; 1594 }; 1595 1596 vopl_out_mipi1: endpoint@3 { 1597 reg = <3>; 1598 remote-endpoint = <&mipi1_in_vopl>; 1599 }; 1600 1601 vopl_out_dp: endpoint@4 { 1602 reg = <4>; 1603 remote-endpoint = <&dp_in_vopl>; 1604 }; 1605 }; 1606 }; 1607 1608 vopl_mmu: iommu@ff8f3f00 { 1609 compatible = "rockchip,iommu"; 1610 reg = <0x0 0xff8f3f00 0x0 0x100>; 1611 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1612 interrupt-names = "vopl_mmu"; 1613 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1614 clock-names = "aclk", "iface"; 1615 power-domains = <&power RK3399_PD_VOPL>; 1616 #iommu-cells = <0>; 1617 status = "disabled"; 1618 }; 1619 1620 vopb: vop@ff900000 { 1621 compatible = "rockchip,rk3399-vop-big"; 1622 reg = <0x0 0xff900000 0x0 0x3efc>; 1623 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1624 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1625 assigned-clock-rates = <400000000>, <100000000>; 1626 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1627 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1628 iommus = <&vopb_mmu>; 1629 power-domains = <&power RK3399_PD_VOPB>; 1630 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1631 reset-names = "axi", "ahb", "dclk"; 1632 status = "disabled"; 1633 1634 vopb_out: port { 1635 #address-cells = <1>; 1636 #size-cells = <0>; 1637 1638 vopb_out_edp: endpoint@0 { 1639 reg = <0>; 1640 remote-endpoint = <&edp_in_vopb>; 1641 }; 1642 1643 vopb_out_mipi: endpoint@1 { 1644 reg = <1>; 1645 remote-endpoint = <&mipi_in_vopb>; 1646 }; 1647 1648 vopb_out_hdmi: endpoint@2 { 1649 reg = <2>; 1650 remote-endpoint = <&hdmi_in_vopb>; 1651 }; 1652 1653 vopb_out_mipi1: endpoint@3 { 1654 reg = <3>; 1655 remote-endpoint = <&mipi1_in_vopb>; 1656 }; 1657 1658 vopb_out_dp: endpoint@4 { 1659 reg = <4>; 1660 remote-endpoint = <&dp_in_vopb>; 1661 }; 1662 }; 1663 }; 1664 1665 vopb_mmu: iommu@ff903f00 { 1666 compatible = "rockchip,iommu"; 1667 reg = <0x0 0xff903f00 0x0 0x100>; 1668 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1669 interrupt-names = "vopb_mmu"; 1670 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1671 clock-names = "aclk", "iface"; 1672 power-domains = <&power RK3399_PD_VOPB>; 1673 #iommu-cells = <0>; 1674 status = "disabled"; 1675 }; 1676 1677 isp0_mmu: iommu@ff914000 { 1678 compatible = "rockchip,iommu"; 1679 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1680 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1681 interrupt-names = "isp0_mmu"; 1682 clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>; 1683 clock-names = "aclk", "iface"; 1684 #iommu-cells = <0>; 1685 rockchip,disable-mmu-reset; 1686 status = "disabled"; 1687 }; 1688 1689 isp1_mmu: iommu@ff924000 { 1690 compatible = "rockchip,iommu"; 1691 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; 1692 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 1693 interrupt-names = "isp1_mmu"; 1694 clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>; 1695 clock-names = "aclk", "iface"; 1696 #iommu-cells = <0>; 1697 rockchip,disable-mmu-reset; 1698 status = "disabled"; 1699 }; 1700 1701 hdmi: hdmi@ff940000 { 1702 compatible = "rockchip,rk3399-dw-hdmi"; 1703 reg = <0x0 0xff940000 0x0 0x20000>; 1704 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 1705 clocks = <&cru PCLK_HDMI_CTRL>, 1706 <&cru SCLK_HDMI_SFR>, 1707 <&cru PLL_VPLL>, 1708 <&cru PCLK_VIO_GRF>, 1709 <&cru SCLK_HDMI_CEC>; 1710 clock-names = "iahb", "isfr", "vpll", "grf", "cec"; 1711 power-domains = <&power RK3399_PD_HDCP>; 1712 reg-io-width = <4>; 1713 rockchip,grf = <&grf>; 1714 status = "disabled"; 1715 1716 ports { 1717 hdmi_in: port { 1718 #address-cells = <1>; 1719 #size-cells = <0>; 1720 1721 hdmi_in_vopb: endpoint@0 { 1722 reg = <0>; 1723 remote-endpoint = <&vopb_out_hdmi>; 1724 }; 1725 hdmi_in_vopl: endpoint@1 { 1726 reg = <1>; 1727 remote-endpoint = <&vopl_out_hdmi>; 1728 }; 1729 }; 1730 }; 1731 }; 1732 1733 mipi_dsi: mipi@ff960000 { 1734 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1735 reg = <0x0 0xff960000 0x0 0x8000>; 1736 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 1737 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, 1738 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; 1739 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1740 power-domains = <&power RK3399_PD_VIO>; 1741 resets = <&cru SRST_P_MIPI_DSI0>; 1742 reset-names = "apb"; 1743 rockchip,grf = <&grf>; 1744 status = "disabled"; 1745 1746 ports { 1747 #address-cells = <1>; 1748 #size-cells = <0>; 1749 1750 mipi_in: port@0 { 1751 reg = <0>; 1752 #address-cells = <1>; 1753 #size-cells = <0>; 1754 1755 mipi_in_vopb: endpoint@0 { 1756 reg = <0>; 1757 remote-endpoint = <&vopb_out_mipi>; 1758 }; 1759 mipi_in_vopl: endpoint@1 { 1760 reg = <1>; 1761 remote-endpoint = <&vopl_out_mipi>; 1762 }; 1763 }; 1764 }; 1765 }; 1766 1767 mipi_dsi1: mipi@ff968000 { 1768 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1769 reg = <0x0 0xff968000 0x0 0x8000>; 1770 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>; 1771 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, 1772 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; 1773 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1774 power-domains = <&power RK3399_PD_VIO>; 1775 resets = <&cru SRST_P_MIPI_DSI1>; 1776 reset-names = "apb"; 1777 rockchip,grf = <&grf>; 1778 status = "disabled"; 1779 1780 ports { 1781 #address-cells = <1>; 1782 #size-cells = <0>; 1783 1784 mipi1_in: port@0 { 1785 reg = <0>; 1786 #address-cells = <1>; 1787 #size-cells = <0>; 1788 1789 mipi1_in_vopb: endpoint@0 { 1790 reg = <0>; 1791 remote-endpoint = <&vopb_out_mipi1>; 1792 }; 1793 1794 mipi1_in_vopl: endpoint@1 { 1795 reg = <1>; 1796 remote-endpoint = <&vopl_out_mipi1>; 1797 }; 1798 }; 1799 }; 1800 }; 1801 1802 edp: edp@ff970000 { 1803 compatible = "rockchip,rk3399-edp"; 1804 reg = <0x0 0xff970000 0x0 0x8000>; 1805 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 1806 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; 1807 clock-names = "dp", "pclk", "grf"; 1808 pinctrl-names = "default"; 1809 pinctrl-0 = <&edp_hpd>; 1810 power-domains = <&power RK3399_PD_EDP>; 1811 resets = <&cru SRST_P_EDP_CTRL>; 1812 reset-names = "dp"; 1813 rockchip,grf = <&grf>; 1814 status = "disabled"; 1815 1816 ports { 1817 #address-cells = <1>; 1818 #size-cells = <0>; 1819 edp_in: port@0 { 1820 reg = <0>; 1821 #address-cells = <1>; 1822 #size-cells = <0>; 1823 1824 edp_in_vopb: endpoint@0 { 1825 reg = <0>; 1826 remote-endpoint = <&vopb_out_edp>; 1827 }; 1828 1829 edp_in_vopl: endpoint@1 { 1830 reg = <1>; 1831 remote-endpoint = <&vopl_out_edp>; 1832 }; 1833 }; 1834 }; 1835 }; 1836 1837 gpu: gpu@ff9a0000 { 1838 compatible = "rockchip,rk3399-mali", "arm,mali-t860"; 1839 reg = <0x0 0xff9a0000 0x0 0x10000>; 1840 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>, 1841 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, 1842 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>; 1843 interrupt-names = "gpu", "job", "mmu"; 1844 clocks = <&cru ACLK_GPU>; 1845 power-domains = <&power RK3399_PD_GPU>; 1846 status = "disabled"; 1847 }; 1848 1849 pinctrl: pinctrl { 1850 compatible = "rockchip,rk3399-pinctrl"; 1851 rockchip,grf = <&grf>; 1852 rockchip,pmu = <&pmugrf>; 1853 #address-cells = <2>; 1854 #size-cells = <2>; 1855 ranges; 1856 1857 gpio0: gpio0@ff720000 { 1858 compatible = "rockchip,gpio-bank"; 1859 reg = <0x0 0xff720000 0x0 0x100>; 1860 clocks = <&pmucru PCLK_GPIO0_PMU>; 1861 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 1862 1863 gpio-controller; 1864 #gpio-cells = <0x2>; 1865 1866 interrupt-controller; 1867 #interrupt-cells = <0x2>; 1868 }; 1869 1870 gpio1: gpio1@ff730000 { 1871 compatible = "rockchip,gpio-bank"; 1872 reg = <0x0 0xff730000 0x0 0x100>; 1873 clocks = <&pmucru PCLK_GPIO1_PMU>; 1874 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 1875 1876 gpio-controller; 1877 #gpio-cells = <0x2>; 1878 1879 interrupt-controller; 1880 #interrupt-cells = <0x2>; 1881 }; 1882 1883 gpio2: gpio2@ff780000 { 1884 compatible = "rockchip,gpio-bank"; 1885 reg = <0x0 0xff780000 0x0 0x100>; 1886 clocks = <&cru PCLK_GPIO2>; 1887 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 1888 1889 gpio-controller; 1890 #gpio-cells = <0x2>; 1891 1892 interrupt-controller; 1893 #interrupt-cells = <0x2>; 1894 }; 1895 1896 gpio3: gpio3@ff788000 { 1897 compatible = "rockchip,gpio-bank"; 1898 reg = <0x0 0xff788000 0x0 0x100>; 1899 clocks = <&cru PCLK_GPIO3>; 1900 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 1901 1902 gpio-controller; 1903 #gpio-cells = <0x2>; 1904 1905 interrupt-controller; 1906 #interrupt-cells = <0x2>; 1907 }; 1908 1909 gpio4: gpio4@ff790000 { 1910 compatible = "rockchip,gpio-bank"; 1911 reg = <0x0 0xff790000 0x0 0x100>; 1912 clocks = <&cru PCLK_GPIO4>; 1913 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 1914 1915 gpio-controller; 1916 #gpio-cells = <0x2>; 1917 1918 interrupt-controller; 1919 #interrupt-cells = <0x2>; 1920 }; 1921 1922 pcfg_pull_up: pcfg-pull-up { 1923 bias-pull-up; 1924 }; 1925 1926 pcfg_pull_down: pcfg-pull-down { 1927 bias-pull-down; 1928 }; 1929 1930 pcfg_pull_none: pcfg-pull-none { 1931 bias-disable; 1932 }; 1933 1934 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1935 bias-disable; 1936 drive-strength = <12>; 1937 }; 1938 1939 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1940 bias-pull-up; 1941 drive-strength = <8>; 1942 }; 1943 1944 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1945 bias-pull-down; 1946 drive-strength = <4>; 1947 }; 1948 1949 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1950 bias-pull-up; 1951 drive-strength = <2>; 1952 }; 1953 1954 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 1955 bias-pull-down; 1956 drive-strength = <12>; 1957 }; 1958 1959 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 1960 bias-disable; 1961 drive-strength = <13>; 1962 }; 1963 1964 clock { 1965 clk_32k: clk-32k { 1966 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; 1967 }; 1968 }; 1969 1970 edp { 1971 edp_hpd: edp-hpd { 1972 rockchip,pins = 1973 <4 23 RK_FUNC_2 &pcfg_pull_none>; 1974 }; 1975 }; 1976 1977 gmac { 1978 rgmii_pins: rgmii-pins { 1979 rockchip,pins = 1980 /* mac_txclk */ 1981 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>, 1982 /* mac_rxclk */ 1983 <3 14 RK_FUNC_1 &pcfg_pull_none>, 1984 /* mac_mdio */ 1985 <3 13 RK_FUNC_1 &pcfg_pull_none>, 1986 /* mac_txen */ 1987 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>, 1988 /* mac_clk */ 1989 <3 11 RK_FUNC_1 &pcfg_pull_none>, 1990 /* mac_rxdv */ 1991 <3 9 RK_FUNC_1 &pcfg_pull_none>, 1992 /* mac_mdc */ 1993 <3 8 RK_FUNC_1 &pcfg_pull_none>, 1994 /* mac_rxd1 */ 1995 <3 7 RK_FUNC_1 &pcfg_pull_none>, 1996 /* mac_rxd0 */ 1997 <3 6 RK_FUNC_1 &pcfg_pull_none>, 1998 /* mac_txd1 */ 1999 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>, 2000 /* mac_txd0 */ 2001 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>, 2002 /* mac_rxd3 */ 2003 <3 3 RK_FUNC_1 &pcfg_pull_none>, 2004 /* mac_rxd2 */ 2005 <3 2 RK_FUNC_1 &pcfg_pull_none>, 2006 /* mac_txd3 */ 2007 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>, 2008 /* mac_txd2 */ 2009 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>; 2010 }; 2011 2012 rmii_pins: rmii-pins { 2013 rockchip,pins = 2014 /* mac_mdio */ 2015 <3 13 RK_FUNC_1 &pcfg_pull_none>, 2016 /* mac_txen */ 2017 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>, 2018 /* mac_clk */ 2019 <3 11 RK_FUNC_1 &pcfg_pull_none>, 2020 /* mac_rxer */ 2021 <3 10 RK_FUNC_1 &pcfg_pull_none>, 2022 /* mac_rxdv */ 2023 <3 9 RK_FUNC_1 &pcfg_pull_none>, 2024 /* mac_mdc */ 2025 <3 8 RK_FUNC_1 &pcfg_pull_none>, 2026 /* mac_rxd1 */ 2027 <3 7 RK_FUNC_1 &pcfg_pull_none>, 2028 /* mac_rxd0 */ 2029 <3 6 RK_FUNC_1 &pcfg_pull_none>, 2030 /* mac_txd1 */ 2031 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>, 2032 /* mac_txd0 */ 2033 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>; 2034 }; 2035 }; 2036 2037 i2c0 { 2038 i2c0_xfer: i2c0-xfer { 2039 rockchip,pins = 2040 <1 15 RK_FUNC_2 &pcfg_pull_none>, 2041 <1 16 RK_FUNC_2 &pcfg_pull_none>; 2042 }; 2043 }; 2044 2045 i2c1 { 2046 i2c1_xfer: i2c1-xfer { 2047 rockchip,pins = 2048 <4 2 RK_FUNC_1 &pcfg_pull_none>, 2049 <4 1 RK_FUNC_1 &pcfg_pull_none>; 2050 }; 2051 }; 2052 2053 i2c2 { 2054 i2c2_xfer: i2c2-xfer { 2055 rockchip,pins = 2056 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>, 2057 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>; 2058 }; 2059 }; 2060 2061 i2c3 { 2062 i2c3_xfer: i2c3-xfer { 2063 rockchip,pins = 2064 <4 17 RK_FUNC_1 &pcfg_pull_none>, 2065 <4 16 RK_FUNC_1 &pcfg_pull_none>; 2066 }; 2067 }; 2068 2069 i2c4 { 2070 i2c4_xfer: i2c4-xfer { 2071 rockchip,pins = 2072 <1 12 RK_FUNC_1 &pcfg_pull_none>, 2073 <1 11 RK_FUNC_1 &pcfg_pull_none>; 2074 }; 2075 }; 2076 2077 i2c5 { 2078 i2c5_xfer: i2c5-xfer { 2079 rockchip,pins = 2080 <3 11 RK_FUNC_2 &pcfg_pull_none>, 2081 <3 10 RK_FUNC_2 &pcfg_pull_none>; 2082 }; 2083 }; 2084 2085 i2c6 { 2086 i2c6_xfer: i2c6-xfer { 2087 rockchip,pins = 2088 <2 10 RK_FUNC_2 &pcfg_pull_none>, 2089 <2 9 RK_FUNC_2 &pcfg_pull_none>; 2090 }; 2091 }; 2092 2093 i2c7 { 2094 i2c7_xfer: i2c7-xfer { 2095 rockchip,pins = 2096 <2 8 RK_FUNC_2 &pcfg_pull_none>, 2097 <2 7 RK_FUNC_2 &pcfg_pull_none>; 2098 }; 2099 }; 2100 2101 i2c8 { 2102 i2c8_xfer: i2c8-xfer { 2103 rockchip,pins = 2104 <1 21 RK_FUNC_1 &pcfg_pull_none>, 2105 <1 20 RK_FUNC_1 &pcfg_pull_none>; 2106 }; 2107 }; 2108 2109 i2s0 { 2110 i2s0_2ch_bus: i2s0-2ch-bus { 2111 rockchip,pins = 2112 <3 24 RK_FUNC_1 &pcfg_pull_none>, 2113 <3 25 RK_FUNC_1 &pcfg_pull_none>, 2114 <3 26 RK_FUNC_1 &pcfg_pull_none>, 2115 <3 27 RK_FUNC_1 &pcfg_pull_none>, 2116 <3 31 RK_FUNC_1 &pcfg_pull_none>, 2117 <4 0 RK_FUNC_1 &pcfg_pull_none>; 2118 }; 2119 2120 i2s0_8ch_bus: i2s0-8ch-bus { 2121 rockchip,pins = 2122 <3 24 RK_FUNC_1 &pcfg_pull_none>, 2123 <3 25 RK_FUNC_1 &pcfg_pull_none>, 2124 <3 26 RK_FUNC_1 &pcfg_pull_none>, 2125 <3 27 RK_FUNC_1 &pcfg_pull_none>, 2126 <3 28 RK_FUNC_1 &pcfg_pull_none>, 2127 <3 29 RK_FUNC_1 &pcfg_pull_none>, 2128 <3 30 RK_FUNC_1 &pcfg_pull_none>, 2129 <3 31 RK_FUNC_1 &pcfg_pull_none>, 2130 <4 0 RK_FUNC_1 &pcfg_pull_none>; 2131 }; 2132 }; 2133 2134 i2s1 { 2135 i2s1_2ch_bus: i2s1-2ch-bus { 2136 rockchip,pins = 2137 <4 3 RK_FUNC_1 &pcfg_pull_none>, 2138 <4 4 RK_FUNC_1 &pcfg_pull_none>, 2139 <4 5 RK_FUNC_1 &pcfg_pull_none>, 2140 <4 6 RK_FUNC_1 &pcfg_pull_none>, 2141 <4 7 RK_FUNC_1 &pcfg_pull_none>; 2142 }; 2143 }; 2144 2145 sdio0 { 2146 sdio0_bus1: sdio0-bus1 { 2147 rockchip,pins = 2148 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>; 2149 }; 2150 2151 sdio0_bus4: sdio0-bus4 { 2152 rockchip,pins = 2153 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>, 2154 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>, 2155 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>, 2156 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>; 2157 }; 2158 2159 sdio0_cmd: sdio0-cmd { 2160 rockchip,pins = 2161 <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>; 2162 }; 2163 2164 sdio0_clk: sdio0-clk { 2165 rockchip,pins = 2166 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 2167 }; 2168 2169 sdio0_cd: sdio0-cd { 2170 rockchip,pins = 2171 <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>; 2172 }; 2173 2174 sdio0_pwr: sdio0-pwr { 2175 rockchip,pins = 2176 <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>; 2177 }; 2178 2179 sdio0_bkpwr: sdio0-bkpwr { 2180 rockchip,pins = 2181 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; 2182 }; 2183 2184 sdio0_wp: sdio0-wp { 2185 rockchip,pins = 2186 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>; 2187 }; 2188 2189 sdio0_int: sdio0-int { 2190 rockchip,pins = 2191 <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>; 2192 }; 2193 }; 2194 2195 sdmmc { 2196 sdmmc_bus1: sdmmc-bus1 { 2197 rockchip,pins = 2198 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; 2199 }; 2200 2201 sdmmc_bus4: sdmmc-bus4 { 2202 rockchip,pins = 2203 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>, 2204 <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>, 2205 <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>, 2206 <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>; 2207 }; 2208 2209 sdmmc_clk: sdmmc-clk { 2210 rockchip,pins = 2211 <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 2212 }; 2213 2214 sdmmc_cmd: sdmmc-cmd { 2215 rockchip,pins = 2216 <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>; 2217 }; 2218 2219 sdmmc_cd: sdmmc-cd { 2220 rockchip,pins = 2221 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>; 2222 }; 2223 2224 sdmmc_wp: sdmmc-wp { 2225 rockchip,pins = 2226 <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; 2227 }; 2228 }; 2229 2230 sleep { 2231 ap_pwroff: ap-pwroff { 2232 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>; 2233 }; 2234 2235 ddrio_pwroff: ddrio-pwroff { 2236 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; 2237 }; 2238 }; 2239 2240 spdif { 2241 spdif_bus: spdif-bus { 2242 rockchip,pins = 2243 <4 21 RK_FUNC_1 &pcfg_pull_none>; 2244 }; 2245 2246 spdif_bus_1: spdif-bus-1 { 2247 rockchip,pins = 2248 <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; 2249 }; 2250 }; 2251 2252 spi0 { 2253 spi0_clk: spi0-clk { 2254 rockchip,pins = 2255 <3 6 RK_FUNC_2 &pcfg_pull_up>; 2256 }; 2257 spi0_cs0: spi0-cs0 { 2258 rockchip,pins = 2259 <3 7 RK_FUNC_2 &pcfg_pull_up>; 2260 }; 2261 spi0_cs1: spi0-cs1 { 2262 rockchip,pins = 2263 <3 8 RK_FUNC_2 &pcfg_pull_up>; 2264 }; 2265 spi0_tx: spi0-tx { 2266 rockchip,pins = 2267 <3 5 RK_FUNC_2 &pcfg_pull_up>; 2268 }; 2269 spi0_rx: spi0-rx { 2270 rockchip,pins = 2271 <3 4 RK_FUNC_2 &pcfg_pull_up>; 2272 }; 2273 }; 2274 2275 spi1 { 2276 spi1_clk: spi1-clk { 2277 rockchip,pins = 2278 <1 9 RK_FUNC_2 &pcfg_pull_up>; 2279 }; 2280 spi1_cs0: spi1-cs0 { 2281 rockchip,pins = 2282 <1 10 RK_FUNC_2 &pcfg_pull_up>; 2283 }; 2284 spi1_rx: spi1-rx { 2285 rockchip,pins = 2286 <1 7 RK_FUNC_2 &pcfg_pull_up>; 2287 }; 2288 spi1_tx: spi1-tx { 2289 rockchip,pins = 2290 <1 8 RK_FUNC_2 &pcfg_pull_up>; 2291 }; 2292 }; 2293 2294 spi2 { 2295 spi2_clk: spi2-clk { 2296 rockchip,pins = 2297 <2 11 RK_FUNC_1 &pcfg_pull_up>; 2298 }; 2299 spi2_cs0: spi2-cs0 { 2300 rockchip,pins = 2301 <2 12 RK_FUNC_1 &pcfg_pull_up>; 2302 }; 2303 spi2_rx: spi2-rx { 2304 rockchip,pins = 2305 <2 9 RK_FUNC_1 &pcfg_pull_up>; 2306 }; 2307 spi2_tx: spi2-tx { 2308 rockchip,pins = 2309 <2 10 RK_FUNC_1 &pcfg_pull_up>; 2310 }; 2311 }; 2312 2313 spi3 { 2314 spi3_clk: spi3-clk { 2315 rockchip,pins = 2316 <1 17 RK_FUNC_1 &pcfg_pull_up>; 2317 }; 2318 spi3_cs0: spi3-cs0 { 2319 rockchip,pins = 2320 <1 18 RK_FUNC_1 &pcfg_pull_up>; 2321 }; 2322 spi3_rx: spi3-rx { 2323 rockchip,pins = 2324 <1 15 RK_FUNC_1 &pcfg_pull_up>; 2325 }; 2326 spi3_tx: spi3-tx { 2327 rockchip,pins = 2328 <1 16 RK_FUNC_1 &pcfg_pull_up>; 2329 }; 2330 }; 2331 2332 spi4 { 2333 spi4_clk: spi4-clk { 2334 rockchip,pins = 2335 <3 2 RK_FUNC_2 &pcfg_pull_up>; 2336 }; 2337 spi4_cs0: spi4-cs0 { 2338 rockchip,pins = 2339 <3 3 RK_FUNC_2 &pcfg_pull_up>; 2340 }; 2341 spi4_rx: spi4-rx { 2342 rockchip,pins = 2343 <3 0 RK_FUNC_2 &pcfg_pull_up>; 2344 }; 2345 spi4_tx: spi4-tx { 2346 rockchip,pins = 2347 <3 1 RK_FUNC_2 &pcfg_pull_up>; 2348 }; 2349 }; 2350 2351 spi5 { 2352 spi5_clk: spi5-clk { 2353 rockchip,pins = 2354 <2 22 RK_FUNC_2 &pcfg_pull_up>; 2355 }; 2356 spi5_cs0: spi5-cs0 { 2357 rockchip,pins = 2358 <2 23 RK_FUNC_2 &pcfg_pull_up>; 2359 }; 2360 spi5_rx: spi5-rx { 2361 rockchip,pins = 2362 <2 20 RK_FUNC_2 &pcfg_pull_up>; 2363 }; 2364 spi5_tx: spi5-tx { 2365 rockchip,pins = 2366 <2 21 RK_FUNC_2 &pcfg_pull_up>; 2367 }; 2368 }; 2369 2370 testclk { 2371 test_clkout0: test-clkout0 { 2372 rockchip,pins = 2373 <0 0 RK_FUNC_1 &pcfg_pull_none>; 2374 }; 2375 2376 test_clkout1: test-clkout1 { 2377 rockchip,pins = 2378 <2 25 RK_FUNC_2 &pcfg_pull_none>; 2379 }; 2380 2381 test_clkout2: test-clkout2 { 2382 rockchip,pins = 2383 <0 8 RK_FUNC_3 &pcfg_pull_none>; 2384 }; 2385 }; 2386 2387 tsadc { 2388 otp_gpio: otp-gpio { 2389 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>; 2390 }; 2391 2392 otp_out: otp-out { 2393 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>; 2394 }; 2395 }; 2396 2397 uart0 { 2398 uart0_xfer: uart0-xfer { 2399 rockchip,pins = 2400 <2 16 RK_FUNC_1 &pcfg_pull_up>, 2401 <2 17 RK_FUNC_1 &pcfg_pull_none>; 2402 }; 2403 2404 uart0_cts: uart0-cts { 2405 rockchip,pins = 2406 <2 18 RK_FUNC_1 &pcfg_pull_none>; 2407 }; 2408 2409 uart0_rts: uart0-rts { 2410 rockchip,pins = 2411 <2 19 RK_FUNC_1 &pcfg_pull_none>; 2412 }; 2413 }; 2414 2415 uart1 { 2416 uart1_xfer: uart1-xfer { 2417 rockchip,pins = 2418 <3 12 RK_FUNC_2 &pcfg_pull_up>, 2419 <3 13 RK_FUNC_2 &pcfg_pull_none>; 2420 }; 2421 }; 2422 2423 uart2a { 2424 uart2a_xfer: uart2a-xfer { 2425 rockchip,pins = 2426 <4 8 RK_FUNC_2 &pcfg_pull_up>, 2427 <4 9 RK_FUNC_2 &pcfg_pull_none>; 2428 }; 2429 }; 2430 2431 uart2b { 2432 uart2b_xfer: uart2b-xfer { 2433 rockchip,pins = 2434 <4 16 RK_FUNC_2 &pcfg_pull_up>, 2435 <4 17 RK_FUNC_2 &pcfg_pull_none>; 2436 }; 2437 }; 2438 2439 uart2c { 2440 uart2c_xfer: uart2c-xfer { 2441 rockchip,pins = 2442 <4 19 RK_FUNC_1 &pcfg_pull_up>, 2443 <4 20 RK_FUNC_1 &pcfg_pull_none>; 2444 }; 2445 }; 2446 2447 uart3 { 2448 uart3_xfer: uart3-xfer { 2449 rockchip,pins = 2450 <3 14 RK_FUNC_2 &pcfg_pull_up>, 2451 <3 15 RK_FUNC_2 &pcfg_pull_none>; 2452 }; 2453 2454 uart3_cts: uart3-cts { 2455 rockchip,pins = 2456 <3 18 RK_FUNC_2 &pcfg_pull_none>; 2457 }; 2458 2459 uart3_rts: uart3-rts { 2460 rockchip,pins = 2461 <3 19 RK_FUNC_2 &pcfg_pull_none>; 2462 }; 2463 }; 2464 2465 uart4 { 2466 uart4_xfer: uart4-xfer { 2467 rockchip,pins = 2468 <1 7 RK_FUNC_1 &pcfg_pull_up>, 2469 <1 8 RK_FUNC_1 &pcfg_pull_none>; 2470 }; 2471 }; 2472 2473 uarthdcp { 2474 uarthdcp_xfer: uarthdcp-xfer { 2475 rockchip,pins = 2476 <4 21 RK_FUNC_2 &pcfg_pull_up>, 2477 <4 22 RK_FUNC_2 &pcfg_pull_none>; 2478 }; 2479 }; 2480 2481 pwm0 { 2482 pwm0_pin: pwm0-pin { 2483 rockchip,pins = 2484 <4 18 RK_FUNC_1 &pcfg_pull_none>; 2485 }; 2486 2487 vop0_pwm_pin: vop0-pwm-pin { 2488 rockchip,pins = 2489 <4 18 RK_FUNC_2 &pcfg_pull_none>; 2490 }; 2491 }; 2492 2493 pwm1 { 2494 pwm1_pin: pwm1-pin { 2495 rockchip,pins = 2496 <4 22 RK_FUNC_1 &pcfg_pull_none>; 2497 }; 2498 2499 vop1_pwm_pin: vop1-pwm-pin { 2500 rockchip,pins = 2501 <4 18 RK_FUNC_3 &pcfg_pull_none>; 2502 }; 2503 }; 2504 2505 pwm2 { 2506 pwm2_pin: pwm2-pin { 2507 rockchip,pins = 2508 <1 19 RK_FUNC_1 &pcfg_pull_none>; 2509 }; 2510 }; 2511 2512 pwm3a { 2513 pwm3a_pin: pwm3a-pin { 2514 rockchip,pins = 2515 <0 6 RK_FUNC_1 &pcfg_pull_none>; 2516 }; 2517 }; 2518 2519 pwm3b { 2520 pwm3b_pin: pwm3b-pin { 2521 rockchip,pins = 2522 <1 14 RK_FUNC_1 &pcfg_pull_none>; 2523 }; 2524 }; 2525 2526 hdmi { 2527 hdmi_i2c_xfer: hdmi-i2c-xfer { 2528 rockchip,pins = 2529 <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>, 2530 <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; 2531 }; 2532 2533 hdmi_cec: hdmi-cec { 2534 rockchip,pins = 2535 <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>; 2536 }; 2537 }; 2538 2539 pcie { 2540 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2541 rockchip,pins = 2542 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2543 }; 2544 2545 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2546 rockchip,pins = 2547 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2548 }; 2549 }; 2550 2551 }; 2552}; 2553