1/* 2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include <dt-bindings/clock/rk3399-cru.h> 44#include <dt-bindings/gpio/gpio.h> 45#include <dt-bindings/interrupt-controller/arm-gic.h> 46#include <dt-bindings/interrupt-controller/irq.h> 47#include <dt-bindings/pinctrl/rockchip.h> 48#include <dt-bindings/power/rk3399-power.h> 49#include <dt-bindings/thermal/thermal.h> 50 51/ { 52 compatible = "rockchip,rk3399"; 53 54 interrupt-parent = <&gic>; 55 #address-cells = <2>; 56 #size-cells = <2>; 57 58 aliases { 59 i2c0 = &i2c0; 60 i2c1 = &i2c1; 61 i2c2 = &i2c2; 62 i2c3 = &i2c3; 63 i2c4 = &i2c4; 64 i2c5 = &i2c5; 65 i2c6 = &i2c6; 66 i2c7 = &i2c7; 67 i2c8 = &i2c8; 68 serial0 = &uart0; 69 serial1 = &uart1; 70 serial2 = &uart2; 71 serial3 = &uart3; 72 serial4 = &uart4; 73 }; 74 75 cpus { 76 #address-cells = <2>; 77 #size-cells = <0>; 78 79 cpu-map { 80 cluster0 { 81 core0 { 82 cpu = <&cpu_l0>; 83 }; 84 core1 { 85 cpu = <&cpu_l1>; 86 }; 87 core2 { 88 cpu = <&cpu_l2>; 89 }; 90 core3 { 91 cpu = <&cpu_l3>; 92 }; 93 }; 94 95 cluster1 { 96 core0 { 97 cpu = <&cpu_b0>; 98 }; 99 core1 { 100 cpu = <&cpu_b1>; 101 }; 102 }; 103 }; 104 105 cpu_l0: cpu@0 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53", "arm,armv8"; 108 reg = <0x0 0x0>; 109 enable-method = "psci"; 110 #cooling-cells = <2>; /* min followed by max */ 111 clocks = <&cru ARMCLKL>; 112 }; 113 114 cpu_l1: cpu@1 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a53", "arm,armv8"; 117 reg = <0x0 0x1>; 118 enable-method = "psci"; 119 clocks = <&cru ARMCLKL>; 120 }; 121 122 cpu_l2: cpu@2 { 123 device_type = "cpu"; 124 compatible = "arm,cortex-a53", "arm,armv8"; 125 reg = <0x0 0x2>; 126 enable-method = "psci"; 127 clocks = <&cru ARMCLKL>; 128 }; 129 130 cpu_l3: cpu@3 { 131 device_type = "cpu"; 132 compatible = "arm,cortex-a53", "arm,armv8"; 133 reg = <0x0 0x3>; 134 enable-method = "psci"; 135 clocks = <&cru ARMCLKL>; 136 }; 137 138 cpu_b0: cpu@100 { 139 device_type = "cpu"; 140 compatible = "arm,cortex-a72", "arm,armv8"; 141 reg = <0x0 0x100>; 142 enable-method = "psci"; 143 #cooling-cells = <2>; /* min followed by max */ 144 clocks = <&cru ARMCLKB>; 145 }; 146 147 cpu_b1: cpu@101 { 148 device_type = "cpu"; 149 compatible = "arm,cortex-a72", "arm,armv8"; 150 reg = <0x0 0x101>; 151 enable-method = "psci"; 152 clocks = <&cru ARMCLKB>; 153 }; 154 }; 155 156 pmu_a53 { 157 compatible = "arm,cortex-a53-pmu"; 158 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 159 }; 160 161 pmu_a72 { 162 compatible = "arm,cortex-a72-pmu"; 163 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 164 }; 165 166 psci { 167 compatible = "arm,psci-1.0"; 168 method = "smc"; 169 }; 170 171 timer { 172 compatible = "arm,armv8-timer"; 173 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 174 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 175 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 176 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 177 }; 178 179 xin24m: xin24m { 180 compatible = "fixed-clock"; 181 clock-frequency = <24000000>; 182 clock-output-names = "xin24m"; 183 #clock-cells = <0>; 184 }; 185 186 amba { 187 compatible = "simple-bus"; 188 #address-cells = <2>; 189 #size-cells = <2>; 190 ranges; 191 192 dmac_bus: dma-controller@ff6d0000 { 193 compatible = "arm,pl330", "arm,primecell"; 194 reg = <0x0 0xff6d0000 0x0 0x4000>; 195 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 196 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 197 #dma-cells = <1>; 198 clocks = <&cru ACLK_DMAC0_PERILP>; 199 clock-names = "apb_pclk"; 200 }; 201 202 dmac_peri: dma-controller@ff6e0000 { 203 compatible = "arm,pl330", "arm,primecell"; 204 reg = <0x0 0xff6e0000 0x0 0x4000>; 205 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 206 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 207 #dma-cells = <1>; 208 clocks = <&cru ACLK_DMAC1_PERILP>; 209 clock-names = "apb_pclk"; 210 }; 211 }; 212 213 gmac: ethernet@fe300000 { 214 compatible = "rockchip,rk3399-gmac"; 215 reg = <0x0 0xfe300000 0x0 0x10000>; 216 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 217 interrupt-names = "macirq"; 218 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 219 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 220 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 221 <&cru PCLK_GMAC>; 222 clock-names = "stmmaceth", "mac_clk_rx", 223 "mac_clk_tx", "clk_mac_ref", 224 "clk_mac_refout", "aclk_mac", 225 "pclk_mac"; 226 power-domains = <&power RK3399_PD_GMAC>; 227 resets = <&cru SRST_A_GMAC>; 228 reset-names = "stmmaceth"; 229 rockchip,grf = <&grf>; 230 status = "disabled"; 231 }; 232 233 sdio0: dwmmc@fe310000 { 234 compatible = "rockchip,rk3399-dw-mshc", 235 "rockchip,rk3288-dw-mshc"; 236 reg = <0x0 0xfe310000 0x0 0x4000>; 237 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 238 clock-freq-min-max = <400000 150000000>; 239 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 240 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 241 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 242 fifo-depth = <0x100>; 243 status = "disabled"; 244 }; 245 246 sdmmc: dwmmc@fe320000 { 247 compatible = "rockchip,rk3399-dw-mshc", 248 "rockchip,rk3288-dw-mshc"; 249 reg = <0x0 0xfe320000 0x0 0x4000>; 250 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 251 clock-freq-min-max = <400000 150000000>; 252 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 253 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 254 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 255 fifo-depth = <0x100>; 256 status = "disabled"; 257 }; 258 259 sdhci: sdhci@fe330000 { 260 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 261 reg = <0x0 0xfe330000 0x0 0x10000>; 262 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 263 arasan,soc-ctl-syscon = <&grf>; 264 assigned-clocks = <&cru SCLK_EMMC>; 265 assigned-clock-rates = <200000000>; 266 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 267 clock-names = "clk_xin", "clk_ahb"; 268 clock-output-names = "emmc_cardclock"; 269 #clock-cells = <0>; 270 phys = <&emmc_phy>; 271 phy-names = "phy_arasan"; 272 status = "disabled"; 273 }; 274 275 pcie0: pcie@f8000000 { 276 compatible = "rockchip,rk3399-pcie"; 277 reg = <0x0 0xf8000000 0x0 0x2000000>, 278 <0x0 0xfd000000 0x0 0x1000000>; 279 reg-names = "axi-base", "apb-base"; 280 #address-cells = <3>; 281 #size-cells = <2>; 282 #interrupt-cells = <1>; 283 bus-range = <0x0 0x1>; 284 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 285 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 286 clock-names = "aclk", "aclk-perf", 287 "hclk", "pm"; 288 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 289 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 290 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 291 interrupt-names = "sys", "legacy", "client"; 292 interrupt-map-mask = <0 0 0 7>; 293 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 294 <0 0 0 2 &pcie0_intc 1>, 295 <0 0 0 3 &pcie0_intc 2>, 296 <0 0 0 4 &pcie0_intc 3>; 297 msi-map = <0x0 &its 0x0 0x1000>; 298 phys = <&pcie_phy>; 299 phy-names = "pcie-phy"; 300 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000 301 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>; 302 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 303 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 304 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 305 <&cru SRST_A_PCIE>; 306 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 307 "pm", "pclk", "aclk"; 308 status = "disabled"; 309 310 pcie0_intc: interrupt-controller { 311 interrupt-controller; 312 #address-cells = <0>; 313 #interrupt-cells = <1>; 314 }; 315 }; 316 317 usb_host0_ehci: usb@fe380000 { 318 compatible = "generic-ehci"; 319 reg = <0x0 0xfe380000 0x0 0x20000>; 320 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 321 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; 322 clock-names = "hclk_host0", "hclk_host0_arb"; 323 phys = <&u2phy0_host>; 324 phy-names = "usb"; 325 status = "disabled"; 326 }; 327 328 usb_host0_ohci: usb@fe3a0000 { 329 compatible = "generic-ohci"; 330 reg = <0x0 0xfe3a0000 0x0 0x20000>; 331 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 332 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; 333 clock-names = "hclk_host0", "hclk_host0_arb"; 334 status = "disabled"; 335 }; 336 337 usb_host1_ehci: usb@fe3c0000 { 338 compatible = "generic-ehci"; 339 reg = <0x0 0xfe3c0000 0x0 0x20000>; 340 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 341 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; 342 clock-names = "hclk_host1", "hclk_host1_arb"; 343 phys = <&u2phy1_host>; 344 phy-names = "usb"; 345 status = "disabled"; 346 }; 347 348 usb_host1_ohci: usb@fe3e0000 { 349 compatible = "generic-ohci"; 350 reg = <0x0 0xfe3e0000 0x0 0x20000>; 351 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 352 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; 353 clock-names = "hclk_host1", "hclk_host1_arb"; 354 status = "disabled"; 355 }; 356 357 gic: interrupt-controller@fee00000 { 358 compatible = "arm,gic-v3"; 359 #interrupt-cells = <4>; 360 #address-cells = <2>; 361 #size-cells = <2>; 362 ranges; 363 interrupt-controller; 364 365 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 366 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 367 <0x0 0xfff00000 0 0x10000>, /* GICC */ 368 <0x0 0xfff10000 0 0x10000>, /* GICH */ 369 <0x0 0xfff20000 0 0x10000>; /* GICV */ 370 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 371 its: interrupt-controller@fee20000 { 372 compatible = "arm,gic-v3-its"; 373 msi-controller; 374 reg = <0x0 0xfee20000 0x0 0x20000>; 375 }; 376 377 ppi-partitions { 378 ppi_cluster0: interrupt-partition-0 { 379 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 380 }; 381 382 ppi_cluster1: interrupt-partition-1 { 383 affinity = <&cpu_b0 &cpu_b1>; 384 }; 385 }; 386 }; 387 388 saradc: saradc@ff100000 { 389 compatible = "rockchip,rk3399-saradc"; 390 reg = <0x0 0xff100000 0x0 0x100>; 391 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 392 #io-channel-cells = <1>; 393 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 394 clock-names = "saradc", "apb_pclk"; 395 resets = <&cru SRST_P_SARADC>; 396 reset-names = "saradc-apb"; 397 status = "disabled"; 398 }; 399 400 i2c1: i2c@ff110000 { 401 compatible = "rockchip,rk3399-i2c"; 402 reg = <0x0 0xff110000 0x0 0x1000>; 403 assigned-clocks = <&cru SCLK_I2C1>; 404 assigned-clock-rates = <200000000>; 405 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 406 clock-names = "i2c", "pclk"; 407 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 408 pinctrl-names = "default"; 409 pinctrl-0 = <&i2c1_xfer>; 410 #address-cells = <1>; 411 #size-cells = <0>; 412 status = "disabled"; 413 }; 414 415 i2c2: i2c@ff120000 { 416 compatible = "rockchip,rk3399-i2c"; 417 reg = <0x0 0xff120000 0x0 0x1000>; 418 assigned-clocks = <&cru SCLK_I2C2>; 419 assigned-clock-rates = <200000000>; 420 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 421 clock-names = "i2c", "pclk"; 422 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 423 pinctrl-names = "default"; 424 pinctrl-0 = <&i2c2_xfer>; 425 #address-cells = <1>; 426 #size-cells = <0>; 427 status = "disabled"; 428 }; 429 430 i2c3: i2c@ff130000 { 431 compatible = "rockchip,rk3399-i2c"; 432 reg = <0x0 0xff130000 0x0 0x1000>; 433 assigned-clocks = <&cru SCLK_I2C3>; 434 assigned-clock-rates = <200000000>; 435 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 436 clock-names = "i2c", "pclk"; 437 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 438 pinctrl-names = "default"; 439 pinctrl-0 = <&i2c3_xfer>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 status = "disabled"; 443 }; 444 445 i2c5: i2c@ff140000 { 446 compatible = "rockchip,rk3399-i2c"; 447 reg = <0x0 0xff140000 0x0 0x1000>; 448 assigned-clocks = <&cru SCLK_I2C5>; 449 assigned-clock-rates = <200000000>; 450 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 451 clock-names = "i2c", "pclk"; 452 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 453 pinctrl-names = "default"; 454 pinctrl-0 = <&i2c5_xfer>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 status = "disabled"; 458 }; 459 460 i2c6: i2c@ff150000 { 461 compatible = "rockchip,rk3399-i2c"; 462 reg = <0x0 0xff150000 0x0 0x1000>; 463 assigned-clocks = <&cru SCLK_I2C6>; 464 assigned-clock-rates = <200000000>; 465 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 466 clock-names = "i2c", "pclk"; 467 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 468 pinctrl-names = "default"; 469 pinctrl-0 = <&i2c6_xfer>; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 status = "disabled"; 473 }; 474 475 i2c7: i2c@ff160000 { 476 compatible = "rockchip,rk3399-i2c"; 477 reg = <0x0 0xff160000 0x0 0x1000>; 478 assigned-clocks = <&cru SCLK_I2C7>; 479 assigned-clock-rates = <200000000>; 480 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 481 clock-names = "i2c", "pclk"; 482 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 483 pinctrl-names = "default"; 484 pinctrl-0 = <&i2c7_xfer>; 485 #address-cells = <1>; 486 #size-cells = <0>; 487 status = "disabled"; 488 }; 489 490 uart0: serial@ff180000 { 491 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 492 reg = <0x0 0xff180000 0x0 0x100>; 493 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 494 clock-names = "baudclk", "apb_pclk"; 495 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 496 reg-shift = <2>; 497 reg-io-width = <4>; 498 pinctrl-names = "default"; 499 pinctrl-0 = <&uart0_xfer>; 500 status = "disabled"; 501 }; 502 503 uart1: serial@ff190000 { 504 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 505 reg = <0x0 0xff190000 0x0 0x100>; 506 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 507 clock-names = "baudclk", "apb_pclk"; 508 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 509 reg-shift = <2>; 510 reg-io-width = <4>; 511 pinctrl-names = "default"; 512 pinctrl-0 = <&uart1_xfer>; 513 status = "disabled"; 514 }; 515 516 uart2: serial@ff1a0000 { 517 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 518 reg = <0x0 0xff1a0000 0x0 0x100>; 519 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 520 clock-names = "baudclk", "apb_pclk"; 521 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 522 reg-shift = <2>; 523 reg-io-width = <4>; 524 pinctrl-names = "default"; 525 pinctrl-0 = <&uart2c_xfer>; 526 status = "disabled"; 527 }; 528 529 uart3: serial@ff1b0000 { 530 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 531 reg = <0x0 0xff1b0000 0x0 0x100>; 532 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 533 clock-names = "baudclk", "apb_pclk"; 534 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 535 reg-shift = <2>; 536 reg-io-width = <4>; 537 pinctrl-names = "default"; 538 pinctrl-0 = <&uart3_xfer>; 539 status = "disabled"; 540 }; 541 542 spi0: spi@ff1c0000 { 543 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 544 reg = <0x0 0xff1c0000 0x0 0x1000>; 545 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 546 clock-names = "spiclk", "apb_pclk"; 547 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 548 pinctrl-names = "default"; 549 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 status = "disabled"; 553 }; 554 555 spi1: spi@ff1d0000 { 556 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 557 reg = <0x0 0xff1d0000 0x0 0x1000>; 558 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 559 clock-names = "spiclk", "apb_pclk"; 560 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 561 pinctrl-names = "default"; 562 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 563 #address-cells = <1>; 564 #size-cells = <0>; 565 status = "disabled"; 566 }; 567 568 spi2: spi@ff1e0000 { 569 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 570 reg = <0x0 0xff1e0000 0x0 0x1000>; 571 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 572 clock-names = "spiclk", "apb_pclk"; 573 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 574 pinctrl-names = "default"; 575 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 576 #address-cells = <1>; 577 #size-cells = <0>; 578 status = "disabled"; 579 }; 580 581 spi4: spi@ff1f0000 { 582 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 583 reg = <0x0 0xff1f0000 0x0 0x1000>; 584 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 585 clock-names = "spiclk", "apb_pclk"; 586 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 587 pinctrl-names = "default"; 588 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 589 #address-cells = <1>; 590 #size-cells = <0>; 591 status = "disabled"; 592 }; 593 594 spi5: spi@ff200000 { 595 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 596 reg = <0x0 0xff200000 0x0 0x1000>; 597 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 598 clock-names = "spiclk", "apb_pclk"; 599 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 600 pinctrl-names = "default"; 601 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 602 #address-cells = <1>; 603 #size-cells = <0>; 604 status = "disabled"; 605 }; 606 607 thermal-zones { 608 cpu_thermal: cpu { 609 polling-delay-passive = <100>; 610 polling-delay = <1000>; 611 612 thermal-sensors = <&tsadc 0>; 613 614 trips { 615 cpu_alert0: cpu_alert0 { 616 temperature = <70000>; 617 hysteresis = <2000>; 618 type = "passive"; 619 }; 620 cpu_alert1: cpu_alert1 { 621 temperature = <75000>; 622 hysteresis = <2000>; 623 type = "passive"; 624 }; 625 cpu_crit: cpu_crit { 626 temperature = <95000>; 627 hysteresis = <2000>; 628 type = "critical"; 629 }; 630 }; 631 632 cooling-maps { 633 map0 { 634 trip = <&cpu_alert0>; 635 cooling-device = 636 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 637 }; 638 map1 { 639 trip = <&cpu_alert1>; 640 cooling-device = 641 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 642 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 643 }; 644 }; 645 }; 646 647 gpu_thermal: gpu { 648 polling-delay-passive = <100>; 649 polling-delay = <1000>; 650 651 thermal-sensors = <&tsadc 1>; 652 653 trips { 654 gpu_alert0: gpu_alert0 { 655 temperature = <75000>; 656 hysteresis = <2000>; 657 type = "passive"; 658 }; 659 gpu_crit: gpu_crit { 660 temperature = <95000>; 661 hysteresis = <2000>; 662 type = "critical"; 663 }; 664 }; 665 666 cooling-maps { 667 map0 { 668 trip = <&gpu_alert0>; 669 cooling-device = 670 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 671 }; 672 }; 673 }; 674 }; 675 676 tsadc: tsadc@ff260000 { 677 compatible = "rockchip,rk3399-tsadc"; 678 reg = <0x0 0xff260000 0x0 0x100>; 679 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 680 assigned-clocks = <&cru SCLK_TSADC>; 681 assigned-clock-rates = <750000>; 682 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 683 clock-names = "tsadc", "apb_pclk"; 684 resets = <&cru SRST_TSADC>; 685 reset-names = "tsadc-apb"; 686 rockchip,grf = <&grf>; 687 rockchip,hw-tshut-temp = <95000>; 688 pinctrl-names = "init", "default", "sleep"; 689 pinctrl-0 = <&otp_gpio>; 690 pinctrl-1 = <&otp_out>; 691 pinctrl-2 = <&otp_gpio>; 692 #thermal-sensor-cells = <1>; 693 status = "disabled"; 694 }; 695 696 qos_gmac: qos@ffa5c000 { 697 compatible = "syscon"; 698 reg = <0x0 0xffa5c000 0x0 0x20>; 699 }; 700 701 qos_hdcp: qos@ffa90000 { 702 compatible = "syscon"; 703 reg = <0x0 0xffa90000 0x0 0x20>; 704 }; 705 706 qos_iep: qos@ffa98000 { 707 compatible = "syscon"; 708 reg = <0x0 0xffa98000 0x0 0x20>; 709 }; 710 711 qos_isp0_m0: qos@ffaa0000 { 712 compatible = "syscon"; 713 reg = <0x0 0xffaa0000 0x0 0x20>; 714 }; 715 716 qos_isp0_m1: qos@ffaa0080 { 717 compatible = "syscon"; 718 reg = <0x0 0xffaa0080 0x0 0x20>; 719 }; 720 721 qos_isp1_m0: qos@ffaa8000 { 722 compatible = "syscon"; 723 reg = <0x0 0xffaa8000 0x0 0x20>; 724 }; 725 726 qos_isp1_m1: qos@ffaa8080 { 727 compatible = "syscon"; 728 reg = <0x0 0xffaa8080 0x0 0x20>; 729 }; 730 731 qos_rga_r: qos@ffab0000 { 732 compatible = "syscon"; 733 reg = <0x0 0xffab0000 0x0 0x20>; 734 }; 735 736 qos_rga_w: qos@ffab0080 { 737 compatible = "syscon"; 738 reg = <0x0 0xffab0080 0x0 0x20>; 739 }; 740 741 qos_video_m0: qos@ffab8000 { 742 compatible = "syscon"; 743 reg = <0x0 0xffab8000 0x0 0x20>; 744 }; 745 746 qos_video_m1_r: qos@ffac0000 { 747 compatible = "syscon"; 748 reg = <0x0 0xffac0000 0x0 0x20>; 749 }; 750 751 qos_video_m1_w: qos@ffac0080 { 752 compatible = "syscon"; 753 reg = <0x0 0xffac0080 0x0 0x20>; 754 }; 755 756 qos_vop_big_r: qos@ffac8000 { 757 compatible = "syscon"; 758 reg = <0x0 0xffac8000 0x0 0x20>; 759 }; 760 761 qos_vop_big_w: qos@ffac8080 { 762 compatible = "syscon"; 763 reg = <0x0 0xffac8080 0x0 0x20>; 764 }; 765 766 qos_vop_little: qos@ffad0000 { 767 compatible = "syscon"; 768 reg = <0x0 0xffad0000 0x0 0x20>; 769 }; 770 771 qos_gpu: qos@ffae0000 { 772 compatible = "syscon"; 773 reg = <0x0 0xffae0000 0x0 0x20>; 774 }; 775 776 pmu: power-management@ff310000 { 777 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 778 reg = <0x0 0xff310000 0x0 0x1000>; 779 780 /* 781 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 782 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 783 * Some of the power domains are grouped together for every 784 * voltage domain. 785 * The detail contents as below. 786 */ 787 power: power-controller { 788 compatible = "rockchip,rk3399-power-controller"; 789 #power-domain-cells = <1>; 790 #address-cells = <1>; 791 #size-cells = <0>; 792 793 /* These power domains are grouped by VD_CENTER */ 794 pd_iep@RK3399_PD_IEP { 795 reg = <RK3399_PD_IEP>; 796 clocks = <&cru ACLK_IEP>, 797 <&cru HCLK_IEP>; 798 pm_qos = <&qos_iep>; 799 }; 800 pd_rga@RK3399_PD_RGA { 801 reg = <RK3399_PD_RGA>; 802 clocks = <&cru ACLK_RGA>, 803 <&cru HCLK_RGA>; 804 pm_qos = <&qos_rga_r>, 805 <&qos_rga_w>; 806 }; 807 pd_vcodec@RK3399_PD_VCODEC { 808 reg = <RK3399_PD_VCODEC>; 809 clocks = <&cru ACLK_VCODEC>, 810 <&cru HCLK_VCODEC>; 811 pm_qos = <&qos_video_m0>; 812 }; 813 pd_vdu@RK3399_PD_VDU { 814 reg = <RK3399_PD_VDU>; 815 clocks = <&cru ACLK_VDU>, 816 <&cru HCLK_VDU>; 817 pm_qos = <&qos_video_m1_r>, 818 <&qos_video_m1_w>; 819 }; 820 821 /* These power domains are grouped by VD_GPU */ 822 pd_gpu@RK3399_PD_GPU { 823 reg = <RK3399_PD_GPU>; 824 clocks = <&cru ACLK_GPU>; 825 pm_qos = <&qos_gpu>; 826 }; 827 828 /* These power domains are grouped by VD_LOGIC */ 829 pd_gmac@RK3399_PD_GMAC { 830 reg = <RK3399_PD_GMAC>; 831 clocks = <&cru ACLK_GMAC>; 832 pm_qos = <&qos_gmac>; 833 }; 834 pd_vio@RK3399_PD_VIO { 835 reg = <RK3399_PD_VIO>; 836 #address-cells = <1>; 837 #size-cells = <0>; 838 839 pd_hdcp@RK3399_PD_HDCP { 840 reg = <RK3399_PD_HDCP>; 841 clocks = <&cru ACLK_HDCP>, 842 <&cru HCLK_HDCP>, 843 <&cru PCLK_HDCP>; 844 pm_qos = <&qos_hdcp>; 845 }; 846 pd_isp0@RK3399_PD_ISP0 { 847 reg = <RK3399_PD_ISP0>; 848 clocks = <&cru ACLK_ISP0>, 849 <&cru HCLK_ISP0>; 850 pm_qos = <&qos_isp0_m0>, 851 <&qos_isp0_m1>; 852 }; 853 pd_isp1@RK3399_PD_ISP1 { 854 reg = <RK3399_PD_ISP1>; 855 clocks = <&cru ACLK_ISP1>, 856 <&cru HCLK_ISP1>; 857 pm_qos = <&qos_isp1_m0>, 858 <&qos_isp1_m1>; 859 }; 860 pd_tcpc0@RK3399_PD_TCPC0 { 861 reg = <RK3399_PD_TCPD0>; 862 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 863 <&cru SCLK_UPHY0_TCPDPHY_REF>; 864 }; 865 pd_tcpc1@RK3399_PD_TCPC1 { 866 reg = <RK3399_PD_TCPD1>; 867 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 868 <&cru SCLK_UPHY1_TCPDPHY_REF>; 869 }; 870 pd_vo@RK3399_PD_VO { 871 reg = <RK3399_PD_VO>; 872 #address-cells = <1>; 873 #size-cells = <0>; 874 875 pd_vopb@RK3399_PD_VOPB { 876 reg = <RK3399_PD_VOPB>; 877 clocks = <&cru ACLK_VOP0>, 878 <&cru HCLK_VOP0>; 879 pm_qos = <&qos_vop_big_r>, 880 <&qos_vop_big_w>; 881 }; 882 pd_vopl@RK3399_PD_VOPL { 883 reg = <RK3399_PD_VOPL>; 884 clocks = <&cru ACLK_VOP1>, 885 <&cru HCLK_VOP1>; 886 pm_qos = <&qos_vop_little>; 887 }; 888 }; 889 }; 890 }; 891 }; 892 893 pmugrf: syscon@ff320000 { 894 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 895 reg = <0x0 0xff320000 0x0 0x1000>; 896 #address-cells = <1>; 897 #size-cells = <1>; 898 899 pmu_io_domains: io-domains { 900 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 901 status = "disabled"; 902 }; 903 }; 904 905 spi3: spi@ff350000 { 906 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 907 reg = <0x0 0xff350000 0x0 0x1000>; 908 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 909 clock-names = "spiclk", "apb_pclk"; 910 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 911 pinctrl-names = "default"; 912 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 913 #address-cells = <1>; 914 #size-cells = <0>; 915 status = "disabled"; 916 }; 917 918 uart4: serial@ff370000 { 919 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 920 reg = <0x0 0xff370000 0x0 0x100>; 921 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 922 clock-names = "baudclk", "apb_pclk"; 923 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 924 reg-shift = <2>; 925 reg-io-width = <4>; 926 pinctrl-names = "default"; 927 pinctrl-0 = <&uart4_xfer>; 928 status = "disabled"; 929 }; 930 931 i2c0: i2c@ff3c0000 { 932 compatible = "rockchip,rk3399-i2c"; 933 reg = <0x0 0xff3c0000 0x0 0x1000>; 934 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 935 assigned-clock-rates = <200000000>; 936 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 937 clock-names = "i2c", "pclk"; 938 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 939 pinctrl-names = "default"; 940 pinctrl-0 = <&i2c0_xfer>; 941 #address-cells = <1>; 942 #size-cells = <0>; 943 status = "disabled"; 944 }; 945 946 i2c4: i2c@ff3d0000 { 947 compatible = "rockchip,rk3399-i2c"; 948 reg = <0x0 0xff3d0000 0x0 0x1000>; 949 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 950 assigned-clock-rates = <200000000>; 951 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 952 clock-names = "i2c", "pclk"; 953 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 954 pinctrl-names = "default"; 955 pinctrl-0 = <&i2c4_xfer>; 956 #address-cells = <1>; 957 #size-cells = <0>; 958 status = "disabled"; 959 }; 960 961 i2c8: i2c@ff3e0000 { 962 compatible = "rockchip,rk3399-i2c"; 963 reg = <0x0 0xff3e0000 0x0 0x1000>; 964 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 965 assigned-clock-rates = <200000000>; 966 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 967 clock-names = "i2c", "pclk"; 968 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 969 pinctrl-names = "default"; 970 pinctrl-0 = <&i2c8_xfer>; 971 #address-cells = <1>; 972 #size-cells = <0>; 973 status = "disabled"; 974 }; 975 976 pwm0: pwm@ff420000 { 977 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 978 reg = <0x0 0xff420000 0x0 0x10>; 979 #pwm-cells = <3>; 980 pinctrl-names = "default"; 981 pinctrl-0 = <&pwm0_pin>; 982 clocks = <&pmucru PCLK_RKPWM_PMU>; 983 clock-names = "pwm"; 984 status = "disabled"; 985 }; 986 987 pwm1: pwm@ff420010 { 988 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 989 reg = <0x0 0xff420010 0x0 0x10>; 990 #pwm-cells = <3>; 991 pinctrl-names = "default"; 992 pinctrl-0 = <&pwm1_pin>; 993 clocks = <&pmucru PCLK_RKPWM_PMU>; 994 clock-names = "pwm"; 995 status = "disabled"; 996 }; 997 998 pwm2: pwm@ff420020 { 999 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1000 reg = <0x0 0xff420020 0x0 0x10>; 1001 #pwm-cells = <3>; 1002 pinctrl-names = "default"; 1003 pinctrl-0 = <&pwm2_pin>; 1004 clocks = <&pmucru PCLK_RKPWM_PMU>; 1005 clock-names = "pwm"; 1006 status = "disabled"; 1007 }; 1008 1009 pwm3: pwm@ff420030 { 1010 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1011 reg = <0x0 0xff420030 0x0 0x10>; 1012 #pwm-cells = <3>; 1013 pinctrl-names = "default"; 1014 pinctrl-0 = <&pwm3a_pin>; 1015 clocks = <&pmucru PCLK_RKPWM_PMU>; 1016 clock-names = "pwm"; 1017 status = "disabled"; 1018 }; 1019 1020 efuse0: efuse@ff690000 { 1021 compatible = "rockchip,rk3399-efuse"; 1022 reg = <0x0 0xff690000 0x0 0x80>; 1023 #address-cells = <1>; 1024 #size-cells = <1>; 1025 clocks = <&cru PCLK_EFUSE1024NS>; 1026 clock-names = "pclk_efuse"; 1027 1028 /* Data cells */ 1029 cpub_leakage: cpu-leakage@17 { 1030 reg = <0x17 0x1>; 1031 }; 1032 gpu_leakage: gpu-leakage@18 { 1033 reg = <0x18 0x1>; 1034 }; 1035 center_leakage: center-leakage@19 { 1036 reg = <0x19 0x1>; 1037 }; 1038 cpul_leakage: cpu-leakage@1a { 1039 reg = <0x1a 0x1>; 1040 }; 1041 logic_leakage: logic-leakage@1b { 1042 reg = <0x1b 0x1>; 1043 }; 1044 wafer_info: wafer-info@1c { 1045 reg = <0x1c 0x1>; 1046 }; 1047 }; 1048 1049 pmucru: pmu-clock-controller@ff750000 { 1050 compatible = "rockchip,rk3399-pmucru"; 1051 reg = <0x0 0xff750000 0x0 0x1000>; 1052 #clock-cells = <1>; 1053 #reset-cells = <1>; 1054 assigned-clocks = <&pmucru PLL_PPLL>; 1055 assigned-clock-rates = <676000000>; 1056 }; 1057 1058 cru: clock-controller@ff760000 { 1059 compatible = "rockchip,rk3399-cru"; 1060 reg = <0x0 0xff760000 0x0 0x1000>; 1061 #clock-cells = <1>; 1062 #reset-cells = <1>; 1063 assigned-clocks = 1064 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1065 <&cru PLL_NPLL>, 1066 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1067 <&cru PCLK_PERIHP>, 1068 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1069 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1070 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; 1071 assigned-clock-rates = 1072 <594000000>, <800000000>, 1073 <1000000000>, 1074 <150000000>, <75000000>, 1075 <37500000>, 1076 <100000000>, <100000000>, 1077 <50000000>, <600000000>, 1078 <100000000>, <50000000>; 1079 }; 1080 1081 grf: syscon@ff770000 { 1082 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1083 reg = <0x0 0xff770000 0x0 0x10000>; 1084 #address-cells = <1>; 1085 #size-cells = <1>; 1086 1087 io_domains: io-domains { 1088 compatible = "rockchip,rk3399-io-voltage-domain"; 1089 status = "disabled"; 1090 }; 1091 1092 u2phy0: usb2-phy@e450 { 1093 compatible = "rockchip,rk3399-usb2phy"; 1094 reg = <0xe450 0x10>; 1095 clocks = <&cru SCLK_USB2PHY0_REF>; 1096 clock-names = "phyclk"; 1097 #clock-cells = <0>; 1098 clock-output-names = "clk_usbphy0_480m"; 1099 status = "disabled"; 1100 1101 u2phy0_host: host-port { 1102 #phy-cells = <0>; 1103 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1104 interrupt-names = "linestate"; 1105 status = "disabled"; 1106 }; 1107 }; 1108 1109 u2phy1: usb2-phy@e460 { 1110 compatible = "rockchip,rk3399-usb2phy"; 1111 reg = <0xe460 0x10>; 1112 clocks = <&cru SCLK_USB2PHY1_REF>; 1113 clock-names = "phyclk"; 1114 #clock-cells = <0>; 1115 clock-output-names = "clk_usbphy1_480m"; 1116 status = "disabled"; 1117 1118 u2phy1_host: host-port { 1119 #phy-cells = <0>; 1120 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1121 interrupt-names = "linestate"; 1122 status = "disabled"; 1123 }; 1124 }; 1125 1126 emmc_phy: phy@f780 { 1127 compatible = "rockchip,rk3399-emmc-phy"; 1128 reg = <0xf780 0x24>; 1129 clocks = <&sdhci>; 1130 clock-names = "emmcclk"; 1131 #phy-cells = <0>; 1132 status = "disabled"; 1133 }; 1134 1135 pcie_phy: pcie-phy { 1136 compatible = "rockchip,rk3399-pcie-phy"; 1137 clocks = <&cru SCLK_PCIEPHY_REF>; 1138 clock-names = "refclk"; 1139 #phy-cells = <0>; 1140 resets = <&cru SRST_PCIEPHY>; 1141 reset-names = "phy"; 1142 status = "disabled"; 1143 }; 1144 }; 1145 1146 tcphy0: phy@ff7c0000 { 1147 compatible = "rockchip,rk3399-typec-phy"; 1148 reg = <0x0 0xff7c0000 0x0 0x40000>; 1149 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1150 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1151 clock-names = "tcpdcore", "tcpdphy-ref"; 1152 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1153 assigned-clock-rates = <50000000>; 1154 resets = <&cru SRST_UPHY0>, 1155 <&cru SRST_UPHY0_PIPE_L00>, 1156 <&cru SRST_P_UPHY0_TCPHY>; 1157 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1158 rockchip,grf = <&grf>; 1159 rockchip,typec-conn-dir = <0xe580 0 16>; 1160 rockchip,usb3tousb2-en = <0xe580 3 19>; 1161 rockchip,external-psm = <0xe588 14 30>; 1162 rockchip,pipe-status = <0xe5c0 0 0>; 1163 status = "disabled"; 1164 1165 tcphy0_dp: dp-port { 1166 #phy-cells = <0>; 1167 }; 1168 1169 tcphy0_usb3: usb3-port { 1170 #phy-cells = <0>; 1171 }; 1172 }; 1173 1174 tcphy1: phy@ff800000 { 1175 compatible = "rockchip,rk3399-typec-phy"; 1176 reg = <0x0 0xff800000 0x0 0x40000>; 1177 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1178 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1179 clock-names = "tcpdcore", "tcpdphy-ref"; 1180 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1181 assigned-clock-rates = <50000000>; 1182 resets = <&cru SRST_UPHY1>, 1183 <&cru SRST_UPHY1_PIPE_L00>, 1184 <&cru SRST_P_UPHY1_TCPHY>; 1185 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1186 rockchip,grf = <&grf>; 1187 rockchip,typec-conn-dir = <0xe58c 0 16>; 1188 rockchip,usb3tousb2-en = <0xe58c 3 19>; 1189 rockchip,external-psm = <0xe594 14 30>; 1190 rockchip,pipe-status = <0xe5c0 16 16>; 1191 status = "disabled"; 1192 1193 tcphy1_dp: dp-port { 1194 #phy-cells = <0>; 1195 }; 1196 1197 tcphy1_usb3: usb3-port { 1198 #phy-cells = <0>; 1199 }; 1200 }; 1201 1202 watchdog@ff848000 { 1203 compatible = "snps,dw-wdt"; 1204 reg = <0x0 0xff848000 0x0 0x100>; 1205 clocks = <&cru PCLK_WDT>; 1206 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1207 }; 1208 1209 rktimer: rktimer@ff850000 { 1210 compatible = "rockchip,rk3399-timer"; 1211 reg = <0x0 0xff850000 0x0 0x1000>; 1212 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1213 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1214 clock-names = "pclk", "timer"; 1215 }; 1216 1217 spdif: spdif@ff870000 { 1218 compatible = "rockchip,rk3399-spdif"; 1219 reg = <0x0 0xff870000 0x0 0x1000>; 1220 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1221 dmas = <&dmac_bus 7>; 1222 dma-names = "tx"; 1223 clock-names = "mclk", "hclk"; 1224 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1225 pinctrl-names = "default"; 1226 pinctrl-0 = <&spdif_bus>; 1227 status = "disabled"; 1228 }; 1229 1230 i2s0: i2s@ff880000 { 1231 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1232 reg = <0x0 0xff880000 0x0 0x1000>; 1233 rockchip,grf = <&grf>; 1234 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1235 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1236 dma-names = "tx", "rx"; 1237 clock-names = "i2s_clk", "i2s_hclk"; 1238 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1239 pinctrl-names = "default"; 1240 pinctrl-0 = <&i2s0_8ch_bus>; 1241 status = "disabled"; 1242 }; 1243 1244 i2s1: i2s@ff890000 { 1245 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1246 reg = <0x0 0xff890000 0x0 0x1000>; 1247 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1248 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1249 dma-names = "tx", "rx"; 1250 clock-names = "i2s_clk", "i2s_hclk"; 1251 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1252 pinctrl-names = "default"; 1253 pinctrl-0 = <&i2s1_2ch_bus>; 1254 status = "disabled"; 1255 }; 1256 1257 i2s2: i2s@ff8a0000 { 1258 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1259 reg = <0x0 0xff8a0000 0x0 0x1000>; 1260 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1261 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1262 dma-names = "tx", "rx"; 1263 clock-names = "i2s_clk", "i2s_hclk"; 1264 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1265 status = "disabled"; 1266 }; 1267 1268 pinctrl: pinctrl { 1269 compatible = "rockchip,rk3399-pinctrl"; 1270 rockchip,grf = <&grf>; 1271 rockchip,pmu = <&pmugrf>; 1272 #address-cells = <2>; 1273 #size-cells = <2>; 1274 ranges; 1275 1276 gpio0: gpio0@ff720000 { 1277 compatible = "rockchip,gpio-bank"; 1278 reg = <0x0 0xff720000 0x0 0x100>; 1279 clocks = <&pmucru PCLK_GPIO0_PMU>; 1280 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 1281 1282 gpio-controller; 1283 #gpio-cells = <0x2>; 1284 1285 interrupt-controller; 1286 #interrupt-cells = <0x2>; 1287 }; 1288 1289 gpio1: gpio1@ff730000 { 1290 compatible = "rockchip,gpio-bank"; 1291 reg = <0x0 0xff730000 0x0 0x100>; 1292 clocks = <&pmucru PCLK_GPIO1_PMU>; 1293 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 1294 1295 gpio-controller; 1296 #gpio-cells = <0x2>; 1297 1298 interrupt-controller; 1299 #interrupt-cells = <0x2>; 1300 }; 1301 1302 gpio2: gpio2@ff780000 { 1303 compatible = "rockchip,gpio-bank"; 1304 reg = <0x0 0xff780000 0x0 0x100>; 1305 clocks = <&cru PCLK_GPIO2>; 1306 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 1307 1308 gpio-controller; 1309 #gpio-cells = <0x2>; 1310 1311 interrupt-controller; 1312 #interrupt-cells = <0x2>; 1313 }; 1314 1315 gpio3: gpio3@ff788000 { 1316 compatible = "rockchip,gpio-bank"; 1317 reg = <0x0 0xff788000 0x0 0x100>; 1318 clocks = <&cru PCLK_GPIO3>; 1319 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 1320 1321 gpio-controller; 1322 #gpio-cells = <0x2>; 1323 1324 interrupt-controller; 1325 #interrupt-cells = <0x2>; 1326 }; 1327 1328 gpio4: gpio4@ff790000 { 1329 compatible = "rockchip,gpio-bank"; 1330 reg = <0x0 0xff790000 0x0 0x100>; 1331 clocks = <&cru PCLK_GPIO4>; 1332 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 1333 1334 gpio-controller; 1335 #gpio-cells = <0x2>; 1336 1337 interrupt-controller; 1338 #interrupt-cells = <0x2>; 1339 }; 1340 1341 pcfg_pull_up: pcfg-pull-up { 1342 bias-pull-up; 1343 }; 1344 1345 pcfg_pull_down: pcfg-pull-down { 1346 bias-pull-down; 1347 }; 1348 1349 pcfg_pull_none: pcfg-pull-none { 1350 bias-disable; 1351 }; 1352 1353 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1354 bias-disable; 1355 drive-strength = <12>; 1356 }; 1357 1358 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1359 bias-pull-up; 1360 drive-strength = <8>; 1361 }; 1362 1363 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1364 bias-pull-down; 1365 drive-strength = <4>; 1366 }; 1367 1368 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1369 bias-pull-up; 1370 drive-strength = <2>; 1371 }; 1372 1373 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 1374 bias-pull-down; 1375 drive-strength = <12>; 1376 }; 1377 1378 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 1379 bias-disable; 1380 drive-strength = <13>; 1381 }; 1382 1383 clock { 1384 clk_32k: clk-32k { 1385 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; 1386 }; 1387 }; 1388 1389 gmac { 1390 rgmii_pins: rgmii-pins { 1391 rockchip,pins = 1392 /* mac_txclk */ 1393 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>, 1394 /* mac_rxclk */ 1395 <3 14 RK_FUNC_1 &pcfg_pull_none>, 1396 /* mac_mdio */ 1397 <3 13 RK_FUNC_1 &pcfg_pull_none>, 1398 /* mac_txen */ 1399 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>, 1400 /* mac_clk */ 1401 <3 11 RK_FUNC_1 &pcfg_pull_none>, 1402 /* mac_rxdv */ 1403 <3 9 RK_FUNC_1 &pcfg_pull_none>, 1404 /* mac_mdc */ 1405 <3 8 RK_FUNC_1 &pcfg_pull_none>, 1406 /* mac_rxd1 */ 1407 <3 7 RK_FUNC_1 &pcfg_pull_none>, 1408 /* mac_rxd0 */ 1409 <3 6 RK_FUNC_1 &pcfg_pull_none>, 1410 /* mac_txd1 */ 1411 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>, 1412 /* mac_txd0 */ 1413 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>, 1414 /* mac_rxd3 */ 1415 <3 3 RK_FUNC_1 &pcfg_pull_none>, 1416 /* mac_rxd2 */ 1417 <3 2 RK_FUNC_1 &pcfg_pull_none>, 1418 /* mac_txd3 */ 1419 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>, 1420 /* mac_txd2 */ 1421 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>; 1422 }; 1423 1424 rmii_pins: rmii-pins { 1425 rockchip,pins = 1426 /* mac_mdio */ 1427 <3 13 RK_FUNC_1 &pcfg_pull_none>, 1428 /* mac_txen */ 1429 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>, 1430 /* mac_clk */ 1431 <3 11 RK_FUNC_1 &pcfg_pull_none>, 1432 /* mac_rxer */ 1433 <3 10 RK_FUNC_1 &pcfg_pull_none>, 1434 /* mac_rxdv */ 1435 <3 9 RK_FUNC_1 &pcfg_pull_none>, 1436 /* mac_mdc */ 1437 <3 8 RK_FUNC_1 &pcfg_pull_none>, 1438 /* mac_rxd1 */ 1439 <3 7 RK_FUNC_1 &pcfg_pull_none>, 1440 /* mac_rxd0 */ 1441 <3 6 RK_FUNC_1 &pcfg_pull_none>, 1442 /* mac_txd1 */ 1443 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>, 1444 /* mac_txd0 */ 1445 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>; 1446 }; 1447 }; 1448 1449 i2c0 { 1450 i2c0_xfer: i2c0-xfer { 1451 rockchip,pins = 1452 <1 15 RK_FUNC_2 &pcfg_pull_none>, 1453 <1 16 RK_FUNC_2 &pcfg_pull_none>; 1454 }; 1455 }; 1456 1457 i2c1 { 1458 i2c1_xfer: i2c1-xfer { 1459 rockchip,pins = 1460 <4 2 RK_FUNC_1 &pcfg_pull_none>, 1461 <4 1 RK_FUNC_1 &pcfg_pull_none>; 1462 }; 1463 }; 1464 1465 i2c2 { 1466 i2c2_xfer: i2c2-xfer { 1467 rockchip,pins = 1468 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>, 1469 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>; 1470 }; 1471 }; 1472 1473 i2c3 { 1474 i2c3_xfer: i2c3-xfer { 1475 rockchip,pins = 1476 <4 17 RK_FUNC_1 &pcfg_pull_none>, 1477 <4 16 RK_FUNC_1 &pcfg_pull_none>; 1478 }; 1479 }; 1480 1481 i2c4 { 1482 i2c4_xfer: i2c4-xfer { 1483 rockchip,pins = 1484 <1 12 RK_FUNC_1 &pcfg_pull_none>, 1485 <1 11 RK_FUNC_1 &pcfg_pull_none>; 1486 }; 1487 }; 1488 1489 i2c5 { 1490 i2c5_xfer: i2c5-xfer { 1491 rockchip,pins = 1492 <3 11 RK_FUNC_2 &pcfg_pull_none>, 1493 <3 10 RK_FUNC_2 &pcfg_pull_none>; 1494 }; 1495 }; 1496 1497 i2c6 { 1498 i2c6_xfer: i2c6-xfer { 1499 rockchip,pins = 1500 <2 10 RK_FUNC_2 &pcfg_pull_none>, 1501 <2 9 RK_FUNC_2 &pcfg_pull_none>; 1502 }; 1503 }; 1504 1505 i2c7 { 1506 i2c7_xfer: i2c7-xfer { 1507 rockchip,pins = 1508 <2 8 RK_FUNC_2 &pcfg_pull_none>, 1509 <2 7 RK_FUNC_2 &pcfg_pull_none>; 1510 }; 1511 }; 1512 1513 i2c8 { 1514 i2c8_xfer: i2c8-xfer { 1515 rockchip,pins = 1516 <1 21 RK_FUNC_1 &pcfg_pull_none>, 1517 <1 20 RK_FUNC_1 &pcfg_pull_none>; 1518 }; 1519 }; 1520 1521 i2s0 { 1522 i2s0_8ch_bus: i2s0-8ch-bus { 1523 rockchip,pins = 1524 <3 24 RK_FUNC_1 &pcfg_pull_none>, 1525 <3 25 RK_FUNC_1 &pcfg_pull_none>, 1526 <3 26 RK_FUNC_1 &pcfg_pull_none>, 1527 <3 27 RK_FUNC_1 &pcfg_pull_none>, 1528 <3 28 RK_FUNC_1 &pcfg_pull_none>, 1529 <3 29 RK_FUNC_1 &pcfg_pull_none>, 1530 <3 30 RK_FUNC_1 &pcfg_pull_none>, 1531 <3 31 RK_FUNC_1 &pcfg_pull_none>, 1532 <4 0 RK_FUNC_1 &pcfg_pull_none>; 1533 }; 1534 }; 1535 1536 i2s1 { 1537 i2s1_2ch_bus: i2s1-2ch-bus { 1538 rockchip,pins = 1539 <4 3 RK_FUNC_1 &pcfg_pull_none>, 1540 <4 4 RK_FUNC_1 &pcfg_pull_none>, 1541 <4 5 RK_FUNC_1 &pcfg_pull_none>, 1542 <4 6 RK_FUNC_1 &pcfg_pull_none>, 1543 <4 7 RK_FUNC_1 &pcfg_pull_none>; 1544 }; 1545 }; 1546 1547 sleep { 1548 ap_pwroff: ap-pwroff { 1549 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>; 1550 }; 1551 1552 ddrio_pwroff: ddrio-pwroff { 1553 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; 1554 }; 1555 }; 1556 1557 spdif { 1558 spdif_bus: spdif-bus { 1559 rockchip,pins = 1560 <4 21 RK_FUNC_1 &pcfg_pull_none>; 1561 }; 1562 }; 1563 1564 spi0 { 1565 spi0_clk: spi0-clk { 1566 rockchip,pins = 1567 <3 6 RK_FUNC_2 &pcfg_pull_up>; 1568 }; 1569 spi0_cs0: spi0-cs0 { 1570 rockchip,pins = 1571 <3 7 RK_FUNC_2 &pcfg_pull_up>; 1572 }; 1573 spi0_cs1: spi0-cs1 { 1574 rockchip,pins = 1575 <3 8 RK_FUNC_2 &pcfg_pull_up>; 1576 }; 1577 spi0_tx: spi0-tx { 1578 rockchip,pins = 1579 <3 5 RK_FUNC_2 &pcfg_pull_up>; 1580 }; 1581 spi0_rx: spi0-rx { 1582 rockchip,pins = 1583 <3 4 RK_FUNC_2 &pcfg_pull_up>; 1584 }; 1585 }; 1586 1587 spi1 { 1588 spi1_clk: spi1-clk { 1589 rockchip,pins = 1590 <1 9 RK_FUNC_2 &pcfg_pull_up>; 1591 }; 1592 spi1_cs0: spi1-cs0 { 1593 rockchip,pins = 1594 <1 10 RK_FUNC_2 &pcfg_pull_up>; 1595 }; 1596 spi1_rx: spi1-rx { 1597 rockchip,pins = 1598 <1 7 RK_FUNC_2 &pcfg_pull_up>; 1599 }; 1600 spi1_tx: spi1-tx { 1601 rockchip,pins = 1602 <1 8 RK_FUNC_2 &pcfg_pull_up>; 1603 }; 1604 }; 1605 1606 spi2 { 1607 spi2_clk: spi2-clk { 1608 rockchip,pins = 1609 <2 11 RK_FUNC_1 &pcfg_pull_up>; 1610 }; 1611 spi2_cs0: spi2-cs0 { 1612 rockchip,pins = 1613 <2 12 RK_FUNC_1 &pcfg_pull_up>; 1614 }; 1615 spi2_rx: spi2-rx { 1616 rockchip,pins = 1617 <2 9 RK_FUNC_1 &pcfg_pull_up>; 1618 }; 1619 spi2_tx: spi2-tx { 1620 rockchip,pins = 1621 <2 10 RK_FUNC_1 &pcfg_pull_up>; 1622 }; 1623 }; 1624 1625 spi3 { 1626 spi3_clk: spi3-clk { 1627 rockchip,pins = 1628 <1 17 RK_FUNC_1 &pcfg_pull_up>; 1629 }; 1630 spi3_cs0: spi3-cs0 { 1631 rockchip,pins = 1632 <1 18 RK_FUNC_1 &pcfg_pull_up>; 1633 }; 1634 spi3_rx: spi3-rx { 1635 rockchip,pins = 1636 <1 15 RK_FUNC_1 &pcfg_pull_up>; 1637 }; 1638 spi3_tx: spi3-tx { 1639 rockchip,pins = 1640 <1 16 RK_FUNC_1 &pcfg_pull_up>; 1641 }; 1642 }; 1643 1644 spi4 { 1645 spi4_clk: spi4-clk { 1646 rockchip,pins = 1647 <3 2 RK_FUNC_2 &pcfg_pull_up>; 1648 }; 1649 spi4_cs0: spi4-cs0 { 1650 rockchip,pins = 1651 <3 3 RK_FUNC_2 &pcfg_pull_up>; 1652 }; 1653 spi4_rx: spi4-rx { 1654 rockchip,pins = 1655 <3 0 RK_FUNC_2 &pcfg_pull_up>; 1656 }; 1657 spi4_tx: spi4-tx { 1658 rockchip,pins = 1659 <3 1 RK_FUNC_2 &pcfg_pull_up>; 1660 }; 1661 }; 1662 1663 spi5 { 1664 spi5_clk: spi5-clk { 1665 rockchip,pins = 1666 <2 22 RK_FUNC_2 &pcfg_pull_up>; 1667 }; 1668 spi5_cs0: spi5-cs0 { 1669 rockchip,pins = 1670 <2 23 RK_FUNC_2 &pcfg_pull_up>; 1671 }; 1672 spi5_rx: spi5-rx { 1673 rockchip,pins = 1674 <2 20 RK_FUNC_2 &pcfg_pull_up>; 1675 }; 1676 spi5_tx: spi5-tx { 1677 rockchip,pins = 1678 <2 21 RK_FUNC_2 &pcfg_pull_up>; 1679 }; 1680 }; 1681 1682 tsadc { 1683 otp_gpio: otp-gpio { 1684 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>; 1685 }; 1686 1687 otp_out: otp-out { 1688 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>; 1689 }; 1690 }; 1691 1692 uart0 { 1693 uart0_xfer: uart0-xfer { 1694 rockchip,pins = 1695 <2 16 RK_FUNC_1 &pcfg_pull_up>, 1696 <2 17 RK_FUNC_1 &pcfg_pull_none>; 1697 }; 1698 1699 uart0_cts: uart0-cts { 1700 rockchip,pins = 1701 <2 18 RK_FUNC_1 &pcfg_pull_none>; 1702 }; 1703 1704 uart0_rts: uart0-rts { 1705 rockchip,pins = 1706 <2 19 RK_FUNC_1 &pcfg_pull_none>; 1707 }; 1708 }; 1709 1710 uart1 { 1711 uart1_xfer: uart1-xfer { 1712 rockchip,pins = 1713 <3 12 RK_FUNC_2 &pcfg_pull_up>, 1714 <3 13 RK_FUNC_2 &pcfg_pull_none>; 1715 }; 1716 }; 1717 1718 uart2a { 1719 uart2a_xfer: uart2a-xfer { 1720 rockchip,pins = 1721 <4 8 RK_FUNC_2 &pcfg_pull_up>, 1722 <4 9 RK_FUNC_2 &pcfg_pull_none>; 1723 }; 1724 }; 1725 1726 uart2b { 1727 uart2b_xfer: uart2b-xfer { 1728 rockchip,pins = 1729 <4 16 RK_FUNC_2 &pcfg_pull_up>, 1730 <4 17 RK_FUNC_2 &pcfg_pull_none>; 1731 }; 1732 }; 1733 1734 uart2c { 1735 uart2c_xfer: uart2c-xfer { 1736 rockchip,pins = 1737 <4 19 RK_FUNC_1 &pcfg_pull_up>, 1738 <4 20 RK_FUNC_1 &pcfg_pull_none>; 1739 }; 1740 }; 1741 1742 uart3 { 1743 uart3_xfer: uart3-xfer { 1744 rockchip,pins = 1745 <3 14 RK_FUNC_2 &pcfg_pull_up>, 1746 <3 15 RK_FUNC_2 &pcfg_pull_none>; 1747 }; 1748 1749 uart3_cts: uart3-cts { 1750 rockchip,pins = 1751 <3 18 RK_FUNC_2 &pcfg_pull_none>; 1752 }; 1753 1754 uart3_rts: uart3-rts { 1755 rockchip,pins = 1756 <3 19 RK_FUNC_2 &pcfg_pull_none>; 1757 }; 1758 }; 1759 1760 uart4 { 1761 uart4_xfer: uart4-xfer { 1762 rockchip,pins = 1763 <1 7 RK_FUNC_1 &pcfg_pull_up>, 1764 <1 8 RK_FUNC_1 &pcfg_pull_none>; 1765 }; 1766 }; 1767 1768 uarthdcp { 1769 uarthdcp_xfer: uarthdcp-xfer { 1770 rockchip,pins = 1771 <4 21 RK_FUNC_2 &pcfg_pull_up>, 1772 <4 22 RK_FUNC_2 &pcfg_pull_none>; 1773 }; 1774 }; 1775 1776 pwm0 { 1777 pwm0_pin: pwm0-pin { 1778 rockchip,pins = 1779 <4 18 RK_FUNC_1 &pcfg_pull_none>; 1780 }; 1781 1782 vop0_pwm_pin: vop0-pwm-pin { 1783 rockchip,pins = 1784 <4 18 RK_FUNC_2 &pcfg_pull_none>; 1785 }; 1786 }; 1787 1788 pwm1 { 1789 pwm1_pin: pwm1-pin { 1790 rockchip,pins = 1791 <4 22 RK_FUNC_1 &pcfg_pull_none>; 1792 }; 1793 1794 vop1_pwm_pin: vop1-pwm-pin { 1795 rockchip,pins = 1796 <4 18 RK_FUNC_3 &pcfg_pull_none>; 1797 }; 1798 }; 1799 1800 pwm2 { 1801 pwm2_pin: pwm2-pin { 1802 rockchip,pins = 1803 <1 19 RK_FUNC_1 &pcfg_pull_none>; 1804 }; 1805 }; 1806 1807 pwm3a { 1808 pwm3a_pin: pwm3a-pin { 1809 rockchip,pins = 1810 <0 6 RK_FUNC_1 &pcfg_pull_none>; 1811 }; 1812 }; 1813 1814 pwm3b { 1815 pwm3b_pin: pwm3b-pin { 1816 rockchip,pins = 1817 <1 14 RK_FUNC_1 &pcfg_pull_none>; 1818 }; 1819 }; 1820 1821 pcie { 1822 pcie_clkreqn: pci-clkreqn { 1823 rockchip,pins = 1824 <2 26 RK_FUNC_2 &pcfg_pull_none>; 1825 }; 1826 1827 pcie_clkreqnb: pci-clkreqnb { 1828 rockchip,pins = 1829 <4 24 RK_FUNC_1 &pcfg_pull_none>; 1830 }; 1831 }; 1832 1833 }; 1834}; 1835