1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3399-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3399-power.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "rockchip,rk3399"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &gmac; 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 i2c6 = &i2c6; 30 i2c7 = &i2c7; 31 i2c8 = &i2c8; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 cpu-map { 44 cluster0 { 45 core0 { 46 cpu = <&cpu_l0>; 47 }; 48 core1 { 49 cpu = <&cpu_l1>; 50 }; 51 core2 { 52 cpu = <&cpu_l2>; 53 }; 54 core3 { 55 cpu = <&cpu_l3>; 56 }; 57 }; 58 59 cluster1 { 60 core0 { 61 cpu = <&cpu_b0>; 62 }; 63 core1 { 64 cpu = <&cpu_b1>; 65 }; 66 }; 67 }; 68 69 cpu_l0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <0x0 0x0>; 73 enable-method = "psci"; 74 capacity-dmips-mhz = <485>; 75 clocks = <&cru ARMCLKL>; 76 #cooling-cells = <2>; /* min followed by max */ 77 dynamic-power-coefficient = <100>; 78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 79 }; 80 81 cpu_l1: cpu@1 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x0 0x1>; 85 enable-method = "psci"; 86 capacity-dmips-mhz = <485>; 87 clocks = <&cru ARMCLKL>; 88 #cooling-cells = <2>; /* min followed by max */ 89 dynamic-power-coefficient = <100>; 90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 91 }; 92 93 cpu_l2: cpu@2 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a53"; 96 reg = <0x0 0x2>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <485>; 99 clocks = <&cru ARMCLKL>; 100 #cooling-cells = <2>; /* min followed by max */ 101 dynamic-power-coefficient = <100>; 102 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 103 }; 104 105 cpu_l3: cpu@3 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53"; 108 reg = <0x0 0x3>; 109 enable-method = "psci"; 110 capacity-dmips-mhz = <485>; 111 clocks = <&cru ARMCLKL>; 112 #cooling-cells = <2>; /* min followed by max */ 113 dynamic-power-coefficient = <100>; 114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 115 }; 116 117 cpu_b0: cpu@100 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a72"; 120 reg = <0x0 0x100>; 121 enable-method = "psci"; 122 capacity-dmips-mhz = <1024>; 123 clocks = <&cru ARMCLKB>; 124 #cooling-cells = <2>; /* min followed by max */ 125 dynamic-power-coefficient = <436>; 126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 127 }; 128 129 cpu_b1: cpu@101 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a72"; 132 reg = <0x0 0x101>; 133 enable-method = "psci"; 134 capacity-dmips-mhz = <1024>; 135 clocks = <&cru ARMCLKB>; 136 #cooling-cells = <2>; /* min followed by max */ 137 dynamic-power-coefficient = <436>; 138 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 139 }; 140 141 idle-states { 142 entry-method = "psci"; 143 144 CPU_SLEEP: cpu-sleep { 145 compatible = "arm,idle-state"; 146 local-timer-stop; 147 arm,psci-suspend-param = <0x0010000>; 148 entry-latency-us = <120>; 149 exit-latency-us = <250>; 150 min-residency-us = <900>; 151 }; 152 153 CLUSTER_SLEEP: cluster-sleep { 154 compatible = "arm,idle-state"; 155 local-timer-stop; 156 arm,psci-suspend-param = <0x1010000>; 157 entry-latency-us = <400>; 158 exit-latency-us = <500>; 159 min-residency-us = <2000>; 160 }; 161 }; 162 }; 163 164 display-subsystem { 165 compatible = "rockchip,display-subsystem"; 166 ports = <&vopl_out>, <&vopb_out>; 167 }; 168 169 pmu_a53 { 170 compatible = "arm,cortex-a53-pmu"; 171 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 172 }; 173 174 pmu_a72 { 175 compatible = "arm,cortex-a72-pmu"; 176 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 177 }; 178 179 psci { 180 compatible = "arm,psci-1.0"; 181 method = "smc"; 182 }; 183 184 timer { 185 compatible = "arm,armv8-timer"; 186 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 187 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 188 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 189 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 190 arm,no-tick-in-suspend; 191 }; 192 193 xin24m: xin24m { 194 compatible = "fixed-clock"; 195 clock-frequency = <24000000>; 196 clock-output-names = "xin24m"; 197 #clock-cells = <0>; 198 }; 199 200 amba: bus { 201 compatible = "simple-bus"; 202 #address-cells = <2>; 203 #size-cells = <2>; 204 ranges; 205 206 dmac_bus: dma-controller@ff6d0000 { 207 compatible = "arm,pl330", "arm,primecell"; 208 reg = <0x0 0xff6d0000 0x0 0x4000>; 209 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 210 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 211 #dma-cells = <1>; 212 clocks = <&cru ACLK_DMAC0_PERILP>; 213 clock-names = "apb_pclk"; 214 }; 215 216 dmac_peri: dma-controller@ff6e0000 { 217 compatible = "arm,pl330", "arm,primecell"; 218 reg = <0x0 0xff6e0000 0x0 0x4000>; 219 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 220 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 221 #dma-cells = <1>; 222 clocks = <&cru ACLK_DMAC1_PERILP>; 223 clock-names = "apb_pclk"; 224 }; 225 }; 226 227 pcie0: pcie@f8000000 { 228 compatible = "rockchip,rk3399-pcie"; 229 reg = <0x0 0xf8000000 0x0 0x2000000>, 230 <0x0 0xfd000000 0x0 0x1000000>; 231 reg-names = "axi-base", "apb-base"; 232 #address-cells = <3>; 233 #size-cells = <2>; 234 #interrupt-cells = <1>; 235 aspm-no-l0s; 236 bus-range = <0x0 0x1f>; 237 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 238 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 239 clock-names = "aclk", "aclk-perf", 240 "hclk", "pm"; 241 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 242 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 243 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 244 interrupt-names = "sys", "legacy", "client"; 245 interrupt-map-mask = <0 0 0 7>; 246 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 247 <0 0 0 2 &pcie0_intc 1>, 248 <0 0 0 3 &pcie0_intc 2>, 249 <0 0 0 4 &pcie0_intc 3>; 250 linux,pci-domain = <0>; 251 max-link-speed = <1>; 252 msi-map = <0x0 &its 0x0 0x1000>; 253 phys = <&pcie_phy 0>, <&pcie_phy 1>, 254 <&pcie_phy 2>, <&pcie_phy 3>; 255 phy-names = "pcie-phy-0", "pcie-phy-1", 256 "pcie-phy-2", "pcie-phy-3"; 257 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000 258 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; 259 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 260 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 261 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 262 <&cru SRST_A_PCIE>; 263 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 264 "pm", "pclk", "aclk"; 265 status = "disabled"; 266 267 pcie0_intc: interrupt-controller { 268 interrupt-controller; 269 #address-cells = <0>; 270 #interrupt-cells = <1>; 271 }; 272 }; 273 274 gmac: ethernet@fe300000 { 275 compatible = "rockchip,rk3399-gmac"; 276 reg = <0x0 0xfe300000 0x0 0x10000>; 277 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 278 interrupt-names = "macirq"; 279 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 280 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 281 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 282 <&cru PCLK_GMAC>; 283 clock-names = "stmmaceth", "mac_clk_rx", 284 "mac_clk_tx", "clk_mac_ref", 285 "clk_mac_refout", "aclk_mac", 286 "pclk_mac"; 287 power-domains = <&power RK3399_PD_GMAC>; 288 resets = <&cru SRST_A_GMAC>; 289 reset-names = "stmmaceth"; 290 rockchip,grf = <&grf>; 291 snps,txpbl = <0x4>; 292 status = "disabled"; 293 }; 294 295 sdio0: mmc@fe310000 { 296 compatible = "rockchip,rk3399-dw-mshc", 297 "rockchip,rk3288-dw-mshc"; 298 reg = <0x0 0xfe310000 0x0 0x4000>; 299 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 300 max-frequency = <150000000>; 301 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 302 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 303 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 304 fifo-depth = <0x100>; 305 power-domains = <&power RK3399_PD_SDIOAUDIO>; 306 resets = <&cru SRST_SDIO0>; 307 reset-names = "reset"; 308 status = "disabled"; 309 }; 310 311 sdmmc: mmc@fe320000 { 312 compatible = "rockchip,rk3399-dw-mshc", 313 "rockchip,rk3288-dw-mshc"; 314 reg = <0x0 0xfe320000 0x0 0x4000>; 315 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 316 max-frequency = <150000000>; 317 assigned-clocks = <&cru HCLK_SD>; 318 assigned-clock-rates = <200000000>; 319 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 320 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 321 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 322 fifo-depth = <0x100>; 323 power-domains = <&power RK3399_PD_SD>; 324 resets = <&cru SRST_SDMMC>; 325 reset-names = "reset"; 326 status = "disabled"; 327 }; 328 329 sdhci: sdhci@fe330000 { 330 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 331 reg = <0x0 0xfe330000 0x0 0x10000>; 332 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 333 arasan,soc-ctl-syscon = <&grf>; 334 assigned-clocks = <&cru SCLK_EMMC>; 335 assigned-clock-rates = <200000000>; 336 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 337 clock-names = "clk_xin", "clk_ahb"; 338 clock-output-names = "emmc_cardclock"; 339 #clock-cells = <0>; 340 phys = <&emmc_phy>; 341 phy-names = "phy_arasan"; 342 power-domains = <&power RK3399_PD_EMMC>; 343 disable-cqe-dcmd; 344 status = "disabled"; 345 }; 346 347 usb_host0_ehci: usb@fe380000 { 348 compatible = "generic-ehci"; 349 reg = <0x0 0xfe380000 0x0 0x20000>; 350 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 351 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 352 <&u2phy0>; 353 phys = <&u2phy0_host>; 354 phy-names = "usb"; 355 status = "disabled"; 356 }; 357 358 usb_host0_ohci: usb@fe3a0000 { 359 compatible = "generic-ohci"; 360 reg = <0x0 0xfe3a0000 0x0 0x20000>; 361 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 362 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 363 <&u2phy0>; 364 phys = <&u2phy0_host>; 365 phy-names = "usb"; 366 status = "disabled"; 367 }; 368 369 usb_host1_ehci: usb@fe3c0000 { 370 compatible = "generic-ehci"; 371 reg = <0x0 0xfe3c0000 0x0 0x20000>; 372 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 373 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 374 <&u2phy1>; 375 phys = <&u2phy1_host>; 376 phy-names = "usb"; 377 status = "disabled"; 378 }; 379 380 usb_host1_ohci: usb@fe3e0000 { 381 compatible = "generic-ohci"; 382 reg = <0x0 0xfe3e0000 0x0 0x20000>; 383 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 384 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 385 <&u2phy1>; 386 phys = <&u2phy1_host>; 387 phy-names = "usb"; 388 status = "disabled"; 389 }; 390 391 usbdrd3_0: usb@fe800000 { 392 compatible = "rockchip,rk3399-dwc3"; 393 #address-cells = <2>; 394 #size-cells = <2>; 395 ranges; 396 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 397 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 398 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 399 clock-names = "ref_clk", "suspend_clk", 400 "bus_clk", "aclk_usb3_rksoc_axi_perf", 401 "aclk_usb3", "grf_clk"; 402 resets = <&cru SRST_A_USB3_OTG0>; 403 reset-names = "usb3-otg"; 404 status = "disabled"; 405 406 usbdrd_dwc3_0: usb@fe800000 { 407 compatible = "snps,dwc3"; 408 reg = <0x0 0xfe800000 0x0 0x100000>; 409 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 410 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, 411 <&cru SCLK_USB3OTG0_SUSPEND>; 412 clock-names = "ref", "bus_early", "suspend"; 413 dr_mode = "otg"; 414 phys = <&u2phy0_otg>, <&tcphy0_usb3>; 415 phy-names = "usb2-phy", "usb3-phy"; 416 phy_type = "utmi_wide"; 417 snps,dis_enblslpm_quirk; 418 snps,dis-u2-freeclk-exists-quirk; 419 snps,dis_u2_susphy_quirk; 420 snps,dis-del-phy-power-chg-quirk; 421 snps,dis-tx-ipgap-linecheck-quirk; 422 power-domains = <&power RK3399_PD_USB3>; 423 status = "disabled"; 424 }; 425 }; 426 427 usbdrd3_1: usb@fe900000 { 428 compatible = "rockchip,rk3399-dwc3"; 429 #address-cells = <2>; 430 #size-cells = <2>; 431 ranges; 432 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, 433 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 434 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 435 clock-names = "ref_clk", "suspend_clk", 436 "bus_clk", "aclk_usb3_rksoc_axi_perf", 437 "aclk_usb3", "grf_clk"; 438 resets = <&cru SRST_A_USB3_OTG1>; 439 reset-names = "usb3-otg"; 440 status = "disabled"; 441 442 usbdrd_dwc3_1: usb@fe900000 { 443 compatible = "snps,dwc3"; 444 reg = <0x0 0xfe900000 0x0 0x100000>; 445 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 446 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>, 447 <&cru SCLK_USB3OTG1_SUSPEND>; 448 clock-names = "ref", "bus_early", "suspend"; 449 dr_mode = "otg"; 450 phys = <&u2phy1_otg>, <&tcphy1_usb3>; 451 phy-names = "usb2-phy", "usb3-phy"; 452 phy_type = "utmi_wide"; 453 snps,dis_enblslpm_quirk; 454 snps,dis-u2-freeclk-exists-quirk; 455 snps,dis_u2_susphy_quirk; 456 snps,dis-del-phy-power-chg-quirk; 457 snps,dis-tx-ipgap-linecheck-quirk; 458 power-domains = <&power RK3399_PD_USB3>; 459 status = "disabled"; 460 }; 461 }; 462 463 cdn_dp: dp@fec00000 { 464 compatible = "rockchip,rk3399-cdn-dp"; 465 reg = <0x0 0xfec00000 0x0 0x100000>; 466 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 467 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>; 468 assigned-clock-rates = <100000000>, <200000000>; 469 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, 470 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; 471 clock-names = "core-clk", "pclk", "spdif", "grf"; 472 phys = <&tcphy0_dp>, <&tcphy1_dp>; 473 power-domains = <&power RK3399_PD_HDCP>; 474 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, 475 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; 476 reset-names = "spdif", "dptx", "apb", "core"; 477 rockchip,grf = <&grf>; 478 #sound-dai-cells = <1>; 479 status = "disabled"; 480 481 ports { 482 dp_in: port { 483 #address-cells = <1>; 484 #size-cells = <0>; 485 486 dp_in_vopb: endpoint@0 { 487 reg = <0>; 488 remote-endpoint = <&vopb_out_dp>; 489 }; 490 491 dp_in_vopl: endpoint@1 { 492 reg = <1>; 493 remote-endpoint = <&vopl_out_dp>; 494 }; 495 }; 496 }; 497 }; 498 499 gic: interrupt-controller@fee00000 { 500 compatible = "arm,gic-v3"; 501 #interrupt-cells = <4>; 502 #address-cells = <2>; 503 #size-cells = <2>; 504 ranges; 505 interrupt-controller; 506 507 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 508 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 509 <0x0 0xfff00000 0 0x10000>, /* GICC */ 510 <0x0 0xfff10000 0 0x10000>, /* GICH */ 511 <0x0 0xfff20000 0 0x10000>; /* GICV */ 512 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 513 its: interrupt-controller@fee20000 { 514 compatible = "arm,gic-v3-its"; 515 msi-controller; 516 #msi-cells = <1>; 517 reg = <0x0 0xfee20000 0x0 0x20000>; 518 }; 519 520 ppi-partitions { 521 ppi_cluster0: interrupt-partition-0 { 522 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 523 }; 524 525 ppi_cluster1: interrupt-partition-1 { 526 affinity = <&cpu_b0 &cpu_b1>; 527 }; 528 }; 529 }; 530 531 saradc: saradc@ff100000 { 532 compatible = "rockchip,rk3399-saradc"; 533 reg = <0x0 0xff100000 0x0 0x100>; 534 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 535 #io-channel-cells = <1>; 536 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 537 clock-names = "saradc", "apb_pclk"; 538 resets = <&cru SRST_P_SARADC>; 539 reset-names = "saradc-apb"; 540 status = "disabled"; 541 }; 542 543 i2c1: i2c@ff110000 { 544 compatible = "rockchip,rk3399-i2c"; 545 reg = <0x0 0xff110000 0x0 0x1000>; 546 assigned-clocks = <&cru SCLK_I2C1>; 547 assigned-clock-rates = <200000000>; 548 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 549 clock-names = "i2c", "pclk"; 550 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 551 pinctrl-names = "default"; 552 pinctrl-0 = <&i2c1_xfer>; 553 #address-cells = <1>; 554 #size-cells = <0>; 555 status = "disabled"; 556 }; 557 558 i2c2: i2c@ff120000 { 559 compatible = "rockchip,rk3399-i2c"; 560 reg = <0x0 0xff120000 0x0 0x1000>; 561 assigned-clocks = <&cru SCLK_I2C2>; 562 assigned-clock-rates = <200000000>; 563 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 564 clock-names = "i2c", "pclk"; 565 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 566 pinctrl-names = "default"; 567 pinctrl-0 = <&i2c2_xfer>; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 status = "disabled"; 571 }; 572 573 i2c3: i2c@ff130000 { 574 compatible = "rockchip,rk3399-i2c"; 575 reg = <0x0 0xff130000 0x0 0x1000>; 576 assigned-clocks = <&cru SCLK_I2C3>; 577 assigned-clock-rates = <200000000>; 578 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 579 clock-names = "i2c", "pclk"; 580 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 581 pinctrl-names = "default"; 582 pinctrl-0 = <&i2c3_xfer>; 583 #address-cells = <1>; 584 #size-cells = <0>; 585 status = "disabled"; 586 }; 587 588 i2c5: i2c@ff140000 { 589 compatible = "rockchip,rk3399-i2c"; 590 reg = <0x0 0xff140000 0x0 0x1000>; 591 assigned-clocks = <&cru SCLK_I2C5>; 592 assigned-clock-rates = <200000000>; 593 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 594 clock-names = "i2c", "pclk"; 595 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 596 pinctrl-names = "default"; 597 pinctrl-0 = <&i2c5_xfer>; 598 #address-cells = <1>; 599 #size-cells = <0>; 600 status = "disabled"; 601 }; 602 603 i2c6: i2c@ff150000 { 604 compatible = "rockchip,rk3399-i2c"; 605 reg = <0x0 0xff150000 0x0 0x1000>; 606 assigned-clocks = <&cru SCLK_I2C6>; 607 assigned-clock-rates = <200000000>; 608 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 609 clock-names = "i2c", "pclk"; 610 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 611 pinctrl-names = "default"; 612 pinctrl-0 = <&i2c6_xfer>; 613 #address-cells = <1>; 614 #size-cells = <0>; 615 status = "disabled"; 616 }; 617 618 i2c7: i2c@ff160000 { 619 compatible = "rockchip,rk3399-i2c"; 620 reg = <0x0 0xff160000 0x0 0x1000>; 621 assigned-clocks = <&cru SCLK_I2C7>; 622 assigned-clock-rates = <200000000>; 623 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 624 clock-names = "i2c", "pclk"; 625 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 626 pinctrl-names = "default"; 627 pinctrl-0 = <&i2c7_xfer>; 628 #address-cells = <1>; 629 #size-cells = <0>; 630 status = "disabled"; 631 }; 632 633 uart0: serial@ff180000 { 634 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 635 reg = <0x0 0xff180000 0x0 0x100>; 636 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 637 clock-names = "baudclk", "apb_pclk"; 638 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 639 reg-shift = <2>; 640 reg-io-width = <4>; 641 pinctrl-names = "default"; 642 pinctrl-0 = <&uart0_xfer>; 643 status = "disabled"; 644 }; 645 646 uart1: serial@ff190000 { 647 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 648 reg = <0x0 0xff190000 0x0 0x100>; 649 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 650 clock-names = "baudclk", "apb_pclk"; 651 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 652 reg-shift = <2>; 653 reg-io-width = <4>; 654 pinctrl-names = "default"; 655 pinctrl-0 = <&uart1_xfer>; 656 status = "disabled"; 657 }; 658 659 uart2: serial@ff1a0000 { 660 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 661 reg = <0x0 0xff1a0000 0x0 0x100>; 662 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 663 clock-names = "baudclk", "apb_pclk"; 664 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 665 reg-shift = <2>; 666 reg-io-width = <4>; 667 pinctrl-names = "default"; 668 pinctrl-0 = <&uart2c_xfer>; 669 status = "disabled"; 670 }; 671 672 uart3: serial@ff1b0000 { 673 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 674 reg = <0x0 0xff1b0000 0x0 0x100>; 675 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 676 clock-names = "baudclk", "apb_pclk"; 677 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 678 reg-shift = <2>; 679 reg-io-width = <4>; 680 pinctrl-names = "default"; 681 pinctrl-0 = <&uart3_xfer>; 682 status = "disabled"; 683 }; 684 685 spi0: spi@ff1c0000 { 686 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 687 reg = <0x0 0xff1c0000 0x0 0x1000>; 688 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 689 clock-names = "spiclk", "apb_pclk"; 690 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 691 dmas = <&dmac_peri 10>, <&dmac_peri 11>; 692 dma-names = "tx", "rx"; 693 pinctrl-names = "default"; 694 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 695 #address-cells = <1>; 696 #size-cells = <0>; 697 status = "disabled"; 698 }; 699 700 spi1: spi@ff1d0000 { 701 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 702 reg = <0x0 0xff1d0000 0x0 0x1000>; 703 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 704 clock-names = "spiclk", "apb_pclk"; 705 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 706 dmas = <&dmac_peri 12>, <&dmac_peri 13>; 707 dma-names = "tx", "rx"; 708 pinctrl-names = "default"; 709 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 710 #address-cells = <1>; 711 #size-cells = <0>; 712 status = "disabled"; 713 }; 714 715 spi2: spi@ff1e0000 { 716 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 717 reg = <0x0 0xff1e0000 0x0 0x1000>; 718 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 719 clock-names = "spiclk", "apb_pclk"; 720 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 721 dmas = <&dmac_peri 14>, <&dmac_peri 15>; 722 dma-names = "tx", "rx"; 723 pinctrl-names = "default"; 724 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 725 #address-cells = <1>; 726 #size-cells = <0>; 727 status = "disabled"; 728 }; 729 730 spi4: spi@ff1f0000 { 731 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 732 reg = <0x0 0xff1f0000 0x0 0x1000>; 733 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 734 clock-names = "spiclk", "apb_pclk"; 735 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 736 dmas = <&dmac_peri 18>, <&dmac_peri 19>; 737 dma-names = "tx", "rx"; 738 pinctrl-names = "default"; 739 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 740 #address-cells = <1>; 741 #size-cells = <0>; 742 status = "disabled"; 743 }; 744 745 spi5: spi@ff200000 { 746 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 747 reg = <0x0 0xff200000 0x0 0x1000>; 748 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 749 clock-names = "spiclk", "apb_pclk"; 750 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 751 dmas = <&dmac_bus 8>, <&dmac_bus 9>; 752 dma-names = "tx", "rx"; 753 pinctrl-names = "default"; 754 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 755 power-domains = <&power RK3399_PD_SDIOAUDIO>; 756 #address-cells = <1>; 757 #size-cells = <0>; 758 status = "disabled"; 759 }; 760 761 thermal_zones: thermal-zones { 762 cpu_thermal: cpu { 763 polling-delay-passive = <100>; 764 polling-delay = <1000>; 765 766 thermal-sensors = <&tsadc 0>; 767 768 trips { 769 cpu_alert0: cpu_alert0 { 770 temperature = <70000>; 771 hysteresis = <2000>; 772 type = "passive"; 773 }; 774 cpu_alert1: cpu_alert1 { 775 temperature = <75000>; 776 hysteresis = <2000>; 777 type = "passive"; 778 }; 779 cpu_crit: cpu_crit { 780 temperature = <95000>; 781 hysteresis = <2000>; 782 type = "critical"; 783 }; 784 }; 785 786 cooling-maps { 787 map0 { 788 trip = <&cpu_alert0>; 789 cooling-device = 790 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 791 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 792 }; 793 map1 { 794 trip = <&cpu_alert1>; 795 cooling-device = 796 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 797 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 798 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 799 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 800 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 801 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 802 }; 803 }; 804 }; 805 806 gpu_thermal: gpu { 807 polling-delay-passive = <100>; 808 polling-delay = <1000>; 809 810 thermal-sensors = <&tsadc 1>; 811 812 trips { 813 gpu_alert0: gpu_alert0 { 814 temperature = <75000>; 815 hysteresis = <2000>; 816 type = "passive"; 817 }; 818 gpu_crit: gpu_crit { 819 temperature = <95000>; 820 hysteresis = <2000>; 821 type = "critical"; 822 }; 823 }; 824 825 cooling-maps { 826 map0 { 827 trip = <&gpu_alert0>; 828 cooling-device = 829 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 830 }; 831 }; 832 }; 833 }; 834 835 tsadc: tsadc@ff260000 { 836 compatible = "rockchip,rk3399-tsadc"; 837 reg = <0x0 0xff260000 0x0 0x100>; 838 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 839 assigned-clocks = <&cru SCLK_TSADC>; 840 assigned-clock-rates = <750000>; 841 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 842 clock-names = "tsadc", "apb_pclk"; 843 resets = <&cru SRST_TSADC>; 844 reset-names = "tsadc-apb"; 845 rockchip,grf = <&grf>; 846 rockchip,hw-tshut-temp = <95000>; 847 pinctrl-names = "init", "default", "sleep"; 848 pinctrl-0 = <&otp_gpio>; 849 pinctrl-1 = <&otp_out>; 850 pinctrl-2 = <&otp_gpio>; 851 #thermal-sensor-cells = <1>; 852 status = "disabled"; 853 }; 854 855 qos_emmc: qos@ffa58000 { 856 compatible = "syscon"; 857 reg = <0x0 0xffa58000 0x0 0x20>; 858 }; 859 860 qos_gmac: qos@ffa5c000 { 861 compatible = "syscon"; 862 reg = <0x0 0xffa5c000 0x0 0x20>; 863 }; 864 865 qos_pcie: qos@ffa60080 { 866 compatible = "syscon"; 867 reg = <0x0 0xffa60080 0x0 0x20>; 868 }; 869 870 qos_usb_host0: qos@ffa60100 { 871 compatible = "syscon"; 872 reg = <0x0 0xffa60100 0x0 0x20>; 873 }; 874 875 qos_usb_host1: qos@ffa60180 { 876 compatible = "syscon"; 877 reg = <0x0 0xffa60180 0x0 0x20>; 878 }; 879 880 qos_usb_otg0: qos@ffa70000 { 881 compatible = "syscon"; 882 reg = <0x0 0xffa70000 0x0 0x20>; 883 }; 884 885 qos_usb_otg1: qos@ffa70080 { 886 compatible = "syscon"; 887 reg = <0x0 0xffa70080 0x0 0x20>; 888 }; 889 890 qos_sd: qos@ffa74000 { 891 compatible = "syscon"; 892 reg = <0x0 0xffa74000 0x0 0x20>; 893 }; 894 895 qos_sdioaudio: qos@ffa76000 { 896 compatible = "syscon"; 897 reg = <0x0 0xffa76000 0x0 0x20>; 898 }; 899 900 qos_hdcp: qos@ffa90000 { 901 compatible = "syscon"; 902 reg = <0x0 0xffa90000 0x0 0x20>; 903 }; 904 905 qos_iep: qos@ffa98000 { 906 compatible = "syscon"; 907 reg = <0x0 0xffa98000 0x0 0x20>; 908 }; 909 910 qos_isp0_m0: qos@ffaa0000 { 911 compatible = "syscon"; 912 reg = <0x0 0xffaa0000 0x0 0x20>; 913 }; 914 915 qos_isp0_m1: qos@ffaa0080 { 916 compatible = "syscon"; 917 reg = <0x0 0xffaa0080 0x0 0x20>; 918 }; 919 920 qos_isp1_m0: qos@ffaa8000 { 921 compatible = "syscon"; 922 reg = <0x0 0xffaa8000 0x0 0x20>; 923 }; 924 925 qos_isp1_m1: qos@ffaa8080 { 926 compatible = "syscon"; 927 reg = <0x0 0xffaa8080 0x0 0x20>; 928 }; 929 930 qos_rga_r: qos@ffab0000 { 931 compatible = "syscon"; 932 reg = <0x0 0xffab0000 0x0 0x20>; 933 }; 934 935 qos_rga_w: qos@ffab0080 { 936 compatible = "syscon"; 937 reg = <0x0 0xffab0080 0x0 0x20>; 938 }; 939 940 qos_video_m0: qos@ffab8000 { 941 compatible = "syscon"; 942 reg = <0x0 0xffab8000 0x0 0x20>; 943 }; 944 945 qos_video_m1_r: qos@ffac0000 { 946 compatible = "syscon"; 947 reg = <0x0 0xffac0000 0x0 0x20>; 948 }; 949 950 qos_video_m1_w: qos@ffac0080 { 951 compatible = "syscon"; 952 reg = <0x0 0xffac0080 0x0 0x20>; 953 }; 954 955 qos_vop_big_r: qos@ffac8000 { 956 compatible = "syscon"; 957 reg = <0x0 0xffac8000 0x0 0x20>; 958 }; 959 960 qos_vop_big_w: qos@ffac8080 { 961 compatible = "syscon"; 962 reg = <0x0 0xffac8080 0x0 0x20>; 963 }; 964 965 qos_vop_little: qos@ffad0000 { 966 compatible = "syscon"; 967 reg = <0x0 0xffad0000 0x0 0x20>; 968 }; 969 970 qos_perihp: qos@ffad8080 { 971 compatible = "syscon"; 972 reg = <0x0 0xffad8080 0x0 0x20>; 973 }; 974 975 qos_gpu: qos@ffae0000 { 976 compatible = "syscon"; 977 reg = <0x0 0xffae0000 0x0 0x20>; 978 }; 979 980 pmu: power-management@ff310000 { 981 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 982 reg = <0x0 0xff310000 0x0 0x1000>; 983 984 /* 985 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 986 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 987 * Some of the power domains are grouped together for every 988 * voltage domain. 989 * The detail contents as below. 990 */ 991 power: power-controller { 992 compatible = "rockchip,rk3399-power-controller"; 993 #power-domain-cells = <1>; 994 #address-cells = <1>; 995 #size-cells = <0>; 996 997 /* These power domains are grouped by VD_CENTER */ 998 pd_iep@RK3399_PD_IEP { 999 reg = <RK3399_PD_IEP>; 1000 clocks = <&cru ACLK_IEP>, 1001 <&cru HCLK_IEP>; 1002 pm_qos = <&qos_iep>; 1003 }; 1004 pd_rga@RK3399_PD_RGA { 1005 reg = <RK3399_PD_RGA>; 1006 clocks = <&cru ACLK_RGA>, 1007 <&cru HCLK_RGA>; 1008 pm_qos = <&qos_rga_r>, 1009 <&qos_rga_w>; 1010 }; 1011 pd_vcodec@RK3399_PD_VCODEC { 1012 reg = <RK3399_PD_VCODEC>; 1013 clocks = <&cru ACLK_VCODEC>, 1014 <&cru HCLK_VCODEC>; 1015 pm_qos = <&qos_video_m0>; 1016 }; 1017 pd_vdu@RK3399_PD_VDU { 1018 reg = <RK3399_PD_VDU>; 1019 clocks = <&cru ACLK_VDU>, 1020 <&cru HCLK_VDU>; 1021 pm_qos = <&qos_video_m1_r>, 1022 <&qos_video_m1_w>; 1023 }; 1024 1025 /* These power domains are grouped by VD_GPU */ 1026 pd_gpu@RK3399_PD_GPU { 1027 reg = <RK3399_PD_GPU>; 1028 clocks = <&cru ACLK_GPU>; 1029 pm_qos = <&qos_gpu>; 1030 }; 1031 1032 /* These power domains are grouped by VD_LOGIC */ 1033 pd_edp@RK3399_PD_EDP { 1034 reg = <RK3399_PD_EDP>; 1035 clocks = <&cru PCLK_EDP_CTRL>; 1036 }; 1037 pd_emmc@RK3399_PD_EMMC { 1038 reg = <RK3399_PD_EMMC>; 1039 clocks = <&cru ACLK_EMMC>; 1040 pm_qos = <&qos_emmc>; 1041 }; 1042 pd_gmac@RK3399_PD_GMAC { 1043 reg = <RK3399_PD_GMAC>; 1044 clocks = <&cru ACLK_GMAC>, 1045 <&cru PCLK_GMAC>; 1046 pm_qos = <&qos_gmac>; 1047 }; 1048 pd_sd@RK3399_PD_SD { 1049 reg = <RK3399_PD_SD>; 1050 clocks = <&cru HCLK_SDMMC>, 1051 <&cru SCLK_SDMMC>; 1052 pm_qos = <&qos_sd>; 1053 }; 1054 pd_sdioaudio@RK3399_PD_SDIOAUDIO { 1055 reg = <RK3399_PD_SDIOAUDIO>; 1056 clocks = <&cru HCLK_SDIO>; 1057 pm_qos = <&qos_sdioaudio>; 1058 }; 1059 pd_usb3@RK3399_PD_USB3 { 1060 reg = <RK3399_PD_USB3>; 1061 clocks = <&cru ACLK_USB3>; 1062 pm_qos = <&qos_usb_otg0>, 1063 <&qos_usb_otg1>; 1064 }; 1065 pd_vio@RK3399_PD_VIO { 1066 reg = <RK3399_PD_VIO>; 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 1070 pd_hdcp@RK3399_PD_HDCP { 1071 reg = <RK3399_PD_HDCP>; 1072 clocks = <&cru ACLK_HDCP>, 1073 <&cru HCLK_HDCP>, 1074 <&cru PCLK_HDCP>; 1075 pm_qos = <&qos_hdcp>; 1076 }; 1077 pd_isp0@RK3399_PD_ISP0 { 1078 reg = <RK3399_PD_ISP0>; 1079 clocks = <&cru ACLK_ISP0>, 1080 <&cru HCLK_ISP0>; 1081 pm_qos = <&qos_isp0_m0>, 1082 <&qos_isp0_m1>; 1083 }; 1084 pd_isp1@RK3399_PD_ISP1 { 1085 reg = <RK3399_PD_ISP1>; 1086 clocks = <&cru ACLK_ISP1>, 1087 <&cru HCLK_ISP1>; 1088 pm_qos = <&qos_isp1_m0>, 1089 <&qos_isp1_m1>; 1090 }; 1091 pd_tcpc0@RK3399_PD_TCPC0 { 1092 reg = <RK3399_PD_TCPD0>; 1093 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1094 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1095 }; 1096 pd_tcpc1@RK3399_PD_TCPC1 { 1097 reg = <RK3399_PD_TCPD1>; 1098 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1099 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1100 }; 1101 pd_vo@RK3399_PD_VO { 1102 reg = <RK3399_PD_VO>; 1103 #address-cells = <1>; 1104 #size-cells = <0>; 1105 1106 pd_vopb@RK3399_PD_VOPB { 1107 reg = <RK3399_PD_VOPB>; 1108 clocks = <&cru ACLK_VOP0>, 1109 <&cru HCLK_VOP0>; 1110 pm_qos = <&qos_vop_big_r>, 1111 <&qos_vop_big_w>; 1112 }; 1113 pd_vopl@RK3399_PD_VOPL { 1114 reg = <RK3399_PD_VOPL>; 1115 clocks = <&cru ACLK_VOP1>, 1116 <&cru HCLK_VOP1>; 1117 pm_qos = <&qos_vop_little>; 1118 }; 1119 }; 1120 }; 1121 }; 1122 }; 1123 1124 pmugrf: syscon@ff320000 { 1125 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1126 reg = <0x0 0xff320000 0x0 0x1000>; 1127 1128 pmu_io_domains: io-domains { 1129 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1130 status = "disabled"; 1131 }; 1132 }; 1133 1134 spi3: spi@ff350000 { 1135 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1136 reg = <0x0 0xff350000 0x0 0x1000>; 1137 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1138 clock-names = "spiclk", "apb_pclk"; 1139 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1140 pinctrl-names = "default"; 1141 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1142 #address-cells = <1>; 1143 #size-cells = <0>; 1144 status = "disabled"; 1145 }; 1146 1147 uart4: serial@ff370000 { 1148 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1149 reg = <0x0 0xff370000 0x0 0x100>; 1150 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1151 clock-names = "baudclk", "apb_pclk"; 1152 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1153 reg-shift = <2>; 1154 reg-io-width = <4>; 1155 pinctrl-names = "default"; 1156 pinctrl-0 = <&uart4_xfer>; 1157 status = "disabled"; 1158 }; 1159 1160 i2c0: i2c@ff3c0000 { 1161 compatible = "rockchip,rk3399-i2c"; 1162 reg = <0x0 0xff3c0000 0x0 0x1000>; 1163 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1164 assigned-clock-rates = <200000000>; 1165 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1166 clock-names = "i2c", "pclk"; 1167 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1168 pinctrl-names = "default"; 1169 pinctrl-0 = <&i2c0_xfer>; 1170 #address-cells = <1>; 1171 #size-cells = <0>; 1172 status = "disabled"; 1173 }; 1174 1175 i2c4: i2c@ff3d0000 { 1176 compatible = "rockchip,rk3399-i2c"; 1177 reg = <0x0 0xff3d0000 0x0 0x1000>; 1178 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1179 assigned-clock-rates = <200000000>; 1180 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1181 clock-names = "i2c", "pclk"; 1182 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1183 pinctrl-names = "default"; 1184 pinctrl-0 = <&i2c4_xfer>; 1185 #address-cells = <1>; 1186 #size-cells = <0>; 1187 status = "disabled"; 1188 }; 1189 1190 i2c8: i2c@ff3e0000 { 1191 compatible = "rockchip,rk3399-i2c"; 1192 reg = <0x0 0xff3e0000 0x0 0x1000>; 1193 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1194 assigned-clock-rates = <200000000>; 1195 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1196 clock-names = "i2c", "pclk"; 1197 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1198 pinctrl-names = "default"; 1199 pinctrl-0 = <&i2c8_xfer>; 1200 #address-cells = <1>; 1201 #size-cells = <0>; 1202 status = "disabled"; 1203 }; 1204 1205 pwm0: pwm@ff420000 { 1206 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1207 reg = <0x0 0xff420000 0x0 0x10>; 1208 #pwm-cells = <3>; 1209 pinctrl-names = "default"; 1210 pinctrl-0 = <&pwm0_pin>; 1211 clocks = <&pmucru PCLK_RKPWM_PMU>; 1212 clock-names = "pwm"; 1213 status = "disabled"; 1214 }; 1215 1216 pwm1: pwm@ff420010 { 1217 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1218 reg = <0x0 0xff420010 0x0 0x10>; 1219 #pwm-cells = <3>; 1220 pinctrl-names = "default"; 1221 pinctrl-0 = <&pwm1_pin>; 1222 clocks = <&pmucru PCLK_RKPWM_PMU>; 1223 clock-names = "pwm"; 1224 status = "disabled"; 1225 }; 1226 1227 pwm2: pwm@ff420020 { 1228 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1229 reg = <0x0 0xff420020 0x0 0x10>; 1230 #pwm-cells = <3>; 1231 pinctrl-names = "default"; 1232 pinctrl-0 = <&pwm2_pin>; 1233 clocks = <&pmucru PCLK_RKPWM_PMU>; 1234 clock-names = "pwm"; 1235 status = "disabled"; 1236 }; 1237 1238 pwm3: pwm@ff420030 { 1239 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1240 reg = <0x0 0xff420030 0x0 0x10>; 1241 #pwm-cells = <3>; 1242 pinctrl-names = "default"; 1243 pinctrl-0 = <&pwm3a_pin>; 1244 clocks = <&pmucru PCLK_RKPWM_PMU>; 1245 clock-names = "pwm"; 1246 status = "disabled"; 1247 }; 1248 1249 vpu: video-codec@ff650000 { 1250 compatible = "rockchip,rk3399-vpu"; 1251 reg = <0x0 0xff650000 0x0 0x800>; 1252 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 1253 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 1254 interrupt-names = "vepu", "vdpu"; 1255 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1256 clock-names = "aclk", "hclk"; 1257 iommus = <&vpu_mmu>; 1258 power-domains = <&power RK3399_PD_VCODEC>; 1259 }; 1260 1261 vpu_mmu: iommu@ff650800 { 1262 compatible = "rockchip,iommu"; 1263 reg = <0x0 0xff650800 0x0 0x40>; 1264 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 1265 interrupt-names = "vpu_mmu"; 1266 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1267 clock-names = "aclk", "iface"; 1268 #iommu-cells = <0>; 1269 power-domains = <&power RK3399_PD_VCODEC>; 1270 }; 1271 1272 vdec_mmu: iommu@ff660480 { 1273 compatible = "rockchip,iommu"; 1274 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; 1275 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1276 interrupt-names = "vdec_mmu"; 1277 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; 1278 clock-names = "aclk", "iface"; 1279 #iommu-cells = <0>; 1280 status = "disabled"; 1281 }; 1282 1283 iep_mmu: iommu@ff670800 { 1284 compatible = "rockchip,iommu"; 1285 reg = <0x0 0xff670800 0x0 0x40>; 1286 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>; 1287 interrupt-names = "iep_mmu"; 1288 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 1289 clock-names = "aclk", "iface"; 1290 #iommu-cells = <0>; 1291 status = "disabled"; 1292 }; 1293 1294 rga: rga@ff680000 { 1295 compatible = "rockchip,rk3399-rga"; 1296 reg = <0x0 0xff680000 0x0 0x10000>; 1297 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>; 1298 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; 1299 clock-names = "aclk", "hclk", "sclk"; 1300 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 1301 reset-names = "core", "axi", "ahb"; 1302 power-domains = <&power RK3399_PD_RGA>; 1303 }; 1304 1305 efuse0: efuse@ff690000 { 1306 compatible = "rockchip,rk3399-efuse"; 1307 reg = <0x0 0xff690000 0x0 0x80>; 1308 #address-cells = <1>; 1309 #size-cells = <1>; 1310 clocks = <&cru PCLK_EFUSE1024NS>; 1311 clock-names = "pclk_efuse"; 1312 1313 /* Data cells */ 1314 cpu_id: cpu-id@7 { 1315 reg = <0x07 0x10>; 1316 }; 1317 cpub_leakage: cpu-leakage@17 { 1318 reg = <0x17 0x1>; 1319 }; 1320 gpu_leakage: gpu-leakage@18 { 1321 reg = <0x18 0x1>; 1322 }; 1323 center_leakage: center-leakage@19 { 1324 reg = <0x19 0x1>; 1325 }; 1326 cpul_leakage: cpu-leakage@1a { 1327 reg = <0x1a 0x1>; 1328 }; 1329 logic_leakage: logic-leakage@1b { 1330 reg = <0x1b 0x1>; 1331 }; 1332 wafer_info: wafer-info@1c { 1333 reg = <0x1c 0x1>; 1334 }; 1335 }; 1336 1337 pmucru: pmu-clock-controller@ff750000 { 1338 compatible = "rockchip,rk3399-pmucru"; 1339 reg = <0x0 0xff750000 0x0 0x1000>; 1340 rockchip,grf = <&pmugrf>; 1341 #clock-cells = <1>; 1342 #reset-cells = <1>; 1343 assigned-clocks = <&pmucru PLL_PPLL>; 1344 assigned-clock-rates = <676000000>; 1345 }; 1346 1347 cru: clock-controller@ff760000 { 1348 compatible = "rockchip,rk3399-cru"; 1349 reg = <0x0 0xff760000 0x0 0x1000>; 1350 rockchip,grf = <&grf>; 1351 #clock-cells = <1>; 1352 #reset-cells = <1>; 1353 assigned-clocks = 1354 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1355 <&cru PLL_NPLL>, 1356 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1357 <&cru PCLK_PERIHP>, 1358 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1359 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1360 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 1361 <&cru ACLK_VIO>, <&cru ACLK_HDCP>, 1362 <&cru ACLK_GIC_PRE>, 1363 <&cru PCLK_DDR>; 1364 assigned-clock-rates = 1365 <594000000>, <800000000>, 1366 <1000000000>, 1367 <150000000>, <75000000>, 1368 <37500000>, 1369 <100000000>, <100000000>, 1370 <50000000>, <600000000>, 1371 <100000000>, <50000000>, 1372 <400000000>, <400000000>, 1373 <200000000>, 1374 <200000000>; 1375 }; 1376 1377 grf: syscon@ff770000 { 1378 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1379 reg = <0x0 0xff770000 0x0 0x10000>; 1380 #address-cells = <1>; 1381 #size-cells = <1>; 1382 1383 io_domains: io-domains { 1384 compatible = "rockchip,rk3399-io-voltage-domain"; 1385 status = "disabled"; 1386 }; 1387 1388 u2phy0: usb2-phy@e450 { 1389 compatible = "rockchip,rk3399-usb2phy"; 1390 reg = <0xe450 0x10>; 1391 clocks = <&cru SCLK_USB2PHY0_REF>; 1392 clock-names = "phyclk"; 1393 #clock-cells = <0>; 1394 clock-output-names = "clk_usbphy0_480m"; 1395 status = "disabled"; 1396 1397 u2phy0_host: host-port { 1398 #phy-cells = <0>; 1399 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1400 interrupt-names = "linestate"; 1401 status = "disabled"; 1402 }; 1403 1404 u2phy0_otg: otg-port { 1405 #phy-cells = <0>; 1406 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1407 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1408 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1409 interrupt-names = "otg-bvalid", "otg-id", 1410 "linestate"; 1411 status = "disabled"; 1412 }; 1413 }; 1414 1415 u2phy1: usb2-phy@e460 { 1416 compatible = "rockchip,rk3399-usb2phy"; 1417 reg = <0xe460 0x10>; 1418 clocks = <&cru SCLK_USB2PHY1_REF>; 1419 clock-names = "phyclk"; 1420 #clock-cells = <0>; 1421 clock-output-names = "clk_usbphy1_480m"; 1422 status = "disabled"; 1423 1424 u2phy1_host: host-port { 1425 #phy-cells = <0>; 1426 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1427 interrupt-names = "linestate"; 1428 status = "disabled"; 1429 }; 1430 1431 u2phy1_otg: otg-port { 1432 #phy-cells = <0>; 1433 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1434 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1435 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1436 interrupt-names = "otg-bvalid", "otg-id", 1437 "linestate"; 1438 status = "disabled"; 1439 }; 1440 }; 1441 1442 emmc_phy: phy@f780 { 1443 compatible = "rockchip,rk3399-emmc-phy"; 1444 reg = <0xf780 0x24>; 1445 clocks = <&sdhci>; 1446 clock-names = "emmcclk"; 1447 #phy-cells = <0>; 1448 status = "disabled"; 1449 }; 1450 1451 pcie_phy: pcie-phy { 1452 compatible = "rockchip,rk3399-pcie-phy"; 1453 clocks = <&cru SCLK_PCIEPHY_REF>; 1454 clock-names = "refclk"; 1455 #phy-cells = <1>; 1456 resets = <&cru SRST_PCIEPHY>; 1457 drive-impedance-ohm = <50>; 1458 reset-names = "phy"; 1459 status = "disabled"; 1460 }; 1461 }; 1462 1463 tcphy0: phy@ff7c0000 { 1464 compatible = "rockchip,rk3399-typec-phy"; 1465 reg = <0x0 0xff7c0000 0x0 0x40000>; 1466 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1467 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1468 clock-names = "tcpdcore", "tcpdphy-ref"; 1469 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1470 assigned-clock-rates = <50000000>; 1471 power-domains = <&power RK3399_PD_TCPD0>; 1472 resets = <&cru SRST_UPHY0>, 1473 <&cru SRST_UPHY0_PIPE_L00>, 1474 <&cru SRST_P_UPHY0_TCPHY>; 1475 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1476 rockchip,grf = <&grf>; 1477 status = "disabled"; 1478 1479 tcphy0_dp: dp-port { 1480 #phy-cells = <0>; 1481 }; 1482 1483 tcphy0_usb3: usb3-port { 1484 #phy-cells = <0>; 1485 }; 1486 }; 1487 1488 tcphy1: phy@ff800000 { 1489 compatible = "rockchip,rk3399-typec-phy"; 1490 reg = <0x0 0xff800000 0x0 0x40000>; 1491 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1492 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1493 clock-names = "tcpdcore", "tcpdphy-ref"; 1494 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1495 assigned-clock-rates = <50000000>; 1496 power-domains = <&power RK3399_PD_TCPD1>; 1497 resets = <&cru SRST_UPHY1>, 1498 <&cru SRST_UPHY1_PIPE_L00>, 1499 <&cru SRST_P_UPHY1_TCPHY>; 1500 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1501 rockchip,grf = <&grf>; 1502 status = "disabled"; 1503 1504 tcphy1_dp: dp-port { 1505 #phy-cells = <0>; 1506 }; 1507 1508 tcphy1_usb3: usb3-port { 1509 #phy-cells = <0>; 1510 }; 1511 }; 1512 1513 watchdog@ff848000 { 1514 compatible = "snps,dw-wdt"; 1515 reg = <0x0 0xff848000 0x0 0x100>; 1516 clocks = <&cru PCLK_WDT>; 1517 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1518 }; 1519 1520 rktimer: rktimer@ff850000 { 1521 compatible = "rockchip,rk3399-timer"; 1522 reg = <0x0 0xff850000 0x0 0x1000>; 1523 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1524 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1525 clock-names = "pclk", "timer"; 1526 }; 1527 1528 spdif: spdif@ff870000 { 1529 compatible = "rockchip,rk3399-spdif"; 1530 reg = <0x0 0xff870000 0x0 0x1000>; 1531 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1532 dmas = <&dmac_bus 7>; 1533 dma-names = "tx"; 1534 clock-names = "mclk", "hclk"; 1535 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1536 pinctrl-names = "default"; 1537 pinctrl-0 = <&spdif_bus>; 1538 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1539 #sound-dai-cells = <0>; 1540 status = "disabled"; 1541 }; 1542 1543 i2s0: i2s@ff880000 { 1544 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1545 reg = <0x0 0xff880000 0x0 0x1000>; 1546 rockchip,grf = <&grf>; 1547 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1548 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1549 dma-names = "tx", "rx"; 1550 clock-names = "i2s_clk", "i2s_hclk"; 1551 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1552 pinctrl-names = "default"; 1553 pinctrl-0 = <&i2s0_8ch_bus>; 1554 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1555 #sound-dai-cells = <0>; 1556 status = "disabled"; 1557 }; 1558 1559 i2s1: i2s@ff890000 { 1560 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1561 reg = <0x0 0xff890000 0x0 0x1000>; 1562 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1563 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1564 dma-names = "tx", "rx"; 1565 clock-names = "i2s_clk", "i2s_hclk"; 1566 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1567 pinctrl-names = "default"; 1568 pinctrl-0 = <&i2s1_2ch_bus>; 1569 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1570 #sound-dai-cells = <0>; 1571 status = "disabled"; 1572 }; 1573 1574 i2s2: i2s@ff8a0000 { 1575 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1576 reg = <0x0 0xff8a0000 0x0 0x1000>; 1577 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1578 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1579 dma-names = "tx", "rx"; 1580 clock-names = "i2s_clk", "i2s_hclk"; 1581 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1582 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1583 #sound-dai-cells = <0>; 1584 status = "disabled"; 1585 }; 1586 1587 vopl: vop@ff8f0000 { 1588 compatible = "rockchip,rk3399-vop-lit"; 1589 reg = <0x0 0xff8f0000 0x0 0x3efc>; 1590 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1591 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1592 assigned-clock-rates = <400000000>, <100000000>; 1593 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1594 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1595 iommus = <&vopl_mmu>; 1596 power-domains = <&power RK3399_PD_VOPL>; 1597 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1598 reset-names = "axi", "ahb", "dclk"; 1599 status = "disabled"; 1600 1601 vopl_out: port { 1602 #address-cells = <1>; 1603 #size-cells = <0>; 1604 1605 vopl_out_mipi: endpoint@0 { 1606 reg = <0>; 1607 remote-endpoint = <&mipi_in_vopl>; 1608 }; 1609 1610 vopl_out_edp: endpoint@1 { 1611 reg = <1>; 1612 remote-endpoint = <&edp_in_vopl>; 1613 }; 1614 1615 vopl_out_hdmi: endpoint@2 { 1616 reg = <2>; 1617 remote-endpoint = <&hdmi_in_vopl>; 1618 }; 1619 1620 vopl_out_mipi1: endpoint@3 { 1621 reg = <3>; 1622 remote-endpoint = <&mipi1_in_vopl>; 1623 }; 1624 1625 vopl_out_dp: endpoint@4 { 1626 reg = <4>; 1627 remote-endpoint = <&dp_in_vopl>; 1628 }; 1629 }; 1630 }; 1631 1632 vopl_mmu: iommu@ff8f3f00 { 1633 compatible = "rockchip,iommu"; 1634 reg = <0x0 0xff8f3f00 0x0 0x100>; 1635 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1636 interrupt-names = "vopl_mmu"; 1637 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1638 clock-names = "aclk", "iface"; 1639 power-domains = <&power RK3399_PD_VOPL>; 1640 #iommu-cells = <0>; 1641 status = "disabled"; 1642 }; 1643 1644 vopb: vop@ff900000 { 1645 compatible = "rockchip,rk3399-vop-big"; 1646 reg = <0x0 0xff900000 0x0 0x3efc>; 1647 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1648 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1649 assigned-clock-rates = <400000000>, <100000000>; 1650 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1651 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1652 iommus = <&vopb_mmu>; 1653 power-domains = <&power RK3399_PD_VOPB>; 1654 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1655 reset-names = "axi", "ahb", "dclk"; 1656 status = "disabled"; 1657 1658 vopb_out: port { 1659 #address-cells = <1>; 1660 #size-cells = <0>; 1661 1662 vopb_out_edp: endpoint@0 { 1663 reg = <0>; 1664 remote-endpoint = <&edp_in_vopb>; 1665 }; 1666 1667 vopb_out_mipi: endpoint@1 { 1668 reg = <1>; 1669 remote-endpoint = <&mipi_in_vopb>; 1670 }; 1671 1672 vopb_out_hdmi: endpoint@2 { 1673 reg = <2>; 1674 remote-endpoint = <&hdmi_in_vopb>; 1675 }; 1676 1677 vopb_out_mipi1: endpoint@3 { 1678 reg = <3>; 1679 remote-endpoint = <&mipi1_in_vopb>; 1680 }; 1681 1682 vopb_out_dp: endpoint@4 { 1683 reg = <4>; 1684 remote-endpoint = <&dp_in_vopb>; 1685 }; 1686 }; 1687 }; 1688 1689 vopb_mmu: iommu@ff903f00 { 1690 compatible = "rockchip,iommu"; 1691 reg = <0x0 0xff903f00 0x0 0x100>; 1692 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1693 interrupt-names = "vopb_mmu"; 1694 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1695 clock-names = "aclk", "iface"; 1696 power-domains = <&power RK3399_PD_VOPB>; 1697 #iommu-cells = <0>; 1698 status = "disabled"; 1699 }; 1700 1701 isp0_mmu: iommu@ff914000 { 1702 compatible = "rockchip,iommu"; 1703 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1704 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1705 interrupt-names = "isp0_mmu"; 1706 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; 1707 clock-names = "aclk", "iface"; 1708 #iommu-cells = <0>; 1709 power-domains = <&power RK3399_PD_ISP0>; 1710 rockchip,disable-mmu-reset; 1711 }; 1712 1713 isp1_mmu: iommu@ff924000 { 1714 compatible = "rockchip,iommu"; 1715 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; 1716 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 1717 interrupt-names = "isp1_mmu"; 1718 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; 1719 clock-names = "aclk", "iface"; 1720 #iommu-cells = <0>; 1721 power-domains = <&power RK3399_PD_ISP1>; 1722 rockchip,disable-mmu-reset; 1723 }; 1724 1725 hdmi_sound: hdmi-sound { 1726 compatible = "simple-audio-card"; 1727 simple-audio-card,format = "i2s"; 1728 simple-audio-card,mclk-fs = <256>; 1729 simple-audio-card,name = "hdmi-sound"; 1730 status = "disabled"; 1731 1732 simple-audio-card,cpu { 1733 sound-dai = <&i2s2>; 1734 }; 1735 simple-audio-card,codec { 1736 sound-dai = <&hdmi>; 1737 }; 1738 }; 1739 1740 hdmi: hdmi@ff940000 { 1741 compatible = "rockchip,rk3399-dw-hdmi"; 1742 reg = <0x0 0xff940000 0x0 0x20000>; 1743 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 1744 clocks = <&cru PCLK_HDMI_CTRL>, 1745 <&cru SCLK_HDMI_SFR>, 1746 <&cru PLL_VPLL>, 1747 <&cru PCLK_VIO_GRF>, 1748 <&cru SCLK_HDMI_CEC>; 1749 clock-names = "iahb", "isfr", "vpll", "grf", "cec"; 1750 power-domains = <&power RK3399_PD_HDCP>; 1751 reg-io-width = <4>; 1752 rockchip,grf = <&grf>; 1753 #sound-dai-cells = <0>; 1754 status = "disabled"; 1755 1756 ports { 1757 hdmi_in: port { 1758 #address-cells = <1>; 1759 #size-cells = <0>; 1760 1761 hdmi_in_vopb: endpoint@0 { 1762 reg = <0>; 1763 remote-endpoint = <&vopb_out_hdmi>; 1764 }; 1765 hdmi_in_vopl: endpoint@1 { 1766 reg = <1>; 1767 remote-endpoint = <&vopl_out_hdmi>; 1768 }; 1769 }; 1770 }; 1771 }; 1772 1773 mipi_dsi: mipi@ff960000 { 1774 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1775 reg = <0x0 0xff960000 0x0 0x8000>; 1776 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 1777 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, 1778 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; 1779 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1780 power-domains = <&power RK3399_PD_VIO>; 1781 resets = <&cru SRST_P_MIPI_DSI0>; 1782 reset-names = "apb"; 1783 rockchip,grf = <&grf>; 1784 #address-cells = <1>; 1785 #size-cells = <0>; 1786 status = "disabled"; 1787 1788 ports { 1789 #address-cells = <1>; 1790 #size-cells = <0>; 1791 1792 mipi_in: port@0 { 1793 reg = <0>; 1794 #address-cells = <1>; 1795 #size-cells = <0>; 1796 1797 mipi_in_vopb: endpoint@0 { 1798 reg = <0>; 1799 remote-endpoint = <&vopb_out_mipi>; 1800 }; 1801 mipi_in_vopl: endpoint@1 { 1802 reg = <1>; 1803 remote-endpoint = <&vopl_out_mipi>; 1804 }; 1805 }; 1806 }; 1807 }; 1808 1809 mipi_dsi1: mipi@ff968000 { 1810 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1811 reg = <0x0 0xff968000 0x0 0x8000>; 1812 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>; 1813 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, 1814 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; 1815 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1816 power-domains = <&power RK3399_PD_VIO>; 1817 resets = <&cru SRST_P_MIPI_DSI1>; 1818 reset-names = "apb"; 1819 rockchip,grf = <&grf>; 1820 #address-cells = <1>; 1821 #size-cells = <0>; 1822 status = "disabled"; 1823 1824 ports { 1825 #address-cells = <1>; 1826 #size-cells = <0>; 1827 1828 mipi1_in: port@0 { 1829 reg = <0>; 1830 #address-cells = <1>; 1831 #size-cells = <0>; 1832 1833 mipi1_in_vopb: endpoint@0 { 1834 reg = <0>; 1835 remote-endpoint = <&vopb_out_mipi1>; 1836 }; 1837 1838 mipi1_in_vopl: endpoint@1 { 1839 reg = <1>; 1840 remote-endpoint = <&vopl_out_mipi1>; 1841 }; 1842 }; 1843 }; 1844 }; 1845 1846 edp: edp@ff970000 { 1847 compatible = "rockchip,rk3399-edp"; 1848 reg = <0x0 0xff970000 0x0 0x8000>; 1849 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 1850 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; 1851 clock-names = "dp", "pclk", "grf"; 1852 pinctrl-names = "default"; 1853 pinctrl-0 = <&edp_hpd>; 1854 power-domains = <&power RK3399_PD_EDP>; 1855 resets = <&cru SRST_P_EDP_CTRL>; 1856 reset-names = "dp"; 1857 rockchip,grf = <&grf>; 1858 status = "disabled"; 1859 1860 ports { 1861 #address-cells = <1>; 1862 #size-cells = <0>; 1863 edp_in: port@0 { 1864 reg = <0>; 1865 #address-cells = <1>; 1866 #size-cells = <0>; 1867 1868 edp_in_vopb: endpoint@0 { 1869 reg = <0>; 1870 remote-endpoint = <&vopb_out_edp>; 1871 }; 1872 1873 edp_in_vopl: endpoint@1 { 1874 reg = <1>; 1875 remote-endpoint = <&vopl_out_edp>; 1876 }; 1877 }; 1878 }; 1879 }; 1880 1881 gpu: gpu@ff9a0000 { 1882 compatible = "rockchip,rk3399-mali", "arm,mali-t860"; 1883 reg = <0x0 0xff9a0000 0x0 0x10000>; 1884 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, 1885 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>, 1886 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>; 1887 interrupt-names = "job", "mmu", "gpu"; 1888 clocks = <&cru ACLK_GPU>; 1889 #cooling-cells = <2>; 1890 power-domains = <&power RK3399_PD_GPU>; 1891 status = "disabled"; 1892 }; 1893 1894 pinctrl: pinctrl { 1895 compatible = "rockchip,rk3399-pinctrl"; 1896 rockchip,grf = <&grf>; 1897 rockchip,pmu = <&pmugrf>; 1898 #address-cells = <2>; 1899 #size-cells = <2>; 1900 ranges; 1901 1902 gpio0: gpio0@ff720000 { 1903 compatible = "rockchip,gpio-bank"; 1904 reg = <0x0 0xff720000 0x0 0x100>; 1905 clocks = <&pmucru PCLK_GPIO0_PMU>; 1906 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 1907 1908 gpio-controller; 1909 #gpio-cells = <0x2>; 1910 1911 interrupt-controller; 1912 #interrupt-cells = <0x2>; 1913 }; 1914 1915 gpio1: gpio1@ff730000 { 1916 compatible = "rockchip,gpio-bank"; 1917 reg = <0x0 0xff730000 0x0 0x100>; 1918 clocks = <&pmucru PCLK_GPIO1_PMU>; 1919 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 1920 1921 gpio-controller; 1922 #gpio-cells = <0x2>; 1923 1924 interrupt-controller; 1925 #interrupt-cells = <0x2>; 1926 }; 1927 1928 gpio2: gpio2@ff780000 { 1929 compatible = "rockchip,gpio-bank"; 1930 reg = <0x0 0xff780000 0x0 0x100>; 1931 clocks = <&cru PCLK_GPIO2>; 1932 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 1933 1934 gpio-controller; 1935 #gpio-cells = <0x2>; 1936 1937 interrupt-controller; 1938 #interrupt-cells = <0x2>; 1939 }; 1940 1941 gpio3: gpio3@ff788000 { 1942 compatible = "rockchip,gpio-bank"; 1943 reg = <0x0 0xff788000 0x0 0x100>; 1944 clocks = <&cru PCLK_GPIO3>; 1945 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 1946 1947 gpio-controller; 1948 #gpio-cells = <0x2>; 1949 1950 interrupt-controller; 1951 #interrupt-cells = <0x2>; 1952 }; 1953 1954 gpio4: gpio4@ff790000 { 1955 compatible = "rockchip,gpio-bank"; 1956 reg = <0x0 0xff790000 0x0 0x100>; 1957 clocks = <&cru PCLK_GPIO4>; 1958 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 1959 1960 gpio-controller; 1961 #gpio-cells = <0x2>; 1962 1963 interrupt-controller; 1964 #interrupt-cells = <0x2>; 1965 }; 1966 1967 pcfg_pull_up: pcfg-pull-up { 1968 bias-pull-up; 1969 }; 1970 1971 pcfg_pull_down: pcfg-pull-down { 1972 bias-pull-down; 1973 }; 1974 1975 pcfg_pull_none: pcfg-pull-none { 1976 bias-disable; 1977 }; 1978 1979 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1980 bias-disable; 1981 drive-strength = <12>; 1982 }; 1983 1984 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 1985 bias-disable; 1986 drive-strength = <13>; 1987 }; 1988 1989 pcfg_pull_none_18ma: pcfg-pull-none-18ma { 1990 bias-disable; 1991 drive-strength = <18>; 1992 }; 1993 1994 pcfg_pull_none_20ma: pcfg-pull-none-20ma { 1995 bias-disable; 1996 drive-strength = <20>; 1997 }; 1998 1999 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 2000 bias-pull-up; 2001 drive-strength = <2>; 2002 }; 2003 2004 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 2005 bias-pull-up; 2006 drive-strength = <8>; 2007 }; 2008 2009 pcfg_pull_up_18ma: pcfg-pull-up-18ma { 2010 bias-pull-up; 2011 drive-strength = <18>; 2012 }; 2013 2014 pcfg_pull_up_20ma: pcfg-pull-up-20ma { 2015 bias-pull-up; 2016 drive-strength = <20>; 2017 }; 2018 2019 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 2020 bias-pull-down; 2021 drive-strength = <4>; 2022 }; 2023 2024 pcfg_pull_down_8ma: pcfg-pull-down-8ma { 2025 bias-pull-down; 2026 drive-strength = <8>; 2027 }; 2028 2029 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 2030 bias-pull-down; 2031 drive-strength = <12>; 2032 }; 2033 2034 pcfg_pull_down_18ma: pcfg-pull-down-18ma { 2035 bias-pull-down; 2036 drive-strength = <18>; 2037 }; 2038 2039 pcfg_pull_down_20ma: pcfg-pull-down-20ma { 2040 bias-pull-down; 2041 drive-strength = <20>; 2042 }; 2043 2044 pcfg_output_high: pcfg-output-high { 2045 output-high; 2046 }; 2047 2048 pcfg_output_low: pcfg-output-low { 2049 output-low; 2050 }; 2051 2052 clock { 2053 clk_32k: clk-32k { 2054 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; 2055 }; 2056 }; 2057 2058 edp { 2059 edp_hpd: edp-hpd { 2060 rockchip,pins = 2061 <4 RK_PC7 2 &pcfg_pull_none>; 2062 }; 2063 }; 2064 2065 gmac { 2066 rgmii_pins: rgmii-pins { 2067 rockchip,pins = 2068 /* mac_txclk */ 2069 <3 RK_PC1 1 &pcfg_pull_none_13ma>, 2070 /* mac_rxclk */ 2071 <3 RK_PB6 1 &pcfg_pull_none>, 2072 /* mac_mdio */ 2073 <3 RK_PB5 1 &pcfg_pull_none>, 2074 /* mac_txen */ 2075 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2076 /* mac_clk */ 2077 <3 RK_PB3 1 &pcfg_pull_none>, 2078 /* mac_rxdv */ 2079 <3 RK_PB1 1 &pcfg_pull_none>, 2080 /* mac_mdc */ 2081 <3 RK_PB0 1 &pcfg_pull_none>, 2082 /* mac_rxd1 */ 2083 <3 RK_PA7 1 &pcfg_pull_none>, 2084 /* mac_rxd0 */ 2085 <3 RK_PA6 1 &pcfg_pull_none>, 2086 /* mac_txd1 */ 2087 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2088 /* mac_txd0 */ 2089 <3 RK_PA4 1 &pcfg_pull_none_13ma>, 2090 /* mac_rxd3 */ 2091 <3 RK_PA3 1 &pcfg_pull_none>, 2092 /* mac_rxd2 */ 2093 <3 RK_PA2 1 &pcfg_pull_none>, 2094 /* mac_txd3 */ 2095 <3 RK_PA1 1 &pcfg_pull_none_13ma>, 2096 /* mac_txd2 */ 2097 <3 RK_PA0 1 &pcfg_pull_none_13ma>; 2098 }; 2099 2100 rmii_pins: rmii-pins { 2101 rockchip,pins = 2102 /* mac_mdio */ 2103 <3 RK_PB5 1 &pcfg_pull_none>, 2104 /* mac_txen */ 2105 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2106 /* mac_clk */ 2107 <3 RK_PB3 1 &pcfg_pull_none>, 2108 /* mac_rxer */ 2109 <3 RK_PB2 1 &pcfg_pull_none>, 2110 /* mac_rxdv */ 2111 <3 RK_PB1 1 &pcfg_pull_none>, 2112 /* mac_mdc */ 2113 <3 RK_PB0 1 &pcfg_pull_none>, 2114 /* mac_rxd1 */ 2115 <3 RK_PA7 1 &pcfg_pull_none>, 2116 /* mac_rxd0 */ 2117 <3 RK_PA6 1 &pcfg_pull_none>, 2118 /* mac_txd1 */ 2119 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2120 /* mac_txd0 */ 2121 <3 RK_PA4 1 &pcfg_pull_none_13ma>; 2122 }; 2123 }; 2124 2125 i2c0 { 2126 i2c0_xfer: i2c0-xfer { 2127 rockchip,pins = 2128 <1 RK_PB7 2 &pcfg_pull_none>, 2129 <1 RK_PC0 2 &pcfg_pull_none>; 2130 }; 2131 }; 2132 2133 i2c1 { 2134 i2c1_xfer: i2c1-xfer { 2135 rockchip,pins = 2136 <4 RK_PA2 1 &pcfg_pull_none>, 2137 <4 RK_PA1 1 &pcfg_pull_none>; 2138 }; 2139 }; 2140 2141 i2c2 { 2142 i2c2_xfer: i2c2-xfer { 2143 rockchip,pins = 2144 <2 RK_PA1 2 &pcfg_pull_none_12ma>, 2145 <2 RK_PA0 2 &pcfg_pull_none_12ma>; 2146 }; 2147 }; 2148 2149 i2c3 { 2150 i2c3_xfer: i2c3-xfer { 2151 rockchip,pins = 2152 <4 RK_PC1 1 &pcfg_pull_none>, 2153 <4 RK_PC0 1 &pcfg_pull_none>; 2154 }; 2155 }; 2156 2157 i2c4 { 2158 i2c4_xfer: i2c4-xfer { 2159 rockchip,pins = 2160 <1 RK_PB4 1 &pcfg_pull_none>, 2161 <1 RK_PB3 1 &pcfg_pull_none>; 2162 }; 2163 }; 2164 2165 i2c5 { 2166 i2c5_xfer: i2c5-xfer { 2167 rockchip,pins = 2168 <3 RK_PB3 2 &pcfg_pull_none>, 2169 <3 RK_PB2 2 &pcfg_pull_none>; 2170 }; 2171 }; 2172 2173 i2c6 { 2174 i2c6_xfer: i2c6-xfer { 2175 rockchip,pins = 2176 <2 RK_PB2 2 &pcfg_pull_none>, 2177 <2 RK_PB1 2 &pcfg_pull_none>; 2178 }; 2179 }; 2180 2181 i2c7 { 2182 i2c7_xfer: i2c7-xfer { 2183 rockchip,pins = 2184 <2 RK_PB0 2 &pcfg_pull_none>, 2185 <2 RK_PA7 2 &pcfg_pull_none>; 2186 }; 2187 }; 2188 2189 i2c8 { 2190 i2c8_xfer: i2c8-xfer { 2191 rockchip,pins = 2192 <1 RK_PC5 1 &pcfg_pull_none>, 2193 <1 RK_PC4 1 &pcfg_pull_none>; 2194 }; 2195 }; 2196 2197 i2s0 { 2198 i2s0_2ch_bus: i2s0-2ch-bus { 2199 rockchip,pins = 2200 <3 RK_PD0 1 &pcfg_pull_none>, 2201 <3 RK_PD1 1 &pcfg_pull_none>, 2202 <3 RK_PD2 1 &pcfg_pull_none>, 2203 <3 RK_PD3 1 &pcfg_pull_none>, 2204 <3 RK_PD7 1 &pcfg_pull_none>, 2205 <4 RK_PA0 1 &pcfg_pull_none>; 2206 }; 2207 2208 i2s0_8ch_bus: i2s0-8ch-bus { 2209 rockchip,pins = 2210 <3 RK_PD0 1 &pcfg_pull_none>, 2211 <3 RK_PD1 1 &pcfg_pull_none>, 2212 <3 RK_PD2 1 &pcfg_pull_none>, 2213 <3 RK_PD3 1 &pcfg_pull_none>, 2214 <3 RK_PD4 1 &pcfg_pull_none>, 2215 <3 RK_PD5 1 &pcfg_pull_none>, 2216 <3 RK_PD6 1 &pcfg_pull_none>, 2217 <3 RK_PD7 1 &pcfg_pull_none>, 2218 <4 RK_PA0 1 &pcfg_pull_none>; 2219 }; 2220 }; 2221 2222 i2s1 { 2223 i2s1_2ch_bus: i2s1-2ch-bus { 2224 rockchip,pins = 2225 <4 RK_PA3 1 &pcfg_pull_none>, 2226 <4 RK_PA4 1 &pcfg_pull_none>, 2227 <4 RK_PA5 1 &pcfg_pull_none>, 2228 <4 RK_PA6 1 &pcfg_pull_none>, 2229 <4 RK_PA7 1 &pcfg_pull_none>; 2230 }; 2231 }; 2232 2233 sdio0 { 2234 sdio0_bus1: sdio0-bus1 { 2235 rockchip,pins = 2236 <2 RK_PC4 1 &pcfg_pull_up>; 2237 }; 2238 2239 sdio0_bus4: sdio0-bus4 { 2240 rockchip,pins = 2241 <2 RK_PC4 1 &pcfg_pull_up>, 2242 <2 RK_PC5 1 &pcfg_pull_up>, 2243 <2 RK_PC6 1 &pcfg_pull_up>, 2244 <2 RK_PC7 1 &pcfg_pull_up>; 2245 }; 2246 2247 sdio0_cmd: sdio0-cmd { 2248 rockchip,pins = 2249 <2 RK_PD0 1 &pcfg_pull_up>; 2250 }; 2251 2252 sdio0_clk: sdio0-clk { 2253 rockchip,pins = 2254 <2 RK_PD1 1 &pcfg_pull_none>; 2255 }; 2256 2257 sdio0_cd: sdio0-cd { 2258 rockchip,pins = 2259 <2 RK_PD2 1 &pcfg_pull_up>; 2260 }; 2261 2262 sdio0_pwr: sdio0-pwr { 2263 rockchip,pins = 2264 <2 RK_PD3 1 &pcfg_pull_up>; 2265 }; 2266 2267 sdio0_bkpwr: sdio0-bkpwr { 2268 rockchip,pins = 2269 <2 RK_PD4 1 &pcfg_pull_up>; 2270 }; 2271 2272 sdio0_wp: sdio0-wp { 2273 rockchip,pins = 2274 <0 RK_PA3 1 &pcfg_pull_up>; 2275 }; 2276 2277 sdio0_int: sdio0-int { 2278 rockchip,pins = 2279 <0 RK_PA4 1 &pcfg_pull_up>; 2280 }; 2281 }; 2282 2283 sdmmc { 2284 sdmmc_bus1: sdmmc-bus1 { 2285 rockchip,pins = 2286 <4 RK_PB0 1 &pcfg_pull_up>; 2287 }; 2288 2289 sdmmc_bus4: sdmmc-bus4 { 2290 rockchip,pins = 2291 <4 RK_PB0 1 &pcfg_pull_up>, 2292 <4 RK_PB1 1 &pcfg_pull_up>, 2293 <4 RK_PB2 1 &pcfg_pull_up>, 2294 <4 RK_PB3 1 &pcfg_pull_up>; 2295 }; 2296 2297 sdmmc_clk: sdmmc-clk { 2298 rockchip,pins = 2299 <4 RK_PB4 1 &pcfg_pull_none>; 2300 }; 2301 2302 sdmmc_cmd: sdmmc-cmd { 2303 rockchip,pins = 2304 <4 RK_PB5 1 &pcfg_pull_up>; 2305 }; 2306 2307 sdmmc_cd: sdmmc-cd { 2308 rockchip,pins = 2309 <0 RK_PA7 1 &pcfg_pull_up>; 2310 }; 2311 2312 sdmmc_wp: sdmmc-wp { 2313 rockchip,pins = 2314 <0 RK_PB0 1 &pcfg_pull_up>; 2315 }; 2316 }; 2317 2318 sleep { 2319 ap_pwroff: ap-pwroff { 2320 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>; 2321 }; 2322 2323 ddrio_pwroff: ddrio-pwroff { 2324 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; 2325 }; 2326 }; 2327 2328 spdif { 2329 spdif_bus: spdif-bus { 2330 rockchip,pins = 2331 <4 RK_PC5 1 &pcfg_pull_none>; 2332 }; 2333 2334 spdif_bus_1: spdif-bus-1 { 2335 rockchip,pins = 2336 <3 RK_PC0 3 &pcfg_pull_none>; 2337 }; 2338 }; 2339 2340 spi0 { 2341 spi0_clk: spi0-clk { 2342 rockchip,pins = 2343 <3 RK_PA6 2 &pcfg_pull_up>; 2344 }; 2345 spi0_cs0: spi0-cs0 { 2346 rockchip,pins = 2347 <3 RK_PA7 2 &pcfg_pull_up>; 2348 }; 2349 spi0_cs1: spi0-cs1 { 2350 rockchip,pins = 2351 <3 RK_PB0 2 &pcfg_pull_up>; 2352 }; 2353 spi0_tx: spi0-tx { 2354 rockchip,pins = 2355 <3 RK_PA5 2 &pcfg_pull_up>; 2356 }; 2357 spi0_rx: spi0-rx { 2358 rockchip,pins = 2359 <3 RK_PA4 2 &pcfg_pull_up>; 2360 }; 2361 }; 2362 2363 spi1 { 2364 spi1_clk: spi1-clk { 2365 rockchip,pins = 2366 <1 RK_PB1 2 &pcfg_pull_up>; 2367 }; 2368 spi1_cs0: spi1-cs0 { 2369 rockchip,pins = 2370 <1 RK_PB2 2 &pcfg_pull_up>; 2371 }; 2372 spi1_rx: spi1-rx { 2373 rockchip,pins = 2374 <1 RK_PA7 2 &pcfg_pull_up>; 2375 }; 2376 spi1_tx: spi1-tx { 2377 rockchip,pins = 2378 <1 RK_PB0 2 &pcfg_pull_up>; 2379 }; 2380 }; 2381 2382 spi2 { 2383 spi2_clk: spi2-clk { 2384 rockchip,pins = 2385 <2 RK_PB3 1 &pcfg_pull_up>; 2386 }; 2387 spi2_cs0: spi2-cs0 { 2388 rockchip,pins = 2389 <2 RK_PB4 1 &pcfg_pull_up>; 2390 }; 2391 spi2_rx: spi2-rx { 2392 rockchip,pins = 2393 <2 RK_PB1 1 &pcfg_pull_up>; 2394 }; 2395 spi2_tx: spi2-tx { 2396 rockchip,pins = 2397 <2 RK_PB2 1 &pcfg_pull_up>; 2398 }; 2399 }; 2400 2401 spi3 { 2402 spi3_clk: spi3-clk { 2403 rockchip,pins = 2404 <1 RK_PC1 1 &pcfg_pull_up>; 2405 }; 2406 spi3_cs0: spi3-cs0 { 2407 rockchip,pins = 2408 <1 RK_PC2 1 &pcfg_pull_up>; 2409 }; 2410 spi3_rx: spi3-rx { 2411 rockchip,pins = 2412 <1 RK_PB7 1 &pcfg_pull_up>; 2413 }; 2414 spi3_tx: spi3-tx { 2415 rockchip,pins = 2416 <1 RK_PC0 1 &pcfg_pull_up>; 2417 }; 2418 }; 2419 2420 spi4 { 2421 spi4_clk: spi4-clk { 2422 rockchip,pins = 2423 <3 RK_PA2 2 &pcfg_pull_up>; 2424 }; 2425 spi4_cs0: spi4-cs0 { 2426 rockchip,pins = 2427 <3 RK_PA3 2 &pcfg_pull_up>; 2428 }; 2429 spi4_rx: spi4-rx { 2430 rockchip,pins = 2431 <3 RK_PA0 2 &pcfg_pull_up>; 2432 }; 2433 spi4_tx: spi4-tx { 2434 rockchip,pins = 2435 <3 RK_PA1 2 &pcfg_pull_up>; 2436 }; 2437 }; 2438 2439 spi5 { 2440 spi5_clk: spi5-clk { 2441 rockchip,pins = 2442 <2 RK_PC6 2 &pcfg_pull_up>; 2443 }; 2444 spi5_cs0: spi5-cs0 { 2445 rockchip,pins = 2446 <2 RK_PC7 2 &pcfg_pull_up>; 2447 }; 2448 spi5_rx: spi5-rx { 2449 rockchip,pins = 2450 <2 RK_PC4 2 &pcfg_pull_up>; 2451 }; 2452 spi5_tx: spi5-tx { 2453 rockchip,pins = 2454 <2 RK_PC5 2 &pcfg_pull_up>; 2455 }; 2456 }; 2457 2458 testclk { 2459 test_clkout0: test-clkout0 { 2460 rockchip,pins = 2461 <0 RK_PA0 1 &pcfg_pull_none>; 2462 }; 2463 2464 test_clkout1: test-clkout1 { 2465 rockchip,pins = 2466 <2 RK_PD1 2 &pcfg_pull_none>; 2467 }; 2468 2469 test_clkout2: test-clkout2 { 2470 rockchip,pins = 2471 <0 RK_PB0 3 &pcfg_pull_none>; 2472 }; 2473 }; 2474 2475 tsadc { 2476 otp_gpio: otp-gpio { 2477 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 2478 }; 2479 2480 otp_out: otp-out { 2481 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; 2482 }; 2483 }; 2484 2485 uart0 { 2486 uart0_xfer: uart0-xfer { 2487 rockchip,pins = 2488 <2 RK_PC0 1 &pcfg_pull_up>, 2489 <2 RK_PC1 1 &pcfg_pull_none>; 2490 }; 2491 2492 uart0_cts: uart0-cts { 2493 rockchip,pins = 2494 <2 RK_PC2 1 &pcfg_pull_none>; 2495 }; 2496 2497 uart0_rts: uart0-rts { 2498 rockchip,pins = 2499 <2 RK_PC3 1 &pcfg_pull_none>; 2500 }; 2501 }; 2502 2503 uart1 { 2504 uart1_xfer: uart1-xfer { 2505 rockchip,pins = 2506 <3 RK_PB4 2 &pcfg_pull_up>, 2507 <3 RK_PB5 2 &pcfg_pull_none>; 2508 }; 2509 }; 2510 2511 uart2a { 2512 uart2a_xfer: uart2a-xfer { 2513 rockchip,pins = 2514 <4 RK_PB0 2 &pcfg_pull_up>, 2515 <4 RK_PB1 2 &pcfg_pull_none>; 2516 }; 2517 }; 2518 2519 uart2b { 2520 uart2b_xfer: uart2b-xfer { 2521 rockchip,pins = 2522 <4 RK_PC0 2 &pcfg_pull_up>, 2523 <4 RK_PC1 2 &pcfg_pull_none>; 2524 }; 2525 }; 2526 2527 uart2c { 2528 uart2c_xfer: uart2c-xfer { 2529 rockchip,pins = 2530 <4 RK_PC3 1 &pcfg_pull_up>, 2531 <4 RK_PC4 1 &pcfg_pull_none>; 2532 }; 2533 }; 2534 2535 uart3 { 2536 uart3_xfer: uart3-xfer { 2537 rockchip,pins = 2538 <3 RK_PB6 2 &pcfg_pull_up>, 2539 <3 RK_PB7 2 &pcfg_pull_none>; 2540 }; 2541 2542 uart3_cts: uart3-cts { 2543 rockchip,pins = 2544 <3 RK_PC0 2 &pcfg_pull_none>; 2545 }; 2546 2547 uart3_rts: uart3-rts { 2548 rockchip,pins = 2549 <3 RK_PC1 2 &pcfg_pull_none>; 2550 }; 2551 }; 2552 2553 uart4 { 2554 uart4_xfer: uart4-xfer { 2555 rockchip,pins = 2556 <1 RK_PA7 1 &pcfg_pull_up>, 2557 <1 RK_PB0 1 &pcfg_pull_none>; 2558 }; 2559 }; 2560 2561 uarthdcp { 2562 uarthdcp_xfer: uarthdcp-xfer { 2563 rockchip,pins = 2564 <4 RK_PC5 2 &pcfg_pull_up>, 2565 <4 RK_PC6 2 &pcfg_pull_none>; 2566 }; 2567 }; 2568 2569 pwm0 { 2570 pwm0_pin: pwm0-pin { 2571 rockchip,pins = 2572 <4 RK_PC2 1 &pcfg_pull_none>; 2573 }; 2574 2575 pwm0_pin_pull_down: pwm0-pin-pull-down { 2576 rockchip,pins = 2577 <4 RK_PC2 1 &pcfg_pull_down>; 2578 }; 2579 2580 vop0_pwm_pin: vop0-pwm-pin { 2581 rockchip,pins = 2582 <4 RK_PC2 2 &pcfg_pull_none>; 2583 }; 2584 2585 vop1_pwm_pin: vop1-pwm-pin { 2586 rockchip,pins = 2587 <4 RK_PC2 3 &pcfg_pull_none>; 2588 }; 2589 }; 2590 2591 pwm1 { 2592 pwm1_pin: pwm1-pin { 2593 rockchip,pins = 2594 <4 RK_PC6 1 &pcfg_pull_none>; 2595 }; 2596 2597 pwm1_pin_pull_down: pwm1-pin-pull-down { 2598 rockchip,pins = 2599 <4 RK_PC6 1 &pcfg_pull_down>; 2600 }; 2601 }; 2602 2603 pwm2 { 2604 pwm2_pin: pwm2-pin { 2605 rockchip,pins = 2606 <1 RK_PC3 1 &pcfg_pull_none>; 2607 }; 2608 2609 pwm2_pin_pull_down: pwm2-pin-pull-down { 2610 rockchip,pins = 2611 <1 RK_PC3 1 &pcfg_pull_down>; 2612 }; 2613 }; 2614 2615 pwm3a { 2616 pwm3a_pin: pwm3a-pin { 2617 rockchip,pins = 2618 <0 RK_PA6 1 &pcfg_pull_none>; 2619 }; 2620 }; 2621 2622 pwm3b { 2623 pwm3b_pin: pwm3b-pin { 2624 rockchip,pins = 2625 <1 RK_PB6 1 &pcfg_pull_none>; 2626 }; 2627 }; 2628 2629 hdmi { 2630 hdmi_i2c_xfer: hdmi-i2c-xfer { 2631 rockchip,pins = 2632 <4 RK_PC1 3 &pcfg_pull_none>, 2633 <4 RK_PC0 3 &pcfg_pull_none>; 2634 }; 2635 2636 hdmi_cec: hdmi-cec { 2637 rockchip,pins = 2638 <4 RK_PC7 1 &pcfg_pull_none>; 2639 }; 2640 }; 2641 2642 pcie { 2643 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2644 rockchip,pins = 2645 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2646 }; 2647 2648 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2649 rockchip,pins = 2650 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2651 }; 2652 }; 2653 2654 }; 2655}; 2656