1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3399-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3399-power.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "rockchip,rk3399"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &gmac; 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 i2c6 = &i2c6; 30 i2c7 = &i2c7; 31 i2c8 = &i2c8; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 cpu-map { 44 cluster0 { 45 core0 { 46 cpu = <&cpu_l0>; 47 }; 48 core1 { 49 cpu = <&cpu_l1>; 50 }; 51 core2 { 52 cpu = <&cpu_l2>; 53 }; 54 core3 { 55 cpu = <&cpu_l3>; 56 }; 57 }; 58 59 cluster1 { 60 core0 { 61 cpu = <&cpu_b0>; 62 }; 63 core1 { 64 cpu = <&cpu_b1>; 65 }; 66 }; 67 }; 68 69 cpu_l0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <0x0 0x0>; 73 enable-method = "psci"; 74 capacity-dmips-mhz = <485>; 75 clocks = <&cru ARMCLKL>; 76 #cooling-cells = <2>; /* min followed by max */ 77 dynamic-power-coefficient = <100>; 78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 79 }; 80 81 cpu_l1: cpu@1 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x0 0x1>; 85 enable-method = "psci"; 86 capacity-dmips-mhz = <485>; 87 clocks = <&cru ARMCLKL>; 88 #cooling-cells = <2>; /* min followed by max */ 89 dynamic-power-coefficient = <100>; 90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 91 }; 92 93 cpu_l2: cpu@2 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a53"; 96 reg = <0x0 0x2>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <485>; 99 clocks = <&cru ARMCLKL>; 100 #cooling-cells = <2>; /* min followed by max */ 101 dynamic-power-coefficient = <100>; 102 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 103 }; 104 105 cpu_l3: cpu@3 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53"; 108 reg = <0x0 0x3>; 109 enable-method = "psci"; 110 capacity-dmips-mhz = <485>; 111 clocks = <&cru ARMCLKL>; 112 #cooling-cells = <2>; /* min followed by max */ 113 dynamic-power-coefficient = <100>; 114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 115 }; 116 117 cpu_b0: cpu@100 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a72"; 120 reg = <0x0 0x100>; 121 enable-method = "psci"; 122 capacity-dmips-mhz = <1024>; 123 clocks = <&cru ARMCLKB>; 124 #cooling-cells = <2>; /* min followed by max */ 125 dynamic-power-coefficient = <436>; 126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 127 }; 128 129 cpu_b1: cpu@101 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a72"; 132 reg = <0x0 0x101>; 133 enable-method = "psci"; 134 capacity-dmips-mhz = <1024>; 135 clocks = <&cru ARMCLKB>; 136 #cooling-cells = <2>; /* min followed by max */ 137 dynamic-power-coefficient = <436>; 138 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 139 }; 140 141 idle-states { 142 entry-method = "psci"; 143 144 CPU_SLEEP: cpu-sleep { 145 compatible = "arm,idle-state"; 146 local-timer-stop; 147 arm,psci-suspend-param = <0x0010000>; 148 entry-latency-us = <120>; 149 exit-latency-us = <250>; 150 min-residency-us = <900>; 151 }; 152 153 CLUSTER_SLEEP: cluster-sleep { 154 compatible = "arm,idle-state"; 155 local-timer-stop; 156 arm,psci-suspend-param = <0x1010000>; 157 entry-latency-us = <400>; 158 exit-latency-us = <500>; 159 min-residency-us = <2000>; 160 }; 161 }; 162 }; 163 164 display-subsystem { 165 compatible = "rockchip,display-subsystem"; 166 ports = <&vopl_out>, <&vopb_out>; 167 }; 168 169 pmu_a53 { 170 compatible = "arm,cortex-a53-pmu"; 171 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 172 }; 173 174 pmu_a72 { 175 compatible = "arm,cortex-a72-pmu"; 176 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 177 }; 178 179 psci { 180 compatible = "arm,psci-1.0"; 181 method = "smc"; 182 }; 183 184 timer { 185 compatible = "arm,armv8-timer"; 186 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 187 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 188 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 189 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 190 arm,no-tick-in-suspend; 191 }; 192 193 xin24m: xin24m { 194 compatible = "fixed-clock"; 195 clock-frequency = <24000000>; 196 clock-output-names = "xin24m"; 197 #clock-cells = <0>; 198 }; 199 200 amba { 201 compatible = "simple-bus"; 202 #address-cells = <2>; 203 #size-cells = <2>; 204 ranges; 205 206 dmac_bus: dma-controller@ff6d0000 { 207 compatible = "arm,pl330", "arm,primecell"; 208 reg = <0x0 0xff6d0000 0x0 0x4000>; 209 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 210 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 211 #dma-cells = <1>; 212 clocks = <&cru ACLK_DMAC0_PERILP>; 213 clock-names = "apb_pclk"; 214 }; 215 216 dmac_peri: dma-controller@ff6e0000 { 217 compatible = "arm,pl330", "arm,primecell"; 218 reg = <0x0 0xff6e0000 0x0 0x4000>; 219 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 220 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 221 #dma-cells = <1>; 222 clocks = <&cru ACLK_DMAC1_PERILP>; 223 clock-names = "apb_pclk"; 224 }; 225 }; 226 227 pcie0: pcie@f8000000 { 228 compatible = "rockchip,rk3399-pcie"; 229 reg = <0x0 0xf8000000 0x0 0x2000000>, 230 <0x0 0xfd000000 0x0 0x1000000>; 231 reg-names = "axi-base", "apb-base"; 232 #address-cells = <3>; 233 #size-cells = <2>; 234 #interrupt-cells = <1>; 235 aspm-no-l0s; 236 bus-range = <0x0 0x1f>; 237 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 238 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 239 clock-names = "aclk", "aclk-perf", 240 "hclk", "pm"; 241 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 242 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 243 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 244 interrupt-names = "sys", "legacy", "client"; 245 interrupt-map-mask = <0 0 0 7>; 246 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 247 <0 0 0 2 &pcie0_intc 1>, 248 <0 0 0 3 &pcie0_intc 2>, 249 <0 0 0 4 &pcie0_intc 3>; 250 linux,pci-domain = <0>; 251 max-link-speed = <1>; 252 msi-map = <0x0 &its 0x0 0x1000>; 253 phys = <&pcie_phy 0>, <&pcie_phy 1>, 254 <&pcie_phy 2>, <&pcie_phy 3>; 255 phy-names = "pcie-phy-0", "pcie-phy-1", 256 "pcie-phy-2", "pcie-phy-3"; 257 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000 258 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; 259 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 260 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 261 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 262 <&cru SRST_A_PCIE>; 263 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 264 "pm", "pclk", "aclk"; 265 status = "disabled"; 266 267 pcie0_intc: interrupt-controller { 268 interrupt-controller; 269 #address-cells = <0>; 270 #interrupt-cells = <1>; 271 }; 272 }; 273 274 gmac: ethernet@fe300000 { 275 compatible = "rockchip,rk3399-gmac"; 276 reg = <0x0 0xfe300000 0x0 0x10000>; 277 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 278 interrupt-names = "macirq"; 279 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 280 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 281 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 282 <&cru PCLK_GMAC>; 283 clock-names = "stmmaceth", "mac_clk_rx", 284 "mac_clk_tx", "clk_mac_ref", 285 "clk_mac_refout", "aclk_mac", 286 "pclk_mac"; 287 power-domains = <&power RK3399_PD_GMAC>; 288 resets = <&cru SRST_A_GMAC>; 289 reset-names = "stmmaceth"; 290 rockchip,grf = <&grf>; 291 status = "disabled"; 292 }; 293 294 sdio0: mmc@fe310000 { 295 compatible = "rockchip,rk3399-dw-mshc", 296 "rockchip,rk3288-dw-mshc"; 297 reg = <0x0 0xfe310000 0x0 0x4000>; 298 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 299 max-frequency = <150000000>; 300 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 301 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 302 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 303 fifo-depth = <0x100>; 304 power-domains = <&power RK3399_PD_SDIOAUDIO>; 305 resets = <&cru SRST_SDIO0>; 306 reset-names = "reset"; 307 status = "disabled"; 308 }; 309 310 sdmmc: mmc@fe320000 { 311 compatible = "rockchip,rk3399-dw-mshc", 312 "rockchip,rk3288-dw-mshc"; 313 reg = <0x0 0xfe320000 0x0 0x4000>; 314 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 315 max-frequency = <150000000>; 316 assigned-clocks = <&cru HCLK_SD>; 317 assigned-clock-rates = <200000000>; 318 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 319 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 320 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 321 fifo-depth = <0x100>; 322 power-domains = <&power RK3399_PD_SD>; 323 resets = <&cru SRST_SDMMC>; 324 reset-names = "reset"; 325 status = "disabled"; 326 }; 327 328 sdhci: sdhci@fe330000 { 329 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 330 reg = <0x0 0xfe330000 0x0 0x10000>; 331 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 332 arasan,soc-ctl-syscon = <&grf>; 333 assigned-clocks = <&cru SCLK_EMMC>; 334 assigned-clock-rates = <200000000>; 335 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 336 clock-names = "clk_xin", "clk_ahb"; 337 clock-output-names = "emmc_cardclock"; 338 #clock-cells = <0>; 339 phys = <&emmc_phy>; 340 phy-names = "phy_arasan"; 341 power-domains = <&power RK3399_PD_EMMC>; 342 disable-cqe-dcmd; 343 status = "disabled"; 344 }; 345 346 usb_host0_ehci: usb@fe380000 { 347 compatible = "generic-ehci"; 348 reg = <0x0 0xfe380000 0x0 0x20000>; 349 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 350 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 351 <&u2phy0>; 352 clock-names = "usbhost", "arbiter", 353 "utmi"; 354 phys = <&u2phy0_host>; 355 phy-names = "usb"; 356 status = "disabled"; 357 }; 358 359 usb_host0_ohci: usb@fe3a0000 { 360 compatible = "generic-ohci"; 361 reg = <0x0 0xfe3a0000 0x0 0x20000>; 362 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 363 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 364 <&u2phy0>; 365 clock-names = "usbhost", "arbiter", 366 "utmi"; 367 phys = <&u2phy0_host>; 368 phy-names = "usb"; 369 status = "disabled"; 370 }; 371 372 usb_host1_ehci: usb@fe3c0000 { 373 compatible = "generic-ehci"; 374 reg = <0x0 0xfe3c0000 0x0 0x20000>; 375 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 376 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 377 <&u2phy1>; 378 clock-names = "usbhost", "arbiter", 379 "utmi"; 380 phys = <&u2phy1_host>; 381 phy-names = "usb"; 382 status = "disabled"; 383 }; 384 385 usb_host1_ohci: usb@fe3e0000 { 386 compatible = "generic-ohci"; 387 reg = <0x0 0xfe3e0000 0x0 0x20000>; 388 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 389 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 390 <&u2phy1>; 391 clock-names = "usbhost", "arbiter", 392 "utmi"; 393 phys = <&u2phy1_host>; 394 phy-names = "usb"; 395 status = "disabled"; 396 }; 397 398 usbdrd3_0: usb@fe800000 { 399 compatible = "rockchip,rk3399-dwc3"; 400 #address-cells = <2>; 401 #size-cells = <2>; 402 ranges; 403 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 404 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 405 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 406 clock-names = "ref_clk", "suspend_clk", 407 "bus_clk", "aclk_usb3_rksoc_axi_perf", 408 "aclk_usb3", "grf_clk"; 409 resets = <&cru SRST_A_USB3_OTG0>; 410 reset-names = "usb3-otg"; 411 status = "disabled"; 412 413 usbdrd_dwc3_0: dwc3 { 414 compatible = "snps,dwc3"; 415 reg = <0x0 0xfe800000 0x0 0x100000>; 416 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 417 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, 418 <&cru SCLK_USB3OTG0_SUSPEND>; 419 clock-names = "ref", "bus_early", "suspend"; 420 dr_mode = "otg"; 421 phys = <&u2phy0_otg>, <&tcphy0_usb3>; 422 phy-names = "usb2-phy", "usb3-phy"; 423 phy_type = "utmi_wide"; 424 snps,dis_enblslpm_quirk; 425 snps,dis-u2-freeclk-exists-quirk; 426 snps,dis_u2_susphy_quirk; 427 snps,dis-del-phy-power-chg-quirk; 428 snps,dis-tx-ipgap-linecheck-quirk; 429 power-domains = <&power RK3399_PD_USB3>; 430 status = "disabled"; 431 }; 432 }; 433 434 usbdrd3_1: usb@fe900000 { 435 compatible = "rockchip,rk3399-dwc3"; 436 #address-cells = <2>; 437 #size-cells = <2>; 438 ranges; 439 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, 440 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 441 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 442 clock-names = "ref_clk", "suspend_clk", 443 "bus_clk", "aclk_usb3_rksoc_axi_perf", 444 "aclk_usb3", "grf_clk"; 445 resets = <&cru SRST_A_USB3_OTG1>; 446 reset-names = "usb3-otg"; 447 status = "disabled"; 448 449 usbdrd_dwc3_1: dwc3 { 450 compatible = "snps,dwc3"; 451 reg = <0x0 0xfe900000 0x0 0x100000>; 452 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 453 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>, 454 <&cru SCLK_USB3OTG1_SUSPEND>; 455 clock-names = "ref", "bus_early", "suspend"; 456 dr_mode = "otg"; 457 phys = <&u2phy1_otg>, <&tcphy1_usb3>; 458 phy-names = "usb2-phy", "usb3-phy"; 459 phy_type = "utmi_wide"; 460 snps,dis_enblslpm_quirk; 461 snps,dis-u2-freeclk-exists-quirk; 462 snps,dis_u2_susphy_quirk; 463 snps,dis-del-phy-power-chg-quirk; 464 snps,dis-tx-ipgap-linecheck-quirk; 465 power-domains = <&power RK3399_PD_USB3>; 466 status = "disabled"; 467 }; 468 }; 469 470 cdn_dp: dp@fec00000 { 471 compatible = "rockchip,rk3399-cdn-dp"; 472 reg = <0x0 0xfec00000 0x0 0x100000>; 473 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 474 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>; 475 assigned-clock-rates = <100000000>, <200000000>; 476 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, 477 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; 478 clock-names = "core-clk", "pclk", "spdif", "grf"; 479 phys = <&tcphy0_dp>, <&tcphy1_dp>; 480 power-domains = <&power RK3399_PD_HDCP>; 481 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, 482 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; 483 reset-names = "spdif", "dptx", "apb", "core"; 484 rockchip,grf = <&grf>; 485 #sound-dai-cells = <1>; 486 status = "disabled"; 487 488 ports { 489 dp_in: port { 490 #address-cells = <1>; 491 #size-cells = <0>; 492 493 dp_in_vopb: endpoint@0 { 494 reg = <0>; 495 remote-endpoint = <&vopb_out_dp>; 496 }; 497 498 dp_in_vopl: endpoint@1 { 499 reg = <1>; 500 remote-endpoint = <&vopl_out_dp>; 501 }; 502 }; 503 }; 504 }; 505 506 gic: interrupt-controller@fee00000 { 507 compatible = "arm,gic-v3"; 508 #interrupt-cells = <4>; 509 #address-cells = <2>; 510 #size-cells = <2>; 511 ranges; 512 interrupt-controller; 513 514 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 515 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 516 <0x0 0xfff00000 0 0x10000>, /* GICC */ 517 <0x0 0xfff10000 0 0x10000>, /* GICH */ 518 <0x0 0xfff20000 0 0x10000>; /* GICV */ 519 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 520 its: interrupt-controller@fee20000 { 521 compatible = "arm,gic-v3-its"; 522 msi-controller; 523 #msi-cells = <1>; 524 reg = <0x0 0xfee20000 0x0 0x20000>; 525 }; 526 527 ppi-partitions { 528 ppi_cluster0: interrupt-partition-0 { 529 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 530 }; 531 532 ppi_cluster1: interrupt-partition-1 { 533 affinity = <&cpu_b0 &cpu_b1>; 534 }; 535 }; 536 }; 537 538 saradc: saradc@ff100000 { 539 compatible = "rockchip,rk3399-saradc"; 540 reg = <0x0 0xff100000 0x0 0x100>; 541 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 542 #io-channel-cells = <1>; 543 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 544 clock-names = "saradc", "apb_pclk"; 545 resets = <&cru SRST_P_SARADC>; 546 reset-names = "saradc-apb"; 547 status = "disabled"; 548 }; 549 550 i2c1: i2c@ff110000 { 551 compatible = "rockchip,rk3399-i2c"; 552 reg = <0x0 0xff110000 0x0 0x1000>; 553 assigned-clocks = <&cru SCLK_I2C1>; 554 assigned-clock-rates = <200000000>; 555 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 556 clock-names = "i2c", "pclk"; 557 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 558 pinctrl-names = "default"; 559 pinctrl-0 = <&i2c1_xfer>; 560 #address-cells = <1>; 561 #size-cells = <0>; 562 status = "disabled"; 563 }; 564 565 i2c2: i2c@ff120000 { 566 compatible = "rockchip,rk3399-i2c"; 567 reg = <0x0 0xff120000 0x0 0x1000>; 568 assigned-clocks = <&cru SCLK_I2C2>; 569 assigned-clock-rates = <200000000>; 570 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 571 clock-names = "i2c", "pclk"; 572 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 573 pinctrl-names = "default"; 574 pinctrl-0 = <&i2c2_xfer>; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 status = "disabled"; 578 }; 579 580 i2c3: i2c@ff130000 { 581 compatible = "rockchip,rk3399-i2c"; 582 reg = <0x0 0xff130000 0x0 0x1000>; 583 assigned-clocks = <&cru SCLK_I2C3>; 584 assigned-clock-rates = <200000000>; 585 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 586 clock-names = "i2c", "pclk"; 587 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 588 pinctrl-names = "default"; 589 pinctrl-0 = <&i2c3_xfer>; 590 #address-cells = <1>; 591 #size-cells = <0>; 592 status = "disabled"; 593 }; 594 595 i2c5: i2c@ff140000 { 596 compatible = "rockchip,rk3399-i2c"; 597 reg = <0x0 0xff140000 0x0 0x1000>; 598 assigned-clocks = <&cru SCLK_I2C5>; 599 assigned-clock-rates = <200000000>; 600 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 601 clock-names = "i2c", "pclk"; 602 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 603 pinctrl-names = "default"; 604 pinctrl-0 = <&i2c5_xfer>; 605 #address-cells = <1>; 606 #size-cells = <0>; 607 status = "disabled"; 608 }; 609 610 i2c6: i2c@ff150000 { 611 compatible = "rockchip,rk3399-i2c"; 612 reg = <0x0 0xff150000 0x0 0x1000>; 613 assigned-clocks = <&cru SCLK_I2C6>; 614 assigned-clock-rates = <200000000>; 615 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 616 clock-names = "i2c", "pclk"; 617 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 618 pinctrl-names = "default"; 619 pinctrl-0 = <&i2c6_xfer>; 620 #address-cells = <1>; 621 #size-cells = <0>; 622 status = "disabled"; 623 }; 624 625 i2c7: i2c@ff160000 { 626 compatible = "rockchip,rk3399-i2c"; 627 reg = <0x0 0xff160000 0x0 0x1000>; 628 assigned-clocks = <&cru SCLK_I2C7>; 629 assigned-clock-rates = <200000000>; 630 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 631 clock-names = "i2c", "pclk"; 632 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 633 pinctrl-names = "default"; 634 pinctrl-0 = <&i2c7_xfer>; 635 #address-cells = <1>; 636 #size-cells = <0>; 637 status = "disabled"; 638 }; 639 640 uart0: serial@ff180000 { 641 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 642 reg = <0x0 0xff180000 0x0 0x100>; 643 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 644 clock-names = "baudclk", "apb_pclk"; 645 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 646 reg-shift = <2>; 647 reg-io-width = <4>; 648 pinctrl-names = "default"; 649 pinctrl-0 = <&uart0_xfer>; 650 status = "disabled"; 651 }; 652 653 uart1: serial@ff190000 { 654 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 655 reg = <0x0 0xff190000 0x0 0x100>; 656 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 657 clock-names = "baudclk", "apb_pclk"; 658 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 659 reg-shift = <2>; 660 reg-io-width = <4>; 661 pinctrl-names = "default"; 662 pinctrl-0 = <&uart1_xfer>; 663 status = "disabled"; 664 }; 665 666 uart2: serial@ff1a0000 { 667 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 668 reg = <0x0 0xff1a0000 0x0 0x100>; 669 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 670 clock-names = "baudclk", "apb_pclk"; 671 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 672 reg-shift = <2>; 673 reg-io-width = <4>; 674 pinctrl-names = "default"; 675 pinctrl-0 = <&uart2c_xfer>; 676 status = "disabled"; 677 }; 678 679 uart3: serial@ff1b0000 { 680 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 681 reg = <0x0 0xff1b0000 0x0 0x100>; 682 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 683 clock-names = "baudclk", "apb_pclk"; 684 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 685 reg-shift = <2>; 686 reg-io-width = <4>; 687 pinctrl-names = "default"; 688 pinctrl-0 = <&uart3_xfer>; 689 status = "disabled"; 690 }; 691 692 spi0: spi@ff1c0000 { 693 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 694 reg = <0x0 0xff1c0000 0x0 0x1000>; 695 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 696 clock-names = "spiclk", "apb_pclk"; 697 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 698 dmas = <&dmac_peri 10>, <&dmac_peri 11>; 699 dma-names = "tx", "rx"; 700 pinctrl-names = "default"; 701 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 702 #address-cells = <1>; 703 #size-cells = <0>; 704 status = "disabled"; 705 }; 706 707 spi1: spi@ff1d0000 { 708 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 709 reg = <0x0 0xff1d0000 0x0 0x1000>; 710 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 711 clock-names = "spiclk", "apb_pclk"; 712 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 713 dmas = <&dmac_peri 12>, <&dmac_peri 13>; 714 dma-names = "tx", "rx"; 715 pinctrl-names = "default"; 716 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 717 #address-cells = <1>; 718 #size-cells = <0>; 719 status = "disabled"; 720 }; 721 722 spi2: spi@ff1e0000 { 723 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 724 reg = <0x0 0xff1e0000 0x0 0x1000>; 725 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 726 clock-names = "spiclk", "apb_pclk"; 727 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 728 dmas = <&dmac_peri 14>, <&dmac_peri 15>; 729 dma-names = "tx", "rx"; 730 pinctrl-names = "default"; 731 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 732 #address-cells = <1>; 733 #size-cells = <0>; 734 status = "disabled"; 735 }; 736 737 spi4: spi@ff1f0000 { 738 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 739 reg = <0x0 0xff1f0000 0x0 0x1000>; 740 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 741 clock-names = "spiclk", "apb_pclk"; 742 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 743 dmas = <&dmac_peri 18>, <&dmac_peri 19>; 744 dma-names = "tx", "rx"; 745 pinctrl-names = "default"; 746 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 747 #address-cells = <1>; 748 #size-cells = <0>; 749 status = "disabled"; 750 }; 751 752 spi5: spi@ff200000 { 753 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 754 reg = <0x0 0xff200000 0x0 0x1000>; 755 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 756 clock-names = "spiclk", "apb_pclk"; 757 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 758 dmas = <&dmac_bus 8>, <&dmac_bus 9>; 759 dma-names = "tx", "rx"; 760 pinctrl-names = "default"; 761 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 762 power-domains = <&power RK3399_PD_SDIOAUDIO>; 763 #address-cells = <1>; 764 #size-cells = <0>; 765 status = "disabled"; 766 }; 767 768 thermal_zones: thermal-zones { 769 cpu_thermal: cpu { 770 polling-delay-passive = <100>; 771 polling-delay = <1000>; 772 773 thermal-sensors = <&tsadc 0>; 774 775 trips { 776 cpu_alert0: cpu_alert0 { 777 temperature = <70000>; 778 hysteresis = <2000>; 779 type = "passive"; 780 }; 781 cpu_alert1: cpu_alert1 { 782 temperature = <75000>; 783 hysteresis = <2000>; 784 type = "passive"; 785 }; 786 cpu_crit: cpu_crit { 787 temperature = <95000>; 788 hysteresis = <2000>; 789 type = "critical"; 790 }; 791 }; 792 793 cooling-maps { 794 map0 { 795 trip = <&cpu_alert0>; 796 cooling-device = 797 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 798 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 799 }; 800 map1 { 801 trip = <&cpu_alert1>; 802 cooling-device = 803 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 804 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 805 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 806 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 807 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 808 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 809 }; 810 }; 811 }; 812 813 gpu_thermal: gpu { 814 polling-delay-passive = <100>; 815 polling-delay = <1000>; 816 817 thermal-sensors = <&tsadc 1>; 818 819 trips { 820 gpu_alert0: gpu_alert0 { 821 temperature = <75000>; 822 hysteresis = <2000>; 823 type = "passive"; 824 }; 825 gpu_crit: gpu_crit { 826 temperature = <95000>; 827 hysteresis = <2000>; 828 type = "critical"; 829 }; 830 }; 831 832 cooling-maps { 833 map0 { 834 trip = <&gpu_alert0>; 835 cooling-device = 836 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 837 }; 838 }; 839 }; 840 }; 841 842 tsadc: tsadc@ff260000 { 843 compatible = "rockchip,rk3399-tsadc"; 844 reg = <0x0 0xff260000 0x0 0x100>; 845 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 846 assigned-clocks = <&cru SCLK_TSADC>; 847 assigned-clock-rates = <750000>; 848 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 849 clock-names = "tsadc", "apb_pclk"; 850 resets = <&cru SRST_TSADC>; 851 reset-names = "tsadc-apb"; 852 rockchip,grf = <&grf>; 853 rockchip,hw-tshut-temp = <95000>; 854 pinctrl-names = "init", "default", "sleep"; 855 pinctrl-0 = <&otp_gpio>; 856 pinctrl-1 = <&otp_out>; 857 pinctrl-2 = <&otp_gpio>; 858 #thermal-sensor-cells = <1>; 859 status = "disabled"; 860 }; 861 862 qos_emmc: qos@ffa58000 { 863 compatible = "syscon"; 864 reg = <0x0 0xffa58000 0x0 0x20>; 865 }; 866 867 qos_gmac: qos@ffa5c000 { 868 compatible = "syscon"; 869 reg = <0x0 0xffa5c000 0x0 0x20>; 870 }; 871 872 qos_pcie: qos@ffa60080 { 873 compatible = "syscon"; 874 reg = <0x0 0xffa60080 0x0 0x20>; 875 }; 876 877 qos_usb_host0: qos@ffa60100 { 878 compatible = "syscon"; 879 reg = <0x0 0xffa60100 0x0 0x20>; 880 }; 881 882 qos_usb_host1: qos@ffa60180 { 883 compatible = "syscon"; 884 reg = <0x0 0xffa60180 0x0 0x20>; 885 }; 886 887 qos_usb_otg0: qos@ffa70000 { 888 compatible = "syscon"; 889 reg = <0x0 0xffa70000 0x0 0x20>; 890 }; 891 892 qos_usb_otg1: qos@ffa70080 { 893 compatible = "syscon"; 894 reg = <0x0 0xffa70080 0x0 0x20>; 895 }; 896 897 qos_sd: qos@ffa74000 { 898 compatible = "syscon"; 899 reg = <0x0 0xffa74000 0x0 0x20>; 900 }; 901 902 qos_sdioaudio: qos@ffa76000 { 903 compatible = "syscon"; 904 reg = <0x0 0xffa76000 0x0 0x20>; 905 }; 906 907 qos_hdcp: qos@ffa90000 { 908 compatible = "syscon"; 909 reg = <0x0 0xffa90000 0x0 0x20>; 910 }; 911 912 qos_iep: qos@ffa98000 { 913 compatible = "syscon"; 914 reg = <0x0 0xffa98000 0x0 0x20>; 915 }; 916 917 qos_isp0_m0: qos@ffaa0000 { 918 compatible = "syscon"; 919 reg = <0x0 0xffaa0000 0x0 0x20>; 920 }; 921 922 qos_isp0_m1: qos@ffaa0080 { 923 compatible = "syscon"; 924 reg = <0x0 0xffaa0080 0x0 0x20>; 925 }; 926 927 qos_isp1_m0: qos@ffaa8000 { 928 compatible = "syscon"; 929 reg = <0x0 0xffaa8000 0x0 0x20>; 930 }; 931 932 qos_isp1_m1: qos@ffaa8080 { 933 compatible = "syscon"; 934 reg = <0x0 0xffaa8080 0x0 0x20>; 935 }; 936 937 qos_rga_r: qos@ffab0000 { 938 compatible = "syscon"; 939 reg = <0x0 0xffab0000 0x0 0x20>; 940 }; 941 942 qos_rga_w: qos@ffab0080 { 943 compatible = "syscon"; 944 reg = <0x0 0xffab0080 0x0 0x20>; 945 }; 946 947 qos_video_m0: qos@ffab8000 { 948 compatible = "syscon"; 949 reg = <0x0 0xffab8000 0x0 0x20>; 950 }; 951 952 qos_video_m1_r: qos@ffac0000 { 953 compatible = "syscon"; 954 reg = <0x0 0xffac0000 0x0 0x20>; 955 }; 956 957 qos_video_m1_w: qos@ffac0080 { 958 compatible = "syscon"; 959 reg = <0x0 0xffac0080 0x0 0x20>; 960 }; 961 962 qos_vop_big_r: qos@ffac8000 { 963 compatible = "syscon"; 964 reg = <0x0 0xffac8000 0x0 0x20>; 965 }; 966 967 qos_vop_big_w: qos@ffac8080 { 968 compatible = "syscon"; 969 reg = <0x0 0xffac8080 0x0 0x20>; 970 }; 971 972 qos_vop_little: qos@ffad0000 { 973 compatible = "syscon"; 974 reg = <0x0 0xffad0000 0x0 0x20>; 975 }; 976 977 qos_perihp: qos@ffad8080 { 978 compatible = "syscon"; 979 reg = <0x0 0xffad8080 0x0 0x20>; 980 }; 981 982 qos_gpu: qos@ffae0000 { 983 compatible = "syscon"; 984 reg = <0x0 0xffae0000 0x0 0x20>; 985 }; 986 987 pmu: power-management@ff310000 { 988 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 989 reg = <0x0 0xff310000 0x0 0x1000>; 990 991 /* 992 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 993 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 994 * Some of the power domains are grouped together for every 995 * voltage domain. 996 * The detail contents as below. 997 */ 998 power: power-controller { 999 compatible = "rockchip,rk3399-power-controller"; 1000 #power-domain-cells = <1>; 1001 #address-cells = <1>; 1002 #size-cells = <0>; 1003 1004 /* These power domains are grouped by VD_CENTER */ 1005 pd_iep@RK3399_PD_IEP { 1006 reg = <RK3399_PD_IEP>; 1007 clocks = <&cru ACLK_IEP>, 1008 <&cru HCLK_IEP>; 1009 pm_qos = <&qos_iep>; 1010 }; 1011 pd_rga@RK3399_PD_RGA { 1012 reg = <RK3399_PD_RGA>; 1013 clocks = <&cru ACLK_RGA>, 1014 <&cru HCLK_RGA>; 1015 pm_qos = <&qos_rga_r>, 1016 <&qos_rga_w>; 1017 }; 1018 pd_vcodec@RK3399_PD_VCODEC { 1019 reg = <RK3399_PD_VCODEC>; 1020 clocks = <&cru ACLK_VCODEC>, 1021 <&cru HCLK_VCODEC>; 1022 pm_qos = <&qos_video_m0>; 1023 }; 1024 pd_vdu@RK3399_PD_VDU { 1025 reg = <RK3399_PD_VDU>; 1026 clocks = <&cru ACLK_VDU>, 1027 <&cru HCLK_VDU>; 1028 pm_qos = <&qos_video_m1_r>, 1029 <&qos_video_m1_w>; 1030 }; 1031 1032 /* These power domains are grouped by VD_GPU */ 1033 pd_gpu@RK3399_PD_GPU { 1034 reg = <RK3399_PD_GPU>; 1035 clocks = <&cru ACLK_GPU>; 1036 pm_qos = <&qos_gpu>; 1037 }; 1038 1039 /* These power domains are grouped by VD_LOGIC */ 1040 pd_edp@RK3399_PD_EDP { 1041 reg = <RK3399_PD_EDP>; 1042 clocks = <&cru PCLK_EDP_CTRL>; 1043 }; 1044 pd_emmc@RK3399_PD_EMMC { 1045 reg = <RK3399_PD_EMMC>; 1046 clocks = <&cru ACLK_EMMC>; 1047 pm_qos = <&qos_emmc>; 1048 }; 1049 pd_gmac@RK3399_PD_GMAC { 1050 reg = <RK3399_PD_GMAC>; 1051 clocks = <&cru ACLK_GMAC>, 1052 <&cru PCLK_GMAC>; 1053 pm_qos = <&qos_gmac>; 1054 }; 1055 pd_sd@RK3399_PD_SD { 1056 reg = <RK3399_PD_SD>; 1057 clocks = <&cru HCLK_SDMMC>, 1058 <&cru SCLK_SDMMC>; 1059 pm_qos = <&qos_sd>; 1060 }; 1061 pd_sdioaudio@RK3399_PD_SDIOAUDIO { 1062 reg = <RK3399_PD_SDIOAUDIO>; 1063 clocks = <&cru HCLK_SDIO>; 1064 pm_qos = <&qos_sdioaudio>; 1065 }; 1066 pd_usb3@RK3399_PD_USB3 { 1067 reg = <RK3399_PD_USB3>; 1068 clocks = <&cru ACLK_USB3>; 1069 pm_qos = <&qos_usb_otg0>, 1070 <&qos_usb_otg1>; 1071 }; 1072 pd_vio@RK3399_PD_VIO { 1073 reg = <RK3399_PD_VIO>; 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 1077 pd_hdcp@RK3399_PD_HDCP { 1078 reg = <RK3399_PD_HDCP>; 1079 clocks = <&cru ACLK_HDCP>, 1080 <&cru HCLK_HDCP>, 1081 <&cru PCLK_HDCP>; 1082 pm_qos = <&qos_hdcp>; 1083 }; 1084 pd_isp0@RK3399_PD_ISP0 { 1085 reg = <RK3399_PD_ISP0>; 1086 clocks = <&cru ACLK_ISP0>, 1087 <&cru HCLK_ISP0>; 1088 pm_qos = <&qos_isp0_m0>, 1089 <&qos_isp0_m1>; 1090 }; 1091 pd_isp1@RK3399_PD_ISP1 { 1092 reg = <RK3399_PD_ISP1>; 1093 clocks = <&cru ACLK_ISP1>, 1094 <&cru HCLK_ISP1>; 1095 pm_qos = <&qos_isp1_m0>, 1096 <&qos_isp1_m1>; 1097 }; 1098 pd_tcpc0@RK3399_PD_TCPC0 { 1099 reg = <RK3399_PD_TCPD0>; 1100 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1101 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1102 }; 1103 pd_tcpc1@RK3399_PD_TCPC1 { 1104 reg = <RK3399_PD_TCPD1>; 1105 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1106 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1107 }; 1108 pd_vo@RK3399_PD_VO { 1109 reg = <RK3399_PD_VO>; 1110 #address-cells = <1>; 1111 #size-cells = <0>; 1112 1113 pd_vopb@RK3399_PD_VOPB { 1114 reg = <RK3399_PD_VOPB>; 1115 clocks = <&cru ACLK_VOP0>, 1116 <&cru HCLK_VOP0>; 1117 pm_qos = <&qos_vop_big_r>, 1118 <&qos_vop_big_w>; 1119 }; 1120 pd_vopl@RK3399_PD_VOPL { 1121 reg = <RK3399_PD_VOPL>; 1122 clocks = <&cru ACLK_VOP1>, 1123 <&cru HCLK_VOP1>; 1124 pm_qos = <&qos_vop_little>; 1125 }; 1126 }; 1127 }; 1128 }; 1129 }; 1130 1131 pmugrf: syscon@ff320000 { 1132 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1133 reg = <0x0 0xff320000 0x0 0x1000>; 1134 #address-cells = <1>; 1135 #size-cells = <1>; 1136 1137 pmu_io_domains: io-domains { 1138 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1139 status = "disabled"; 1140 }; 1141 }; 1142 1143 spi3: spi@ff350000 { 1144 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1145 reg = <0x0 0xff350000 0x0 0x1000>; 1146 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1147 clock-names = "spiclk", "apb_pclk"; 1148 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1149 pinctrl-names = "default"; 1150 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1151 #address-cells = <1>; 1152 #size-cells = <0>; 1153 status = "disabled"; 1154 }; 1155 1156 uart4: serial@ff370000 { 1157 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1158 reg = <0x0 0xff370000 0x0 0x100>; 1159 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1160 clock-names = "baudclk", "apb_pclk"; 1161 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1162 reg-shift = <2>; 1163 reg-io-width = <4>; 1164 pinctrl-names = "default"; 1165 pinctrl-0 = <&uart4_xfer>; 1166 status = "disabled"; 1167 }; 1168 1169 i2c0: i2c@ff3c0000 { 1170 compatible = "rockchip,rk3399-i2c"; 1171 reg = <0x0 0xff3c0000 0x0 0x1000>; 1172 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1173 assigned-clock-rates = <200000000>; 1174 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1175 clock-names = "i2c", "pclk"; 1176 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1177 pinctrl-names = "default"; 1178 pinctrl-0 = <&i2c0_xfer>; 1179 #address-cells = <1>; 1180 #size-cells = <0>; 1181 status = "disabled"; 1182 }; 1183 1184 i2c4: i2c@ff3d0000 { 1185 compatible = "rockchip,rk3399-i2c"; 1186 reg = <0x0 0xff3d0000 0x0 0x1000>; 1187 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1188 assigned-clock-rates = <200000000>; 1189 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1190 clock-names = "i2c", "pclk"; 1191 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1192 pinctrl-names = "default"; 1193 pinctrl-0 = <&i2c4_xfer>; 1194 #address-cells = <1>; 1195 #size-cells = <0>; 1196 status = "disabled"; 1197 }; 1198 1199 i2c8: i2c@ff3e0000 { 1200 compatible = "rockchip,rk3399-i2c"; 1201 reg = <0x0 0xff3e0000 0x0 0x1000>; 1202 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1203 assigned-clock-rates = <200000000>; 1204 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1205 clock-names = "i2c", "pclk"; 1206 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1207 pinctrl-names = "default"; 1208 pinctrl-0 = <&i2c8_xfer>; 1209 #address-cells = <1>; 1210 #size-cells = <0>; 1211 status = "disabled"; 1212 }; 1213 1214 pwm0: pwm@ff420000 { 1215 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1216 reg = <0x0 0xff420000 0x0 0x10>; 1217 #pwm-cells = <3>; 1218 pinctrl-names = "default"; 1219 pinctrl-0 = <&pwm0_pin>; 1220 clocks = <&pmucru PCLK_RKPWM_PMU>; 1221 clock-names = "pwm"; 1222 status = "disabled"; 1223 }; 1224 1225 pwm1: pwm@ff420010 { 1226 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1227 reg = <0x0 0xff420010 0x0 0x10>; 1228 #pwm-cells = <3>; 1229 pinctrl-names = "default"; 1230 pinctrl-0 = <&pwm1_pin>; 1231 clocks = <&pmucru PCLK_RKPWM_PMU>; 1232 clock-names = "pwm"; 1233 status = "disabled"; 1234 }; 1235 1236 pwm2: pwm@ff420020 { 1237 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1238 reg = <0x0 0xff420020 0x0 0x10>; 1239 #pwm-cells = <3>; 1240 pinctrl-names = "default"; 1241 pinctrl-0 = <&pwm2_pin>; 1242 clocks = <&pmucru PCLK_RKPWM_PMU>; 1243 clock-names = "pwm"; 1244 status = "disabled"; 1245 }; 1246 1247 pwm3: pwm@ff420030 { 1248 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1249 reg = <0x0 0xff420030 0x0 0x10>; 1250 #pwm-cells = <3>; 1251 pinctrl-names = "default"; 1252 pinctrl-0 = <&pwm3a_pin>; 1253 clocks = <&pmucru PCLK_RKPWM_PMU>; 1254 clock-names = "pwm"; 1255 status = "disabled"; 1256 }; 1257 1258 vpu: video-codec@ff650000 { 1259 compatible = "rockchip,rk3399-vpu"; 1260 reg = <0x0 0xff650000 0x0 0x800>; 1261 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 1262 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 1263 interrupt-names = "vepu", "vdpu"; 1264 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1265 clock-names = "aclk", "hclk"; 1266 iommus = <&vpu_mmu>; 1267 power-domains = <&power RK3399_PD_VCODEC>; 1268 }; 1269 1270 vpu_mmu: iommu@ff650800 { 1271 compatible = "rockchip,iommu"; 1272 reg = <0x0 0xff650800 0x0 0x40>; 1273 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 1274 interrupt-names = "vpu_mmu"; 1275 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1276 clock-names = "aclk", "iface"; 1277 #iommu-cells = <0>; 1278 power-domains = <&power RK3399_PD_VCODEC>; 1279 }; 1280 1281 vdec_mmu: iommu@ff660480 { 1282 compatible = "rockchip,iommu"; 1283 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; 1284 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1285 interrupt-names = "vdec_mmu"; 1286 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; 1287 clock-names = "aclk", "iface"; 1288 #iommu-cells = <0>; 1289 status = "disabled"; 1290 }; 1291 1292 iep_mmu: iommu@ff670800 { 1293 compatible = "rockchip,iommu"; 1294 reg = <0x0 0xff670800 0x0 0x40>; 1295 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>; 1296 interrupt-names = "iep_mmu"; 1297 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 1298 clock-names = "aclk", "iface"; 1299 #iommu-cells = <0>; 1300 status = "disabled"; 1301 }; 1302 1303 rga: rga@ff680000 { 1304 compatible = "rockchip,rk3399-rga"; 1305 reg = <0x0 0xff680000 0x0 0x10000>; 1306 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>; 1307 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; 1308 clock-names = "aclk", "hclk", "sclk"; 1309 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 1310 reset-names = "core", "axi", "ahb"; 1311 power-domains = <&power RK3399_PD_RGA>; 1312 }; 1313 1314 efuse0: efuse@ff690000 { 1315 compatible = "rockchip,rk3399-efuse"; 1316 reg = <0x0 0xff690000 0x0 0x80>; 1317 #address-cells = <1>; 1318 #size-cells = <1>; 1319 clocks = <&cru PCLK_EFUSE1024NS>; 1320 clock-names = "pclk_efuse"; 1321 1322 /* Data cells */ 1323 cpu_id: cpu-id@7 { 1324 reg = <0x07 0x10>; 1325 }; 1326 cpub_leakage: cpu-leakage@17 { 1327 reg = <0x17 0x1>; 1328 }; 1329 gpu_leakage: gpu-leakage@18 { 1330 reg = <0x18 0x1>; 1331 }; 1332 center_leakage: center-leakage@19 { 1333 reg = <0x19 0x1>; 1334 }; 1335 cpul_leakage: cpu-leakage@1a { 1336 reg = <0x1a 0x1>; 1337 }; 1338 logic_leakage: logic-leakage@1b { 1339 reg = <0x1b 0x1>; 1340 }; 1341 wafer_info: wafer-info@1c { 1342 reg = <0x1c 0x1>; 1343 }; 1344 }; 1345 1346 pmucru: pmu-clock-controller@ff750000 { 1347 compatible = "rockchip,rk3399-pmucru"; 1348 reg = <0x0 0xff750000 0x0 0x1000>; 1349 rockchip,grf = <&pmugrf>; 1350 #clock-cells = <1>; 1351 #reset-cells = <1>; 1352 assigned-clocks = <&pmucru PLL_PPLL>; 1353 assigned-clock-rates = <676000000>; 1354 }; 1355 1356 cru: clock-controller@ff760000 { 1357 compatible = "rockchip,rk3399-cru"; 1358 reg = <0x0 0xff760000 0x0 0x1000>; 1359 rockchip,grf = <&grf>; 1360 #clock-cells = <1>; 1361 #reset-cells = <1>; 1362 assigned-clocks = 1363 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1364 <&cru PLL_NPLL>, 1365 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1366 <&cru PCLK_PERIHP>, 1367 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1368 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1369 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 1370 <&cru ACLK_VIO>, <&cru ACLK_HDCP>, 1371 <&cru ACLK_GIC_PRE>, 1372 <&cru PCLK_DDR>; 1373 assigned-clock-rates = 1374 <594000000>, <800000000>, 1375 <1000000000>, 1376 <150000000>, <75000000>, 1377 <37500000>, 1378 <100000000>, <100000000>, 1379 <50000000>, <600000000>, 1380 <100000000>, <50000000>, 1381 <400000000>, <400000000>, 1382 <200000000>, 1383 <200000000>; 1384 }; 1385 1386 grf: syscon@ff770000 { 1387 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1388 reg = <0x0 0xff770000 0x0 0x10000>; 1389 #address-cells = <1>; 1390 #size-cells = <1>; 1391 1392 io_domains: io-domains { 1393 compatible = "rockchip,rk3399-io-voltage-domain"; 1394 status = "disabled"; 1395 }; 1396 1397 u2phy0: usb2-phy@e450 { 1398 compatible = "rockchip,rk3399-usb2phy"; 1399 reg = <0xe450 0x10>; 1400 clocks = <&cru SCLK_USB2PHY0_REF>; 1401 clock-names = "phyclk"; 1402 #clock-cells = <0>; 1403 clock-output-names = "clk_usbphy0_480m"; 1404 status = "disabled"; 1405 1406 u2phy0_host: host-port { 1407 #phy-cells = <0>; 1408 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1409 interrupt-names = "linestate"; 1410 status = "disabled"; 1411 }; 1412 1413 u2phy0_otg: otg-port { 1414 #phy-cells = <0>; 1415 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1416 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1417 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1418 interrupt-names = "otg-bvalid", "otg-id", 1419 "linestate"; 1420 status = "disabled"; 1421 }; 1422 }; 1423 1424 u2phy1: usb2-phy@e460 { 1425 compatible = "rockchip,rk3399-usb2phy"; 1426 reg = <0xe460 0x10>; 1427 clocks = <&cru SCLK_USB2PHY1_REF>; 1428 clock-names = "phyclk"; 1429 #clock-cells = <0>; 1430 clock-output-names = "clk_usbphy1_480m"; 1431 status = "disabled"; 1432 1433 u2phy1_host: host-port { 1434 #phy-cells = <0>; 1435 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1436 interrupt-names = "linestate"; 1437 status = "disabled"; 1438 }; 1439 1440 u2phy1_otg: otg-port { 1441 #phy-cells = <0>; 1442 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1443 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1444 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1445 interrupt-names = "otg-bvalid", "otg-id", 1446 "linestate"; 1447 status = "disabled"; 1448 }; 1449 }; 1450 1451 emmc_phy: phy@f780 { 1452 compatible = "rockchip,rk3399-emmc-phy"; 1453 reg = <0xf780 0x24>; 1454 clocks = <&sdhci>; 1455 clock-names = "emmcclk"; 1456 #phy-cells = <0>; 1457 status = "disabled"; 1458 }; 1459 1460 pcie_phy: pcie-phy { 1461 compatible = "rockchip,rk3399-pcie-phy"; 1462 clocks = <&cru SCLK_PCIEPHY_REF>; 1463 clock-names = "refclk"; 1464 #phy-cells = <1>; 1465 resets = <&cru SRST_PCIEPHY>; 1466 drive-impedance-ohm = <50>; 1467 reset-names = "phy"; 1468 status = "disabled"; 1469 }; 1470 }; 1471 1472 tcphy0: phy@ff7c0000 { 1473 compatible = "rockchip,rk3399-typec-phy"; 1474 reg = <0x0 0xff7c0000 0x0 0x40000>; 1475 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1476 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1477 clock-names = "tcpdcore", "tcpdphy-ref"; 1478 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1479 assigned-clock-rates = <50000000>; 1480 power-domains = <&power RK3399_PD_TCPD0>; 1481 resets = <&cru SRST_UPHY0>, 1482 <&cru SRST_UPHY0_PIPE_L00>, 1483 <&cru SRST_P_UPHY0_TCPHY>; 1484 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1485 rockchip,grf = <&grf>; 1486 status = "disabled"; 1487 1488 tcphy0_dp: dp-port { 1489 #phy-cells = <0>; 1490 }; 1491 1492 tcphy0_usb3: usb3-port { 1493 #phy-cells = <0>; 1494 }; 1495 }; 1496 1497 tcphy1: phy@ff800000 { 1498 compatible = "rockchip,rk3399-typec-phy"; 1499 reg = <0x0 0xff800000 0x0 0x40000>; 1500 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1501 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1502 clock-names = "tcpdcore", "tcpdphy-ref"; 1503 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1504 assigned-clock-rates = <50000000>; 1505 power-domains = <&power RK3399_PD_TCPD1>; 1506 resets = <&cru SRST_UPHY1>, 1507 <&cru SRST_UPHY1_PIPE_L00>, 1508 <&cru SRST_P_UPHY1_TCPHY>; 1509 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1510 rockchip,grf = <&grf>; 1511 status = "disabled"; 1512 1513 tcphy1_dp: dp-port { 1514 #phy-cells = <0>; 1515 }; 1516 1517 tcphy1_usb3: usb3-port { 1518 #phy-cells = <0>; 1519 }; 1520 }; 1521 1522 watchdog@ff848000 { 1523 compatible = "snps,dw-wdt"; 1524 reg = <0x0 0xff848000 0x0 0x100>; 1525 clocks = <&cru PCLK_WDT>; 1526 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1527 }; 1528 1529 rktimer: rktimer@ff850000 { 1530 compatible = "rockchip,rk3399-timer"; 1531 reg = <0x0 0xff850000 0x0 0x1000>; 1532 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1533 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1534 clock-names = "pclk", "timer"; 1535 }; 1536 1537 spdif: spdif@ff870000 { 1538 compatible = "rockchip,rk3399-spdif"; 1539 reg = <0x0 0xff870000 0x0 0x1000>; 1540 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1541 dmas = <&dmac_bus 7>; 1542 dma-names = "tx"; 1543 clock-names = "mclk", "hclk"; 1544 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1545 pinctrl-names = "default"; 1546 pinctrl-0 = <&spdif_bus>; 1547 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1548 #sound-dai-cells = <0>; 1549 status = "disabled"; 1550 }; 1551 1552 i2s0: i2s@ff880000 { 1553 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1554 reg = <0x0 0xff880000 0x0 0x1000>; 1555 rockchip,grf = <&grf>; 1556 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1557 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1558 dma-names = "tx", "rx"; 1559 clock-names = "i2s_clk", "i2s_hclk"; 1560 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1561 pinctrl-names = "default"; 1562 pinctrl-0 = <&i2s0_8ch_bus>; 1563 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1564 #sound-dai-cells = <0>; 1565 status = "disabled"; 1566 }; 1567 1568 i2s1: i2s@ff890000 { 1569 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1570 reg = <0x0 0xff890000 0x0 0x1000>; 1571 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1572 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1573 dma-names = "tx", "rx"; 1574 clock-names = "i2s_clk", "i2s_hclk"; 1575 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1576 pinctrl-names = "default"; 1577 pinctrl-0 = <&i2s1_2ch_bus>; 1578 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1579 #sound-dai-cells = <0>; 1580 status = "disabled"; 1581 }; 1582 1583 i2s2: i2s@ff8a0000 { 1584 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1585 reg = <0x0 0xff8a0000 0x0 0x1000>; 1586 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1587 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1588 dma-names = "tx", "rx"; 1589 clock-names = "i2s_clk", "i2s_hclk"; 1590 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1591 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1592 #sound-dai-cells = <0>; 1593 status = "disabled"; 1594 }; 1595 1596 vopl: vop@ff8f0000 { 1597 compatible = "rockchip,rk3399-vop-lit"; 1598 reg = <0x0 0xff8f0000 0x0 0x3efc>; 1599 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1600 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1601 assigned-clock-rates = <400000000>, <100000000>; 1602 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1603 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1604 iommus = <&vopl_mmu>; 1605 power-domains = <&power RK3399_PD_VOPL>; 1606 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1607 reset-names = "axi", "ahb", "dclk"; 1608 status = "disabled"; 1609 1610 vopl_out: port { 1611 #address-cells = <1>; 1612 #size-cells = <0>; 1613 1614 vopl_out_mipi: endpoint@0 { 1615 reg = <0>; 1616 remote-endpoint = <&mipi_in_vopl>; 1617 }; 1618 1619 vopl_out_edp: endpoint@1 { 1620 reg = <1>; 1621 remote-endpoint = <&edp_in_vopl>; 1622 }; 1623 1624 vopl_out_hdmi: endpoint@2 { 1625 reg = <2>; 1626 remote-endpoint = <&hdmi_in_vopl>; 1627 }; 1628 1629 vopl_out_mipi1: endpoint@3 { 1630 reg = <3>; 1631 remote-endpoint = <&mipi1_in_vopl>; 1632 }; 1633 1634 vopl_out_dp: endpoint@4 { 1635 reg = <4>; 1636 remote-endpoint = <&dp_in_vopl>; 1637 }; 1638 }; 1639 }; 1640 1641 vopl_mmu: iommu@ff8f3f00 { 1642 compatible = "rockchip,iommu"; 1643 reg = <0x0 0xff8f3f00 0x0 0x100>; 1644 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1645 interrupt-names = "vopl_mmu"; 1646 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1647 clock-names = "aclk", "iface"; 1648 power-domains = <&power RK3399_PD_VOPL>; 1649 #iommu-cells = <0>; 1650 status = "disabled"; 1651 }; 1652 1653 vopb: vop@ff900000 { 1654 compatible = "rockchip,rk3399-vop-big"; 1655 reg = <0x0 0xff900000 0x0 0x3efc>; 1656 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1657 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1658 assigned-clock-rates = <400000000>, <100000000>; 1659 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1660 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1661 iommus = <&vopb_mmu>; 1662 power-domains = <&power RK3399_PD_VOPB>; 1663 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1664 reset-names = "axi", "ahb", "dclk"; 1665 status = "disabled"; 1666 1667 vopb_out: port { 1668 #address-cells = <1>; 1669 #size-cells = <0>; 1670 1671 vopb_out_edp: endpoint@0 { 1672 reg = <0>; 1673 remote-endpoint = <&edp_in_vopb>; 1674 }; 1675 1676 vopb_out_mipi: endpoint@1 { 1677 reg = <1>; 1678 remote-endpoint = <&mipi_in_vopb>; 1679 }; 1680 1681 vopb_out_hdmi: endpoint@2 { 1682 reg = <2>; 1683 remote-endpoint = <&hdmi_in_vopb>; 1684 }; 1685 1686 vopb_out_mipi1: endpoint@3 { 1687 reg = <3>; 1688 remote-endpoint = <&mipi1_in_vopb>; 1689 }; 1690 1691 vopb_out_dp: endpoint@4 { 1692 reg = <4>; 1693 remote-endpoint = <&dp_in_vopb>; 1694 }; 1695 }; 1696 }; 1697 1698 vopb_mmu: iommu@ff903f00 { 1699 compatible = "rockchip,iommu"; 1700 reg = <0x0 0xff903f00 0x0 0x100>; 1701 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1702 interrupt-names = "vopb_mmu"; 1703 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1704 clock-names = "aclk", "iface"; 1705 power-domains = <&power RK3399_PD_VOPB>; 1706 #iommu-cells = <0>; 1707 status = "disabled"; 1708 }; 1709 1710 isp0_mmu: iommu@ff914000 { 1711 compatible = "rockchip,iommu"; 1712 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1713 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1714 interrupt-names = "isp0_mmu"; 1715 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; 1716 clock-names = "aclk", "iface"; 1717 #iommu-cells = <0>; 1718 power-domains = <&power RK3399_PD_ISP0>; 1719 rockchip,disable-mmu-reset; 1720 }; 1721 1722 isp1_mmu: iommu@ff924000 { 1723 compatible = "rockchip,iommu"; 1724 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; 1725 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 1726 interrupt-names = "isp1_mmu"; 1727 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; 1728 clock-names = "aclk", "iface"; 1729 #iommu-cells = <0>; 1730 power-domains = <&power RK3399_PD_ISP1>; 1731 rockchip,disable-mmu-reset; 1732 }; 1733 1734 hdmi_sound: hdmi-sound { 1735 compatible = "simple-audio-card"; 1736 simple-audio-card,format = "i2s"; 1737 simple-audio-card,mclk-fs = <256>; 1738 simple-audio-card,name = "hdmi-sound"; 1739 status = "disabled"; 1740 1741 simple-audio-card,cpu { 1742 sound-dai = <&i2s2>; 1743 }; 1744 simple-audio-card,codec { 1745 sound-dai = <&hdmi>; 1746 }; 1747 }; 1748 1749 hdmi: hdmi@ff940000 { 1750 compatible = "rockchip,rk3399-dw-hdmi"; 1751 reg = <0x0 0xff940000 0x0 0x20000>; 1752 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 1753 clocks = <&cru PCLK_HDMI_CTRL>, 1754 <&cru SCLK_HDMI_SFR>, 1755 <&cru PLL_VPLL>, 1756 <&cru PCLK_VIO_GRF>, 1757 <&cru SCLK_HDMI_CEC>; 1758 clock-names = "iahb", "isfr", "vpll", "grf", "cec"; 1759 power-domains = <&power RK3399_PD_HDCP>; 1760 reg-io-width = <4>; 1761 rockchip,grf = <&grf>; 1762 #sound-dai-cells = <0>; 1763 status = "disabled"; 1764 1765 ports { 1766 hdmi_in: port { 1767 #address-cells = <1>; 1768 #size-cells = <0>; 1769 1770 hdmi_in_vopb: endpoint@0 { 1771 reg = <0>; 1772 remote-endpoint = <&vopb_out_hdmi>; 1773 }; 1774 hdmi_in_vopl: endpoint@1 { 1775 reg = <1>; 1776 remote-endpoint = <&vopl_out_hdmi>; 1777 }; 1778 }; 1779 }; 1780 }; 1781 1782 mipi_dsi: mipi@ff960000 { 1783 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1784 reg = <0x0 0xff960000 0x0 0x8000>; 1785 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 1786 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, 1787 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; 1788 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1789 power-domains = <&power RK3399_PD_VIO>; 1790 resets = <&cru SRST_P_MIPI_DSI0>; 1791 reset-names = "apb"; 1792 rockchip,grf = <&grf>; 1793 #address-cells = <1>; 1794 #size-cells = <0>; 1795 status = "disabled"; 1796 1797 ports { 1798 #address-cells = <1>; 1799 #size-cells = <0>; 1800 1801 mipi_in: port@0 { 1802 reg = <0>; 1803 #address-cells = <1>; 1804 #size-cells = <0>; 1805 1806 mipi_in_vopb: endpoint@0 { 1807 reg = <0>; 1808 remote-endpoint = <&vopb_out_mipi>; 1809 }; 1810 mipi_in_vopl: endpoint@1 { 1811 reg = <1>; 1812 remote-endpoint = <&vopl_out_mipi>; 1813 }; 1814 }; 1815 }; 1816 }; 1817 1818 mipi_dsi1: mipi@ff968000 { 1819 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1820 reg = <0x0 0xff968000 0x0 0x8000>; 1821 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>; 1822 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, 1823 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; 1824 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1825 power-domains = <&power RK3399_PD_VIO>; 1826 resets = <&cru SRST_P_MIPI_DSI1>; 1827 reset-names = "apb"; 1828 rockchip,grf = <&grf>; 1829 #address-cells = <1>; 1830 #size-cells = <0>; 1831 status = "disabled"; 1832 1833 ports { 1834 #address-cells = <1>; 1835 #size-cells = <0>; 1836 1837 mipi1_in: port@0 { 1838 reg = <0>; 1839 #address-cells = <1>; 1840 #size-cells = <0>; 1841 1842 mipi1_in_vopb: endpoint@0 { 1843 reg = <0>; 1844 remote-endpoint = <&vopb_out_mipi1>; 1845 }; 1846 1847 mipi1_in_vopl: endpoint@1 { 1848 reg = <1>; 1849 remote-endpoint = <&vopl_out_mipi1>; 1850 }; 1851 }; 1852 }; 1853 }; 1854 1855 edp: edp@ff970000 { 1856 compatible = "rockchip,rk3399-edp"; 1857 reg = <0x0 0xff970000 0x0 0x8000>; 1858 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 1859 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; 1860 clock-names = "dp", "pclk", "grf"; 1861 pinctrl-names = "default"; 1862 pinctrl-0 = <&edp_hpd>; 1863 power-domains = <&power RK3399_PD_EDP>; 1864 resets = <&cru SRST_P_EDP_CTRL>; 1865 reset-names = "dp"; 1866 rockchip,grf = <&grf>; 1867 status = "disabled"; 1868 1869 ports { 1870 #address-cells = <1>; 1871 #size-cells = <0>; 1872 edp_in: port@0 { 1873 reg = <0>; 1874 #address-cells = <1>; 1875 #size-cells = <0>; 1876 1877 edp_in_vopb: endpoint@0 { 1878 reg = <0>; 1879 remote-endpoint = <&vopb_out_edp>; 1880 }; 1881 1882 edp_in_vopl: endpoint@1 { 1883 reg = <1>; 1884 remote-endpoint = <&vopl_out_edp>; 1885 }; 1886 }; 1887 }; 1888 }; 1889 1890 gpu: gpu@ff9a0000 { 1891 compatible = "rockchip,rk3399-mali", "arm,mali-t860"; 1892 reg = <0x0 0xff9a0000 0x0 0x10000>; 1893 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>, 1894 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, 1895 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>; 1896 interrupt-names = "gpu", "job", "mmu"; 1897 clocks = <&cru ACLK_GPU>; 1898 #cooling-cells = <2>; 1899 power-domains = <&power RK3399_PD_GPU>; 1900 status = "disabled"; 1901 }; 1902 1903 pinctrl: pinctrl { 1904 compatible = "rockchip,rk3399-pinctrl"; 1905 rockchip,grf = <&grf>; 1906 rockchip,pmu = <&pmugrf>; 1907 #address-cells = <2>; 1908 #size-cells = <2>; 1909 ranges; 1910 1911 gpio0: gpio0@ff720000 { 1912 compatible = "rockchip,gpio-bank"; 1913 reg = <0x0 0xff720000 0x0 0x100>; 1914 clocks = <&pmucru PCLK_GPIO0_PMU>; 1915 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 1916 1917 gpio-controller; 1918 #gpio-cells = <0x2>; 1919 1920 interrupt-controller; 1921 #interrupt-cells = <0x2>; 1922 }; 1923 1924 gpio1: gpio1@ff730000 { 1925 compatible = "rockchip,gpio-bank"; 1926 reg = <0x0 0xff730000 0x0 0x100>; 1927 clocks = <&pmucru PCLK_GPIO1_PMU>; 1928 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 1929 1930 gpio-controller; 1931 #gpio-cells = <0x2>; 1932 1933 interrupt-controller; 1934 #interrupt-cells = <0x2>; 1935 }; 1936 1937 gpio2: gpio2@ff780000 { 1938 compatible = "rockchip,gpio-bank"; 1939 reg = <0x0 0xff780000 0x0 0x100>; 1940 clocks = <&cru PCLK_GPIO2>; 1941 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 1942 1943 gpio-controller; 1944 #gpio-cells = <0x2>; 1945 1946 interrupt-controller; 1947 #interrupt-cells = <0x2>; 1948 }; 1949 1950 gpio3: gpio3@ff788000 { 1951 compatible = "rockchip,gpio-bank"; 1952 reg = <0x0 0xff788000 0x0 0x100>; 1953 clocks = <&cru PCLK_GPIO3>; 1954 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 1955 1956 gpio-controller; 1957 #gpio-cells = <0x2>; 1958 1959 interrupt-controller; 1960 #interrupt-cells = <0x2>; 1961 }; 1962 1963 gpio4: gpio4@ff790000 { 1964 compatible = "rockchip,gpio-bank"; 1965 reg = <0x0 0xff790000 0x0 0x100>; 1966 clocks = <&cru PCLK_GPIO4>; 1967 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 1968 1969 gpio-controller; 1970 #gpio-cells = <0x2>; 1971 1972 interrupt-controller; 1973 #interrupt-cells = <0x2>; 1974 }; 1975 1976 pcfg_pull_up: pcfg-pull-up { 1977 bias-pull-up; 1978 }; 1979 1980 pcfg_pull_down: pcfg-pull-down { 1981 bias-pull-down; 1982 }; 1983 1984 pcfg_pull_none: pcfg-pull-none { 1985 bias-disable; 1986 }; 1987 1988 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1989 bias-disable; 1990 drive-strength = <12>; 1991 }; 1992 1993 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 1994 bias-disable; 1995 drive-strength = <13>; 1996 }; 1997 1998 pcfg_pull_none_18ma: pcfg-pull-none-18ma { 1999 bias-disable; 2000 drive-strength = <18>; 2001 }; 2002 2003 pcfg_pull_none_20ma: pcfg-pull-none-20ma { 2004 bias-disable; 2005 drive-strength = <20>; 2006 }; 2007 2008 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 2009 bias-pull-up; 2010 drive-strength = <2>; 2011 }; 2012 2013 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 2014 bias-pull-up; 2015 drive-strength = <8>; 2016 }; 2017 2018 pcfg_pull_up_18ma: pcfg-pull-up-18ma { 2019 bias-pull-up; 2020 drive-strength = <18>; 2021 }; 2022 2023 pcfg_pull_up_20ma: pcfg-pull-up-20ma { 2024 bias-pull-up; 2025 drive-strength = <20>; 2026 }; 2027 2028 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 2029 bias-pull-down; 2030 drive-strength = <4>; 2031 }; 2032 2033 pcfg_pull_down_8ma: pcfg-pull-down-8ma { 2034 bias-pull-down; 2035 drive-strength = <8>; 2036 }; 2037 2038 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 2039 bias-pull-down; 2040 drive-strength = <12>; 2041 }; 2042 2043 pcfg_pull_down_18ma: pcfg-pull-down-18ma { 2044 bias-pull-down; 2045 drive-strength = <18>; 2046 }; 2047 2048 pcfg_pull_down_20ma: pcfg-pull-down-20ma { 2049 bias-pull-down; 2050 drive-strength = <20>; 2051 }; 2052 2053 pcfg_output_high: pcfg-output-high { 2054 output-high; 2055 }; 2056 2057 pcfg_output_low: pcfg-output-low { 2058 output-low; 2059 }; 2060 2061 clock { 2062 clk_32k: clk-32k { 2063 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; 2064 }; 2065 }; 2066 2067 edp { 2068 edp_hpd: edp-hpd { 2069 rockchip,pins = 2070 <4 RK_PC7 2 &pcfg_pull_none>; 2071 }; 2072 }; 2073 2074 gmac { 2075 rgmii_pins: rgmii-pins { 2076 rockchip,pins = 2077 /* mac_txclk */ 2078 <3 RK_PC1 1 &pcfg_pull_none_13ma>, 2079 /* mac_rxclk */ 2080 <3 RK_PB6 1 &pcfg_pull_none>, 2081 /* mac_mdio */ 2082 <3 RK_PB5 1 &pcfg_pull_none>, 2083 /* mac_txen */ 2084 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2085 /* mac_clk */ 2086 <3 RK_PB3 1 &pcfg_pull_none>, 2087 /* mac_rxdv */ 2088 <3 RK_PB1 1 &pcfg_pull_none>, 2089 /* mac_mdc */ 2090 <3 RK_PB0 1 &pcfg_pull_none>, 2091 /* mac_rxd1 */ 2092 <3 RK_PA7 1 &pcfg_pull_none>, 2093 /* mac_rxd0 */ 2094 <3 RK_PA6 1 &pcfg_pull_none>, 2095 /* mac_txd1 */ 2096 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2097 /* mac_txd0 */ 2098 <3 RK_PA4 1 &pcfg_pull_none_13ma>, 2099 /* mac_rxd3 */ 2100 <3 RK_PA3 1 &pcfg_pull_none>, 2101 /* mac_rxd2 */ 2102 <3 RK_PA2 1 &pcfg_pull_none>, 2103 /* mac_txd3 */ 2104 <3 RK_PA1 1 &pcfg_pull_none_13ma>, 2105 /* mac_txd2 */ 2106 <3 RK_PA0 1 &pcfg_pull_none_13ma>; 2107 }; 2108 2109 rmii_pins: rmii-pins { 2110 rockchip,pins = 2111 /* mac_mdio */ 2112 <3 RK_PB5 1 &pcfg_pull_none>, 2113 /* mac_txen */ 2114 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2115 /* mac_clk */ 2116 <3 RK_PB3 1 &pcfg_pull_none>, 2117 /* mac_rxer */ 2118 <3 RK_PB2 1 &pcfg_pull_none>, 2119 /* mac_rxdv */ 2120 <3 RK_PB1 1 &pcfg_pull_none>, 2121 /* mac_mdc */ 2122 <3 RK_PB0 1 &pcfg_pull_none>, 2123 /* mac_rxd1 */ 2124 <3 RK_PA7 1 &pcfg_pull_none>, 2125 /* mac_rxd0 */ 2126 <3 RK_PA6 1 &pcfg_pull_none>, 2127 /* mac_txd1 */ 2128 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2129 /* mac_txd0 */ 2130 <3 RK_PA4 1 &pcfg_pull_none_13ma>; 2131 }; 2132 }; 2133 2134 i2c0 { 2135 i2c0_xfer: i2c0-xfer { 2136 rockchip,pins = 2137 <1 RK_PB7 2 &pcfg_pull_none>, 2138 <1 RK_PC0 2 &pcfg_pull_none>; 2139 }; 2140 }; 2141 2142 i2c1 { 2143 i2c1_xfer: i2c1-xfer { 2144 rockchip,pins = 2145 <4 RK_PA2 1 &pcfg_pull_none>, 2146 <4 RK_PA1 1 &pcfg_pull_none>; 2147 }; 2148 }; 2149 2150 i2c2 { 2151 i2c2_xfer: i2c2-xfer { 2152 rockchip,pins = 2153 <2 RK_PA1 2 &pcfg_pull_none_12ma>, 2154 <2 RK_PA0 2 &pcfg_pull_none_12ma>; 2155 }; 2156 }; 2157 2158 i2c3 { 2159 i2c3_xfer: i2c3-xfer { 2160 rockchip,pins = 2161 <4 RK_PC1 1 &pcfg_pull_none>, 2162 <4 RK_PC0 1 &pcfg_pull_none>; 2163 }; 2164 }; 2165 2166 i2c4 { 2167 i2c4_xfer: i2c4-xfer { 2168 rockchip,pins = 2169 <1 RK_PB4 1 &pcfg_pull_none>, 2170 <1 RK_PB3 1 &pcfg_pull_none>; 2171 }; 2172 }; 2173 2174 i2c5 { 2175 i2c5_xfer: i2c5-xfer { 2176 rockchip,pins = 2177 <3 RK_PB3 2 &pcfg_pull_none>, 2178 <3 RK_PB2 2 &pcfg_pull_none>; 2179 }; 2180 }; 2181 2182 i2c6 { 2183 i2c6_xfer: i2c6-xfer { 2184 rockchip,pins = 2185 <2 RK_PB2 2 &pcfg_pull_none>, 2186 <2 RK_PB1 2 &pcfg_pull_none>; 2187 }; 2188 }; 2189 2190 i2c7 { 2191 i2c7_xfer: i2c7-xfer { 2192 rockchip,pins = 2193 <2 RK_PB0 2 &pcfg_pull_none>, 2194 <2 RK_PA7 2 &pcfg_pull_none>; 2195 }; 2196 }; 2197 2198 i2c8 { 2199 i2c8_xfer: i2c8-xfer { 2200 rockchip,pins = 2201 <1 RK_PC5 1 &pcfg_pull_none>, 2202 <1 RK_PC4 1 &pcfg_pull_none>; 2203 }; 2204 }; 2205 2206 i2s0 { 2207 i2s0_2ch_bus: i2s0-2ch-bus { 2208 rockchip,pins = 2209 <3 RK_PD0 1 &pcfg_pull_none>, 2210 <3 RK_PD1 1 &pcfg_pull_none>, 2211 <3 RK_PD2 1 &pcfg_pull_none>, 2212 <3 RK_PD3 1 &pcfg_pull_none>, 2213 <3 RK_PD7 1 &pcfg_pull_none>, 2214 <4 RK_PA0 1 &pcfg_pull_none>; 2215 }; 2216 2217 i2s0_8ch_bus: i2s0-8ch-bus { 2218 rockchip,pins = 2219 <3 RK_PD0 1 &pcfg_pull_none>, 2220 <3 RK_PD1 1 &pcfg_pull_none>, 2221 <3 RK_PD2 1 &pcfg_pull_none>, 2222 <3 RK_PD3 1 &pcfg_pull_none>, 2223 <3 RK_PD4 1 &pcfg_pull_none>, 2224 <3 RK_PD5 1 &pcfg_pull_none>, 2225 <3 RK_PD6 1 &pcfg_pull_none>, 2226 <3 RK_PD7 1 &pcfg_pull_none>, 2227 <4 RK_PA0 1 &pcfg_pull_none>; 2228 }; 2229 }; 2230 2231 i2s1 { 2232 i2s1_2ch_bus: i2s1-2ch-bus { 2233 rockchip,pins = 2234 <4 RK_PA3 1 &pcfg_pull_none>, 2235 <4 RK_PA4 1 &pcfg_pull_none>, 2236 <4 RK_PA5 1 &pcfg_pull_none>, 2237 <4 RK_PA6 1 &pcfg_pull_none>, 2238 <4 RK_PA7 1 &pcfg_pull_none>; 2239 }; 2240 }; 2241 2242 sdio0 { 2243 sdio0_bus1: sdio0-bus1 { 2244 rockchip,pins = 2245 <2 RK_PC4 1 &pcfg_pull_up>; 2246 }; 2247 2248 sdio0_bus4: sdio0-bus4 { 2249 rockchip,pins = 2250 <2 RK_PC4 1 &pcfg_pull_up>, 2251 <2 RK_PC5 1 &pcfg_pull_up>, 2252 <2 RK_PC6 1 &pcfg_pull_up>, 2253 <2 RK_PC7 1 &pcfg_pull_up>; 2254 }; 2255 2256 sdio0_cmd: sdio0-cmd { 2257 rockchip,pins = 2258 <2 RK_PD0 1 &pcfg_pull_up>; 2259 }; 2260 2261 sdio0_clk: sdio0-clk { 2262 rockchip,pins = 2263 <2 RK_PD1 1 &pcfg_pull_none>; 2264 }; 2265 2266 sdio0_cd: sdio0-cd { 2267 rockchip,pins = 2268 <2 RK_PD2 1 &pcfg_pull_up>; 2269 }; 2270 2271 sdio0_pwr: sdio0-pwr { 2272 rockchip,pins = 2273 <2 RK_PD3 1 &pcfg_pull_up>; 2274 }; 2275 2276 sdio0_bkpwr: sdio0-bkpwr { 2277 rockchip,pins = 2278 <2 RK_PD4 1 &pcfg_pull_up>; 2279 }; 2280 2281 sdio0_wp: sdio0-wp { 2282 rockchip,pins = 2283 <0 RK_PA3 1 &pcfg_pull_up>; 2284 }; 2285 2286 sdio0_int: sdio0-int { 2287 rockchip,pins = 2288 <0 RK_PA4 1 &pcfg_pull_up>; 2289 }; 2290 }; 2291 2292 sdmmc { 2293 sdmmc_bus1: sdmmc-bus1 { 2294 rockchip,pins = 2295 <4 RK_PB0 1 &pcfg_pull_up>; 2296 }; 2297 2298 sdmmc_bus4: sdmmc-bus4 { 2299 rockchip,pins = 2300 <4 RK_PB0 1 &pcfg_pull_up>, 2301 <4 RK_PB1 1 &pcfg_pull_up>, 2302 <4 RK_PB2 1 &pcfg_pull_up>, 2303 <4 RK_PB3 1 &pcfg_pull_up>; 2304 }; 2305 2306 sdmmc_clk: sdmmc-clk { 2307 rockchip,pins = 2308 <4 RK_PB4 1 &pcfg_pull_none>; 2309 }; 2310 2311 sdmmc_cmd: sdmmc-cmd { 2312 rockchip,pins = 2313 <4 RK_PB5 1 &pcfg_pull_up>; 2314 }; 2315 2316 sdmmc_cd: sdmmc-cd { 2317 rockchip,pins = 2318 <0 RK_PA7 1 &pcfg_pull_up>; 2319 }; 2320 2321 sdmmc_wp: sdmmc-wp { 2322 rockchip,pins = 2323 <0 RK_PB0 1 &pcfg_pull_up>; 2324 }; 2325 }; 2326 2327 sleep { 2328 ap_pwroff: ap-pwroff { 2329 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>; 2330 }; 2331 2332 ddrio_pwroff: ddrio-pwroff { 2333 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; 2334 }; 2335 }; 2336 2337 spdif { 2338 spdif_bus: spdif-bus { 2339 rockchip,pins = 2340 <4 RK_PC5 1 &pcfg_pull_none>; 2341 }; 2342 2343 spdif_bus_1: spdif-bus-1 { 2344 rockchip,pins = 2345 <3 RK_PC0 3 &pcfg_pull_none>; 2346 }; 2347 }; 2348 2349 spi0 { 2350 spi0_clk: spi0-clk { 2351 rockchip,pins = 2352 <3 RK_PA6 2 &pcfg_pull_up>; 2353 }; 2354 spi0_cs0: spi0-cs0 { 2355 rockchip,pins = 2356 <3 RK_PA7 2 &pcfg_pull_up>; 2357 }; 2358 spi0_cs1: spi0-cs1 { 2359 rockchip,pins = 2360 <3 RK_PB0 2 &pcfg_pull_up>; 2361 }; 2362 spi0_tx: spi0-tx { 2363 rockchip,pins = 2364 <3 RK_PA5 2 &pcfg_pull_up>; 2365 }; 2366 spi0_rx: spi0-rx { 2367 rockchip,pins = 2368 <3 RK_PA4 2 &pcfg_pull_up>; 2369 }; 2370 }; 2371 2372 spi1 { 2373 spi1_clk: spi1-clk { 2374 rockchip,pins = 2375 <1 RK_PB1 2 &pcfg_pull_up>; 2376 }; 2377 spi1_cs0: spi1-cs0 { 2378 rockchip,pins = 2379 <1 RK_PB2 2 &pcfg_pull_up>; 2380 }; 2381 spi1_rx: spi1-rx { 2382 rockchip,pins = 2383 <1 RK_PA7 2 &pcfg_pull_up>; 2384 }; 2385 spi1_tx: spi1-tx { 2386 rockchip,pins = 2387 <1 RK_PB0 2 &pcfg_pull_up>; 2388 }; 2389 }; 2390 2391 spi2 { 2392 spi2_clk: spi2-clk { 2393 rockchip,pins = 2394 <2 RK_PB3 1 &pcfg_pull_up>; 2395 }; 2396 spi2_cs0: spi2-cs0 { 2397 rockchip,pins = 2398 <2 RK_PB4 1 &pcfg_pull_up>; 2399 }; 2400 spi2_rx: spi2-rx { 2401 rockchip,pins = 2402 <2 RK_PB1 1 &pcfg_pull_up>; 2403 }; 2404 spi2_tx: spi2-tx { 2405 rockchip,pins = 2406 <2 RK_PB2 1 &pcfg_pull_up>; 2407 }; 2408 }; 2409 2410 spi3 { 2411 spi3_clk: spi3-clk { 2412 rockchip,pins = 2413 <1 RK_PC1 1 &pcfg_pull_up>; 2414 }; 2415 spi3_cs0: spi3-cs0 { 2416 rockchip,pins = 2417 <1 RK_PC2 1 &pcfg_pull_up>; 2418 }; 2419 spi3_rx: spi3-rx { 2420 rockchip,pins = 2421 <1 RK_PB7 1 &pcfg_pull_up>; 2422 }; 2423 spi3_tx: spi3-tx { 2424 rockchip,pins = 2425 <1 RK_PC0 1 &pcfg_pull_up>; 2426 }; 2427 }; 2428 2429 spi4 { 2430 spi4_clk: spi4-clk { 2431 rockchip,pins = 2432 <3 RK_PA2 2 &pcfg_pull_up>; 2433 }; 2434 spi4_cs0: spi4-cs0 { 2435 rockchip,pins = 2436 <3 RK_PA3 2 &pcfg_pull_up>; 2437 }; 2438 spi4_rx: spi4-rx { 2439 rockchip,pins = 2440 <3 RK_PA0 2 &pcfg_pull_up>; 2441 }; 2442 spi4_tx: spi4-tx { 2443 rockchip,pins = 2444 <3 RK_PA1 2 &pcfg_pull_up>; 2445 }; 2446 }; 2447 2448 spi5 { 2449 spi5_clk: spi5-clk { 2450 rockchip,pins = 2451 <2 RK_PC6 2 &pcfg_pull_up>; 2452 }; 2453 spi5_cs0: spi5-cs0 { 2454 rockchip,pins = 2455 <2 RK_PC7 2 &pcfg_pull_up>; 2456 }; 2457 spi5_rx: spi5-rx { 2458 rockchip,pins = 2459 <2 RK_PC4 2 &pcfg_pull_up>; 2460 }; 2461 spi5_tx: spi5-tx { 2462 rockchip,pins = 2463 <2 RK_PC5 2 &pcfg_pull_up>; 2464 }; 2465 }; 2466 2467 testclk { 2468 test_clkout0: test-clkout0 { 2469 rockchip,pins = 2470 <0 RK_PA0 1 &pcfg_pull_none>; 2471 }; 2472 2473 test_clkout1: test-clkout1 { 2474 rockchip,pins = 2475 <2 RK_PD1 2 &pcfg_pull_none>; 2476 }; 2477 2478 test_clkout2: test-clkout2 { 2479 rockchip,pins = 2480 <0 RK_PB0 3 &pcfg_pull_none>; 2481 }; 2482 }; 2483 2484 tsadc { 2485 otp_gpio: otp-gpio { 2486 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 2487 }; 2488 2489 otp_out: otp-out { 2490 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; 2491 }; 2492 }; 2493 2494 uart0 { 2495 uart0_xfer: uart0-xfer { 2496 rockchip,pins = 2497 <2 RK_PC0 1 &pcfg_pull_up>, 2498 <2 RK_PC1 1 &pcfg_pull_none>; 2499 }; 2500 2501 uart0_cts: uart0-cts { 2502 rockchip,pins = 2503 <2 RK_PC2 1 &pcfg_pull_none>; 2504 }; 2505 2506 uart0_rts: uart0-rts { 2507 rockchip,pins = 2508 <2 RK_PC3 1 &pcfg_pull_none>; 2509 }; 2510 }; 2511 2512 uart1 { 2513 uart1_xfer: uart1-xfer { 2514 rockchip,pins = 2515 <3 RK_PB4 2 &pcfg_pull_up>, 2516 <3 RK_PB5 2 &pcfg_pull_none>; 2517 }; 2518 }; 2519 2520 uart2a { 2521 uart2a_xfer: uart2a-xfer { 2522 rockchip,pins = 2523 <4 RK_PB0 2 &pcfg_pull_up>, 2524 <4 RK_PB1 2 &pcfg_pull_none>; 2525 }; 2526 }; 2527 2528 uart2b { 2529 uart2b_xfer: uart2b-xfer { 2530 rockchip,pins = 2531 <4 RK_PC0 2 &pcfg_pull_up>, 2532 <4 RK_PC1 2 &pcfg_pull_none>; 2533 }; 2534 }; 2535 2536 uart2c { 2537 uart2c_xfer: uart2c-xfer { 2538 rockchip,pins = 2539 <4 RK_PC3 1 &pcfg_pull_up>, 2540 <4 RK_PC4 1 &pcfg_pull_none>; 2541 }; 2542 }; 2543 2544 uart3 { 2545 uart3_xfer: uart3-xfer { 2546 rockchip,pins = 2547 <3 RK_PB6 2 &pcfg_pull_up>, 2548 <3 RK_PB7 2 &pcfg_pull_none>; 2549 }; 2550 2551 uart3_cts: uart3-cts { 2552 rockchip,pins = 2553 <3 RK_PC0 2 &pcfg_pull_none>; 2554 }; 2555 2556 uart3_rts: uart3-rts { 2557 rockchip,pins = 2558 <3 RK_PC1 2 &pcfg_pull_none>; 2559 }; 2560 }; 2561 2562 uart4 { 2563 uart4_xfer: uart4-xfer { 2564 rockchip,pins = 2565 <1 RK_PA7 1 &pcfg_pull_up>, 2566 <1 RK_PB0 1 &pcfg_pull_none>; 2567 }; 2568 }; 2569 2570 uarthdcp { 2571 uarthdcp_xfer: uarthdcp-xfer { 2572 rockchip,pins = 2573 <4 RK_PC5 2 &pcfg_pull_up>, 2574 <4 RK_PC6 2 &pcfg_pull_none>; 2575 }; 2576 }; 2577 2578 pwm0 { 2579 pwm0_pin: pwm0-pin { 2580 rockchip,pins = 2581 <4 RK_PC2 1 &pcfg_pull_none>; 2582 }; 2583 2584 pwm0_pin_pull_down: pwm0-pin-pull-down { 2585 rockchip,pins = 2586 <4 RK_PC2 1 &pcfg_pull_down>; 2587 }; 2588 2589 vop0_pwm_pin: vop0-pwm-pin { 2590 rockchip,pins = 2591 <4 RK_PC2 2 &pcfg_pull_none>; 2592 }; 2593 2594 vop1_pwm_pin: vop1-pwm-pin { 2595 rockchip,pins = 2596 <4 RK_PC2 3 &pcfg_pull_none>; 2597 }; 2598 }; 2599 2600 pwm1 { 2601 pwm1_pin: pwm1-pin { 2602 rockchip,pins = 2603 <4 RK_PC6 1 &pcfg_pull_none>; 2604 }; 2605 2606 pwm1_pin_pull_down: pwm1-pin-pull-down { 2607 rockchip,pins = 2608 <4 RK_PC6 1 &pcfg_pull_down>; 2609 }; 2610 }; 2611 2612 pwm2 { 2613 pwm2_pin: pwm2-pin { 2614 rockchip,pins = 2615 <1 RK_PC3 1 &pcfg_pull_none>; 2616 }; 2617 2618 pwm2_pin_pull_down: pwm2-pin-pull-down { 2619 rockchip,pins = 2620 <1 RK_PC3 1 &pcfg_pull_down>; 2621 }; 2622 }; 2623 2624 pwm3a { 2625 pwm3a_pin: pwm3a-pin { 2626 rockchip,pins = 2627 <0 RK_PA6 1 &pcfg_pull_none>; 2628 }; 2629 }; 2630 2631 pwm3b { 2632 pwm3b_pin: pwm3b-pin { 2633 rockchip,pins = 2634 <1 RK_PB6 1 &pcfg_pull_none>; 2635 }; 2636 }; 2637 2638 hdmi { 2639 hdmi_i2c_xfer: hdmi-i2c-xfer { 2640 rockchip,pins = 2641 <4 RK_PC1 3 &pcfg_pull_none>, 2642 <4 RK_PC0 3 &pcfg_pull_none>; 2643 }; 2644 2645 hdmi_cec: hdmi-cec { 2646 rockchip,pins = 2647 <4 RK_PC7 1 &pcfg_pull_none>; 2648 }; 2649 }; 2650 2651 pcie { 2652 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2653 rockchip,pins = 2654 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2655 }; 2656 2657 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2658 rockchip,pins = 2659 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2660 }; 2661 }; 2662 2663 }; 2664}; 2665