1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3399-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3399-power.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "rockchip,rk3399"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &gmac; 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 i2c6 = &i2c6; 30 i2c7 = &i2c7; 31 i2c8 = &i2c8; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 cpu-map { 44 cluster0 { 45 core0 { 46 cpu = <&cpu_l0>; 47 }; 48 core1 { 49 cpu = <&cpu_l1>; 50 }; 51 core2 { 52 cpu = <&cpu_l2>; 53 }; 54 core3 { 55 cpu = <&cpu_l3>; 56 }; 57 }; 58 59 cluster1 { 60 core0 { 61 cpu = <&cpu_b0>; 62 }; 63 core1 { 64 cpu = <&cpu_b1>; 65 }; 66 }; 67 }; 68 69 cpu_l0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <0x0 0x0>; 73 enable-method = "psci"; 74 capacity-dmips-mhz = <485>; 75 clocks = <&cru ARMCLKL>; 76 #cooling-cells = <2>; /* min followed by max */ 77 dynamic-power-coefficient = <100>; 78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 79 }; 80 81 cpu_l1: cpu@1 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x0 0x1>; 85 enable-method = "psci"; 86 capacity-dmips-mhz = <485>; 87 clocks = <&cru ARMCLKL>; 88 #cooling-cells = <2>; /* min followed by max */ 89 dynamic-power-coefficient = <100>; 90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 91 }; 92 93 cpu_l2: cpu@2 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a53"; 96 reg = <0x0 0x2>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <485>; 99 clocks = <&cru ARMCLKL>; 100 #cooling-cells = <2>; /* min followed by max */ 101 dynamic-power-coefficient = <100>; 102 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 103 }; 104 105 cpu_l3: cpu@3 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53"; 108 reg = <0x0 0x3>; 109 enable-method = "psci"; 110 capacity-dmips-mhz = <485>; 111 clocks = <&cru ARMCLKL>; 112 #cooling-cells = <2>; /* min followed by max */ 113 dynamic-power-coefficient = <100>; 114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 115 }; 116 117 cpu_b0: cpu@100 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a72"; 120 reg = <0x0 0x100>; 121 enable-method = "psci"; 122 capacity-dmips-mhz = <1024>; 123 clocks = <&cru ARMCLKB>; 124 #cooling-cells = <2>; /* min followed by max */ 125 dynamic-power-coefficient = <436>; 126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 127 128 thermal-idle { 129 #cooling-cells = <2>; 130 duration-us = <10000>; 131 exit-latency-us = <500>; 132 }; 133 }; 134 135 cpu_b1: cpu@101 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a72"; 138 reg = <0x0 0x101>; 139 enable-method = "psci"; 140 capacity-dmips-mhz = <1024>; 141 clocks = <&cru ARMCLKB>; 142 #cooling-cells = <2>; /* min followed by max */ 143 dynamic-power-coefficient = <436>; 144 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 145 146 thermal-idle { 147 #cooling-cells = <2>; 148 duration-us = <10000>; 149 exit-latency-us = <500>; 150 }; 151 }; 152 153 idle-states { 154 entry-method = "psci"; 155 156 CPU_SLEEP: cpu-sleep { 157 compatible = "arm,idle-state"; 158 local-timer-stop; 159 arm,psci-suspend-param = <0x0010000>; 160 entry-latency-us = <120>; 161 exit-latency-us = <250>; 162 min-residency-us = <900>; 163 }; 164 165 CLUSTER_SLEEP: cluster-sleep { 166 compatible = "arm,idle-state"; 167 local-timer-stop; 168 arm,psci-suspend-param = <0x1010000>; 169 entry-latency-us = <400>; 170 exit-latency-us = <500>; 171 min-residency-us = <2000>; 172 }; 173 }; 174 }; 175 176 display-subsystem { 177 compatible = "rockchip,display-subsystem"; 178 ports = <&vopl_out>, <&vopb_out>; 179 }; 180 181 dmc: memory-controller { 182 compatible = "rockchip,rk3399-dmc"; 183 rockchip,pmu = <&pmugrf>; 184 devfreq-events = <&dfi>; 185 clocks = <&cru SCLK_DDRC>; 186 clock-names = "dmc_clk"; 187 status = "disabled"; 188 }; 189 190 pmu_a53 { 191 compatible = "arm,cortex-a53-pmu"; 192 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 193 }; 194 195 pmu_a72 { 196 compatible = "arm,cortex-a72-pmu"; 197 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 198 }; 199 200 psci { 201 compatible = "arm,psci-1.0"; 202 method = "smc"; 203 }; 204 205 timer { 206 compatible = "arm,armv8-timer"; 207 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 208 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 209 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 210 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 211 arm,no-tick-in-suspend; 212 }; 213 214 xin24m: xin24m { 215 compatible = "fixed-clock"; 216 clock-frequency = <24000000>; 217 clock-output-names = "xin24m"; 218 #clock-cells = <0>; 219 }; 220 221 pcie0: pcie@f8000000 { 222 compatible = "rockchip,rk3399-pcie"; 223 reg = <0x0 0xf8000000 0x0 0x2000000>, 224 <0x0 0xfd000000 0x0 0x1000000>; 225 reg-names = "axi-base", "apb-base"; 226 device_type = "pci"; 227 #address-cells = <3>; 228 #size-cells = <2>; 229 #interrupt-cells = <1>; 230 aspm-no-l0s; 231 bus-range = <0x0 0x1f>; 232 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 233 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 234 clock-names = "aclk", "aclk-perf", 235 "hclk", "pm"; 236 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 237 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 238 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 239 interrupt-names = "sys", "legacy", "client"; 240 interrupt-map-mask = <0 0 0 7>; 241 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 242 <0 0 0 2 &pcie0_intc 1>, 243 <0 0 0 3 &pcie0_intc 2>, 244 <0 0 0 4 &pcie0_intc 3>; 245 max-link-speed = <1>; 246 msi-map = <0x0 &its 0x0 0x1000>; 247 phys = <&pcie_phy 0>, <&pcie_phy 1>, 248 <&pcie_phy 2>, <&pcie_phy 3>; 249 phy-names = "pcie-phy-0", "pcie-phy-1", 250 "pcie-phy-2", "pcie-phy-3"; 251 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>, 252 <0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; 253 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 254 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 255 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 256 <&cru SRST_A_PCIE>; 257 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 258 "pm", "pclk", "aclk"; 259 status = "disabled"; 260 261 pcie0_intc: interrupt-controller { 262 interrupt-controller; 263 #address-cells = <0>; 264 #interrupt-cells = <1>; 265 }; 266 }; 267 268 pcie0_ep: pcie-ep@f8000000 { 269 compatible = "rockchip,rk3399-pcie-ep"; 270 reg = <0x0 0xfd000000 0x0 0x1000000>, 271 <0x0 0xfa000000 0x0 0x2000000>; 272 reg-names = "apb-base", "mem-base"; 273 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 274 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 275 clock-names = "aclk", "aclk-perf", 276 "hclk", "pm"; 277 max-functions = /bits/ 8 <8>; 278 num-lanes = <4>; 279 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 280 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 281 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 282 <&cru SRST_A_PCIE>; 283 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 284 "pm", "pclk", "aclk"; 285 phys = <&pcie_phy 0>, <&pcie_phy 1>, 286 <&pcie_phy 2>, <&pcie_phy 3>; 287 phy-names = "pcie-phy-0", "pcie-phy-1", 288 "pcie-phy-2", "pcie-phy-3"; 289 rockchip,max-outbound-regions = <32>; 290 pinctrl-names = "default"; 291 pinctrl-0 = <&pcie_clkreqnb_cpm>; 292 status = "disabled"; 293 }; 294 295 gmac: ethernet@fe300000 { 296 compatible = "rockchip,rk3399-gmac"; 297 reg = <0x0 0xfe300000 0x0 0x10000>; 298 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 299 interrupt-names = "macirq"; 300 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 301 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 302 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 303 <&cru PCLK_GMAC>; 304 clock-names = "stmmaceth", "mac_clk_rx", 305 "mac_clk_tx", "clk_mac_ref", 306 "clk_mac_refout", "aclk_mac", 307 "pclk_mac"; 308 power-domains = <&power RK3399_PD_GMAC>; 309 resets = <&cru SRST_A_GMAC>; 310 reset-names = "stmmaceth"; 311 rockchip,grf = <&grf>; 312 snps,txpbl = <0x4>; 313 status = "disabled"; 314 }; 315 316 sdio0: mmc@fe310000 { 317 compatible = "rockchip,rk3399-dw-mshc", 318 "rockchip,rk3288-dw-mshc"; 319 reg = <0x0 0xfe310000 0x0 0x4000>; 320 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 321 max-frequency = <150000000>; 322 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 323 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 324 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 325 fifo-depth = <0x100>; 326 power-domains = <&power RK3399_PD_SDIOAUDIO>; 327 resets = <&cru SRST_SDIO0>; 328 reset-names = "reset"; 329 status = "disabled"; 330 }; 331 332 sdmmc: mmc@fe320000 { 333 compatible = "rockchip,rk3399-dw-mshc", 334 "rockchip,rk3288-dw-mshc"; 335 reg = <0x0 0xfe320000 0x0 0x4000>; 336 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 337 max-frequency = <150000000>; 338 assigned-clocks = <&cru HCLK_SD>; 339 assigned-clock-rates = <200000000>; 340 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 341 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 342 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 343 fifo-depth = <0x100>; 344 power-domains = <&power RK3399_PD_SD>; 345 resets = <&cru SRST_SDMMC>; 346 reset-names = "reset"; 347 status = "disabled"; 348 }; 349 350 sdhci: mmc@fe330000 { 351 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 352 reg = <0x0 0xfe330000 0x0 0x10000>; 353 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 354 arasan,soc-ctl-syscon = <&grf>; 355 assigned-clocks = <&cru SCLK_EMMC>; 356 assigned-clock-rates = <200000000>; 357 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 358 clock-names = "clk_xin", "clk_ahb"; 359 clock-output-names = "emmc_cardclock"; 360 #clock-cells = <0>; 361 phys = <&emmc_phy>; 362 phy-names = "phy_arasan"; 363 power-domains = <&power RK3399_PD_EMMC>; 364 disable-cqe-dcmd; 365 status = "disabled"; 366 }; 367 368 usb_host0_ehci: usb@fe380000 { 369 compatible = "generic-ehci"; 370 reg = <0x0 0xfe380000 0x0 0x20000>; 371 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 372 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 373 <&u2phy0>; 374 phys = <&u2phy0_host>; 375 phy-names = "usb"; 376 status = "disabled"; 377 }; 378 379 usb_host0_ohci: usb@fe3a0000 { 380 compatible = "generic-ohci"; 381 reg = <0x0 0xfe3a0000 0x0 0x20000>; 382 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 383 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 384 <&u2phy0>; 385 phys = <&u2phy0_host>; 386 phy-names = "usb"; 387 status = "disabled"; 388 }; 389 390 usb_host1_ehci: usb@fe3c0000 { 391 compatible = "generic-ehci"; 392 reg = <0x0 0xfe3c0000 0x0 0x20000>; 393 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 394 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 395 <&u2phy1>; 396 phys = <&u2phy1_host>; 397 phy-names = "usb"; 398 status = "disabled"; 399 }; 400 401 usb_host1_ohci: usb@fe3e0000 { 402 compatible = "generic-ohci"; 403 reg = <0x0 0xfe3e0000 0x0 0x20000>; 404 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 405 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 406 <&u2phy1>; 407 phys = <&u2phy1_host>; 408 phy-names = "usb"; 409 status = "disabled"; 410 }; 411 412 debug@fe430000 { 413 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 414 reg = <0 0xfe430000 0 0x1000>; 415 clocks = <&cru PCLK_COREDBG_L>; 416 clock-names = "apb_pclk"; 417 cpu = <&cpu_l0>; 418 }; 419 420 debug@fe432000 { 421 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 422 reg = <0 0xfe432000 0 0x1000>; 423 clocks = <&cru PCLK_COREDBG_L>; 424 clock-names = "apb_pclk"; 425 cpu = <&cpu_l1>; 426 }; 427 428 debug@fe434000 { 429 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 430 reg = <0 0xfe434000 0 0x1000>; 431 clocks = <&cru PCLK_COREDBG_L>; 432 clock-names = "apb_pclk"; 433 cpu = <&cpu_l2>; 434 }; 435 436 debug@fe436000 { 437 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 438 reg = <0 0xfe436000 0 0x1000>; 439 clocks = <&cru PCLK_COREDBG_L>; 440 clock-names = "apb_pclk"; 441 cpu = <&cpu_l3>; 442 }; 443 444 debug@fe610000 { 445 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 446 reg = <0 0xfe610000 0 0x1000>; 447 clocks = <&cru PCLK_COREDBG_B>; 448 clock-names = "apb_pclk"; 449 cpu = <&cpu_b0>; 450 }; 451 452 debug@fe710000 { 453 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 454 reg = <0 0xfe710000 0 0x1000>; 455 clocks = <&cru PCLK_COREDBG_B>; 456 clock-names = "apb_pclk"; 457 cpu = <&cpu_b1>; 458 }; 459 460 usbdrd3_0: usb@fe800000 { 461 compatible = "rockchip,rk3399-dwc3"; 462 #address-cells = <2>; 463 #size-cells = <2>; 464 ranges; 465 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 466 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 467 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 468 clock-names = "ref_clk", "suspend_clk", 469 "bus_clk", "aclk_usb3_rksoc_axi_perf", 470 "aclk_usb3", "grf_clk"; 471 resets = <&cru SRST_A_USB3_OTG0>; 472 reset-names = "usb3-otg"; 473 status = "disabled"; 474 475 usbdrd_dwc3_0: usb@fe800000 { 476 compatible = "snps,dwc3"; 477 reg = <0x0 0xfe800000 0x0 0x100000>; 478 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 479 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, 480 <&cru SCLK_USB3OTG0_SUSPEND>; 481 clock-names = "ref", "bus_early", "suspend"; 482 dr_mode = "otg"; 483 phys = <&u2phy0_otg>, <&tcphy0_usb3>; 484 phy-names = "usb2-phy", "usb3-phy"; 485 phy_type = "utmi_wide"; 486 snps,dis_enblslpm_quirk; 487 snps,dis-u2-freeclk-exists-quirk; 488 snps,dis_u2_susphy_quirk; 489 snps,dis-del-phy-power-chg-quirk; 490 snps,dis-tx-ipgap-linecheck-quirk; 491 power-domains = <&power RK3399_PD_USB3>; 492 status = "disabled"; 493 }; 494 }; 495 496 usbdrd3_1: usb@fe900000 { 497 compatible = "rockchip,rk3399-dwc3"; 498 #address-cells = <2>; 499 #size-cells = <2>; 500 ranges; 501 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, 502 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 503 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 504 clock-names = "ref_clk", "suspend_clk", 505 "bus_clk", "aclk_usb3_rksoc_axi_perf", 506 "aclk_usb3", "grf_clk"; 507 resets = <&cru SRST_A_USB3_OTG1>; 508 reset-names = "usb3-otg"; 509 status = "disabled"; 510 511 usbdrd_dwc3_1: usb@fe900000 { 512 compatible = "snps,dwc3"; 513 reg = <0x0 0xfe900000 0x0 0x100000>; 514 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 515 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>, 516 <&cru SCLK_USB3OTG1_SUSPEND>; 517 clock-names = "ref", "bus_early", "suspend"; 518 dr_mode = "otg"; 519 phys = <&u2phy1_otg>, <&tcphy1_usb3>; 520 phy-names = "usb2-phy", "usb3-phy"; 521 phy_type = "utmi_wide"; 522 snps,dis_enblslpm_quirk; 523 snps,dis-u2-freeclk-exists-quirk; 524 snps,dis_u2_susphy_quirk; 525 snps,dis-del-phy-power-chg-quirk; 526 snps,dis-tx-ipgap-linecheck-quirk; 527 power-domains = <&power RK3399_PD_USB3>; 528 status = "disabled"; 529 }; 530 }; 531 532 cdn_dp: dp@fec00000 { 533 compatible = "rockchip,rk3399-cdn-dp"; 534 reg = <0x0 0xfec00000 0x0 0x100000>; 535 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 536 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>; 537 assigned-clock-rates = <100000000>, <200000000>; 538 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, 539 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; 540 clock-names = "core-clk", "pclk", "spdif", "grf"; 541 phys = <&tcphy0_dp>, <&tcphy1_dp>; 542 power-domains = <&power RK3399_PD_HDCP>; 543 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, 544 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; 545 reset-names = "spdif", "dptx", "apb", "core"; 546 rockchip,grf = <&grf>; 547 #sound-dai-cells = <1>; 548 status = "disabled"; 549 550 ports { 551 dp_in: port { 552 #address-cells = <1>; 553 #size-cells = <0>; 554 555 dp_in_vopb: endpoint@0 { 556 reg = <0>; 557 remote-endpoint = <&vopb_out_dp>; 558 }; 559 560 dp_in_vopl: endpoint@1 { 561 reg = <1>; 562 remote-endpoint = <&vopl_out_dp>; 563 }; 564 }; 565 }; 566 }; 567 568 gic: interrupt-controller@fee00000 { 569 compatible = "arm,gic-v3"; 570 #interrupt-cells = <4>; 571 #address-cells = <2>; 572 #size-cells = <2>; 573 ranges; 574 interrupt-controller; 575 576 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 577 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 578 <0x0 0xfff00000 0 0x10000>, /* GICC */ 579 <0x0 0xfff10000 0 0x10000>, /* GICH */ 580 <0x0 0xfff20000 0 0x10000>; /* GICV */ 581 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 582 its: msi-controller@fee20000 { 583 compatible = "arm,gic-v3-its"; 584 msi-controller; 585 #msi-cells = <1>; 586 reg = <0x0 0xfee20000 0x0 0x20000>; 587 }; 588 589 ppi-partitions { 590 ppi_cluster0: interrupt-partition-0 { 591 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 592 }; 593 594 ppi_cluster1: interrupt-partition-1 { 595 affinity = <&cpu_b0 &cpu_b1>; 596 }; 597 }; 598 }; 599 600 saradc: saradc@ff100000 { 601 compatible = "rockchip,rk3399-saradc"; 602 reg = <0x0 0xff100000 0x0 0x100>; 603 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 604 #io-channel-cells = <1>; 605 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 606 clock-names = "saradc", "apb_pclk"; 607 resets = <&cru SRST_P_SARADC>; 608 reset-names = "saradc-apb"; 609 status = "disabled"; 610 }; 611 612 crypto0: crypto@ff8b0000 { 613 compatible = "rockchip,rk3399-crypto"; 614 reg = <0x0 0xff8b0000 0x0 0x4000>; 615 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>; 616 clocks = <&cru HCLK_M_CRYPTO0>, <&cru HCLK_S_CRYPTO0>, <&cru SCLK_CRYPTO0>; 617 clock-names = "hclk_master", "hclk_slave", "sclk"; 618 resets = <&cru SRST_CRYPTO0>, <&cru SRST_CRYPTO0_S>, <&cru SRST_CRYPTO0_M>; 619 reset-names = "master", "slave", "crypto-rst"; 620 }; 621 622 crypto1: crypto@ff8b8000 { 623 compatible = "rockchip,rk3399-crypto"; 624 reg = <0x0 0xff8b8000 0x0 0x4000>; 625 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 626 clocks = <&cru HCLK_M_CRYPTO1>, <&cru HCLK_S_CRYPTO1>, <&cru SCLK_CRYPTO1>; 627 clock-names = "hclk_master", "hclk_slave", "sclk"; 628 resets = <&cru SRST_CRYPTO1>, <&cru SRST_CRYPTO1_S>, <&cru SRST_CRYPTO1_M>; 629 reset-names = "master", "slave", "crypto-rst"; 630 }; 631 632 i2c1: i2c@ff110000 { 633 compatible = "rockchip,rk3399-i2c"; 634 reg = <0x0 0xff110000 0x0 0x1000>; 635 assigned-clocks = <&cru SCLK_I2C1>; 636 assigned-clock-rates = <200000000>; 637 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 638 clock-names = "i2c", "pclk"; 639 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 640 pinctrl-names = "default"; 641 pinctrl-0 = <&i2c1_xfer>; 642 #address-cells = <1>; 643 #size-cells = <0>; 644 status = "disabled"; 645 }; 646 647 i2c2: i2c@ff120000 { 648 compatible = "rockchip,rk3399-i2c"; 649 reg = <0x0 0xff120000 0x0 0x1000>; 650 assigned-clocks = <&cru SCLK_I2C2>; 651 assigned-clock-rates = <200000000>; 652 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 653 clock-names = "i2c", "pclk"; 654 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 655 pinctrl-names = "default"; 656 pinctrl-0 = <&i2c2_xfer>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 status = "disabled"; 660 }; 661 662 i2c3: i2c@ff130000 { 663 compatible = "rockchip,rk3399-i2c"; 664 reg = <0x0 0xff130000 0x0 0x1000>; 665 assigned-clocks = <&cru SCLK_I2C3>; 666 assigned-clock-rates = <200000000>; 667 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 668 clock-names = "i2c", "pclk"; 669 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 670 pinctrl-names = "default"; 671 pinctrl-0 = <&i2c3_xfer>; 672 #address-cells = <1>; 673 #size-cells = <0>; 674 status = "disabled"; 675 }; 676 677 i2c5: i2c@ff140000 { 678 compatible = "rockchip,rk3399-i2c"; 679 reg = <0x0 0xff140000 0x0 0x1000>; 680 assigned-clocks = <&cru SCLK_I2C5>; 681 assigned-clock-rates = <200000000>; 682 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 683 clock-names = "i2c", "pclk"; 684 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 685 pinctrl-names = "default"; 686 pinctrl-0 = <&i2c5_xfer>; 687 #address-cells = <1>; 688 #size-cells = <0>; 689 status = "disabled"; 690 }; 691 692 i2c6: i2c@ff150000 { 693 compatible = "rockchip,rk3399-i2c"; 694 reg = <0x0 0xff150000 0x0 0x1000>; 695 assigned-clocks = <&cru SCLK_I2C6>; 696 assigned-clock-rates = <200000000>; 697 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 698 clock-names = "i2c", "pclk"; 699 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 700 pinctrl-names = "default"; 701 pinctrl-0 = <&i2c6_xfer>; 702 #address-cells = <1>; 703 #size-cells = <0>; 704 status = "disabled"; 705 }; 706 707 i2c7: i2c@ff160000 { 708 compatible = "rockchip,rk3399-i2c"; 709 reg = <0x0 0xff160000 0x0 0x1000>; 710 assigned-clocks = <&cru SCLK_I2C7>; 711 assigned-clock-rates = <200000000>; 712 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 713 clock-names = "i2c", "pclk"; 714 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 715 pinctrl-names = "default"; 716 pinctrl-0 = <&i2c7_xfer>; 717 #address-cells = <1>; 718 #size-cells = <0>; 719 status = "disabled"; 720 }; 721 722 uart0: serial@ff180000 { 723 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 724 reg = <0x0 0xff180000 0x0 0x100>; 725 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 726 clock-names = "baudclk", "apb_pclk"; 727 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 728 reg-shift = <2>; 729 reg-io-width = <4>; 730 pinctrl-names = "default"; 731 pinctrl-0 = <&uart0_xfer>; 732 status = "disabled"; 733 }; 734 735 uart1: serial@ff190000 { 736 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 737 reg = <0x0 0xff190000 0x0 0x100>; 738 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 739 clock-names = "baudclk", "apb_pclk"; 740 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 741 reg-shift = <2>; 742 reg-io-width = <4>; 743 pinctrl-names = "default"; 744 pinctrl-0 = <&uart1_xfer>; 745 status = "disabled"; 746 }; 747 748 uart2: serial@ff1a0000 { 749 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 750 reg = <0x0 0xff1a0000 0x0 0x100>; 751 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 752 clock-names = "baudclk", "apb_pclk"; 753 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 754 reg-shift = <2>; 755 reg-io-width = <4>; 756 pinctrl-names = "default"; 757 pinctrl-0 = <&uart2c_xfer>; 758 status = "disabled"; 759 }; 760 761 uart3: serial@ff1b0000 { 762 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 763 reg = <0x0 0xff1b0000 0x0 0x100>; 764 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 765 clock-names = "baudclk", "apb_pclk"; 766 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 767 reg-shift = <2>; 768 reg-io-width = <4>; 769 pinctrl-names = "default"; 770 pinctrl-0 = <&uart3_xfer>; 771 status = "disabled"; 772 }; 773 774 spi0: spi@ff1c0000 { 775 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 776 reg = <0x0 0xff1c0000 0x0 0x1000>; 777 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 778 clock-names = "spiclk", "apb_pclk"; 779 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 780 dmas = <&dmac_peri 10>, <&dmac_peri 11>; 781 dma-names = "tx", "rx"; 782 pinctrl-names = "default"; 783 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 784 #address-cells = <1>; 785 #size-cells = <0>; 786 status = "disabled"; 787 }; 788 789 spi1: spi@ff1d0000 { 790 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 791 reg = <0x0 0xff1d0000 0x0 0x1000>; 792 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 793 clock-names = "spiclk", "apb_pclk"; 794 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 795 dmas = <&dmac_peri 12>, <&dmac_peri 13>; 796 dma-names = "tx", "rx"; 797 pinctrl-names = "default"; 798 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 799 #address-cells = <1>; 800 #size-cells = <0>; 801 status = "disabled"; 802 }; 803 804 spi2: spi@ff1e0000 { 805 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 806 reg = <0x0 0xff1e0000 0x0 0x1000>; 807 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 808 clock-names = "spiclk", "apb_pclk"; 809 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 810 dmas = <&dmac_peri 14>, <&dmac_peri 15>; 811 dma-names = "tx", "rx"; 812 pinctrl-names = "default"; 813 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 814 #address-cells = <1>; 815 #size-cells = <0>; 816 status = "disabled"; 817 }; 818 819 spi4: spi@ff1f0000 { 820 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 821 reg = <0x0 0xff1f0000 0x0 0x1000>; 822 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 823 clock-names = "spiclk", "apb_pclk"; 824 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 825 dmas = <&dmac_peri 18>, <&dmac_peri 19>; 826 dma-names = "tx", "rx"; 827 pinctrl-names = "default"; 828 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 829 #address-cells = <1>; 830 #size-cells = <0>; 831 status = "disabled"; 832 }; 833 834 spi5: spi@ff200000 { 835 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 836 reg = <0x0 0xff200000 0x0 0x1000>; 837 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 838 clock-names = "spiclk", "apb_pclk"; 839 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 840 dmas = <&dmac_bus 8>, <&dmac_bus 9>; 841 dma-names = "tx", "rx"; 842 pinctrl-names = "default"; 843 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 844 power-domains = <&power RK3399_PD_SDIOAUDIO>; 845 #address-cells = <1>; 846 #size-cells = <0>; 847 status = "disabled"; 848 }; 849 850 thermal_zones: thermal-zones { 851 cpu_thermal: cpu-thermal { 852 polling-delay-passive = <100>; 853 polling-delay = <1000>; 854 855 thermal-sensors = <&tsadc 0>; 856 857 trips { 858 cpu_alert0: cpu_alert0 { 859 temperature = <70000>; 860 hysteresis = <2000>; 861 type = "passive"; 862 }; 863 cpu_alert1: cpu_alert1 { 864 temperature = <75000>; 865 hysteresis = <2000>; 866 type = "passive"; 867 }; 868 cpu_crit: cpu_crit { 869 temperature = <95000>; 870 hysteresis = <2000>; 871 type = "critical"; 872 }; 873 }; 874 875 cooling-maps { 876 map0 { 877 trip = <&cpu_alert0>; 878 cooling-device = 879 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 880 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 881 }; 882 map1 { 883 trip = <&cpu_alert1>; 884 cooling-device = 885 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 886 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 887 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 888 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 889 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 890 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 891 }; 892 }; 893 }; 894 895 gpu_thermal: gpu-thermal { 896 polling-delay-passive = <100>; 897 polling-delay = <1000>; 898 899 thermal-sensors = <&tsadc 1>; 900 901 trips { 902 gpu_alert0: gpu_alert0 { 903 temperature = <75000>; 904 hysteresis = <2000>; 905 type = "passive"; 906 }; 907 gpu_crit: gpu_crit { 908 temperature = <95000>; 909 hysteresis = <2000>; 910 type = "critical"; 911 }; 912 }; 913 914 cooling-maps { 915 map0 { 916 trip = <&gpu_alert0>; 917 cooling-device = 918 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 919 }; 920 }; 921 }; 922 }; 923 924 tsadc: tsadc@ff260000 { 925 compatible = "rockchip,rk3399-tsadc"; 926 reg = <0x0 0xff260000 0x0 0x100>; 927 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 928 assigned-clocks = <&cru SCLK_TSADC>; 929 assigned-clock-rates = <750000>; 930 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 931 clock-names = "tsadc", "apb_pclk"; 932 resets = <&cru SRST_TSADC>; 933 reset-names = "tsadc-apb"; 934 rockchip,grf = <&grf>; 935 rockchip,hw-tshut-temp = <95000>; 936 pinctrl-names = "init", "default", "sleep"; 937 pinctrl-0 = <&otp_pin>; 938 pinctrl-1 = <&otp_out>; 939 pinctrl-2 = <&otp_pin>; 940 #thermal-sensor-cells = <1>; 941 status = "disabled"; 942 }; 943 944 qos_emmc: qos@ffa58000 { 945 compatible = "rockchip,rk3399-qos", "syscon"; 946 reg = <0x0 0xffa58000 0x0 0x20>; 947 }; 948 949 qos_gmac: qos@ffa5c000 { 950 compatible = "rockchip,rk3399-qos", "syscon"; 951 reg = <0x0 0xffa5c000 0x0 0x20>; 952 }; 953 954 qos_pcie: qos@ffa60080 { 955 compatible = "rockchip,rk3399-qos", "syscon"; 956 reg = <0x0 0xffa60080 0x0 0x20>; 957 }; 958 959 qos_usb_host0: qos@ffa60100 { 960 compatible = "rockchip,rk3399-qos", "syscon"; 961 reg = <0x0 0xffa60100 0x0 0x20>; 962 }; 963 964 qos_usb_host1: qos@ffa60180 { 965 compatible = "rockchip,rk3399-qos", "syscon"; 966 reg = <0x0 0xffa60180 0x0 0x20>; 967 }; 968 969 qos_usb_otg0: qos@ffa70000 { 970 compatible = "rockchip,rk3399-qos", "syscon"; 971 reg = <0x0 0xffa70000 0x0 0x20>; 972 }; 973 974 qos_usb_otg1: qos@ffa70080 { 975 compatible = "rockchip,rk3399-qos", "syscon"; 976 reg = <0x0 0xffa70080 0x0 0x20>; 977 }; 978 979 qos_sd: qos@ffa74000 { 980 compatible = "rockchip,rk3399-qos", "syscon"; 981 reg = <0x0 0xffa74000 0x0 0x20>; 982 }; 983 984 qos_sdioaudio: qos@ffa76000 { 985 compatible = "rockchip,rk3399-qos", "syscon"; 986 reg = <0x0 0xffa76000 0x0 0x20>; 987 }; 988 989 qos_hdcp: qos@ffa90000 { 990 compatible = "rockchip,rk3399-qos", "syscon"; 991 reg = <0x0 0xffa90000 0x0 0x20>; 992 }; 993 994 qos_iep: qos@ffa98000 { 995 compatible = "rockchip,rk3399-qos", "syscon"; 996 reg = <0x0 0xffa98000 0x0 0x20>; 997 }; 998 999 qos_isp0_m0: qos@ffaa0000 { 1000 compatible = "rockchip,rk3399-qos", "syscon"; 1001 reg = <0x0 0xffaa0000 0x0 0x20>; 1002 }; 1003 1004 qos_isp0_m1: qos@ffaa0080 { 1005 compatible = "rockchip,rk3399-qos", "syscon"; 1006 reg = <0x0 0xffaa0080 0x0 0x20>; 1007 }; 1008 1009 qos_isp1_m0: qos@ffaa8000 { 1010 compatible = "rockchip,rk3399-qos", "syscon"; 1011 reg = <0x0 0xffaa8000 0x0 0x20>; 1012 }; 1013 1014 qos_isp1_m1: qos@ffaa8080 { 1015 compatible = "rockchip,rk3399-qos", "syscon"; 1016 reg = <0x0 0xffaa8080 0x0 0x20>; 1017 }; 1018 1019 qos_rga_r: qos@ffab0000 { 1020 compatible = "rockchip,rk3399-qos", "syscon"; 1021 reg = <0x0 0xffab0000 0x0 0x20>; 1022 }; 1023 1024 qos_rga_w: qos@ffab0080 { 1025 compatible = "rockchip,rk3399-qos", "syscon"; 1026 reg = <0x0 0xffab0080 0x0 0x20>; 1027 }; 1028 1029 qos_video_m0: qos@ffab8000 { 1030 compatible = "rockchip,rk3399-qos", "syscon"; 1031 reg = <0x0 0xffab8000 0x0 0x20>; 1032 }; 1033 1034 qos_video_m1_r: qos@ffac0000 { 1035 compatible = "rockchip,rk3399-qos", "syscon"; 1036 reg = <0x0 0xffac0000 0x0 0x20>; 1037 }; 1038 1039 qos_video_m1_w: qos@ffac0080 { 1040 compatible = "rockchip,rk3399-qos", "syscon"; 1041 reg = <0x0 0xffac0080 0x0 0x20>; 1042 }; 1043 1044 qos_vop_big_r: qos@ffac8000 { 1045 compatible = "rockchip,rk3399-qos", "syscon"; 1046 reg = <0x0 0xffac8000 0x0 0x20>; 1047 }; 1048 1049 qos_vop_big_w: qos@ffac8080 { 1050 compatible = "rockchip,rk3399-qos", "syscon"; 1051 reg = <0x0 0xffac8080 0x0 0x20>; 1052 }; 1053 1054 qos_vop_little: qos@ffad0000 { 1055 compatible = "rockchip,rk3399-qos", "syscon"; 1056 reg = <0x0 0xffad0000 0x0 0x20>; 1057 }; 1058 1059 qos_perihp: qos@ffad8080 { 1060 compatible = "rockchip,rk3399-qos", "syscon"; 1061 reg = <0x0 0xffad8080 0x0 0x20>; 1062 }; 1063 1064 qos_gpu: qos@ffae0000 { 1065 compatible = "rockchip,rk3399-qos", "syscon"; 1066 reg = <0x0 0xffae0000 0x0 0x20>; 1067 }; 1068 1069 pmu: power-management@ff310000 { 1070 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 1071 reg = <0x0 0xff310000 0x0 0x1000>; 1072 1073 /* 1074 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 1075 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 1076 * Some of the power domains are grouped together for every 1077 * voltage domain. 1078 * The detail contents as below. 1079 */ 1080 power: power-controller { 1081 compatible = "rockchip,rk3399-power-controller"; 1082 #power-domain-cells = <1>; 1083 #address-cells = <1>; 1084 #size-cells = <0>; 1085 1086 /* These power domains are grouped by VD_CENTER */ 1087 power-domain@RK3399_PD_IEP { 1088 reg = <RK3399_PD_IEP>; 1089 clocks = <&cru ACLK_IEP>, 1090 <&cru HCLK_IEP>; 1091 pm_qos = <&qos_iep>; 1092 #power-domain-cells = <0>; 1093 }; 1094 power-domain@RK3399_PD_RGA { 1095 reg = <RK3399_PD_RGA>; 1096 clocks = <&cru ACLK_RGA>, 1097 <&cru HCLK_RGA>; 1098 pm_qos = <&qos_rga_r>, 1099 <&qos_rga_w>; 1100 #power-domain-cells = <0>; 1101 }; 1102 power-domain@RK3399_PD_VCODEC { 1103 reg = <RK3399_PD_VCODEC>; 1104 clocks = <&cru ACLK_VCODEC>, 1105 <&cru HCLK_VCODEC>; 1106 pm_qos = <&qos_video_m0>; 1107 #power-domain-cells = <0>; 1108 }; 1109 power-domain@RK3399_PD_VDU { 1110 reg = <RK3399_PD_VDU>; 1111 clocks = <&cru ACLK_VDU>, 1112 <&cru HCLK_VDU>; 1113 pm_qos = <&qos_video_m1_r>, 1114 <&qos_video_m1_w>; 1115 #power-domain-cells = <0>; 1116 }; 1117 1118 /* These power domains are grouped by VD_GPU */ 1119 power-domain@RK3399_PD_GPU { 1120 reg = <RK3399_PD_GPU>; 1121 clocks = <&cru ACLK_GPU>; 1122 pm_qos = <&qos_gpu>; 1123 #power-domain-cells = <0>; 1124 }; 1125 1126 /* These power domains are grouped by VD_LOGIC */ 1127 power-domain@RK3399_PD_EDP { 1128 reg = <RK3399_PD_EDP>; 1129 clocks = <&cru PCLK_EDP_CTRL>; 1130 #power-domain-cells = <0>; 1131 }; 1132 power-domain@RK3399_PD_EMMC { 1133 reg = <RK3399_PD_EMMC>; 1134 clocks = <&cru ACLK_EMMC>; 1135 pm_qos = <&qos_emmc>; 1136 #power-domain-cells = <0>; 1137 }; 1138 power-domain@RK3399_PD_GMAC { 1139 reg = <RK3399_PD_GMAC>; 1140 clocks = <&cru ACLK_GMAC>, 1141 <&cru PCLK_GMAC>; 1142 pm_qos = <&qos_gmac>; 1143 #power-domain-cells = <0>; 1144 }; 1145 power-domain@RK3399_PD_SD { 1146 reg = <RK3399_PD_SD>; 1147 clocks = <&cru HCLK_SDMMC>, 1148 <&cru SCLK_SDMMC>; 1149 pm_qos = <&qos_sd>; 1150 #power-domain-cells = <0>; 1151 }; 1152 power-domain@RK3399_PD_SDIOAUDIO { 1153 reg = <RK3399_PD_SDIOAUDIO>; 1154 clocks = <&cru HCLK_SDIO>; 1155 pm_qos = <&qos_sdioaudio>; 1156 #power-domain-cells = <0>; 1157 }; 1158 power-domain@RK3399_PD_TCPD0 { 1159 reg = <RK3399_PD_TCPD0>; 1160 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1161 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1162 #power-domain-cells = <0>; 1163 }; 1164 power-domain@RK3399_PD_TCPD1 { 1165 reg = <RK3399_PD_TCPD1>; 1166 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1167 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1168 #power-domain-cells = <0>; 1169 }; 1170 power-domain@RK3399_PD_USB3 { 1171 reg = <RK3399_PD_USB3>; 1172 clocks = <&cru ACLK_USB3>; 1173 pm_qos = <&qos_usb_otg0>, 1174 <&qos_usb_otg1>; 1175 #power-domain-cells = <0>; 1176 }; 1177 power-domain@RK3399_PD_VIO { 1178 reg = <RK3399_PD_VIO>; 1179 #power-domain-cells = <1>; 1180 #address-cells = <1>; 1181 #size-cells = <0>; 1182 1183 power-domain@RK3399_PD_HDCP { 1184 reg = <RK3399_PD_HDCP>; 1185 clocks = <&cru ACLK_HDCP>, 1186 <&cru HCLK_HDCP>, 1187 <&cru PCLK_HDCP>; 1188 pm_qos = <&qos_hdcp>; 1189 #power-domain-cells = <0>; 1190 }; 1191 power-domain@RK3399_PD_ISP0 { 1192 reg = <RK3399_PD_ISP0>; 1193 clocks = <&cru ACLK_ISP0>, 1194 <&cru HCLK_ISP0>; 1195 pm_qos = <&qos_isp0_m0>, 1196 <&qos_isp0_m1>; 1197 #power-domain-cells = <0>; 1198 }; 1199 power-domain@RK3399_PD_ISP1 { 1200 reg = <RK3399_PD_ISP1>; 1201 clocks = <&cru ACLK_ISP1>, 1202 <&cru HCLK_ISP1>; 1203 pm_qos = <&qos_isp1_m0>, 1204 <&qos_isp1_m1>; 1205 #power-domain-cells = <0>; 1206 }; 1207 power-domain@RK3399_PD_VO { 1208 reg = <RK3399_PD_VO>; 1209 #power-domain-cells = <1>; 1210 #address-cells = <1>; 1211 #size-cells = <0>; 1212 1213 power-domain@RK3399_PD_VOPB { 1214 reg = <RK3399_PD_VOPB>; 1215 clocks = <&cru ACLK_VOP0>, 1216 <&cru HCLK_VOP0>; 1217 pm_qos = <&qos_vop_big_r>, 1218 <&qos_vop_big_w>; 1219 #power-domain-cells = <0>; 1220 }; 1221 power-domain@RK3399_PD_VOPL { 1222 reg = <RK3399_PD_VOPL>; 1223 clocks = <&cru ACLK_VOP1>, 1224 <&cru HCLK_VOP1>; 1225 pm_qos = <&qos_vop_little>; 1226 #power-domain-cells = <0>; 1227 }; 1228 }; 1229 }; 1230 }; 1231 }; 1232 1233 pmugrf: syscon@ff320000 { 1234 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1235 reg = <0x0 0xff320000 0x0 0x1000>; 1236 1237 pmu_io_domains: io-domains { 1238 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1239 status = "disabled"; 1240 }; 1241 }; 1242 1243 spi3: spi@ff350000 { 1244 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1245 reg = <0x0 0xff350000 0x0 0x1000>; 1246 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1247 clock-names = "spiclk", "apb_pclk"; 1248 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1249 pinctrl-names = "default"; 1250 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1251 #address-cells = <1>; 1252 #size-cells = <0>; 1253 status = "disabled"; 1254 }; 1255 1256 uart4: serial@ff370000 { 1257 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1258 reg = <0x0 0xff370000 0x0 0x100>; 1259 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1260 clock-names = "baudclk", "apb_pclk"; 1261 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1262 reg-shift = <2>; 1263 reg-io-width = <4>; 1264 pinctrl-names = "default"; 1265 pinctrl-0 = <&uart4_xfer>; 1266 status = "disabled"; 1267 }; 1268 1269 i2c0: i2c@ff3c0000 { 1270 compatible = "rockchip,rk3399-i2c"; 1271 reg = <0x0 0xff3c0000 0x0 0x1000>; 1272 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1273 assigned-clock-rates = <200000000>; 1274 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1275 clock-names = "i2c", "pclk"; 1276 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1277 pinctrl-names = "default"; 1278 pinctrl-0 = <&i2c0_xfer>; 1279 #address-cells = <1>; 1280 #size-cells = <0>; 1281 status = "disabled"; 1282 }; 1283 1284 i2c4: i2c@ff3d0000 { 1285 compatible = "rockchip,rk3399-i2c"; 1286 reg = <0x0 0xff3d0000 0x0 0x1000>; 1287 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1288 assigned-clock-rates = <200000000>; 1289 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1290 clock-names = "i2c", "pclk"; 1291 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1292 pinctrl-names = "default"; 1293 pinctrl-0 = <&i2c4_xfer>; 1294 #address-cells = <1>; 1295 #size-cells = <0>; 1296 status = "disabled"; 1297 }; 1298 1299 i2c8: i2c@ff3e0000 { 1300 compatible = "rockchip,rk3399-i2c"; 1301 reg = <0x0 0xff3e0000 0x0 0x1000>; 1302 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1303 assigned-clock-rates = <200000000>; 1304 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1305 clock-names = "i2c", "pclk"; 1306 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1307 pinctrl-names = "default"; 1308 pinctrl-0 = <&i2c8_xfer>; 1309 #address-cells = <1>; 1310 #size-cells = <0>; 1311 status = "disabled"; 1312 }; 1313 1314 pwm0: pwm@ff420000 { 1315 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1316 reg = <0x0 0xff420000 0x0 0x10>; 1317 #pwm-cells = <3>; 1318 pinctrl-names = "default"; 1319 pinctrl-0 = <&pwm0_pin>; 1320 clocks = <&pmucru PCLK_RKPWM_PMU>; 1321 status = "disabled"; 1322 }; 1323 1324 pwm1: pwm@ff420010 { 1325 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1326 reg = <0x0 0xff420010 0x0 0x10>; 1327 #pwm-cells = <3>; 1328 pinctrl-names = "default"; 1329 pinctrl-0 = <&pwm1_pin>; 1330 clocks = <&pmucru PCLK_RKPWM_PMU>; 1331 status = "disabled"; 1332 }; 1333 1334 pwm2: pwm@ff420020 { 1335 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1336 reg = <0x0 0xff420020 0x0 0x10>; 1337 #pwm-cells = <3>; 1338 pinctrl-names = "default"; 1339 pinctrl-0 = <&pwm2_pin>; 1340 clocks = <&pmucru PCLK_RKPWM_PMU>; 1341 status = "disabled"; 1342 }; 1343 1344 pwm3: pwm@ff420030 { 1345 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1346 reg = <0x0 0xff420030 0x0 0x10>; 1347 #pwm-cells = <3>; 1348 pinctrl-names = "default"; 1349 pinctrl-0 = <&pwm3a_pin>; 1350 clocks = <&pmucru PCLK_RKPWM_PMU>; 1351 status = "disabled"; 1352 }; 1353 1354 dfi: dfi@ff630000 { 1355 reg = <0x00 0xff630000 0x00 0x4000>; 1356 compatible = "rockchip,rk3399-dfi"; 1357 rockchip,pmu = <&pmugrf>; 1358 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1359 clocks = <&cru PCLK_DDR_MON>; 1360 clock-names = "pclk_ddr_mon"; 1361 status = "disabled"; 1362 }; 1363 1364 vpu: video-codec@ff650000 { 1365 compatible = "rockchip,rk3399-vpu"; 1366 reg = <0x0 0xff650000 0x0 0x800>; 1367 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 1368 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 1369 interrupt-names = "vepu", "vdpu"; 1370 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1371 clock-names = "aclk", "hclk"; 1372 iommus = <&vpu_mmu>; 1373 power-domains = <&power RK3399_PD_VCODEC>; 1374 }; 1375 1376 vpu_mmu: iommu@ff650800 { 1377 compatible = "rockchip,iommu"; 1378 reg = <0x0 0xff650800 0x0 0x40>; 1379 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 1380 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1381 clock-names = "aclk", "iface"; 1382 #iommu-cells = <0>; 1383 power-domains = <&power RK3399_PD_VCODEC>; 1384 }; 1385 1386 vdec: video-codec@ff660000 { 1387 compatible = "rockchip,rk3399-vdec"; 1388 reg = <0x0 0xff660000 0x0 0x400>; 1389 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1390 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, 1391 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; 1392 clock-names = "axi", "ahb", "cabac", "core"; 1393 iommus = <&vdec_mmu>; 1394 power-domains = <&power RK3399_PD_VDU>; 1395 }; 1396 1397 vdec_mmu: iommu@ff660480 { 1398 compatible = "rockchip,iommu"; 1399 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; 1400 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1401 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; 1402 clock-names = "aclk", "iface"; 1403 power-domains = <&power RK3399_PD_VDU>; 1404 #iommu-cells = <0>; 1405 }; 1406 1407 iep_mmu: iommu@ff670800 { 1408 compatible = "rockchip,iommu"; 1409 reg = <0x0 0xff670800 0x0 0x40>; 1410 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>; 1411 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 1412 clock-names = "aclk", "iface"; 1413 #iommu-cells = <0>; 1414 status = "disabled"; 1415 }; 1416 1417 rga: rga@ff680000 { 1418 compatible = "rockchip,rk3399-rga"; 1419 reg = <0x0 0xff680000 0x0 0x10000>; 1420 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>; 1421 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; 1422 clock-names = "aclk", "hclk", "sclk"; 1423 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 1424 reset-names = "core", "axi", "ahb"; 1425 power-domains = <&power RK3399_PD_RGA>; 1426 }; 1427 1428 efuse0: efuse@ff690000 { 1429 compatible = "rockchip,rk3399-efuse"; 1430 reg = <0x0 0xff690000 0x0 0x80>; 1431 #address-cells = <1>; 1432 #size-cells = <1>; 1433 clocks = <&cru PCLK_EFUSE1024NS>; 1434 clock-names = "pclk_efuse"; 1435 1436 /* Data cells */ 1437 cpu_id: cpu-id@7 { 1438 reg = <0x07 0x10>; 1439 }; 1440 cpub_leakage: cpu-leakage@17 { 1441 reg = <0x17 0x1>; 1442 }; 1443 gpu_leakage: gpu-leakage@18 { 1444 reg = <0x18 0x1>; 1445 }; 1446 center_leakage: center-leakage@19 { 1447 reg = <0x19 0x1>; 1448 }; 1449 cpul_leakage: cpu-leakage@1a { 1450 reg = <0x1a 0x1>; 1451 }; 1452 logic_leakage: logic-leakage@1b { 1453 reg = <0x1b 0x1>; 1454 }; 1455 wafer_info: wafer-info@1c { 1456 reg = <0x1c 0x1>; 1457 }; 1458 }; 1459 1460 dmac_bus: dma-controller@ff6d0000 { 1461 compatible = "arm,pl330", "arm,primecell"; 1462 reg = <0x0 0xff6d0000 0x0 0x4000>; 1463 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 1464 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 1465 #dma-cells = <1>; 1466 arm,pl330-periph-burst; 1467 clocks = <&cru ACLK_DMAC0_PERILP>; 1468 clock-names = "apb_pclk"; 1469 }; 1470 1471 dmac_peri: dma-controller@ff6e0000 { 1472 compatible = "arm,pl330", "arm,primecell"; 1473 reg = <0x0 0xff6e0000 0x0 0x4000>; 1474 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 1475 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 1476 #dma-cells = <1>; 1477 arm,pl330-periph-burst; 1478 clocks = <&cru ACLK_DMAC1_PERILP>; 1479 clock-names = "apb_pclk"; 1480 }; 1481 1482 pmucru: clock-controller@ff750000 { 1483 compatible = "rockchip,rk3399-pmucru"; 1484 reg = <0x0 0xff750000 0x0 0x1000>; 1485 clocks = <&xin24m>; 1486 clock-names = "xin24m"; 1487 rockchip,grf = <&pmugrf>; 1488 #clock-cells = <1>; 1489 #reset-cells = <1>; 1490 assigned-clocks = <&pmucru PLL_PPLL>; 1491 assigned-clock-rates = <676000000>; 1492 }; 1493 1494 cru: clock-controller@ff760000 { 1495 compatible = "rockchip,rk3399-cru"; 1496 reg = <0x0 0xff760000 0x0 0x1000>; 1497 clocks = <&xin24m>; 1498 clock-names = "xin24m"; 1499 rockchip,grf = <&grf>; 1500 #clock-cells = <1>; 1501 #reset-cells = <1>; 1502 assigned-clocks = 1503 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1504 <&cru PLL_NPLL>, 1505 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1506 <&cru PCLK_PERIHP>, 1507 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1508 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1509 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 1510 <&cru ACLK_VIO>, <&cru ACLK_HDCP>, 1511 <&cru ACLK_GIC_PRE>, 1512 <&cru PCLK_DDR>, 1513 <&cru ACLK_VDU>; 1514 assigned-clock-rates = 1515 <594000000>, <800000000>, 1516 <1000000000>, 1517 <150000000>, <75000000>, 1518 <37500000>, 1519 <100000000>, <100000000>, 1520 <50000000>, <600000000>, 1521 <100000000>, <50000000>, 1522 <400000000>, <400000000>, 1523 <200000000>, 1524 <200000000>, 1525 <400000000>; 1526 }; 1527 1528 grf: syscon@ff770000 { 1529 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1530 reg = <0x0 0xff770000 0x0 0x10000>; 1531 #address-cells = <1>; 1532 #size-cells = <1>; 1533 1534 io_domains: io-domains { 1535 compatible = "rockchip,rk3399-io-voltage-domain"; 1536 status = "disabled"; 1537 }; 1538 1539 mipi_dphy_rx0: mipi-dphy-rx0 { 1540 compatible = "rockchip,rk3399-mipi-dphy-rx0"; 1541 clocks = <&cru SCLK_MIPIDPHY_REF>, 1542 <&cru SCLK_DPHY_RX0_CFG>, 1543 <&cru PCLK_VIO_GRF>; 1544 clock-names = "dphy-ref", "dphy-cfg", "grf"; 1545 power-domains = <&power RK3399_PD_VIO>; 1546 #phy-cells = <0>; 1547 status = "disabled"; 1548 }; 1549 1550 u2phy0: usb2phy@e450 { 1551 compatible = "rockchip,rk3399-usb2phy"; 1552 reg = <0xe450 0x10>; 1553 clocks = <&cru SCLK_USB2PHY0_REF>; 1554 clock-names = "phyclk"; 1555 #clock-cells = <0>; 1556 clock-output-names = "clk_usbphy0_480m"; 1557 status = "disabled"; 1558 1559 u2phy0_host: host-port { 1560 #phy-cells = <0>; 1561 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1562 interrupt-names = "linestate"; 1563 status = "disabled"; 1564 }; 1565 1566 u2phy0_otg: otg-port { 1567 #phy-cells = <0>; 1568 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1569 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1570 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1571 interrupt-names = "otg-bvalid", "otg-id", 1572 "linestate"; 1573 status = "disabled"; 1574 }; 1575 }; 1576 1577 u2phy1: usb2phy@e460 { 1578 compatible = "rockchip,rk3399-usb2phy"; 1579 reg = <0xe460 0x10>; 1580 clocks = <&cru SCLK_USB2PHY1_REF>; 1581 clock-names = "phyclk"; 1582 #clock-cells = <0>; 1583 clock-output-names = "clk_usbphy1_480m"; 1584 status = "disabled"; 1585 1586 u2phy1_host: host-port { 1587 #phy-cells = <0>; 1588 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1589 interrupt-names = "linestate"; 1590 status = "disabled"; 1591 }; 1592 1593 u2phy1_otg: otg-port { 1594 #phy-cells = <0>; 1595 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1596 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1597 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1598 interrupt-names = "otg-bvalid", "otg-id", 1599 "linestate"; 1600 status = "disabled"; 1601 }; 1602 }; 1603 1604 emmc_phy: phy@f780 { 1605 compatible = "rockchip,rk3399-emmc-phy"; 1606 reg = <0xf780 0x24>; 1607 clocks = <&sdhci>; 1608 clock-names = "emmcclk"; 1609 drive-impedance-ohm = <50>; 1610 #phy-cells = <0>; 1611 status = "disabled"; 1612 }; 1613 1614 pcie_phy: pcie-phy { 1615 compatible = "rockchip,rk3399-pcie-phy"; 1616 clocks = <&cru SCLK_PCIEPHY_REF>; 1617 clock-names = "refclk"; 1618 #phy-cells = <1>; 1619 resets = <&cru SRST_PCIEPHY>; 1620 reset-names = "phy"; 1621 status = "disabled"; 1622 }; 1623 }; 1624 1625 tcphy0: phy@ff7c0000 { 1626 compatible = "rockchip,rk3399-typec-phy"; 1627 reg = <0x0 0xff7c0000 0x0 0x40000>; 1628 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1629 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1630 clock-names = "tcpdcore", "tcpdphy-ref"; 1631 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1632 assigned-clock-rates = <50000000>; 1633 power-domains = <&power RK3399_PD_TCPD0>; 1634 resets = <&cru SRST_UPHY0>, 1635 <&cru SRST_UPHY0_PIPE_L00>, 1636 <&cru SRST_P_UPHY0_TCPHY>; 1637 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1638 rockchip,grf = <&grf>; 1639 status = "disabled"; 1640 1641 tcphy0_dp: dp-port { 1642 #phy-cells = <0>; 1643 }; 1644 1645 tcphy0_usb3: usb3-port { 1646 #phy-cells = <0>; 1647 }; 1648 }; 1649 1650 tcphy1: phy@ff800000 { 1651 compatible = "rockchip,rk3399-typec-phy"; 1652 reg = <0x0 0xff800000 0x0 0x40000>; 1653 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1654 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1655 clock-names = "tcpdcore", "tcpdphy-ref"; 1656 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1657 assigned-clock-rates = <50000000>; 1658 power-domains = <&power RK3399_PD_TCPD1>; 1659 resets = <&cru SRST_UPHY1>, 1660 <&cru SRST_UPHY1_PIPE_L00>, 1661 <&cru SRST_P_UPHY1_TCPHY>; 1662 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1663 rockchip,grf = <&grf>; 1664 status = "disabled"; 1665 1666 tcphy1_dp: dp-port { 1667 #phy-cells = <0>; 1668 }; 1669 1670 tcphy1_usb3: usb3-port { 1671 #phy-cells = <0>; 1672 }; 1673 }; 1674 1675 watchdog@ff848000 { 1676 compatible = "rockchip,rk3399-wdt", "snps,dw-wdt"; 1677 reg = <0x0 0xff848000 0x0 0x100>; 1678 clocks = <&cru PCLK_WDT>; 1679 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1680 }; 1681 1682 rktimer: rktimer@ff850000 { 1683 compatible = "rockchip,rk3399-timer"; 1684 reg = <0x0 0xff850000 0x0 0x1000>; 1685 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1686 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1687 clock-names = "pclk", "timer"; 1688 }; 1689 1690 spdif: spdif@ff870000 { 1691 compatible = "rockchip,rk3399-spdif"; 1692 reg = <0x0 0xff870000 0x0 0x1000>; 1693 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1694 dmas = <&dmac_bus 7>; 1695 dma-names = "tx"; 1696 clock-names = "mclk", "hclk"; 1697 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1698 pinctrl-names = "default"; 1699 pinctrl-0 = <&spdif_bus>; 1700 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1701 #sound-dai-cells = <0>; 1702 status = "disabled"; 1703 }; 1704 1705 i2s0: i2s@ff880000 { 1706 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1707 reg = <0x0 0xff880000 0x0 0x1000>; 1708 rockchip,grf = <&grf>; 1709 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1710 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1711 dma-names = "tx", "rx"; 1712 clock-names = "i2s_clk", "i2s_hclk"; 1713 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1714 pinctrl-names = "bclk_on", "bclk_off"; 1715 pinctrl-0 = <&i2s0_8ch_bus>; 1716 pinctrl-1 = <&i2s0_8ch_bus_bclk_off>; 1717 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1718 #sound-dai-cells = <0>; 1719 status = "disabled"; 1720 }; 1721 1722 i2s1: i2s@ff890000 { 1723 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1724 reg = <0x0 0xff890000 0x0 0x1000>; 1725 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1726 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1727 dma-names = "tx", "rx"; 1728 clock-names = "i2s_clk", "i2s_hclk"; 1729 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1730 pinctrl-names = "default"; 1731 pinctrl-0 = <&i2s1_2ch_bus>; 1732 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1733 #sound-dai-cells = <0>; 1734 status = "disabled"; 1735 }; 1736 1737 i2s2: i2s@ff8a0000 { 1738 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1739 reg = <0x0 0xff8a0000 0x0 0x1000>; 1740 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1741 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1742 dma-names = "tx", "rx"; 1743 clock-names = "i2s_clk", "i2s_hclk"; 1744 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1745 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1746 #sound-dai-cells = <0>; 1747 status = "disabled"; 1748 }; 1749 1750 vopl: vop@ff8f0000 { 1751 compatible = "rockchip,rk3399-vop-lit"; 1752 reg = <0x0 0xff8f0000 0x0 0x2000>, <0x0 0xff8f2000 0x0 0x400>; 1753 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1754 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1755 assigned-clock-rates = <400000000>, <100000000>; 1756 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1757 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1758 iommus = <&vopl_mmu>; 1759 power-domains = <&power RK3399_PD_VOPL>; 1760 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1761 reset-names = "axi", "ahb", "dclk"; 1762 status = "disabled"; 1763 1764 vopl_out: port { 1765 #address-cells = <1>; 1766 #size-cells = <0>; 1767 1768 vopl_out_mipi: endpoint@0 { 1769 reg = <0>; 1770 remote-endpoint = <&mipi_in_vopl>; 1771 }; 1772 1773 vopl_out_edp: endpoint@1 { 1774 reg = <1>; 1775 remote-endpoint = <&edp_in_vopl>; 1776 }; 1777 1778 vopl_out_hdmi: endpoint@2 { 1779 reg = <2>; 1780 remote-endpoint = <&hdmi_in_vopl>; 1781 }; 1782 1783 vopl_out_mipi1: endpoint@3 { 1784 reg = <3>; 1785 remote-endpoint = <&mipi1_in_vopl>; 1786 }; 1787 1788 vopl_out_dp: endpoint@4 { 1789 reg = <4>; 1790 remote-endpoint = <&dp_in_vopl>; 1791 }; 1792 }; 1793 }; 1794 1795 vopl_mmu: iommu@ff8f3f00 { 1796 compatible = "rockchip,iommu"; 1797 reg = <0x0 0xff8f3f00 0x0 0x100>; 1798 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1799 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1800 clock-names = "aclk", "iface"; 1801 power-domains = <&power RK3399_PD_VOPL>; 1802 #iommu-cells = <0>; 1803 status = "disabled"; 1804 }; 1805 1806 vopb: vop@ff900000 { 1807 compatible = "rockchip,rk3399-vop-big"; 1808 reg = <0x0 0xff900000 0x0 0x2000>, <0x0 0xff902000 0x0 0x1000>; 1809 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1810 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1811 assigned-clock-rates = <400000000>, <100000000>; 1812 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1813 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1814 iommus = <&vopb_mmu>; 1815 power-domains = <&power RK3399_PD_VOPB>; 1816 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1817 reset-names = "axi", "ahb", "dclk"; 1818 status = "disabled"; 1819 1820 vopb_out: port { 1821 #address-cells = <1>; 1822 #size-cells = <0>; 1823 1824 vopb_out_edp: endpoint@0 { 1825 reg = <0>; 1826 remote-endpoint = <&edp_in_vopb>; 1827 }; 1828 1829 vopb_out_mipi: endpoint@1 { 1830 reg = <1>; 1831 remote-endpoint = <&mipi_in_vopb>; 1832 }; 1833 1834 vopb_out_hdmi: endpoint@2 { 1835 reg = <2>; 1836 remote-endpoint = <&hdmi_in_vopb>; 1837 }; 1838 1839 vopb_out_mipi1: endpoint@3 { 1840 reg = <3>; 1841 remote-endpoint = <&mipi1_in_vopb>; 1842 }; 1843 1844 vopb_out_dp: endpoint@4 { 1845 reg = <4>; 1846 remote-endpoint = <&dp_in_vopb>; 1847 }; 1848 }; 1849 }; 1850 1851 vopb_mmu: iommu@ff903f00 { 1852 compatible = "rockchip,iommu"; 1853 reg = <0x0 0xff903f00 0x0 0x100>; 1854 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1855 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1856 clock-names = "aclk", "iface"; 1857 power-domains = <&power RK3399_PD_VOPB>; 1858 #iommu-cells = <0>; 1859 status = "disabled"; 1860 }; 1861 1862 isp0: isp0@ff910000 { 1863 compatible = "rockchip,rk3399-cif-isp"; 1864 reg = <0x0 0xff910000 0x0 0x4000>; 1865 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1866 clocks = <&cru SCLK_ISP0>, 1867 <&cru ACLK_ISP0_WRAPPER>, 1868 <&cru HCLK_ISP0_WRAPPER>; 1869 clock-names = "isp", "aclk", "hclk"; 1870 iommus = <&isp0_mmu>; 1871 phys = <&mipi_dphy_rx0>; 1872 phy-names = "dphy"; 1873 power-domains = <&power RK3399_PD_ISP0>; 1874 status = "disabled"; 1875 1876 ports { 1877 #address-cells = <1>; 1878 #size-cells = <0>; 1879 1880 port@0 { 1881 reg = <0>; 1882 #address-cells = <1>; 1883 #size-cells = <0>; 1884 }; 1885 }; 1886 }; 1887 1888 isp0_mmu: iommu@ff914000 { 1889 compatible = "rockchip,iommu"; 1890 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1891 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1892 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; 1893 clock-names = "aclk", "iface"; 1894 #iommu-cells = <0>; 1895 power-domains = <&power RK3399_PD_ISP0>; 1896 rockchip,disable-mmu-reset; 1897 }; 1898 1899 isp1: isp1@ff920000 { 1900 compatible = "rockchip,rk3399-cif-isp"; 1901 reg = <0x0 0xff920000 0x0 0x4000>; 1902 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 1903 clocks = <&cru SCLK_ISP1>, 1904 <&cru ACLK_ISP1_WRAPPER>, 1905 <&cru HCLK_ISP1_WRAPPER>; 1906 clock-names = "isp", "aclk", "hclk"; 1907 iommus = <&isp1_mmu>; 1908 phys = <&mipi_dsi1>; 1909 phy-names = "dphy"; 1910 power-domains = <&power RK3399_PD_ISP1>; 1911 status = "disabled"; 1912 1913 ports { 1914 #address-cells = <1>; 1915 #size-cells = <0>; 1916 1917 port@0 { 1918 reg = <0>; 1919 #address-cells = <1>; 1920 #size-cells = <0>; 1921 }; 1922 }; 1923 }; 1924 1925 isp1_mmu: iommu@ff924000 { 1926 compatible = "rockchip,iommu"; 1927 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; 1928 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 1929 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; 1930 clock-names = "aclk", "iface"; 1931 #iommu-cells = <0>; 1932 power-domains = <&power RK3399_PD_ISP1>; 1933 rockchip,disable-mmu-reset; 1934 }; 1935 1936 hdmi_sound: hdmi-sound { 1937 compatible = "simple-audio-card"; 1938 simple-audio-card,format = "i2s"; 1939 simple-audio-card,mclk-fs = <256>; 1940 simple-audio-card,name = "hdmi-sound"; 1941 status = "disabled"; 1942 1943 simple-audio-card,cpu { 1944 sound-dai = <&i2s2>; 1945 }; 1946 simple-audio-card,codec { 1947 sound-dai = <&hdmi>; 1948 }; 1949 }; 1950 1951 hdmi: hdmi@ff940000 { 1952 compatible = "rockchip,rk3399-dw-hdmi"; 1953 reg = <0x0 0xff940000 0x0 0x20000>; 1954 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 1955 clocks = <&cru PCLK_HDMI_CTRL>, 1956 <&cru SCLK_HDMI_SFR>, 1957 <&cru SCLK_HDMI_CEC>, 1958 <&cru PCLK_VIO_GRF>, 1959 <&cru PLL_VPLL>; 1960 clock-names = "iahb", "isfr", "cec", "grf", "ref"; 1961 power-domains = <&power RK3399_PD_HDCP>; 1962 reg-io-width = <4>; 1963 rockchip,grf = <&grf>; 1964 #sound-dai-cells = <0>; 1965 status = "disabled"; 1966 1967 ports { 1968 hdmi_in: port { 1969 #address-cells = <1>; 1970 #size-cells = <0>; 1971 1972 hdmi_in_vopb: endpoint@0 { 1973 reg = <0>; 1974 remote-endpoint = <&vopb_out_hdmi>; 1975 }; 1976 hdmi_in_vopl: endpoint@1 { 1977 reg = <1>; 1978 remote-endpoint = <&vopl_out_hdmi>; 1979 }; 1980 }; 1981 }; 1982 }; 1983 1984 mipi_dsi: dsi@ff960000 { 1985 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1986 reg = <0x0 0xff960000 0x0 0x8000>; 1987 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 1988 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, 1989 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; 1990 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1991 power-domains = <&power RK3399_PD_VIO>; 1992 resets = <&cru SRST_P_MIPI_DSI0>; 1993 reset-names = "apb"; 1994 rockchip,grf = <&grf>; 1995 #address-cells = <1>; 1996 #size-cells = <0>; 1997 status = "disabled"; 1998 1999 ports { 2000 #address-cells = <1>; 2001 #size-cells = <0>; 2002 2003 mipi_in: port@0 { 2004 reg = <0>; 2005 #address-cells = <1>; 2006 #size-cells = <0>; 2007 2008 mipi_in_vopb: endpoint@0 { 2009 reg = <0>; 2010 remote-endpoint = <&vopb_out_mipi>; 2011 }; 2012 2013 mipi_in_vopl: endpoint@1 { 2014 reg = <1>; 2015 remote-endpoint = <&vopl_out_mipi>; 2016 }; 2017 }; 2018 2019 mipi_out: port@1 { 2020 reg = <1>; 2021 }; 2022 }; 2023 }; 2024 2025 mipi_dsi1: dsi@ff968000 { 2026 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 2027 reg = <0x0 0xff968000 0x0 0x8000>; 2028 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>; 2029 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, 2030 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; 2031 clock-names = "ref", "pclk", "phy_cfg", "grf"; 2032 power-domains = <&power RK3399_PD_VIO>; 2033 resets = <&cru SRST_P_MIPI_DSI1>; 2034 reset-names = "apb"; 2035 rockchip,grf = <&grf>; 2036 #address-cells = <1>; 2037 #size-cells = <0>; 2038 #phy-cells = <0>; 2039 status = "disabled"; 2040 2041 ports { 2042 #address-cells = <1>; 2043 #size-cells = <0>; 2044 2045 mipi1_in: port@0 { 2046 reg = <0>; 2047 #address-cells = <1>; 2048 #size-cells = <0>; 2049 2050 mipi1_in_vopb: endpoint@0 { 2051 reg = <0>; 2052 remote-endpoint = <&vopb_out_mipi1>; 2053 }; 2054 2055 mipi1_in_vopl: endpoint@1 { 2056 reg = <1>; 2057 remote-endpoint = <&vopl_out_mipi1>; 2058 }; 2059 }; 2060 2061 mipi1_out: port@1 { 2062 reg = <1>; 2063 }; 2064 }; 2065 }; 2066 2067 edp: dp@ff970000 { 2068 compatible = "rockchip,rk3399-edp"; 2069 reg = <0x0 0xff970000 0x0 0x8000>; 2070 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 2071 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; 2072 clock-names = "dp", "pclk", "grf"; 2073 pinctrl-names = "default"; 2074 pinctrl-0 = <&edp_hpd>; 2075 power-domains = <&power RK3399_PD_EDP>; 2076 resets = <&cru SRST_P_EDP_CTRL>; 2077 reset-names = "dp"; 2078 rockchip,grf = <&grf>; 2079 status = "disabled"; 2080 2081 ports { 2082 #address-cells = <1>; 2083 #size-cells = <0>; 2084 2085 edp_in: port@0 { 2086 reg = <0>; 2087 #address-cells = <1>; 2088 #size-cells = <0>; 2089 2090 edp_in_vopb: endpoint@0 { 2091 reg = <0>; 2092 remote-endpoint = <&vopb_out_edp>; 2093 }; 2094 2095 edp_in_vopl: endpoint@1 { 2096 reg = <1>; 2097 remote-endpoint = <&vopl_out_edp>; 2098 }; 2099 }; 2100 2101 edp_out: port@1 { 2102 reg = <1>; 2103 }; 2104 }; 2105 }; 2106 2107 gpu: gpu@ff9a0000 { 2108 compatible = "rockchip,rk3399-mali", "arm,mali-t860"; 2109 reg = <0x0 0xff9a0000 0x0 0x10000>; 2110 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, 2111 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>, 2112 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>; 2113 interrupt-names = "job", "mmu", "gpu"; 2114 clocks = <&cru ACLK_GPU>; 2115 #cooling-cells = <2>; 2116 power-domains = <&power RK3399_PD_GPU>; 2117 status = "disabled"; 2118 }; 2119 2120 pinctrl: pinctrl { 2121 compatible = "rockchip,rk3399-pinctrl"; 2122 rockchip,grf = <&grf>; 2123 rockchip,pmu = <&pmugrf>; 2124 #address-cells = <2>; 2125 #size-cells = <2>; 2126 ranges; 2127 2128 gpio0: gpio@ff720000 { 2129 compatible = "rockchip,gpio-bank"; 2130 reg = <0x0 0xff720000 0x0 0x100>; 2131 clocks = <&pmucru PCLK_GPIO0_PMU>; 2132 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 2133 2134 gpio-controller; 2135 #gpio-cells = <0x2>; 2136 2137 interrupt-controller; 2138 #interrupt-cells = <0x2>; 2139 }; 2140 2141 gpio1: gpio@ff730000 { 2142 compatible = "rockchip,gpio-bank"; 2143 reg = <0x0 0xff730000 0x0 0x100>; 2144 clocks = <&pmucru PCLK_GPIO1_PMU>; 2145 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 2146 2147 gpio-controller; 2148 #gpio-cells = <0x2>; 2149 2150 interrupt-controller; 2151 #interrupt-cells = <0x2>; 2152 }; 2153 2154 gpio2: gpio@ff780000 { 2155 compatible = "rockchip,gpio-bank"; 2156 reg = <0x0 0xff780000 0x0 0x100>; 2157 clocks = <&cru PCLK_GPIO2>; 2158 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 2159 2160 gpio-controller; 2161 #gpio-cells = <0x2>; 2162 2163 interrupt-controller; 2164 #interrupt-cells = <0x2>; 2165 }; 2166 2167 gpio3: gpio@ff788000 { 2168 compatible = "rockchip,gpio-bank"; 2169 reg = <0x0 0xff788000 0x0 0x100>; 2170 clocks = <&cru PCLK_GPIO3>; 2171 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 2172 2173 gpio-controller; 2174 #gpio-cells = <0x2>; 2175 2176 interrupt-controller; 2177 #interrupt-cells = <0x2>; 2178 }; 2179 2180 gpio4: gpio@ff790000 { 2181 compatible = "rockchip,gpio-bank"; 2182 reg = <0x0 0xff790000 0x0 0x100>; 2183 clocks = <&cru PCLK_GPIO4>; 2184 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 2185 2186 gpio-controller; 2187 #gpio-cells = <0x2>; 2188 2189 interrupt-controller; 2190 #interrupt-cells = <0x2>; 2191 }; 2192 2193 pcfg_pull_up: pcfg-pull-up { 2194 bias-pull-up; 2195 }; 2196 2197 pcfg_pull_down: pcfg-pull-down { 2198 bias-pull-down; 2199 }; 2200 2201 pcfg_pull_none: pcfg-pull-none { 2202 bias-disable; 2203 }; 2204 2205 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 2206 bias-disable; 2207 drive-strength = <12>; 2208 }; 2209 2210 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 2211 bias-disable; 2212 drive-strength = <13>; 2213 }; 2214 2215 pcfg_pull_none_18ma: pcfg-pull-none-18ma { 2216 bias-disable; 2217 drive-strength = <18>; 2218 }; 2219 2220 pcfg_pull_none_20ma: pcfg-pull-none-20ma { 2221 bias-disable; 2222 drive-strength = <20>; 2223 }; 2224 2225 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 2226 bias-pull-up; 2227 drive-strength = <2>; 2228 }; 2229 2230 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 2231 bias-pull-up; 2232 drive-strength = <8>; 2233 }; 2234 2235 pcfg_pull_up_18ma: pcfg-pull-up-18ma { 2236 bias-pull-up; 2237 drive-strength = <18>; 2238 }; 2239 2240 pcfg_pull_up_20ma: pcfg-pull-up-20ma { 2241 bias-pull-up; 2242 drive-strength = <20>; 2243 }; 2244 2245 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 2246 bias-pull-down; 2247 drive-strength = <4>; 2248 }; 2249 2250 pcfg_pull_down_8ma: pcfg-pull-down-8ma { 2251 bias-pull-down; 2252 drive-strength = <8>; 2253 }; 2254 2255 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 2256 bias-pull-down; 2257 drive-strength = <12>; 2258 }; 2259 2260 pcfg_pull_down_18ma: pcfg-pull-down-18ma { 2261 bias-pull-down; 2262 drive-strength = <18>; 2263 }; 2264 2265 pcfg_pull_down_20ma: pcfg-pull-down-20ma { 2266 bias-pull-down; 2267 drive-strength = <20>; 2268 }; 2269 2270 pcfg_output_high: pcfg-output-high { 2271 output-high; 2272 }; 2273 2274 pcfg_output_low: pcfg-output-low { 2275 output-low; 2276 }; 2277 2278 pcfg_input_enable: pcfg-input-enable { 2279 input-enable; 2280 }; 2281 2282 pcfg_input_pull_up: pcfg-input-pull-up { 2283 input-enable; 2284 bias-pull-up; 2285 }; 2286 2287 pcfg_input_pull_down: pcfg-input-pull-down { 2288 input-enable; 2289 bias-pull-down; 2290 }; 2291 2292 clock { 2293 clk_32k: clk-32k { 2294 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; 2295 }; 2296 }; 2297 2298 cif { 2299 cif_clkin: cif-clkin { 2300 rockchip,pins = 2301 <2 RK_PB2 3 &pcfg_pull_none>; 2302 }; 2303 2304 cif_clkouta: cif-clkouta { 2305 rockchip,pins = 2306 <2 RK_PB3 3 &pcfg_pull_none>; 2307 }; 2308 }; 2309 2310 edp { 2311 edp_hpd: edp-hpd { 2312 rockchip,pins = 2313 <4 RK_PC7 2 &pcfg_pull_none>; 2314 }; 2315 }; 2316 2317 gmac { 2318 rgmii_pins: rgmii-pins { 2319 rockchip,pins = 2320 /* mac_txclk */ 2321 <3 RK_PC1 1 &pcfg_pull_none_13ma>, 2322 /* mac_rxclk */ 2323 <3 RK_PB6 1 &pcfg_pull_none>, 2324 /* mac_mdio */ 2325 <3 RK_PB5 1 &pcfg_pull_none>, 2326 /* mac_txen */ 2327 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2328 /* mac_clk */ 2329 <3 RK_PB3 1 &pcfg_pull_none>, 2330 /* mac_rxdv */ 2331 <3 RK_PB1 1 &pcfg_pull_none>, 2332 /* mac_mdc */ 2333 <3 RK_PB0 1 &pcfg_pull_none>, 2334 /* mac_rxd1 */ 2335 <3 RK_PA7 1 &pcfg_pull_none>, 2336 /* mac_rxd0 */ 2337 <3 RK_PA6 1 &pcfg_pull_none>, 2338 /* mac_txd1 */ 2339 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2340 /* mac_txd0 */ 2341 <3 RK_PA4 1 &pcfg_pull_none_13ma>, 2342 /* mac_rxd3 */ 2343 <3 RK_PA3 1 &pcfg_pull_none>, 2344 /* mac_rxd2 */ 2345 <3 RK_PA2 1 &pcfg_pull_none>, 2346 /* mac_txd3 */ 2347 <3 RK_PA1 1 &pcfg_pull_none_13ma>, 2348 /* mac_txd2 */ 2349 <3 RK_PA0 1 &pcfg_pull_none_13ma>; 2350 }; 2351 2352 rmii_pins: rmii-pins { 2353 rockchip,pins = 2354 /* mac_mdio */ 2355 <3 RK_PB5 1 &pcfg_pull_none>, 2356 /* mac_txen */ 2357 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2358 /* mac_clk */ 2359 <3 RK_PB3 1 &pcfg_pull_none>, 2360 /* mac_rxer */ 2361 <3 RK_PB2 1 &pcfg_pull_none>, 2362 /* mac_rxdv */ 2363 <3 RK_PB1 1 &pcfg_pull_none>, 2364 /* mac_mdc */ 2365 <3 RK_PB0 1 &pcfg_pull_none>, 2366 /* mac_rxd1 */ 2367 <3 RK_PA7 1 &pcfg_pull_none>, 2368 /* mac_rxd0 */ 2369 <3 RK_PA6 1 &pcfg_pull_none>, 2370 /* mac_txd1 */ 2371 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2372 /* mac_txd0 */ 2373 <3 RK_PA4 1 &pcfg_pull_none_13ma>; 2374 }; 2375 }; 2376 2377 i2c0 { 2378 i2c0_xfer: i2c0-xfer { 2379 rockchip,pins = 2380 <1 RK_PB7 2 &pcfg_pull_none>, 2381 <1 RK_PC0 2 &pcfg_pull_none>; 2382 }; 2383 }; 2384 2385 i2c1 { 2386 i2c1_xfer: i2c1-xfer { 2387 rockchip,pins = 2388 <4 RK_PA2 1 &pcfg_pull_none>, 2389 <4 RK_PA1 1 &pcfg_pull_none>; 2390 }; 2391 }; 2392 2393 i2c2 { 2394 i2c2_xfer: i2c2-xfer { 2395 rockchip,pins = 2396 <2 RK_PA1 2 &pcfg_pull_none_12ma>, 2397 <2 RK_PA0 2 &pcfg_pull_none_12ma>; 2398 }; 2399 }; 2400 2401 i2c3 { 2402 i2c3_xfer: i2c3-xfer { 2403 rockchip,pins = 2404 <4 RK_PC1 1 &pcfg_pull_none>, 2405 <4 RK_PC0 1 &pcfg_pull_none>; 2406 }; 2407 }; 2408 2409 i2c4 { 2410 i2c4_xfer: i2c4-xfer { 2411 rockchip,pins = 2412 <1 RK_PB4 1 &pcfg_pull_none>, 2413 <1 RK_PB3 1 &pcfg_pull_none>; 2414 }; 2415 }; 2416 2417 i2c5 { 2418 i2c5_xfer: i2c5-xfer { 2419 rockchip,pins = 2420 <3 RK_PB3 2 &pcfg_pull_none>, 2421 <3 RK_PB2 2 &pcfg_pull_none>; 2422 }; 2423 }; 2424 2425 i2c6 { 2426 i2c6_xfer: i2c6-xfer { 2427 rockchip,pins = 2428 <2 RK_PB2 2 &pcfg_pull_none>, 2429 <2 RK_PB1 2 &pcfg_pull_none>; 2430 }; 2431 }; 2432 2433 i2c7 { 2434 i2c7_xfer: i2c7-xfer { 2435 rockchip,pins = 2436 <2 RK_PB0 2 &pcfg_pull_none>, 2437 <2 RK_PA7 2 &pcfg_pull_none>; 2438 }; 2439 }; 2440 2441 i2c8 { 2442 i2c8_xfer: i2c8-xfer { 2443 rockchip,pins = 2444 <1 RK_PC5 1 &pcfg_pull_none>, 2445 <1 RK_PC4 1 &pcfg_pull_none>; 2446 }; 2447 }; 2448 2449 i2s0 { 2450 i2s0_2ch_bus: i2s0-2ch-bus { 2451 rockchip,pins = 2452 <3 RK_PD0 1 &pcfg_pull_none>, 2453 <3 RK_PD1 1 &pcfg_pull_none>, 2454 <3 RK_PD2 1 &pcfg_pull_none>, 2455 <3 RK_PD3 1 &pcfg_pull_none>, 2456 <3 RK_PD7 1 &pcfg_pull_none>, 2457 <4 RK_PA0 1 &pcfg_pull_none>; 2458 }; 2459 2460 i2s0_2ch_bus_bclk_off: i2s0-2ch-bus-bclk-off { 2461 rockchip,pins = 2462 <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, 2463 <3 RK_PD1 1 &pcfg_pull_none>, 2464 <3 RK_PD2 1 &pcfg_pull_none>, 2465 <3 RK_PD3 1 &pcfg_pull_none>, 2466 <3 RK_PD7 1 &pcfg_pull_none>, 2467 <4 RK_PA0 1 &pcfg_pull_none>; 2468 }; 2469 2470 i2s0_8ch_bus: i2s0-8ch-bus { 2471 rockchip,pins = 2472 <3 RK_PD0 1 &pcfg_pull_none>, 2473 <3 RK_PD1 1 &pcfg_pull_none>, 2474 <3 RK_PD2 1 &pcfg_pull_none>, 2475 <3 RK_PD3 1 &pcfg_pull_none>, 2476 <3 RK_PD4 1 &pcfg_pull_none>, 2477 <3 RK_PD5 1 &pcfg_pull_none>, 2478 <3 RK_PD6 1 &pcfg_pull_none>, 2479 <3 RK_PD7 1 &pcfg_pull_none>, 2480 <4 RK_PA0 1 &pcfg_pull_none>; 2481 }; 2482 2483 i2s0_8ch_bus_bclk_off: i2s0-8ch-bus-bclk-off { 2484 rockchip,pins = 2485 <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, 2486 <3 RK_PD1 1 &pcfg_pull_none>, 2487 <3 RK_PD2 1 &pcfg_pull_none>, 2488 <3 RK_PD3 1 &pcfg_pull_none>, 2489 <3 RK_PD4 1 &pcfg_pull_none>, 2490 <3 RK_PD5 1 &pcfg_pull_none>, 2491 <3 RK_PD6 1 &pcfg_pull_none>, 2492 <3 RK_PD7 1 &pcfg_pull_none>, 2493 <4 RK_PA0 1 &pcfg_pull_none>; 2494 }; 2495 }; 2496 2497 i2s1 { 2498 i2s1_2ch_bus: i2s1-2ch-bus { 2499 rockchip,pins = 2500 <4 RK_PA3 1 &pcfg_pull_none>, 2501 <4 RK_PA4 1 &pcfg_pull_none>, 2502 <4 RK_PA5 1 &pcfg_pull_none>, 2503 <4 RK_PA6 1 &pcfg_pull_none>, 2504 <4 RK_PA7 1 &pcfg_pull_none>; 2505 }; 2506 2507 i2s1_2ch_bus_bclk_off: i2s1-2ch-bus-bclk-off { 2508 rockchip,pins = 2509 <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>, 2510 <4 RK_PA4 1 &pcfg_pull_none>, 2511 <4 RK_PA5 1 &pcfg_pull_none>, 2512 <4 RK_PA6 1 &pcfg_pull_none>, 2513 <4 RK_PA7 1 &pcfg_pull_none>; 2514 }; 2515 }; 2516 2517 sdio0 { 2518 sdio0_bus1: sdio0-bus1 { 2519 rockchip,pins = 2520 <2 RK_PC4 1 &pcfg_pull_up>; 2521 }; 2522 2523 sdio0_bus4: sdio0-bus4 { 2524 rockchip,pins = 2525 <2 RK_PC4 1 &pcfg_pull_up>, 2526 <2 RK_PC5 1 &pcfg_pull_up>, 2527 <2 RK_PC6 1 &pcfg_pull_up>, 2528 <2 RK_PC7 1 &pcfg_pull_up>; 2529 }; 2530 2531 sdio0_cmd: sdio0-cmd { 2532 rockchip,pins = 2533 <2 RK_PD0 1 &pcfg_pull_up>; 2534 }; 2535 2536 sdio0_clk: sdio0-clk { 2537 rockchip,pins = 2538 <2 RK_PD1 1 &pcfg_pull_none>; 2539 }; 2540 2541 sdio0_cd: sdio0-cd { 2542 rockchip,pins = 2543 <2 RK_PD2 1 &pcfg_pull_up>; 2544 }; 2545 2546 sdio0_pwr: sdio0-pwr { 2547 rockchip,pins = 2548 <2 RK_PD3 1 &pcfg_pull_up>; 2549 }; 2550 2551 sdio0_bkpwr: sdio0-bkpwr { 2552 rockchip,pins = 2553 <2 RK_PD4 1 &pcfg_pull_up>; 2554 }; 2555 2556 sdio0_wp: sdio0-wp { 2557 rockchip,pins = 2558 <0 RK_PA3 1 &pcfg_pull_up>; 2559 }; 2560 2561 sdio0_int: sdio0-int { 2562 rockchip,pins = 2563 <0 RK_PA4 1 &pcfg_pull_up>; 2564 }; 2565 }; 2566 2567 sdmmc { 2568 sdmmc_bus1: sdmmc-bus1 { 2569 rockchip,pins = 2570 <4 RK_PB0 1 &pcfg_pull_up>; 2571 }; 2572 2573 sdmmc_bus4: sdmmc-bus4 { 2574 rockchip,pins = 2575 <4 RK_PB0 1 &pcfg_pull_up>, 2576 <4 RK_PB1 1 &pcfg_pull_up>, 2577 <4 RK_PB2 1 &pcfg_pull_up>, 2578 <4 RK_PB3 1 &pcfg_pull_up>; 2579 }; 2580 2581 sdmmc_clk: sdmmc-clk { 2582 rockchip,pins = 2583 <4 RK_PB4 1 &pcfg_pull_none>; 2584 }; 2585 2586 sdmmc_cmd: sdmmc-cmd { 2587 rockchip,pins = 2588 <4 RK_PB5 1 &pcfg_pull_up>; 2589 }; 2590 2591 sdmmc_cd: sdmmc-cd { 2592 rockchip,pins = 2593 <0 RK_PA7 1 &pcfg_pull_up>; 2594 }; 2595 2596 sdmmc_wp: sdmmc-wp { 2597 rockchip,pins = 2598 <0 RK_PB0 1 &pcfg_pull_up>; 2599 }; 2600 }; 2601 2602 suspend { 2603 ap_pwroff: ap-pwroff { 2604 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>; 2605 }; 2606 2607 ddrio_pwroff: ddrio-pwroff { 2608 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; 2609 }; 2610 }; 2611 2612 spdif { 2613 spdif_bus: spdif-bus { 2614 rockchip,pins = 2615 <4 RK_PC5 1 &pcfg_pull_none>; 2616 }; 2617 2618 spdif_bus_1: spdif-bus-1 { 2619 rockchip,pins = 2620 <3 RK_PC0 3 &pcfg_pull_none>; 2621 }; 2622 }; 2623 2624 spi0 { 2625 spi0_clk: spi0-clk { 2626 rockchip,pins = 2627 <3 RK_PA6 2 &pcfg_pull_up>; 2628 }; 2629 spi0_cs0: spi0-cs0 { 2630 rockchip,pins = 2631 <3 RK_PA7 2 &pcfg_pull_up>; 2632 }; 2633 spi0_cs1: spi0-cs1 { 2634 rockchip,pins = 2635 <3 RK_PB0 2 &pcfg_pull_up>; 2636 }; 2637 spi0_tx: spi0-tx { 2638 rockchip,pins = 2639 <3 RK_PA5 2 &pcfg_pull_up>; 2640 }; 2641 spi0_rx: spi0-rx { 2642 rockchip,pins = 2643 <3 RK_PA4 2 &pcfg_pull_up>; 2644 }; 2645 }; 2646 2647 spi1 { 2648 spi1_clk: spi1-clk { 2649 rockchip,pins = 2650 <1 RK_PB1 2 &pcfg_pull_up>; 2651 }; 2652 spi1_cs0: spi1-cs0 { 2653 rockchip,pins = 2654 <1 RK_PB2 2 &pcfg_pull_up>; 2655 }; 2656 spi1_rx: spi1-rx { 2657 rockchip,pins = 2658 <1 RK_PA7 2 &pcfg_pull_up>; 2659 }; 2660 spi1_tx: spi1-tx { 2661 rockchip,pins = 2662 <1 RK_PB0 2 &pcfg_pull_up>; 2663 }; 2664 }; 2665 2666 spi2 { 2667 spi2_clk: spi2-clk { 2668 rockchip,pins = 2669 <2 RK_PB3 1 &pcfg_pull_up>; 2670 }; 2671 spi2_cs0: spi2-cs0 { 2672 rockchip,pins = 2673 <2 RK_PB4 1 &pcfg_pull_up>; 2674 }; 2675 spi2_rx: spi2-rx { 2676 rockchip,pins = 2677 <2 RK_PB1 1 &pcfg_pull_up>; 2678 }; 2679 spi2_tx: spi2-tx { 2680 rockchip,pins = 2681 <2 RK_PB2 1 &pcfg_pull_up>; 2682 }; 2683 }; 2684 2685 spi3 { 2686 spi3_clk: spi3-clk { 2687 rockchip,pins = 2688 <1 RK_PC1 1 &pcfg_pull_up>; 2689 }; 2690 spi3_cs0: spi3-cs0 { 2691 rockchip,pins = 2692 <1 RK_PC2 1 &pcfg_pull_up>; 2693 }; 2694 spi3_rx: spi3-rx { 2695 rockchip,pins = 2696 <1 RK_PB7 1 &pcfg_pull_up>; 2697 }; 2698 spi3_tx: spi3-tx { 2699 rockchip,pins = 2700 <1 RK_PC0 1 &pcfg_pull_up>; 2701 }; 2702 }; 2703 2704 spi4 { 2705 spi4_clk: spi4-clk { 2706 rockchip,pins = 2707 <3 RK_PA2 2 &pcfg_pull_up>; 2708 }; 2709 spi4_cs0: spi4-cs0 { 2710 rockchip,pins = 2711 <3 RK_PA3 2 &pcfg_pull_up>; 2712 }; 2713 spi4_rx: spi4-rx { 2714 rockchip,pins = 2715 <3 RK_PA0 2 &pcfg_pull_up>; 2716 }; 2717 spi4_tx: spi4-tx { 2718 rockchip,pins = 2719 <3 RK_PA1 2 &pcfg_pull_up>; 2720 }; 2721 }; 2722 2723 spi5 { 2724 spi5_clk: spi5-clk { 2725 rockchip,pins = 2726 <2 RK_PC6 2 &pcfg_pull_up>; 2727 }; 2728 spi5_cs0: spi5-cs0 { 2729 rockchip,pins = 2730 <2 RK_PC7 2 &pcfg_pull_up>; 2731 }; 2732 spi5_rx: spi5-rx { 2733 rockchip,pins = 2734 <2 RK_PC4 2 &pcfg_pull_up>; 2735 }; 2736 spi5_tx: spi5-tx { 2737 rockchip,pins = 2738 <2 RK_PC5 2 &pcfg_pull_up>; 2739 }; 2740 }; 2741 2742 testclk { 2743 test_clkout0: test-clkout0 { 2744 rockchip,pins = 2745 <0 RK_PA0 1 &pcfg_pull_none>; 2746 }; 2747 2748 test_clkout1: test-clkout1 { 2749 rockchip,pins = 2750 <2 RK_PD1 2 &pcfg_pull_none>; 2751 }; 2752 2753 test_clkout2: test-clkout2 { 2754 rockchip,pins = 2755 <0 RK_PB0 3 &pcfg_pull_none>; 2756 }; 2757 }; 2758 2759 tsadc { 2760 otp_pin: otp-pin { 2761 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 2762 }; 2763 2764 otp_out: otp-out { 2765 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; 2766 }; 2767 }; 2768 2769 uart0 { 2770 uart0_xfer: uart0-xfer { 2771 rockchip,pins = 2772 <2 RK_PC0 1 &pcfg_pull_up>, 2773 <2 RK_PC1 1 &pcfg_pull_none>; 2774 }; 2775 2776 uart0_cts: uart0-cts { 2777 rockchip,pins = 2778 <2 RK_PC2 1 &pcfg_pull_none>; 2779 }; 2780 2781 uart0_rts: uart0-rts { 2782 rockchip,pins = 2783 <2 RK_PC3 1 &pcfg_pull_none>; 2784 }; 2785 }; 2786 2787 uart1 { 2788 uart1_xfer: uart1-xfer { 2789 rockchip,pins = 2790 <3 RK_PB4 2 &pcfg_pull_up>, 2791 <3 RK_PB5 2 &pcfg_pull_none>; 2792 }; 2793 }; 2794 2795 uart2a { 2796 uart2a_xfer: uart2a-xfer { 2797 rockchip,pins = 2798 <4 RK_PB0 2 &pcfg_pull_up>, 2799 <4 RK_PB1 2 &pcfg_pull_none>; 2800 }; 2801 }; 2802 2803 uart2b { 2804 uart2b_xfer: uart2b-xfer { 2805 rockchip,pins = 2806 <4 RK_PC0 2 &pcfg_pull_up>, 2807 <4 RK_PC1 2 &pcfg_pull_none>; 2808 }; 2809 }; 2810 2811 uart2c { 2812 uart2c_xfer: uart2c-xfer { 2813 rockchip,pins = 2814 <4 RK_PC3 1 &pcfg_pull_up>, 2815 <4 RK_PC4 1 &pcfg_pull_none>; 2816 }; 2817 }; 2818 2819 uart3 { 2820 uart3_xfer: uart3-xfer { 2821 rockchip,pins = 2822 <3 RK_PB6 2 &pcfg_pull_up>, 2823 <3 RK_PB7 2 &pcfg_pull_none>; 2824 }; 2825 2826 uart3_cts: uart3-cts { 2827 rockchip,pins = 2828 <3 RK_PC0 2 &pcfg_pull_none>; 2829 }; 2830 2831 uart3_rts: uart3-rts { 2832 rockchip,pins = 2833 <3 RK_PC1 2 &pcfg_pull_none>; 2834 }; 2835 }; 2836 2837 uart4 { 2838 uart4_xfer: uart4-xfer { 2839 rockchip,pins = 2840 <1 RK_PA7 1 &pcfg_pull_up>, 2841 <1 RK_PB0 1 &pcfg_pull_none>; 2842 }; 2843 }; 2844 2845 uarthdcp { 2846 uarthdcp_xfer: uarthdcp-xfer { 2847 rockchip,pins = 2848 <4 RK_PC5 2 &pcfg_pull_up>, 2849 <4 RK_PC6 2 &pcfg_pull_none>; 2850 }; 2851 }; 2852 2853 pwm0 { 2854 pwm0_pin: pwm0-pin { 2855 rockchip,pins = 2856 <4 RK_PC2 1 &pcfg_pull_none>; 2857 }; 2858 2859 pwm0_pin_pull_down: pwm0-pin-pull-down { 2860 rockchip,pins = 2861 <4 RK_PC2 1 &pcfg_pull_down>; 2862 }; 2863 2864 vop0_pwm_pin: vop0-pwm-pin { 2865 rockchip,pins = 2866 <4 RK_PC2 2 &pcfg_pull_none>; 2867 }; 2868 2869 vop1_pwm_pin: vop1-pwm-pin { 2870 rockchip,pins = 2871 <4 RK_PC2 3 &pcfg_pull_none>; 2872 }; 2873 }; 2874 2875 pwm1 { 2876 pwm1_pin: pwm1-pin { 2877 rockchip,pins = 2878 <4 RK_PC6 1 &pcfg_pull_none>; 2879 }; 2880 2881 pwm1_pin_pull_down: pwm1-pin-pull-down { 2882 rockchip,pins = 2883 <4 RK_PC6 1 &pcfg_pull_down>; 2884 }; 2885 }; 2886 2887 pwm2 { 2888 pwm2_pin: pwm2-pin { 2889 rockchip,pins = 2890 <1 RK_PC3 1 &pcfg_pull_none>; 2891 }; 2892 2893 pwm2_pin_pull_down: pwm2-pin-pull-down { 2894 rockchip,pins = 2895 <1 RK_PC3 1 &pcfg_pull_down>; 2896 }; 2897 }; 2898 2899 pwm3a { 2900 pwm3a_pin: pwm3a-pin { 2901 rockchip,pins = 2902 <0 RK_PA6 1 &pcfg_pull_none>; 2903 }; 2904 }; 2905 2906 pwm3b { 2907 pwm3b_pin: pwm3b-pin { 2908 rockchip,pins = 2909 <1 RK_PB6 1 &pcfg_pull_none>; 2910 }; 2911 }; 2912 2913 hdmi { 2914 hdmi_i2c_xfer: hdmi-i2c-xfer { 2915 rockchip,pins = 2916 <4 RK_PC1 3 &pcfg_pull_none>, 2917 <4 RK_PC0 3 &pcfg_pull_none>; 2918 }; 2919 2920 hdmi_cec: hdmi-cec { 2921 rockchip,pins = 2922 <4 RK_PC7 1 &pcfg_pull_none>; 2923 }; 2924 }; 2925 2926 pcie { 2927 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2928 rockchip,pins = 2929 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2930 }; 2931 2932 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2933 rockchip,pins = 2934 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2935 }; 2936 }; 2937 2938 }; 2939}; 2940