1/* 2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include <dt-bindings/clock/rk3399-cru.h> 44#include <dt-bindings/gpio/gpio.h> 45#include <dt-bindings/interrupt-controller/arm-gic.h> 46#include <dt-bindings/interrupt-controller/irq.h> 47#include <dt-bindings/pinctrl/rockchip.h> 48#include <dt-bindings/power/rk3399-power.h> 49#include <dt-bindings/thermal/thermal.h> 50 51/ { 52 compatible = "rockchip,rk3399"; 53 54 interrupt-parent = <&gic>; 55 #address-cells = <2>; 56 #size-cells = <2>; 57 58 aliases { 59 i2c0 = &i2c0; 60 i2c1 = &i2c1; 61 i2c2 = &i2c2; 62 i2c3 = &i2c3; 63 i2c4 = &i2c4; 64 i2c5 = &i2c5; 65 i2c6 = &i2c6; 66 i2c7 = &i2c7; 67 i2c8 = &i2c8; 68 serial0 = &uart0; 69 serial1 = &uart1; 70 serial2 = &uart2; 71 serial3 = &uart3; 72 serial4 = &uart4; 73 }; 74 75 cpus { 76 #address-cells = <2>; 77 #size-cells = <0>; 78 79 cpu-map { 80 cluster0 { 81 core0 { 82 cpu = <&cpu_l0>; 83 }; 84 core1 { 85 cpu = <&cpu_l1>; 86 }; 87 core2 { 88 cpu = <&cpu_l2>; 89 }; 90 core3 { 91 cpu = <&cpu_l3>; 92 }; 93 }; 94 95 cluster1 { 96 core0 { 97 cpu = <&cpu_b0>; 98 }; 99 core1 { 100 cpu = <&cpu_b1>; 101 }; 102 }; 103 }; 104 105 cpu_l0: cpu@0 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53", "arm,armv8"; 108 reg = <0x0 0x0>; 109 enable-method = "psci"; 110 #cooling-cells = <2>; /* min followed by max */ 111 clocks = <&cru ARMCLKL>; 112 }; 113 114 cpu_l1: cpu@1 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a53", "arm,armv8"; 117 reg = <0x0 0x1>; 118 enable-method = "psci"; 119 clocks = <&cru ARMCLKL>; 120 }; 121 122 cpu_l2: cpu@2 { 123 device_type = "cpu"; 124 compatible = "arm,cortex-a53", "arm,armv8"; 125 reg = <0x0 0x2>; 126 enable-method = "psci"; 127 clocks = <&cru ARMCLKL>; 128 }; 129 130 cpu_l3: cpu@3 { 131 device_type = "cpu"; 132 compatible = "arm,cortex-a53", "arm,armv8"; 133 reg = <0x0 0x3>; 134 enable-method = "psci"; 135 clocks = <&cru ARMCLKL>; 136 }; 137 138 cpu_b0: cpu@100 { 139 device_type = "cpu"; 140 compatible = "arm,cortex-a72", "arm,armv8"; 141 reg = <0x0 0x100>; 142 enable-method = "psci"; 143 #cooling-cells = <2>; /* min followed by max */ 144 clocks = <&cru ARMCLKB>; 145 }; 146 147 cpu_b1: cpu@101 { 148 device_type = "cpu"; 149 compatible = "arm,cortex-a72", "arm,armv8"; 150 reg = <0x0 0x101>; 151 enable-method = "psci"; 152 clocks = <&cru ARMCLKB>; 153 }; 154 }; 155 156 pmu_a53 { 157 compatible = "arm,cortex-a53-pmu"; 158 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 159 }; 160 161 pmu_a72 { 162 compatible = "arm,cortex-a72-pmu"; 163 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 164 }; 165 166 psci { 167 compatible = "arm,psci-1.0"; 168 method = "smc"; 169 }; 170 171 timer { 172 compatible = "arm,armv8-timer"; 173 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 174 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 175 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 176 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 177 arm,no-tick-in-suspend; 178 }; 179 180 xin24m: xin24m { 181 compatible = "fixed-clock"; 182 clock-frequency = <24000000>; 183 clock-output-names = "xin24m"; 184 #clock-cells = <0>; 185 }; 186 187 amba { 188 compatible = "simple-bus"; 189 #address-cells = <2>; 190 #size-cells = <2>; 191 ranges; 192 193 dmac_bus: dma-controller@ff6d0000 { 194 compatible = "arm,pl330", "arm,primecell"; 195 reg = <0x0 0xff6d0000 0x0 0x4000>; 196 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 197 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 198 #dma-cells = <1>; 199 clocks = <&cru ACLK_DMAC0_PERILP>; 200 clock-names = "apb_pclk"; 201 }; 202 203 dmac_peri: dma-controller@ff6e0000 { 204 compatible = "arm,pl330", "arm,primecell"; 205 reg = <0x0 0xff6e0000 0x0 0x4000>; 206 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 207 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 208 #dma-cells = <1>; 209 clocks = <&cru ACLK_DMAC1_PERILP>; 210 clock-names = "apb_pclk"; 211 }; 212 }; 213 214 gmac: ethernet@fe300000 { 215 compatible = "rockchip,rk3399-gmac"; 216 reg = <0x0 0xfe300000 0x0 0x10000>; 217 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 218 interrupt-names = "macirq"; 219 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 220 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 221 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 222 <&cru PCLK_GMAC>; 223 clock-names = "stmmaceth", "mac_clk_rx", 224 "mac_clk_tx", "clk_mac_ref", 225 "clk_mac_refout", "aclk_mac", 226 "pclk_mac"; 227 power-domains = <&power RK3399_PD_GMAC>; 228 resets = <&cru SRST_A_GMAC>; 229 reset-names = "stmmaceth"; 230 rockchip,grf = <&grf>; 231 status = "disabled"; 232 }; 233 234 sdio0: dwmmc@fe310000 { 235 compatible = "rockchip,rk3399-dw-mshc", 236 "rockchip,rk3288-dw-mshc"; 237 reg = <0x0 0xfe310000 0x0 0x4000>; 238 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 239 max-frequency = <150000000>; 240 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 241 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 242 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 243 fifo-depth = <0x100>; 244 status = "disabled"; 245 }; 246 247 sdmmc: dwmmc@fe320000 { 248 compatible = "rockchip,rk3399-dw-mshc", 249 "rockchip,rk3288-dw-mshc"; 250 reg = <0x0 0xfe320000 0x0 0x4000>; 251 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 252 max-frequency = <150000000>; 253 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 254 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 255 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 256 fifo-depth = <0x100>; 257 power-domains = <&power RK3399_PD_SD>; 258 status = "disabled"; 259 }; 260 261 sdhci: sdhci@fe330000 { 262 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 263 reg = <0x0 0xfe330000 0x0 0x10000>; 264 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 265 arasan,soc-ctl-syscon = <&grf>; 266 assigned-clocks = <&cru SCLK_EMMC>; 267 assigned-clock-rates = <200000000>; 268 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 269 clock-names = "clk_xin", "clk_ahb"; 270 clock-output-names = "emmc_cardclock"; 271 #clock-cells = <0>; 272 phys = <&emmc_phy>; 273 phy-names = "phy_arasan"; 274 power-domains = <&power RK3399_PD_EMMC>; 275 status = "disabled"; 276 }; 277 278 pcie0: pcie@f8000000 { 279 compatible = "rockchip,rk3399-pcie"; 280 reg = <0x0 0xf8000000 0x0 0x2000000>, 281 <0x0 0xfd000000 0x0 0x1000000>; 282 reg-names = "axi-base", "apb-base"; 283 #address-cells = <3>; 284 #size-cells = <2>; 285 #interrupt-cells = <1>; 286 aspm-no-l0s; 287 bus-range = <0x0 0x1>; 288 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 289 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 290 clock-names = "aclk", "aclk-perf", 291 "hclk", "pm"; 292 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 293 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 294 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 295 interrupt-names = "sys", "legacy", "client"; 296 interrupt-map-mask = <0 0 0 7>; 297 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 298 <0 0 0 2 &pcie0_intc 1>, 299 <0 0 0 3 &pcie0_intc 2>, 300 <0 0 0 4 &pcie0_intc 3>; 301 max-link-speed = <1>; 302 msi-map = <0x0 &its 0x0 0x1000>; 303 phys = <&pcie_phy>; 304 phy-names = "pcie-phy"; 305 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000 306 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>; 307 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 308 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 309 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 310 <&cru SRST_A_PCIE>; 311 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 312 "pm", "pclk", "aclk"; 313 status = "disabled"; 314 315 pcie0_intc: interrupt-controller { 316 interrupt-controller; 317 #address-cells = <0>; 318 #interrupt-cells = <1>; 319 }; 320 }; 321 322 usb_host0_ehci: usb@fe380000 { 323 compatible = "generic-ehci"; 324 reg = <0x0 0xfe380000 0x0 0x20000>; 325 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 326 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 327 <&u2phy0>; 328 clock-names = "usbhost", "arbiter", 329 "utmi"; 330 phys = <&u2phy0_host>; 331 phy-names = "usb"; 332 status = "disabled"; 333 }; 334 335 usb_host0_ohci: usb@fe3a0000 { 336 compatible = "generic-ohci"; 337 reg = <0x0 0xfe3a0000 0x0 0x20000>; 338 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 339 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 340 <&u2phy0>; 341 clock-names = "usbhost", "arbiter", 342 "utmi"; 343 phys = <&u2phy0_host>; 344 phy-names = "usb"; 345 status = "disabled"; 346 }; 347 348 usb_host1_ehci: usb@fe3c0000 { 349 compatible = "generic-ehci"; 350 reg = <0x0 0xfe3c0000 0x0 0x20000>; 351 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 352 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 353 <&u2phy1>; 354 clock-names = "usbhost", "arbiter", 355 "utmi"; 356 phys = <&u2phy1_host>; 357 phy-names = "usb"; 358 status = "disabled"; 359 }; 360 361 usb_host1_ohci: usb@fe3e0000 { 362 compatible = "generic-ohci"; 363 reg = <0x0 0xfe3e0000 0x0 0x20000>; 364 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 365 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 366 <&u2phy1>; 367 clock-names = "usbhost", "arbiter", 368 "utmi"; 369 phys = <&u2phy1_host>; 370 phy-names = "usb"; 371 status = "disabled"; 372 }; 373 374 gic: interrupt-controller@fee00000 { 375 compatible = "arm,gic-v3"; 376 #interrupt-cells = <4>; 377 #address-cells = <2>; 378 #size-cells = <2>; 379 ranges; 380 interrupt-controller; 381 382 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 383 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 384 <0x0 0xfff00000 0 0x10000>, /* GICC */ 385 <0x0 0xfff10000 0 0x10000>, /* GICH */ 386 <0x0 0xfff20000 0 0x10000>; /* GICV */ 387 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 388 its: interrupt-controller@fee20000 { 389 compatible = "arm,gic-v3-its"; 390 msi-controller; 391 reg = <0x0 0xfee20000 0x0 0x20000>; 392 }; 393 394 ppi-partitions { 395 ppi_cluster0: interrupt-partition-0 { 396 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 397 }; 398 399 ppi_cluster1: interrupt-partition-1 { 400 affinity = <&cpu_b0 &cpu_b1>; 401 }; 402 }; 403 }; 404 405 saradc: saradc@ff100000 { 406 compatible = "rockchip,rk3399-saradc"; 407 reg = <0x0 0xff100000 0x0 0x100>; 408 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 409 #io-channel-cells = <1>; 410 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 411 clock-names = "saradc", "apb_pclk"; 412 resets = <&cru SRST_P_SARADC>; 413 reset-names = "saradc-apb"; 414 status = "disabled"; 415 }; 416 417 i2c1: i2c@ff110000 { 418 compatible = "rockchip,rk3399-i2c"; 419 reg = <0x0 0xff110000 0x0 0x1000>; 420 assigned-clocks = <&cru SCLK_I2C1>; 421 assigned-clock-rates = <200000000>; 422 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 423 clock-names = "i2c", "pclk"; 424 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 425 pinctrl-names = "default"; 426 pinctrl-0 = <&i2c1_xfer>; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 status = "disabled"; 430 }; 431 432 i2c2: i2c@ff120000 { 433 compatible = "rockchip,rk3399-i2c"; 434 reg = <0x0 0xff120000 0x0 0x1000>; 435 assigned-clocks = <&cru SCLK_I2C2>; 436 assigned-clock-rates = <200000000>; 437 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 438 clock-names = "i2c", "pclk"; 439 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 440 pinctrl-names = "default"; 441 pinctrl-0 = <&i2c2_xfer>; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 status = "disabled"; 445 }; 446 447 i2c3: i2c@ff130000 { 448 compatible = "rockchip,rk3399-i2c"; 449 reg = <0x0 0xff130000 0x0 0x1000>; 450 assigned-clocks = <&cru SCLK_I2C3>; 451 assigned-clock-rates = <200000000>; 452 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 453 clock-names = "i2c", "pclk"; 454 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 455 pinctrl-names = "default"; 456 pinctrl-0 = <&i2c3_xfer>; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 status = "disabled"; 460 }; 461 462 i2c5: i2c@ff140000 { 463 compatible = "rockchip,rk3399-i2c"; 464 reg = <0x0 0xff140000 0x0 0x1000>; 465 assigned-clocks = <&cru SCLK_I2C5>; 466 assigned-clock-rates = <200000000>; 467 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 468 clock-names = "i2c", "pclk"; 469 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 470 pinctrl-names = "default"; 471 pinctrl-0 = <&i2c5_xfer>; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 status = "disabled"; 475 }; 476 477 i2c6: i2c@ff150000 { 478 compatible = "rockchip,rk3399-i2c"; 479 reg = <0x0 0xff150000 0x0 0x1000>; 480 assigned-clocks = <&cru SCLK_I2C6>; 481 assigned-clock-rates = <200000000>; 482 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 483 clock-names = "i2c", "pclk"; 484 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 485 pinctrl-names = "default"; 486 pinctrl-0 = <&i2c6_xfer>; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 status = "disabled"; 490 }; 491 492 i2c7: i2c@ff160000 { 493 compatible = "rockchip,rk3399-i2c"; 494 reg = <0x0 0xff160000 0x0 0x1000>; 495 assigned-clocks = <&cru SCLK_I2C7>; 496 assigned-clock-rates = <200000000>; 497 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 498 clock-names = "i2c", "pclk"; 499 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 500 pinctrl-names = "default"; 501 pinctrl-0 = <&i2c7_xfer>; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 status = "disabled"; 505 }; 506 507 uart0: serial@ff180000 { 508 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 509 reg = <0x0 0xff180000 0x0 0x100>; 510 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 511 clock-names = "baudclk", "apb_pclk"; 512 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 513 reg-shift = <2>; 514 reg-io-width = <4>; 515 pinctrl-names = "default"; 516 pinctrl-0 = <&uart0_xfer>; 517 status = "disabled"; 518 }; 519 520 uart1: serial@ff190000 { 521 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 522 reg = <0x0 0xff190000 0x0 0x100>; 523 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 524 clock-names = "baudclk", "apb_pclk"; 525 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 526 reg-shift = <2>; 527 reg-io-width = <4>; 528 pinctrl-names = "default"; 529 pinctrl-0 = <&uart1_xfer>; 530 status = "disabled"; 531 }; 532 533 uart2: serial@ff1a0000 { 534 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 535 reg = <0x0 0xff1a0000 0x0 0x100>; 536 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 537 clock-names = "baudclk", "apb_pclk"; 538 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 539 reg-shift = <2>; 540 reg-io-width = <4>; 541 pinctrl-names = "default"; 542 pinctrl-0 = <&uart2c_xfer>; 543 status = "disabled"; 544 }; 545 546 uart3: serial@ff1b0000 { 547 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 548 reg = <0x0 0xff1b0000 0x0 0x100>; 549 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 550 clock-names = "baudclk", "apb_pclk"; 551 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 552 reg-shift = <2>; 553 reg-io-width = <4>; 554 pinctrl-names = "default"; 555 pinctrl-0 = <&uart3_xfer>; 556 status = "disabled"; 557 }; 558 559 spi0: spi@ff1c0000 { 560 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 561 reg = <0x0 0xff1c0000 0x0 0x1000>; 562 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 563 clock-names = "spiclk", "apb_pclk"; 564 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 565 pinctrl-names = "default"; 566 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 status = "disabled"; 570 }; 571 572 spi1: spi@ff1d0000 { 573 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 574 reg = <0x0 0xff1d0000 0x0 0x1000>; 575 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 576 clock-names = "spiclk", "apb_pclk"; 577 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 578 pinctrl-names = "default"; 579 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 580 #address-cells = <1>; 581 #size-cells = <0>; 582 status = "disabled"; 583 }; 584 585 spi2: spi@ff1e0000 { 586 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 587 reg = <0x0 0xff1e0000 0x0 0x1000>; 588 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 589 clock-names = "spiclk", "apb_pclk"; 590 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 591 pinctrl-names = "default"; 592 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 593 #address-cells = <1>; 594 #size-cells = <0>; 595 status = "disabled"; 596 }; 597 598 spi4: spi@ff1f0000 { 599 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 600 reg = <0x0 0xff1f0000 0x0 0x1000>; 601 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 602 clock-names = "spiclk", "apb_pclk"; 603 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 604 pinctrl-names = "default"; 605 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 status = "disabled"; 609 }; 610 611 spi5: spi@ff200000 { 612 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 613 reg = <0x0 0xff200000 0x0 0x1000>; 614 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 615 clock-names = "spiclk", "apb_pclk"; 616 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 617 pinctrl-names = "default"; 618 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 619 #address-cells = <1>; 620 #size-cells = <0>; 621 status = "disabled"; 622 }; 623 624 thermal_zones: thermal-zones { 625 cpu_thermal: cpu { 626 polling-delay-passive = <100>; 627 polling-delay = <1000>; 628 629 thermal-sensors = <&tsadc 0>; 630 631 trips { 632 cpu_alert0: cpu_alert0 { 633 temperature = <70000>; 634 hysteresis = <2000>; 635 type = "passive"; 636 }; 637 cpu_alert1: cpu_alert1 { 638 temperature = <75000>; 639 hysteresis = <2000>; 640 type = "passive"; 641 }; 642 cpu_crit: cpu_crit { 643 temperature = <95000>; 644 hysteresis = <2000>; 645 type = "critical"; 646 }; 647 }; 648 649 cooling-maps { 650 map0 { 651 trip = <&cpu_alert0>; 652 cooling-device = 653 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 654 }; 655 map1 { 656 trip = <&cpu_alert1>; 657 cooling-device = 658 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 659 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 660 }; 661 }; 662 }; 663 664 gpu_thermal: gpu { 665 polling-delay-passive = <100>; 666 polling-delay = <1000>; 667 668 thermal-sensors = <&tsadc 1>; 669 670 trips { 671 gpu_alert0: gpu_alert0 { 672 temperature = <75000>; 673 hysteresis = <2000>; 674 type = "passive"; 675 }; 676 gpu_crit: gpu_crit { 677 temperature = <95000>; 678 hysteresis = <2000>; 679 type = "critical"; 680 }; 681 }; 682 683 cooling-maps { 684 map0 { 685 trip = <&gpu_alert0>; 686 cooling-device = 687 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 688 }; 689 }; 690 }; 691 }; 692 693 tsadc: tsadc@ff260000 { 694 compatible = "rockchip,rk3399-tsadc"; 695 reg = <0x0 0xff260000 0x0 0x100>; 696 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 697 assigned-clocks = <&cru SCLK_TSADC>; 698 assigned-clock-rates = <750000>; 699 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 700 clock-names = "tsadc", "apb_pclk"; 701 resets = <&cru SRST_TSADC>; 702 reset-names = "tsadc-apb"; 703 rockchip,grf = <&grf>; 704 rockchip,hw-tshut-temp = <95000>; 705 pinctrl-names = "init", "default", "sleep"; 706 pinctrl-0 = <&otp_gpio>; 707 pinctrl-1 = <&otp_out>; 708 pinctrl-2 = <&otp_gpio>; 709 #thermal-sensor-cells = <1>; 710 status = "disabled"; 711 }; 712 713 qos_sd: qos@ffa74000 { 714 compatible = "syscon"; 715 reg = <0x0 0xffa74000 0x0 0x20>; 716 }; 717 718 qos_emmc: qos@ffa58000 { 719 compatible = "syscon"; 720 reg = <0x0 0xffa58000 0x0 0x20>; 721 }; 722 723 qos_gmac: qos@ffa5c000 { 724 compatible = "syscon"; 725 reg = <0x0 0xffa5c000 0x0 0x20>; 726 }; 727 728 qos_hdcp: qos@ffa90000 { 729 compatible = "syscon"; 730 reg = <0x0 0xffa90000 0x0 0x20>; 731 }; 732 733 qos_iep: qos@ffa98000 { 734 compatible = "syscon"; 735 reg = <0x0 0xffa98000 0x0 0x20>; 736 }; 737 738 qos_isp0_m0: qos@ffaa0000 { 739 compatible = "syscon"; 740 reg = <0x0 0xffaa0000 0x0 0x20>; 741 }; 742 743 qos_isp0_m1: qos@ffaa0080 { 744 compatible = "syscon"; 745 reg = <0x0 0xffaa0080 0x0 0x20>; 746 }; 747 748 qos_isp1_m0: qos@ffaa8000 { 749 compatible = "syscon"; 750 reg = <0x0 0xffaa8000 0x0 0x20>; 751 }; 752 753 qos_isp1_m1: qos@ffaa8080 { 754 compatible = "syscon"; 755 reg = <0x0 0xffaa8080 0x0 0x20>; 756 }; 757 758 qos_rga_r: qos@ffab0000 { 759 compatible = "syscon"; 760 reg = <0x0 0xffab0000 0x0 0x20>; 761 }; 762 763 qos_rga_w: qos@ffab0080 { 764 compatible = "syscon"; 765 reg = <0x0 0xffab0080 0x0 0x20>; 766 }; 767 768 qos_video_m0: qos@ffab8000 { 769 compatible = "syscon"; 770 reg = <0x0 0xffab8000 0x0 0x20>; 771 }; 772 773 qos_video_m1_r: qos@ffac0000 { 774 compatible = "syscon"; 775 reg = <0x0 0xffac0000 0x0 0x20>; 776 }; 777 778 qos_video_m1_w: qos@ffac0080 { 779 compatible = "syscon"; 780 reg = <0x0 0xffac0080 0x0 0x20>; 781 }; 782 783 qos_vop_big_r: qos@ffac8000 { 784 compatible = "syscon"; 785 reg = <0x0 0xffac8000 0x0 0x20>; 786 }; 787 788 qos_vop_big_w: qos@ffac8080 { 789 compatible = "syscon"; 790 reg = <0x0 0xffac8080 0x0 0x20>; 791 }; 792 793 qos_vop_little: qos@ffad0000 { 794 compatible = "syscon"; 795 reg = <0x0 0xffad0000 0x0 0x20>; 796 }; 797 798 qos_gpu: qos@ffae0000 { 799 compatible = "syscon"; 800 reg = <0x0 0xffae0000 0x0 0x20>; 801 }; 802 803 pmu: power-management@ff310000 { 804 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 805 reg = <0x0 0xff310000 0x0 0x1000>; 806 807 /* 808 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 809 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 810 * Some of the power domains are grouped together for every 811 * voltage domain. 812 * The detail contents as below. 813 */ 814 power: power-controller { 815 compatible = "rockchip,rk3399-power-controller"; 816 #power-domain-cells = <1>; 817 #address-cells = <1>; 818 #size-cells = <0>; 819 820 /* These power domains are grouped by VD_CENTER */ 821 pd_iep@RK3399_PD_IEP { 822 reg = <RK3399_PD_IEP>; 823 clocks = <&cru ACLK_IEP>, 824 <&cru HCLK_IEP>; 825 pm_qos = <&qos_iep>; 826 }; 827 pd_rga@RK3399_PD_RGA { 828 reg = <RK3399_PD_RGA>; 829 clocks = <&cru ACLK_RGA>, 830 <&cru HCLK_RGA>; 831 pm_qos = <&qos_rga_r>, 832 <&qos_rga_w>; 833 }; 834 pd_vcodec@RK3399_PD_VCODEC { 835 reg = <RK3399_PD_VCODEC>; 836 clocks = <&cru ACLK_VCODEC>, 837 <&cru HCLK_VCODEC>; 838 pm_qos = <&qos_video_m0>; 839 }; 840 pd_vdu@RK3399_PD_VDU { 841 reg = <RK3399_PD_VDU>; 842 clocks = <&cru ACLK_VDU>, 843 <&cru HCLK_VDU>; 844 pm_qos = <&qos_video_m1_r>, 845 <&qos_video_m1_w>; 846 }; 847 848 /* These power domains are grouped by VD_GPU */ 849 pd_gpu@RK3399_PD_GPU { 850 reg = <RK3399_PD_GPU>; 851 clocks = <&cru ACLK_GPU>; 852 pm_qos = <&qos_gpu>; 853 }; 854 855 /* These power domains are grouped by VD_LOGIC */ 856 pd_emmc@RK3399_PD_EMMC { 857 reg = <RK3399_PD_EMMC>; 858 clocks = <&cru ACLK_EMMC>; 859 pm_qos = <&qos_emmc>; 860 }; 861 pd_gmac@RK3399_PD_GMAC { 862 reg = <RK3399_PD_GMAC>; 863 clocks = <&cru ACLK_GMAC>, 864 <&cru PCLK_GMAC>; 865 pm_qos = <&qos_gmac>; 866 }; 867 pd_sd@RK3399_PD_SD { 868 reg = <RK3399_PD_SD>; 869 clocks = <&cru HCLK_SDMMC>, 870 <&cru SCLK_SDMMC>; 871 pm_qos = <&qos_sd>; 872 }; 873 pd_vio@RK3399_PD_VIO { 874 reg = <RK3399_PD_VIO>; 875 #address-cells = <1>; 876 #size-cells = <0>; 877 878 pd_hdcp@RK3399_PD_HDCP { 879 reg = <RK3399_PD_HDCP>; 880 clocks = <&cru ACLK_HDCP>, 881 <&cru HCLK_HDCP>, 882 <&cru PCLK_HDCP>; 883 pm_qos = <&qos_hdcp>; 884 }; 885 pd_isp0@RK3399_PD_ISP0 { 886 reg = <RK3399_PD_ISP0>; 887 clocks = <&cru ACLK_ISP0>, 888 <&cru HCLK_ISP0>; 889 pm_qos = <&qos_isp0_m0>, 890 <&qos_isp0_m1>; 891 }; 892 pd_isp1@RK3399_PD_ISP1 { 893 reg = <RK3399_PD_ISP1>; 894 clocks = <&cru ACLK_ISP1>, 895 <&cru HCLK_ISP1>; 896 pm_qos = <&qos_isp1_m0>, 897 <&qos_isp1_m1>; 898 }; 899 pd_tcpc0@RK3399_PD_TCPC0 { 900 reg = <RK3399_PD_TCPD0>; 901 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 902 <&cru SCLK_UPHY0_TCPDPHY_REF>; 903 }; 904 pd_tcpc1@RK3399_PD_TCPC1 { 905 reg = <RK3399_PD_TCPD1>; 906 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 907 <&cru SCLK_UPHY1_TCPDPHY_REF>; 908 }; 909 pd_vo@RK3399_PD_VO { 910 reg = <RK3399_PD_VO>; 911 #address-cells = <1>; 912 #size-cells = <0>; 913 914 pd_vopb@RK3399_PD_VOPB { 915 reg = <RK3399_PD_VOPB>; 916 clocks = <&cru ACLK_VOP0>, 917 <&cru HCLK_VOP0>; 918 pm_qos = <&qos_vop_big_r>, 919 <&qos_vop_big_w>; 920 }; 921 pd_vopl@RK3399_PD_VOPL { 922 reg = <RK3399_PD_VOPL>; 923 clocks = <&cru ACLK_VOP1>, 924 <&cru HCLK_VOP1>; 925 pm_qos = <&qos_vop_little>; 926 }; 927 }; 928 }; 929 }; 930 }; 931 932 pmugrf: syscon@ff320000 { 933 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 934 reg = <0x0 0xff320000 0x0 0x1000>; 935 #address-cells = <1>; 936 #size-cells = <1>; 937 938 pmu_io_domains: io-domains { 939 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 940 status = "disabled"; 941 }; 942 }; 943 944 spi3: spi@ff350000 { 945 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 946 reg = <0x0 0xff350000 0x0 0x1000>; 947 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 948 clock-names = "spiclk", "apb_pclk"; 949 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 950 pinctrl-names = "default"; 951 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 952 #address-cells = <1>; 953 #size-cells = <0>; 954 status = "disabled"; 955 }; 956 957 uart4: serial@ff370000 { 958 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 959 reg = <0x0 0xff370000 0x0 0x100>; 960 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 961 clock-names = "baudclk", "apb_pclk"; 962 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 963 reg-shift = <2>; 964 reg-io-width = <4>; 965 pinctrl-names = "default"; 966 pinctrl-0 = <&uart4_xfer>; 967 status = "disabled"; 968 }; 969 970 i2c0: i2c@ff3c0000 { 971 compatible = "rockchip,rk3399-i2c"; 972 reg = <0x0 0xff3c0000 0x0 0x1000>; 973 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 974 assigned-clock-rates = <200000000>; 975 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 976 clock-names = "i2c", "pclk"; 977 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 978 pinctrl-names = "default"; 979 pinctrl-0 = <&i2c0_xfer>; 980 #address-cells = <1>; 981 #size-cells = <0>; 982 status = "disabled"; 983 }; 984 985 i2c4: i2c@ff3d0000 { 986 compatible = "rockchip,rk3399-i2c"; 987 reg = <0x0 0xff3d0000 0x0 0x1000>; 988 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 989 assigned-clock-rates = <200000000>; 990 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 991 clock-names = "i2c", "pclk"; 992 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 993 pinctrl-names = "default"; 994 pinctrl-0 = <&i2c4_xfer>; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 status = "disabled"; 998 }; 999 1000 i2c8: i2c@ff3e0000 { 1001 compatible = "rockchip,rk3399-i2c"; 1002 reg = <0x0 0xff3e0000 0x0 0x1000>; 1003 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1004 assigned-clock-rates = <200000000>; 1005 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1006 clock-names = "i2c", "pclk"; 1007 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1008 pinctrl-names = "default"; 1009 pinctrl-0 = <&i2c8_xfer>; 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 status = "disabled"; 1013 }; 1014 1015 pwm0: pwm@ff420000 { 1016 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1017 reg = <0x0 0xff420000 0x0 0x10>; 1018 #pwm-cells = <3>; 1019 pinctrl-names = "default"; 1020 pinctrl-0 = <&pwm0_pin>; 1021 clocks = <&pmucru PCLK_RKPWM_PMU>; 1022 clock-names = "pwm"; 1023 status = "disabled"; 1024 }; 1025 1026 pwm1: pwm@ff420010 { 1027 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1028 reg = <0x0 0xff420010 0x0 0x10>; 1029 #pwm-cells = <3>; 1030 pinctrl-names = "default"; 1031 pinctrl-0 = <&pwm1_pin>; 1032 clocks = <&pmucru PCLK_RKPWM_PMU>; 1033 clock-names = "pwm"; 1034 status = "disabled"; 1035 }; 1036 1037 pwm2: pwm@ff420020 { 1038 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1039 reg = <0x0 0xff420020 0x0 0x10>; 1040 #pwm-cells = <3>; 1041 pinctrl-names = "default"; 1042 pinctrl-0 = <&pwm2_pin>; 1043 clocks = <&pmucru PCLK_RKPWM_PMU>; 1044 clock-names = "pwm"; 1045 status = "disabled"; 1046 }; 1047 1048 pwm3: pwm@ff420030 { 1049 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1050 reg = <0x0 0xff420030 0x0 0x10>; 1051 #pwm-cells = <3>; 1052 pinctrl-names = "default"; 1053 pinctrl-0 = <&pwm3a_pin>; 1054 clocks = <&pmucru PCLK_RKPWM_PMU>; 1055 clock-names = "pwm"; 1056 status = "disabled"; 1057 }; 1058 1059 efuse0: efuse@ff690000 { 1060 compatible = "rockchip,rk3399-efuse"; 1061 reg = <0x0 0xff690000 0x0 0x80>; 1062 #address-cells = <1>; 1063 #size-cells = <1>; 1064 clocks = <&cru PCLK_EFUSE1024NS>; 1065 clock-names = "pclk_efuse"; 1066 1067 /* Data cells */ 1068 cpu_id: cpu-id@7 { 1069 reg = <0x07 0x10>; 1070 }; 1071 cpub_leakage: cpu-leakage@17 { 1072 reg = <0x17 0x1>; 1073 }; 1074 gpu_leakage: gpu-leakage@18 { 1075 reg = <0x18 0x1>; 1076 }; 1077 center_leakage: center-leakage@19 { 1078 reg = <0x19 0x1>; 1079 }; 1080 cpul_leakage: cpu-leakage@1a { 1081 reg = <0x1a 0x1>; 1082 }; 1083 logic_leakage: logic-leakage@1b { 1084 reg = <0x1b 0x1>; 1085 }; 1086 wafer_info: wafer-info@1c { 1087 reg = <0x1c 0x1>; 1088 }; 1089 }; 1090 1091 pmucru: pmu-clock-controller@ff750000 { 1092 compatible = "rockchip,rk3399-pmucru"; 1093 reg = <0x0 0xff750000 0x0 0x1000>; 1094 rockchip,grf = <&pmugrf>; 1095 #clock-cells = <1>; 1096 #reset-cells = <1>; 1097 assigned-clocks = <&pmucru PLL_PPLL>; 1098 assigned-clock-rates = <676000000>; 1099 }; 1100 1101 cru: clock-controller@ff760000 { 1102 compatible = "rockchip,rk3399-cru"; 1103 reg = <0x0 0xff760000 0x0 0x1000>; 1104 rockchip,grf = <&grf>; 1105 #clock-cells = <1>; 1106 #reset-cells = <1>; 1107 assigned-clocks = 1108 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1109 <&cru PLL_NPLL>, 1110 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1111 <&cru PCLK_PERIHP>, 1112 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1113 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1114 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; 1115 assigned-clock-rates = 1116 <594000000>, <800000000>, 1117 <1000000000>, 1118 <150000000>, <75000000>, 1119 <37500000>, 1120 <100000000>, <100000000>, 1121 <50000000>, <600000000>, 1122 <100000000>, <50000000>; 1123 }; 1124 1125 grf: syscon@ff770000 { 1126 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1127 reg = <0x0 0xff770000 0x0 0x10000>; 1128 #address-cells = <1>; 1129 #size-cells = <1>; 1130 1131 io_domains: io-domains { 1132 compatible = "rockchip,rk3399-io-voltage-domain"; 1133 status = "disabled"; 1134 }; 1135 1136 u2phy0: usb2-phy@e450 { 1137 compatible = "rockchip,rk3399-usb2phy"; 1138 reg = <0xe450 0x10>; 1139 clocks = <&cru SCLK_USB2PHY0_REF>; 1140 clock-names = "phyclk"; 1141 #clock-cells = <0>; 1142 clock-output-names = "clk_usbphy0_480m"; 1143 status = "disabled"; 1144 1145 u2phy0_host: host-port { 1146 #phy-cells = <0>; 1147 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1148 interrupt-names = "linestate"; 1149 status = "disabled"; 1150 }; 1151 1152 u2phy0_otg: otg-port { 1153 #phy-cells = <0>; 1154 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1155 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1156 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1157 interrupt-names = "otg-bvalid", "otg-id", 1158 "linestate"; 1159 status = "disabled"; 1160 }; 1161 }; 1162 1163 u2phy1: usb2-phy@e460 { 1164 compatible = "rockchip,rk3399-usb2phy"; 1165 reg = <0xe460 0x10>; 1166 clocks = <&cru SCLK_USB2PHY1_REF>; 1167 clock-names = "phyclk"; 1168 #clock-cells = <0>; 1169 clock-output-names = "clk_usbphy1_480m"; 1170 status = "disabled"; 1171 1172 u2phy1_host: host-port { 1173 #phy-cells = <0>; 1174 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1175 interrupt-names = "linestate"; 1176 status = "disabled"; 1177 }; 1178 1179 u2phy1_otg: otg-port { 1180 #phy-cells = <0>; 1181 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1182 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1183 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1184 interrupt-names = "otg-bvalid", "otg-id", 1185 "linestate"; 1186 status = "disabled"; 1187 }; 1188 }; 1189 1190 emmc_phy: phy@f780 { 1191 compatible = "rockchip,rk3399-emmc-phy"; 1192 reg = <0xf780 0x24>; 1193 clocks = <&sdhci>; 1194 clock-names = "emmcclk"; 1195 #phy-cells = <0>; 1196 status = "disabled"; 1197 }; 1198 1199 pcie_phy: pcie-phy { 1200 compatible = "rockchip,rk3399-pcie-phy"; 1201 clocks = <&cru SCLK_PCIEPHY_REF>; 1202 clock-names = "refclk"; 1203 #phy-cells = <0>; 1204 resets = <&cru SRST_PCIEPHY>; 1205 reset-names = "phy"; 1206 status = "disabled"; 1207 }; 1208 }; 1209 1210 tcphy0: phy@ff7c0000 { 1211 compatible = "rockchip,rk3399-typec-phy"; 1212 reg = <0x0 0xff7c0000 0x0 0x40000>; 1213 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1214 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1215 clock-names = "tcpdcore", "tcpdphy-ref"; 1216 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1217 assigned-clock-rates = <50000000>; 1218 power-domains = <&power RK3399_PD_TCPD0>; 1219 resets = <&cru SRST_UPHY0>, 1220 <&cru SRST_UPHY0_PIPE_L00>, 1221 <&cru SRST_P_UPHY0_TCPHY>; 1222 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1223 rockchip,grf = <&grf>; 1224 rockchip,typec-conn-dir = <0xe580 0 16>; 1225 rockchip,usb3tousb2-en = <0xe580 3 19>; 1226 rockchip,external-psm = <0xe588 14 30>; 1227 rockchip,pipe-status = <0xe5c0 0 0>; 1228 status = "disabled"; 1229 1230 tcphy0_dp: dp-port { 1231 #phy-cells = <0>; 1232 }; 1233 1234 tcphy0_usb3: usb3-port { 1235 #phy-cells = <0>; 1236 }; 1237 }; 1238 1239 tcphy1: phy@ff800000 { 1240 compatible = "rockchip,rk3399-typec-phy"; 1241 reg = <0x0 0xff800000 0x0 0x40000>; 1242 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1243 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1244 clock-names = "tcpdcore", "tcpdphy-ref"; 1245 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1246 assigned-clock-rates = <50000000>; 1247 power-domains = <&power RK3399_PD_TCPD1>; 1248 resets = <&cru SRST_UPHY1>, 1249 <&cru SRST_UPHY1_PIPE_L00>, 1250 <&cru SRST_P_UPHY1_TCPHY>; 1251 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1252 rockchip,grf = <&grf>; 1253 rockchip,typec-conn-dir = <0xe58c 0 16>; 1254 rockchip,usb3tousb2-en = <0xe58c 3 19>; 1255 rockchip,external-psm = <0xe594 14 30>; 1256 rockchip,pipe-status = <0xe5c0 16 16>; 1257 status = "disabled"; 1258 1259 tcphy1_dp: dp-port { 1260 #phy-cells = <0>; 1261 }; 1262 1263 tcphy1_usb3: usb3-port { 1264 #phy-cells = <0>; 1265 }; 1266 }; 1267 1268 watchdog@ff848000 { 1269 compatible = "snps,dw-wdt"; 1270 reg = <0x0 0xff848000 0x0 0x100>; 1271 clocks = <&cru PCLK_WDT>; 1272 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1273 }; 1274 1275 rktimer: rktimer@ff850000 { 1276 compatible = "rockchip,rk3399-timer"; 1277 reg = <0x0 0xff850000 0x0 0x1000>; 1278 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1279 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1280 clock-names = "pclk", "timer"; 1281 }; 1282 1283 spdif: spdif@ff870000 { 1284 compatible = "rockchip,rk3399-spdif"; 1285 reg = <0x0 0xff870000 0x0 0x1000>; 1286 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1287 dmas = <&dmac_bus 7>; 1288 dma-names = "tx"; 1289 clock-names = "mclk", "hclk"; 1290 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1291 pinctrl-names = "default"; 1292 pinctrl-0 = <&spdif_bus>; 1293 status = "disabled"; 1294 }; 1295 1296 i2s0: i2s@ff880000 { 1297 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1298 reg = <0x0 0xff880000 0x0 0x1000>; 1299 rockchip,grf = <&grf>; 1300 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1301 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1302 dma-names = "tx", "rx"; 1303 clock-names = "i2s_clk", "i2s_hclk"; 1304 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1305 pinctrl-names = "default"; 1306 pinctrl-0 = <&i2s0_8ch_bus>; 1307 status = "disabled"; 1308 }; 1309 1310 i2s1: i2s@ff890000 { 1311 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1312 reg = <0x0 0xff890000 0x0 0x1000>; 1313 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1314 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1315 dma-names = "tx", "rx"; 1316 clock-names = "i2s_clk", "i2s_hclk"; 1317 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1318 pinctrl-names = "default"; 1319 pinctrl-0 = <&i2s1_2ch_bus>; 1320 status = "disabled"; 1321 }; 1322 1323 i2s2: i2s@ff8a0000 { 1324 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1325 reg = <0x0 0xff8a0000 0x0 0x1000>; 1326 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1327 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1328 dma-names = "tx", "rx"; 1329 clock-names = "i2s_clk", "i2s_hclk"; 1330 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1331 status = "disabled"; 1332 }; 1333 1334 pinctrl: pinctrl { 1335 compatible = "rockchip,rk3399-pinctrl"; 1336 rockchip,grf = <&grf>; 1337 rockchip,pmu = <&pmugrf>; 1338 #address-cells = <2>; 1339 #size-cells = <2>; 1340 ranges; 1341 1342 gpio0: gpio0@ff720000 { 1343 compatible = "rockchip,gpio-bank"; 1344 reg = <0x0 0xff720000 0x0 0x100>; 1345 clocks = <&pmucru PCLK_GPIO0_PMU>; 1346 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 1347 1348 gpio-controller; 1349 #gpio-cells = <0x2>; 1350 1351 interrupt-controller; 1352 #interrupt-cells = <0x2>; 1353 }; 1354 1355 gpio1: gpio1@ff730000 { 1356 compatible = "rockchip,gpio-bank"; 1357 reg = <0x0 0xff730000 0x0 0x100>; 1358 clocks = <&pmucru PCLK_GPIO1_PMU>; 1359 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 1360 1361 gpio-controller; 1362 #gpio-cells = <0x2>; 1363 1364 interrupt-controller; 1365 #interrupt-cells = <0x2>; 1366 }; 1367 1368 gpio2: gpio2@ff780000 { 1369 compatible = "rockchip,gpio-bank"; 1370 reg = <0x0 0xff780000 0x0 0x100>; 1371 clocks = <&cru PCLK_GPIO2>; 1372 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 1373 1374 gpio-controller; 1375 #gpio-cells = <0x2>; 1376 1377 interrupt-controller; 1378 #interrupt-cells = <0x2>; 1379 }; 1380 1381 gpio3: gpio3@ff788000 { 1382 compatible = "rockchip,gpio-bank"; 1383 reg = <0x0 0xff788000 0x0 0x100>; 1384 clocks = <&cru PCLK_GPIO3>; 1385 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 1386 1387 gpio-controller; 1388 #gpio-cells = <0x2>; 1389 1390 interrupt-controller; 1391 #interrupt-cells = <0x2>; 1392 }; 1393 1394 gpio4: gpio4@ff790000 { 1395 compatible = "rockchip,gpio-bank"; 1396 reg = <0x0 0xff790000 0x0 0x100>; 1397 clocks = <&cru PCLK_GPIO4>; 1398 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 1399 1400 gpio-controller; 1401 #gpio-cells = <0x2>; 1402 1403 interrupt-controller; 1404 #interrupt-cells = <0x2>; 1405 }; 1406 1407 pcfg_pull_up: pcfg-pull-up { 1408 bias-pull-up; 1409 }; 1410 1411 pcfg_pull_down: pcfg-pull-down { 1412 bias-pull-down; 1413 }; 1414 1415 pcfg_pull_none: pcfg-pull-none { 1416 bias-disable; 1417 }; 1418 1419 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1420 bias-disable; 1421 drive-strength = <12>; 1422 }; 1423 1424 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1425 bias-pull-up; 1426 drive-strength = <8>; 1427 }; 1428 1429 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1430 bias-pull-down; 1431 drive-strength = <4>; 1432 }; 1433 1434 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1435 bias-pull-up; 1436 drive-strength = <2>; 1437 }; 1438 1439 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 1440 bias-pull-down; 1441 drive-strength = <12>; 1442 }; 1443 1444 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 1445 bias-disable; 1446 drive-strength = <13>; 1447 }; 1448 1449 clock { 1450 clk_32k: clk-32k { 1451 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; 1452 }; 1453 }; 1454 1455 edp { 1456 edp_hpd: edp-hpd { 1457 rockchip,pins = 1458 <4 23 RK_FUNC_2 &pcfg_pull_none>; 1459 }; 1460 }; 1461 1462 gmac { 1463 rgmii_pins: rgmii-pins { 1464 rockchip,pins = 1465 /* mac_txclk */ 1466 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>, 1467 /* mac_rxclk */ 1468 <3 14 RK_FUNC_1 &pcfg_pull_none>, 1469 /* mac_mdio */ 1470 <3 13 RK_FUNC_1 &pcfg_pull_none>, 1471 /* mac_txen */ 1472 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>, 1473 /* mac_clk */ 1474 <3 11 RK_FUNC_1 &pcfg_pull_none>, 1475 /* mac_rxdv */ 1476 <3 9 RK_FUNC_1 &pcfg_pull_none>, 1477 /* mac_mdc */ 1478 <3 8 RK_FUNC_1 &pcfg_pull_none>, 1479 /* mac_rxd1 */ 1480 <3 7 RK_FUNC_1 &pcfg_pull_none>, 1481 /* mac_rxd0 */ 1482 <3 6 RK_FUNC_1 &pcfg_pull_none>, 1483 /* mac_txd1 */ 1484 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>, 1485 /* mac_txd0 */ 1486 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>, 1487 /* mac_rxd3 */ 1488 <3 3 RK_FUNC_1 &pcfg_pull_none>, 1489 /* mac_rxd2 */ 1490 <3 2 RK_FUNC_1 &pcfg_pull_none>, 1491 /* mac_txd3 */ 1492 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>, 1493 /* mac_txd2 */ 1494 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>; 1495 }; 1496 1497 rmii_pins: rmii-pins { 1498 rockchip,pins = 1499 /* mac_mdio */ 1500 <3 13 RK_FUNC_1 &pcfg_pull_none>, 1501 /* mac_txen */ 1502 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>, 1503 /* mac_clk */ 1504 <3 11 RK_FUNC_1 &pcfg_pull_none>, 1505 /* mac_rxer */ 1506 <3 10 RK_FUNC_1 &pcfg_pull_none>, 1507 /* mac_rxdv */ 1508 <3 9 RK_FUNC_1 &pcfg_pull_none>, 1509 /* mac_mdc */ 1510 <3 8 RK_FUNC_1 &pcfg_pull_none>, 1511 /* mac_rxd1 */ 1512 <3 7 RK_FUNC_1 &pcfg_pull_none>, 1513 /* mac_rxd0 */ 1514 <3 6 RK_FUNC_1 &pcfg_pull_none>, 1515 /* mac_txd1 */ 1516 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>, 1517 /* mac_txd0 */ 1518 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>; 1519 }; 1520 }; 1521 1522 i2c0 { 1523 i2c0_xfer: i2c0-xfer { 1524 rockchip,pins = 1525 <1 15 RK_FUNC_2 &pcfg_pull_none>, 1526 <1 16 RK_FUNC_2 &pcfg_pull_none>; 1527 }; 1528 }; 1529 1530 i2c1 { 1531 i2c1_xfer: i2c1-xfer { 1532 rockchip,pins = 1533 <4 2 RK_FUNC_1 &pcfg_pull_none>, 1534 <4 1 RK_FUNC_1 &pcfg_pull_none>; 1535 }; 1536 }; 1537 1538 i2c2 { 1539 i2c2_xfer: i2c2-xfer { 1540 rockchip,pins = 1541 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>, 1542 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>; 1543 }; 1544 }; 1545 1546 i2c3 { 1547 i2c3_xfer: i2c3-xfer { 1548 rockchip,pins = 1549 <4 17 RK_FUNC_1 &pcfg_pull_none>, 1550 <4 16 RK_FUNC_1 &pcfg_pull_none>; 1551 }; 1552 }; 1553 1554 i2c4 { 1555 i2c4_xfer: i2c4-xfer { 1556 rockchip,pins = 1557 <1 12 RK_FUNC_1 &pcfg_pull_none>, 1558 <1 11 RK_FUNC_1 &pcfg_pull_none>; 1559 }; 1560 }; 1561 1562 i2c5 { 1563 i2c5_xfer: i2c5-xfer { 1564 rockchip,pins = 1565 <3 11 RK_FUNC_2 &pcfg_pull_none>, 1566 <3 10 RK_FUNC_2 &pcfg_pull_none>; 1567 }; 1568 }; 1569 1570 i2c6 { 1571 i2c6_xfer: i2c6-xfer { 1572 rockchip,pins = 1573 <2 10 RK_FUNC_2 &pcfg_pull_none>, 1574 <2 9 RK_FUNC_2 &pcfg_pull_none>; 1575 }; 1576 }; 1577 1578 i2c7 { 1579 i2c7_xfer: i2c7-xfer { 1580 rockchip,pins = 1581 <2 8 RK_FUNC_2 &pcfg_pull_none>, 1582 <2 7 RK_FUNC_2 &pcfg_pull_none>; 1583 }; 1584 }; 1585 1586 i2c8 { 1587 i2c8_xfer: i2c8-xfer { 1588 rockchip,pins = 1589 <1 21 RK_FUNC_1 &pcfg_pull_none>, 1590 <1 20 RK_FUNC_1 &pcfg_pull_none>; 1591 }; 1592 }; 1593 1594 i2s0 { 1595 i2s0_8ch_bus: i2s0-8ch-bus { 1596 rockchip,pins = 1597 <3 24 RK_FUNC_1 &pcfg_pull_none>, 1598 <3 25 RK_FUNC_1 &pcfg_pull_none>, 1599 <3 26 RK_FUNC_1 &pcfg_pull_none>, 1600 <3 27 RK_FUNC_1 &pcfg_pull_none>, 1601 <3 28 RK_FUNC_1 &pcfg_pull_none>, 1602 <3 29 RK_FUNC_1 &pcfg_pull_none>, 1603 <3 30 RK_FUNC_1 &pcfg_pull_none>, 1604 <3 31 RK_FUNC_1 &pcfg_pull_none>, 1605 <4 0 RK_FUNC_1 &pcfg_pull_none>; 1606 }; 1607 }; 1608 1609 i2s1 { 1610 i2s1_2ch_bus: i2s1-2ch-bus { 1611 rockchip,pins = 1612 <4 3 RK_FUNC_1 &pcfg_pull_none>, 1613 <4 4 RK_FUNC_1 &pcfg_pull_none>, 1614 <4 5 RK_FUNC_1 &pcfg_pull_none>, 1615 <4 6 RK_FUNC_1 &pcfg_pull_none>, 1616 <4 7 RK_FUNC_1 &pcfg_pull_none>; 1617 }; 1618 }; 1619 1620 sleep { 1621 ap_pwroff: ap-pwroff { 1622 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>; 1623 }; 1624 1625 ddrio_pwroff: ddrio-pwroff { 1626 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; 1627 }; 1628 }; 1629 1630 spdif { 1631 spdif_bus: spdif-bus { 1632 rockchip,pins = 1633 <4 21 RK_FUNC_1 &pcfg_pull_none>; 1634 }; 1635 }; 1636 1637 spi0 { 1638 spi0_clk: spi0-clk { 1639 rockchip,pins = 1640 <3 6 RK_FUNC_2 &pcfg_pull_up>; 1641 }; 1642 spi0_cs0: spi0-cs0 { 1643 rockchip,pins = 1644 <3 7 RK_FUNC_2 &pcfg_pull_up>; 1645 }; 1646 spi0_cs1: spi0-cs1 { 1647 rockchip,pins = 1648 <3 8 RK_FUNC_2 &pcfg_pull_up>; 1649 }; 1650 spi0_tx: spi0-tx { 1651 rockchip,pins = 1652 <3 5 RK_FUNC_2 &pcfg_pull_up>; 1653 }; 1654 spi0_rx: spi0-rx { 1655 rockchip,pins = 1656 <3 4 RK_FUNC_2 &pcfg_pull_up>; 1657 }; 1658 }; 1659 1660 spi1 { 1661 spi1_clk: spi1-clk { 1662 rockchip,pins = 1663 <1 9 RK_FUNC_2 &pcfg_pull_up>; 1664 }; 1665 spi1_cs0: spi1-cs0 { 1666 rockchip,pins = 1667 <1 10 RK_FUNC_2 &pcfg_pull_up>; 1668 }; 1669 spi1_rx: spi1-rx { 1670 rockchip,pins = 1671 <1 7 RK_FUNC_2 &pcfg_pull_up>; 1672 }; 1673 spi1_tx: spi1-tx { 1674 rockchip,pins = 1675 <1 8 RK_FUNC_2 &pcfg_pull_up>; 1676 }; 1677 }; 1678 1679 spi2 { 1680 spi2_clk: spi2-clk { 1681 rockchip,pins = 1682 <2 11 RK_FUNC_1 &pcfg_pull_up>; 1683 }; 1684 spi2_cs0: spi2-cs0 { 1685 rockchip,pins = 1686 <2 12 RK_FUNC_1 &pcfg_pull_up>; 1687 }; 1688 spi2_rx: spi2-rx { 1689 rockchip,pins = 1690 <2 9 RK_FUNC_1 &pcfg_pull_up>; 1691 }; 1692 spi2_tx: spi2-tx { 1693 rockchip,pins = 1694 <2 10 RK_FUNC_1 &pcfg_pull_up>; 1695 }; 1696 }; 1697 1698 spi3 { 1699 spi3_clk: spi3-clk { 1700 rockchip,pins = 1701 <1 17 RK_FUNC_1 &pcfg_pull_up>; 1702 }; 1703 spi3_cs0: spi3-cs0 { 1704 rockchip,pins = 1705 <1 18 RK_FUNC_1 &pcfg_pull_up>; 1706 }; 1707 spi3_rx: spi3-rx { 1708 rockchip,pins = 1709 <1 15 RK_FUNC_1 &pcfg_pull_up>; 1710 }; 1711 spi3_tx: spi3-tx { 1712 rockchip,pins = 1713 <1 16 RK_FUNC_1 &pcfg_pull_up>; 1714 }; 1715 }; 1716 1717 spi4 { 1718 spi4_clk: spi4-clk { 1719 rockchip,pins = 1720 <3 2 RK_FUNC_2 &pcfg_pull_up>; 1721 }; 1722 spi4_cs0: spi4-cs0 { 1723 rockchip,pins = 1724 <3 3 RK_FUNC_2 &pcfg_pull_up>; 1725 }; 1726 spi4_rx: spi4-rx { 1727 rockchip,pins = 1728 <3 0 RK_FUNC_2 &pcfg_pull_up>; 1729 }; 1730 spi4_tx: spi4-tx { 1731 rockchip,pins = 1732 <3 1 RK_FUNC_2 &pcfg_pull_up>; 1733 }; 1734 }; 1735 1736 spi5 { 1737 spi5_clk: spi5-clk { 1738 rockchip,pins = 1739 <2 22 RK_FUNC_2 &pcfg_pull_up>; 1740 }; 1741 spi5_cs0: spi5-cs0 { 1742 rockchip,pins = 1743 <2 23 RK_FUNC_2 &pcfg_pull_up>; 1744 }; 1745 spi5_rx: spi5-rx { 1746 rockchip,pins = 1747 <2 20 RK_FUNC_2 &pcfg_pull_up>; 1748 }; 1749 spi5_tx: spi5-tx { 1750 rockchip,pins = 1751 <2 21 RK_FUNC_2 &pcfg_pull_up>; 1752 }; 1753 }; 1754 1755 tsadc { 1756 otp_gpio: otp-gpio { 1757 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>; 1758 }; 1759 1760 otp_out: otp-out { 1761 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>; 1762 }; 1763 }; 1764 1765 uart0 { 1766 uart0_xfer: uart0-xfer { 1767 rockchip,pins = 1768 <2 16 RK_FUNC_1 &pcfg_pull_up>, 1769 <2 17 RK_FUNC_1 &pcfg_pull_none>; 1770 }; 1771 1772 uart0_cts: uart0-cts { 1773 rockchip,pins = 1774 <2 18 RK_FUNC_1 &pcfg_pull_none>; 1775 }; 1776 1777 uart0_rts: uart0-rts { 1778 rockchip,pins = 1779 <2 19 RK_FUNC_1 &pcfg_pull_none>; 1780 }; 1781 }; 1782 1783 uart1 { 1784 uart1_xfer: uart1-xfer { 1785 rockchip,pins = 1786 <3 12 RK_FUNC_2 &pcfg_pull_up>, 1787 <3 13 RK_FUNC_2 &pcfg_pull_none>; 1788 }; 1789 }; 1790 1791 uart2a { 1792 uart2a_xfer: uart2a-xfer { 1793 rockchip,pins = 1794 <4 8 RK_FUNC_2 &pcfg_pull_up>, 1795 <4 9 RK_FUNC_2 &pcfg_pull_none>; 1796 }; 1797 }; 1798 1799 uart2b { 1800 uart2b_xfer: uart2b-xfer { 1801 rockchip,pins = 1802 <4 16 RK_FUNC_2 &pcfg_pull_up>, 1803 <4 17 RK_FUNC_2 &pcfg_pull_none>; 1804 }; 1805 }; 1806 1807 uart2c { 1808 uart2c_xfer: uart2c-xfer { 1809 rockchip,pins = 1810 <4 19 RK_FUNC_1 &pcfg_pull_up>, 1811 <4 20 RK_FUNC_1 &pcfg_pull_none>; 1812 }; 1813 }; 1814 1815 uart3 { 1816 uart3_xfer: uart3-xfer { 1817 rockchip,pins = 1818 <3 14 RK_FUNC_2 &pcfg_pull_up>, 1819 <3 15 RK_FUNC_2 &pcfg_pull_none>; 1820 }; 1821 1822 uart3_cts: uart3-cts { 1823 rockchip,pins = 1824 <3 18 RK_FUNC_2 &pcfg_pull_none>; 1825 }; 1826 1827 uart3_rts: uart3-rts { 1828 rockchip,pins = 1829 <3 19 RK_FUNC_2 &pcfg_pull_none>; 1830 }; 1831 }; 1832 1833 uart4 { 1834 uart4_xfer: uart4-xfer { 1835 rockchip,pins = 1836 <1 7 RK_FUNC_1 &pcfg_pull_up>, 1837 <1 8 RK_FUNC_1 &pcfg_pull_none>; 1838 }; 1839 }; 1840 1841 uarthdcp { 1842 uarthdcp_xfer: uarthdcp-xfer { 1843 rockchip,pins = 1844 <4 21 RK_FUNC_2 &pcfg_pull_up>, 1845 <4 22 RK_FUNC_2 &pcfg_pull_none>; 1846 }; 1847 }; 1848 1849 pwm0 { 1850 pwm0_pin: pwm0-pin { 1851 rockchip,pins = 1852 <4 18 RK_FUNC_1 &pcfg_pull_none>; 1853 }; 1854 1855 vop0_pwm_pin: vop0-pwm-pin { 1856 rockchip,pins = 1857 <4 18 RK_FUNC_2 &pcfg_pull_none>; 1858 }; 1859 }; 1860 1861 pwm1 { 1862 pwm1_pin: pwm1-pin { 1863 rockchip,pins = 1864 <4 22 RK_FUNC_1 &pcfg_pull_none>; 1865 }; 1866 1867 vop1_pwm_pin: vop1-pwm-pin { 1868 rockchip,pins = 1869 <4 18 RK_FUNC_3 &pcfg_pull_none>; 1870 }; 1871 }; 1872 1873 pwm2 { 1874 pwm2_pin: pwm2-pin { 1875 rockchip,pins = 1876 <1 19 RK_FUNC_1 &pcfg_pull_none>; 1877 }; 1878 }; 1879 1880 pwm3a { 1881 pwm3a_pin: pwm3a-pin { 1882 rockchip,pins = 1883 <0 6 RK_FUNC_1 &pcfg_pull_none>; 1884 }; 1885 }; 1886 1887 pwm3b { 1888 pwm3b_pin: pwm3b-pin { 1889 rockchip,pins = 1890 <1 14 RK_FUNC_1 &pcfg_pull_none>; 1891 }; 1892 }; 1893 1894 pcie { 1895 pcie_clkreqn: pci-clkreqn { 1896 rockchip,pins = 1897 <2 26 RK_FUNC_2 &pcfg_pull_none>; 1898 }; 1899 1900 pcie_clkreqnb: pci-clkreqnb { 1901 rockchip,pins = 1902 <4 24 RK_FUNC_1 &pcfg_pull_none>; 1903 }; 1904 }; 1905 1906 }; 1907}; 1908