1/* 2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include <dt-bindings/clock/rk3399-cru.h> 44#include <dt-bindings/gpio/gpio.h> 45#include <dt-bindings/interrupt-controller/arm-gic.h> 46#include <dt-bindings/interrupt-controller/irq.h> 47#include <dt-bindings/pinctrl/rockchip.h> 48#include <dt-bindings/power/rk3399-power.h> 49#include <dt-bindings/thermal/thermal.h> 50 51/ { 52 compatible = "rockchip,rk3399"; 53 54 interrupt-parent = <&gic>; 55 #address-cells = <2>; 56 #size-cells = <2>; 57 58 aliases { 59 ethernet0 = &gmac; 60 i2c0 = &i2c0; 61 i2c1 = &i2c1; 62 i2c2 = &i2c2; 63 i2c3 = &i2c3; 64 i2c4 = &i2c4; 65 i2c5 = &i2c5; 66 i2c6 = &i2c6; 67 i2c7 = &i2c7; 68 i2c8 = &i2c8; 69 serial0 = &uart0; 70 serial1 = &uart1; 71 serial2 = &uart2; 72 serial3 = &uart3; 73 serial4 = &uart4; 74 }; 75 76 cpus { 77 #address-cells = <2>; 78 #size-cells = <0>; 79 80 cpu-map { 81 cluster0 { 82 core0 { 83 cpu = <&cpu_l0>; 84 }; 85 core1 { 86 cpu = <&cpu_l1>; 87 }; 88 core2 { 89 cpu = <&cpu_l2>; 90 }; 91 core3 { 92 cpu = <&cpu_l3>; 93 }; 94 }; 95 96 cluster1 { 97 core0 { 98 cpu = <&cpu_b0>; 99 }; 100 core1 { 101 cpu = <&cpu_b1>; 102 }; 103 }; 104 }; 105 106 cpu_l0: cpu@0 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a53", "arm,armv8"; 109 reg = <0x0 0x0>; 110 enable-method = "psci"; 111 #cooling-cells = <2>; /* min followed by max */ 112 clocks = <&cru ARMCLKL>; 113 }; 114 115 cpu_l1: cpu@1 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a53", "arm,armv8"; 118 reg = <0x0 0x1>; 119 enable-method = "psci"; 120 clocks = <&cru ARMCLKL>; 121 }; 122 123 cpu_l2: cpu@2 { 124 device_type = "cpu"; 125 compatible = "arm,cortex-a53", "arm,armv8"; 126 reg = <0x0 0x2>; 127 enable-method = "psci"; 128 clocks = <&cru ARMCLKL>; 129 }; 130 131 cpu_l3: cpu@3 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-a53", "arm,armv8"; 134 reg = <0x0 0x3>; 135 enable-method = "psci"; 136 clocks = <&cru ARMCLKL>; 137 }; 138 139 cpu_b0: cpu@100 { 140 device_type = "cpu"; 141 compatible = "arm,cortex-a72", "arm,armv8"; 142 reg = <0x0 0x100>; 143 enable-method = "psci"; 144 #cooling-cells = <2>; /* min followed by max */ 145 clocks = <&cru ARMCLKB>; 146 }; 147 148 cpu_b1: cpu@101 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a72", "arm,armv8"; 151 reg = <0x0 0x101>; 152 enable-method = "psci"; 153 clocks = <&cru ARMCLKB>; 154 }; 155 }; 156 157 pmu_a53 { 158 compatible = "arm,cortex-a53-pmu"; 159 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 160 }; 161 162 pmu_a72 { 163 compatible = "arm,cortex-a72-pmu"; 164 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 165 }; 166 167 psci { 168 compatible = "arm,psci-1.0"; 169 method = "smc"; 170 }; 171 172 timer { 173 compatible = "arm,armv8-timer"; 174 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 175 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 176 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 177 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 178 arm,no-tick-in-suspend; 179 }; 180 181 xin24m: xin24m { 182 compatible = "fixed-clock"; 183 clock-frequency = <24000000>; 184 clock-output-names = "xin24m"; 185 #clock-cells = <0>; 186 }; 187 188 amba { 189 compatible = "simple-bus"; 190 #address-cells = <2>; 191 #size-cells = <2>; 192 ranges; 193 194 dmac_bus: dma-controller@ff6d0000 { 195 compatible = "arm,pl330", "arm,primecell"; 196 reg = <0x0 0xff6d0000 0x0 0x4000>; 197 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 198 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 199 #dma-cells = <1>; 200 clocks = <&cru ACLK_DMAC0_PERILP>; 201 clock-names = "apb_pclk"; 202 }; 203 204 dmac_peri: dma-controller@ff6e0000 { 205 compatible = "arm,pl330", "arm,primecell"; 206 reg = <0x0 0xff6e0000 0x0 0x4000>; 207 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 208 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 209 #dma-cells = <1>; 210 clocks = <&cru ACLK_DMAC1_PERILP>; 211 clock-names = "apb_pclk"; 212 }; 213 }; 214 215 pcie0: pcie@f8000000 { 216 compatible = "rockchip,rk3399-pcie"; 217 reg = <0x0 0xf8000000 0x0 0x2000000>, 218 <0x0 0xfd000000 0x0 0x1000000>; 219 reg-names = "axi-base", "apb-base"; 220 #address-cells = <3>; 221 #size-cells = <2>; 222 #interrupt-cells = <1>; 223 aspm-no-l0s; 224 bus-range = <0x0 0x1f>; 225 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 226 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 227 clock-names = "aclk", "aclk-perf", 228 "hclk", "pm"; 229 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 230 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 231 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 232 interrupt-names = "sys", "legacy", "client"; 233 interrupt-map-mask = <0 0 0 7>; 234 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 235 <0 0 0 2 &pcie0_intc 1>, 236 <0 0 0 3 &pcie0_intc 2>, 237 <0 0 0 4 &pcie0_intc 3>; 238 linux,pci-domain = <0>; 239 max-link-speed = <1>; 240 msi-map = <0x0 &its 0x0 0x1000>; 241 phys = <&pcie_phy>; 242 phy-names = "pcie-phy"; 243 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000 244 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; 245 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 246 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 247 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 248 <&cru SRST_A_PCIE>; 249 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 250 "pm", "pclk", "aclk"; 251 status = "disabled"; 252 253 pcie0_intc: interrupt-controller { 254 interrupt-controller; 255 #address-cells = <0>; 256 #interrupt-cells = <1>; 257 }; 258 }; 259 260 gmac: ethernet@fe300000 { 261 compatible = "rockchip,rk3399-gmac"; 262 reg = <0x0 0xfe300000 0x0 0x10000>; 263 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 264 interrupt-names = "macirq"; 265 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 266 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 267 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 268 <&cru PCLK_GMAC>; 269 clock-names = "stmmaceth", "mac_clk_rx", 270 "mac_clk_tx", "clk_mac_ref", 271 "clk_mac_refout", "aclk_mac", 272 "pclk_mac"; 273 power-domains = <&power RK3399_PD_GMAC>; 274 resets = <&cru SRST_A_GMAC>; 275 reset-names = "stmmaceth"; 276 rockchip,grf = <&grf>; 277 status = "disabled"; 278 }; 279 280 sdio0: dwmmc@fe310000 { 281 compatible = "rockchip,rk3399-dw-mshc", 282 "rockchip,rk3288-dw-mshc"; 283 reg = <0x0 0xfe310000 0x0 0x4000>; 284 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 285 max-frequency = <150000000>; 286 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 287 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 288 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 289 fifo-depth = <0x100>; 290 resets = <&cru SRST_SDIO0>; 291 reset-names = "reset"; 292 status = "disabled"; 293 }; 294 295 sdmmc: dwmmc@fe320000 { 296 compatible = "rockchip,rk3399-dw-mshc", 297 "rockchip,rk3288-dw-mshc"; 298 reg = <0x0 0xfe320000 0x0 0x4000>; 299 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 300 max-frequency = <150000000>; 301 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 302 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 303 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 304 fifo-depth = <0x100>; 305 power-domains = <&power RK3399_PD_SD>; 306 resets = <&cru SRST_SDMMC>; 307 reset-names = "reset"; 308 status = "disabled"; 309 }; 310 311 sdhci: sdhci@fe330000 { 312 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 313 reg = <0x0 0xfe330000 0x0 0x10000>; 314 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 315 arasan,soc-ctl-syscon = <&grf>; 316 assigned-clocks = <&cru SCLK_EMMC>; 317 assigned-clock-rates = <200000000>; 318 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 319 clock-names = "clk_xin", "clk_ahb"; 320 clock-output-names = "emmc_cardclock"; 321 #clock-cells = <0>; 322 phys = <&emmc_phy>; 323 phy-names = "phy_arasan"; 324 power-domains = <&power RK3399_PD_EMMC>; 325 status = "disabled"; 326 }; 327 328 usb_host0_ehci: usb@fe380000 { 329 compatible = "generic-ehci"; 330 reg = <0x0 0xfe380000 0x0 0x20000>; 331 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 332 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 333 <&u2phy0>; 334 clock-names = "usbhost", "arbiter", 335 "utmi"; 336 phys = <&u2phy0_host>; 337 phy-names = "usb"; 338 status = "disabled"; 339 }; 340 341 usb_host0_ohci: usb@fe3a0000 { 342 compatible = "generic-ohci"; 343 reg = <0x0 0xfe3a0000 0x0 0x20000>; 344 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 345 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 346 <&u2phy0>; 347 clock-names = "usbhost", "arbiter", 348 "utmi"; 349 phys = <&u2phy0_host>; 350 phy-names = "usb"; 351 status = "disabled"; 352 }; 353 354 usb_host1_ehci: usb@fe3c0000 { 355 compatible = "generic-ehci"; 356 reg = <0x0 0xfe3c0000 0x0 0x20000>; 357 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 358 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 359 <&u2phy1>; 360 clock-names = "usbhost", "arbiter", 361 "utmi"; 362 phys = <&u2phy1_host>; 363 phy-names = "usb"; 364 status = "disabled"; 365 }; 366 367 usb_host1_ohci: usb@fe3e0000 { 368 compatible = "generic-ohci"; 369 reg = <0x0 0xfe3e0000 0x0 0x20000>; 370 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 371 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 372 <&u2phy1>; 373 clock-names = "usbhost", "arbiter", 374 "utmi"; 375 phys = <&u2phy1_host>; 376 phy-names = "usb"; 377 status = "disabled"; 378 }; 379 380 usbdrd3_0: usb@fe800000 { 381 compatible = "rockchip,rk3399-dwc3"; 382 #address-cells = <2>; 383 #size-cells = <2>; 384 ranges; 385 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 386 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>; 387 clock-names = "ref_clk", "suspend_clk", 388 "bus_clk", "grf_clk"; 389 status = "disabled"; 390 391 usbdrd_dwc3_0: dwc3 { 392 compatible = "snps,dwc3"; 393 reg = <0x0 0xfe800000 0x0 0x100000>; 394 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 395 dr_mode = "otg"; 396 phys = <&u2phy0_otg>; 397 phy-names = "usb2-phy"; 398 phy_type = "utmi_wide"; 399 snps,dis_enblslpm_quirk; 400 snps,dis-u2-freeclk-exists-quirk; 401 snps,dis_u2_susphy_quirk; 402 snps,dis-del-phy-power-chg-quirk; 403 status = "disabled"; 404 }; 405 }; 406 407 usbdrd3_1: usb@fe900000 { 408 compatible = "rockchip,rk3399-dwc3"; 409 #address-cells = <2>; 410 #size-cells = <2>; 411 ranges; 412 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, 413 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>; 414 clock-names = "ref_clk", "suspend_clk", 415 "bus_clk", "grf_clk"; 416 status = "disabled"; 417 418 usbdrd_dwc3_1: dwc3 { 419 compatible = "snps,dwc3"; 420 reg = <0x0 0xfe900000 0x0 0x100000>; 421 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 422 dr_mode = "otg"; 423 phys = <&u2phy1_otg>; 424 phy-names = "usb2-phy"; 425 phy_type = "utmi_wide"; 426 snps,dis_enblslpm_quirk; 427 snps,dis-u2-freeclk-exists-quirk; 428 snps,dis_u2_susphy_quirk; 429 snps,dis-del-phy-power-chg-quirk; 430 status = "disabled"; 431 }; 432 }; 433 434 gic: interrupt-controller@fee00000 { 435 compatible = "arm,gic-v3"; 436 #interrupt-cells = <4>; 437 #address-cells = <2>; 438 #size-cells = <2>; 439 ranges; 440 interrupt-controller; 441 442 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 443 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 444 <0x0 0xfff00000 0 0x10000>, /* GICC */ 445 <0x0 0xfff10000 0 0x10000>, /* GICH */ 446 <0x0 0xfff20000 0 0x10000>; /* GICV */ 447 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 448 its: interrupt-controller@fee20000 { 449 compatible = "arm,gic-v3-its"; 450 msi-controller; 451 reg = <0x0 0xfee20000 0x0 0x20000>; 452 }; 453 454 ppi-partitions { 455 ppi_cluster0: interrupt-partition-0 { 456 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 457 }; 458 459 ppi_cluster1: interrupt-partition-1 { 460 affinity = <&cpu_b0 &cpu_b1>; 461 }; 462 }; 463 }; 464 465 saradc: saradc@ff100000 { 466 compatible = "rockchip,rk3399-saradc"; 467 reg = <0x0 0xff100000 0x0 0x100>; 468 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 469 #io-channel-cells = <1>; 470 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 471 clock-names = "saradc", "apb_pclk"; 472 resets = <&cru SRST_P_SARADC>; 473 reset-names = "saradc-apb"; 474 status = "disabled"; 475 }; 476 477 i2c1: i2c@ff110000 { 478 compatible = "rockchip,rk3399-i2c"; 479 reg = <0x0 0xff110000 0x0 0x1000>; 480 assigned-clocks = <&cru SCLK_I2C1>; 481 assigned-clock-rates = <200000000>; 482 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 483 clock-names = "i2c", "pclk"; 484 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 485 pinctrl-names = "default"; 486 pinctrl-0 = <&i2c1_xfer>; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 status = "disabled"; 490 }; 491 492 i2c2: i2c@ff120000 { 493 compatible = "rockchip,rk3399-i2c"; 494 reg = <0x0 0xff120000 0x0 0x1000>; 495 assigned-clocks = <&cru SCLK_I2C2>; 496 assigned-clock-rates = <200000000>; 497 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 498 clock-names = "i2c", "pclk"; 499 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 500 pinctrl-names = "default"; 501 pinctrl-0 = <&i2c2_xfer>; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 status = "disabled"; 505 }; 506 507 i2c3: i2c@ff130000 { 508 compatible = "rockchip,rk3399-i2c"; 509 reg = <0x0 0xff130000 0x0 0x1000>; 510 assigned-clocks = <&cru SCLK_I2C3>; 511 assigned-clock-rates = <200000000>; 512 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 513 clock-names = "i2c", "pclk"; 514 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 515 pinctrl-names = "default"; 516 pinctrl-0 = <&i2c3_xfer>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 status = "disabled"; 520 }; 521 522 i2c5: i2c@ff140000 { 523 compatible = "rockchip,rk3399-i2c"; 524 reg = <0x0 0xff140000 0x0 0x1000>; 525 assigned-clocks = <&cru SCLK_I2C5>; 526 assigned-clock-rates = <200000000>; 527 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 528 clock-names = "i2c", "pclk"; 529 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 530 pinctrl-names = "default"; 531 pinctrl-0 = <&i2c5_xfer>; 532 #address-cells = <1>; 533 #size-cells = <0>; 534 status = "disabled"; 535 }; 536 537 i2c6: i2c@ff150000 { 538 compatible = "rockchip,rk3399-i2c"; 539 reg = <0x0 0xff150000 0x0 0x1000>; 540 assigned-clocks = <&cru SCLK_I2C6>; 541 assigned-clock-rates = <200000000>; 542 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 543 clock-names = "i2c", "pclk"; 544 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 545 pinctrl-names = "default"; 546 pinctrl-0 = <&i2c6_xfer>; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 status = "disabled"; 550 }; 551 552 i2c7: i2c@ff160000 { 553 compatible = "rockchip,rk3399-i2c"; 554 reg = <0x0 0xff160000 0x0 0x1000>; 555 assigned-clocks = <&cru SCLK_I2C7>; 556 assigned-clock-rates = <200000000>; 557 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 558 clock-names = "i2c", "pclk"; 559 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 560 pinctrl-names = "default"; 561 pinctrl-0 = <&i2c7_xfer>; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 status = "disabled"; 565 }; 566 567 uart0: serial@ff180000 { 568 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 569 reg = <0x0 0xff180000 0x0 0x100>; 570 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 571 clock-names = "baudclk", "apb_pclk"; 572 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 573 reg-shift = <2>; 574 reg-io-width = <4>; 575 pinctrl-names = "default"; 576 pinctrl-0 = <&uart0_xfer>; 577 status = "disabled"; 578 }; 579 580 uart1: serial@ff190000 { 581 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 582 reg = <0x0 0xff190000 0x0 0x100>; 583 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 584 clock-names = "baudclk", "apb_pclk"; 585 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 586 reg-shift = <2>; 587 reg-io-width = <4>; 588 pinctrl-names = "default"; 589 pinctrl-0 = <&uart1_xfer>; 590 status = "disabled"; 591 }; 592 593 uart2: serial@ff1a0000 { 594 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 595 reg = <0x0 0xff1a0000 0x0 0x100>; 596 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 597 clock-names = "baudclk", "apb_pclk"; 598 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 599 reg-shift = <2>; 600 reg-io-width = <4>; 601 pinctrl-names = "default"; 602 pinctrl-0 = <&uart2c_xfer>; 603 status = "disabled"; 604 }; 605 606 uart3: serial@ff1b0000 { 607 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 608 reg = <0x0 0xff1b0000 0x0 0x100>; 609 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 610 clock-names = "baudclk", "apb_pclk"; 611 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 612 reg-shift = <2>; 613 reg-io-width = <4>; 614 pinctrl-names = "default"; 615 pinctrl-0 = <&uart3_xfer>; 616 status = "disabled"; 617 }; 618 619 spi0: spi@ff1c0000 { 620 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 621 reg = <0x0 0xff1c0000 0x0 0x1000>; 622 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 623 clock-names = "spiclk", "apb_pclk"; 624 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 625 pinctrl-names = "default"; 626 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 627 #address-cells = <1>; 628 #size-cells = <0>; 629 status = "disabled"; 630 }; 631 632 spi1: spi@ff1d0000 { 633 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 634 reg = <0x0 0xff1d0000 0x0 0x1000>; 635 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 636 clock-names = "spiclk", "apb_pclk"; 637 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 638 pinctrl-names = "default"; 639 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 640 #address-cells = <1>; 641 #size-cells = <0>; 642 status = "disabled"; 643 }; 644 645 spi2: spi@ff1e0000 { 646 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 647 reg = <0x0 0xff1e0000 0x0 0x1000>; 648 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 649 clock-names = "spiclk", "apb_pclk"; 650 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 651 pinctrl-names = "default"; 652 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 653 #address-cells = <1>; 654 #size-cells = <0>; 655 status = "disabled"; 656 }; 657 658 spi4: spi@ff1f0000 { 659 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 660 reg = <0x0 0xff1f0000 0x0 0x1000>; 661 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 662 clock-names = "spiclk", "apb_pclk"; 663 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 664 pinctrl-names = "default"; 665 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 666 #address-cells = <1>; 667 #size-cells = <0>; 668 status = "disabled"; 669 }; 670 671 spi5: spi@ff200000 { 672 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 673 reg = <0x0 0xff200000 0x0 0x1000>; 674 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 675 clock-names = "spiclk", "apb_pclk"; 676 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 677 pinctrl-names = "default"; 678 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 679 #address-cells = <1>; 680 #size-cells = <0>; 681 status = "disabled"; 682 }; 683 684 thermal_zones: thermal-zones { 685 cpu_thermal: cpu { 686 polling-delay-passive = <100>; 687 polling-delay = <1000>; 688 689 thermal-sensors = <&tsadc 0>; 690 691 trips { 692 cpu_alert0: cpu_alert0 { 693 temperature = <70000>; 694 hysteresis = <2000>; 695 type = "passive"; 696 }; 697 cpu_alert1: cpu_alert1 { 698 temperature = <75000>; 699 hysteresis = <2000>; 700 type = "passive"; 701 }; 702 cpu_crit: cpu_crit { 703 temperature = <95000>; 704 hysteresis = <2000>; 705 type = "critical"; 706 }; 707 }; 708 709 cooling-maps { 710 map0 { 711 trip = <&cpu_alert0>; 712 cooling-device = 713 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 714 }; 715 map1 { 716 trip = <&cpu_alert1>; 717 cooling-device = 718 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 719 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 720 }; 721 }; 722 }; 723 724 gpu_thermal: gpu { 725 polling-delay-passive = <100>; 726 polling-delay = <1000>; 727 728 thermal-sensors = <&tsadc 1>; 729 730 trips { 731 gpu_alert0: gpu_alert0 { 732 temperature = <75000>; 733 hysteresis = <2000>; 734 type = "passive"; 735 }; 736 gpu_crit: gpu_crit { 737 temperature = <95000>; 738 hysteresis = <2000>; 739 type = "critical"; 740 }; 741 }; 742 743 cooling-maps { 744 map0 { 745 trip = <&gpu_alert0>; 746 cooling-device = 747 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 748 }; 749 }; 750 }; 751 }; 752 753 tsadc: tsadc@ff260000 { 754 compatible = "rockchip,rk3399-tsadc"; 755 reg = <0x0 0xff260000 0x0 0x100>; 756 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 757 assigned-clocks = <&cru SCLK_TSADC>; 758 assigned-clock-rates = <750000>; 759 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 760 clock-names = "tsadc", "apb_pclk"; 761 resets = <&cru SRST_TSADC>; 762 reset-names = "tsadc-apb"; 763 rockchip,grf = <&grf>; 764 rockchip,hw-tshut-temp = <95000>; 765 pinctrl-names = "init", "default", "sleep"; 766 pinctrl-0 = <&otp_gpio>; 767 pinctrl-1 = <&otp_out>; 768 pinctrl-2 = <&otp_gpio>; 769 #thermal-sensor-cells = <1>; 770 status = "disabled"; 771 }; 772 773 qos_emmc: qos@ffa58000 { 774 compatible = "syscon"; 775 reg = <0x0 0xffa58000 0x0 0x20>; 776 }; 777 778 qos_gmac: qos@ffa5c000 { 779 compatible = "syscon"; 780 reg = <0x0 0xffa5c000 0x0 0x20>; 781 }; 782 783 qos_pcie: qos@ffa60080 { 784 compatible = "syscon"; 785 reg = <0x0 0xffa60080 0x0 0x20>; 786 }; 787 788 qos_usb_host0: qos@ffa60100 { 789 compatible = "syscon"; 790 reg = <0x0 0xffa60100 0x0 0x20>; 791 }; 792 793 qos_usb_host1: qos@ffa60180 { 794 compatible = "syscon"; 795 reg = <0x0 0xffa60180 0x0 0x20>; 796 }; 797 798 qos_usb_otg0: qos@ffa70000 { 799 compatible = "syscon"; 800 reg = <0x0 0xffa70000 0x0 0x20>; 801 }; 802 803 qos_usb_otg1: qos@ffa70080 { 804 compatible = "syscon"; 805 reg = <0x0 0xffa70080 0x0 0x20>; 806 }; 807 808 qos_sd: qos@ffa74000 { 809 compatible = "syscon"; 810 reg = <0x0 0xffa74000 0x0 0x20>; 811 }; 812 813 qos_sdioaudio: qos@ffa76000 { 814 compatible = "syscon"; 815 reg = <0x0 0xffa76000 0x0 0x20>; 816 }; 817 818 qos_hdcp: qos@ffa90000 { 819 compatible = "syscon"; 820 reg = <0x0 0xffa90000 0x0 0x20>; 821 }; 822 823 qos_iep: qos@ffa98000 { 824 compatible = "syscon"; 825 reg = <0x0 0xffa98000 0x0 0x20>; 826 }; 827 828 qos_isp0_m0: qos@ffaa0000 { 829 compatible = "syscon"; 830 reg = <0x0 0xffaa0000 0x0 0x20>; 831 }; 832 833 qos_isp0_m1: qos@ffaa0080 { 834 compatible = "syscon"; 835 reg = <0x0 0xffaa0080 0x0 0x20>; 836 }; 837 838 qos_isp1_m0: qos@ffaa8000 { 839 compatible = "syscon"; 840 reg = <0x0 0xffaa8000 0x0 0x20>; 841 }; 842 843 qos_isp1_m1: qos@ffaa8080 { 844 compatible = "syscon"; 845 reg = <0x0 0xffaa8080 0x0 0x20>; 846 }; 847 848 qos_rga_r: qos@ffab0000 { 849 compatible = "syscon"; 850 reg = <0x0 0xffab0000 0x0 0x20>; 851 }; 852 853 qos_rga_w: qos@ffab0080 { 854 compatible = "syscon"; 855 reg = <0x0 0xffab0080 0x0 0x20>; 856 }; 857 858 qos_video_m0: qos@ffab8000 { 859 compatible = "syscon"; 860 reg = <0x0 0xffab8000 0x0 0x20>; 861 }; 862 863 qos_video_m1_r: qos@ffac0000 { 864 compatible = "syscon"; 865 reg = <0x0 0xffac0000 0x0 0x20>; 866 }; 867 868 qos_video_m1_w: qos@ffac0080 { 869 compatible = "syscon"; 870 reg = <0x0 0xffac0080 0x0 0x20>; 871 }; 872 873 qos_vop_big_r: qos@ffac8000 { 874 compatible = "syscon"; 875 reg = <0x0 0xffac8000 0x0 0x20>; 876 }; 877 878 qos_vop_big_w: qos@ffac8080 { 879 compatible = "syscon"; 880 reg = <0x0 0xffac8080 0x0 0x20>; 881 }; 882 883 qos_vop_little: qos@ffad0000 { 884 compatible = "syscon"; 885 reg = <0x0 0xffad0000 0x0 0x20>; 886 }; 887 888 qos_perihp: qos@ffad8080 { 889 compatible = "syscon"; 890 reg = <0x0 0xffad8080 0x0 0x20>; 891 }; 892 893 qos_gpu: qos@ffae0000 { 894 compatible = "syscon"; 895 reg = <0x0 0xffae0000 0x0 0x20>; 896 }; 897 898 pmu: power-management@ff310000 { 899 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 900 reg = <0x0 0xff310000 0x0 0x1000>; 901 902 /* 903 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 904 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 905 * Some of the power domains are grouped together for every 906 * voltage domain. 907 * The detail contents as below. 908 */ 909 power: power-controller { 910 compatible = "rockchip,rk3399-power-controller"; 911 #power-domain-cells = <1>; 912 #address-cells = <1>; 913 #size-cells = <0>; 914 915 /* These power domains are grouped by VD_CENTER */ 916 pd_iep@RK3399_PD_IEP { 917 reg = <RK3399_PD_IEP>; 918 clocks = <&cru ACLK_IEP>, 919 <&cru HCLK_IEP>; 920 pm_qos = <&qos_iep>; 921 }; 922 pd_rga@RK3399_PD_RGA { 923 reg = <RK3399_PD_RGA>; 924 clocks = <&cru ACLK_RGA>, 925 <&cru HCLK_RGA>; 926 pm_qos = <&qos_rga_r>, 927 <&qos_rga_w>; 928 }; 929 pd_vcodec@RK3399_PD_VCODEC { 930 reg = <RK3399_PD_VCODEC>; 931 clocks = <&cru ACLK_VCODEC>, 932 <&cru HCLK_VCODEC>; 933 pm_qos = <&qos_video_m0>; 934 }; 935 pd_vdu@RK3399_PD_VDU { 936 reg = <RK3399_PD_VDU>; 937 clocks = <&cru ACLK_VDU>, 938 <&cru HCLK_VDU>; 939 pm_qos = <&qos_video_m1_r>, 940 <&qos_video_m1_w>; 941 }; 942 943 /* These power domains are grouped by VD_GPU */ 944 pd_gpu@RK3399_PD_GPU { 945 reg = <RK3399_PD_GPU>; 946 clocks = <&cru ACLK_GPU>; 947 pm_qos = <&qos_gpu>; 948 }; 949 950 /* These power domains are grouped by VD_LOGIC */ 951 pd_emmc@RK3399_PD_EMMC { 952 reg = <RK3399_PD_EMMC>; 953 clocks = <&cru ACLK_EMMC>; 954 pm_qos = <&qos_emmc>; 955 }; 956 pd_gmac@RK3399_PD_GMAC { 957 reg = <RK3399_PD_GMAC>; 958 clocks = <&cru ACLK_GMAC>, 959 <&cru PCLK_GMAC>; 960 pm_qos = <&qos_gmac>; 961 }; 962 pd_sd@RK3399_PD_SD { 963 reg = <RK3399_PD_SD>; 964 clocks = <&cru HCLK_SDMMC>, 965 <&cru SCLK_SDMMC>; 966 pm_qos = <&qos_sd>; 967 }; 968 pd_vio@RK3399_PD_VIO { 969 reg = <RK3399_PD_VIO>; 970 #address-cells = <1>; 971 #size-cells = <0>; 972 973 pd_hdcp@RK3399_PD_HDCP { 974 reg = <RK3399_PD_HDCP>; 975 clocks = <&cru ACLK_HDCP>, 976 <&cru HCLK_HDCP>, 977 <&cru PCLK_HDCP>; 978 pm_qos = <&qos_hdcp>; 979 }; 980 pd_isp0@RK3399_PD_ISP0 { 981 reg = <RK3399_PD_ISP0>; 982 clocks = <&cru ACLK_ISP0>, 983 <&cru HCLK_ISP0>; 984 pm_qos = <&qos_isp0_m0>, 985 <&qos_isp0_m1>; 986 }; 987 pd_isp1@RK3399_PD_ISP1 { 988 reg = <RK3399_PD_ISP1>; 989 clocks = <&cru ACLK_ISP1>, 990 <&cru HCLK_ISP1>; 991 pm_qos = <&qos_isp1_m0>, 992 <&qos_isp1_m1>; 993 }; 994 pd_tcpc0@RK3399_PD_TCPC0 { 995 reg = <RK3399_PD_TCPD0>; 996 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 997 <&cru SCLK_UPHY0_TCPDPHY_REF>; 998 }; 999 pd_tcpc1@RK3399_PD_TCPC1 { 1000 reg = <RK3399_PD_TCPD1>; 1001 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1002 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1003 }; 1004 pd_vo@RK3399_PD_VO { 1005 reg = <RK3399_PD_VO>; 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 1009 pd_vopb@RK3399_PD_VOPB { 1010 reg = <RK3399_PD_VOPB>; 1011 clocks = <&cru ACLK_VOP0>, 1012 <&cru HCLK_VOP0>; 1013 pm_qos = <&qos_vop_big_r>, 1014 <&qos_vop_big_w>; 1015 }; 1016 pd_vopl@RK3399_PD_VOPL { 1017 reg = <RK3399_PD_VOPL>; 1018 clocks = <&cru ACLK_VOP1>, 1019 <&cru HCLK_VOP1>; 1020 pm_qos = <&qos_vop_little>; 1021 }; 1022 }; 1023 }; 1024 }; 1025 }; 1026 1027 pmugrf: syscon@ff320000 { 1028 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1029 reg = <0x0 0xff320000 0x0 0x1000>; 1030 #address-cells = <1>; 1031 #size-cells = <1>; 1032 1033 pmu_io_domains: io-domains { 1034 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1035 status = "disabled"; 1036 }; 1037 }; 1038 1039 spi3: spi@ff350000 { 1040 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1041 reg = <0x0 0xff350000 0x0 0x1000>; 1042 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1043 clock-names = "spiclk", "apb_pclk"; 1044 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1045 pinctrl-names = "default"; 1046 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1047 #address-cells = <1>; 1048 #size-cells = <0>; 1049 status = "disabled"; 1050 }; 1051 1052 uart4: serial@ff370000 { 1053 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1054 reg = <0x0 0xff370000 0x0 0x100>; 1055 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1056 clock-names = "baudclk", "apb_pclk"; 1057 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1058 reg-shift = <2>; 1059 reg-io-width = <4>; 1060 pinctrl-names = "default"; 1061 pinctrl-0 = <&uart4_xfer>; 1062 status = "disabled"; 1063 }; 1064 1065 i2c0: i2c@ff3c0000 { 1066 compatible = "rockchip,rk3399-i2c"; 1067 reg = <0x0 0xff3c0000 0x0 0x1000>; 1068 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1069 assigned-clock-rates = <200000000>; 1070 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1071 clock-names = "i2c", "pclk"; 1072 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1073 pinctrl-names = "default"; 1074 pinctrl-0 = <&i2c0_xfer>; 1075 #address-cells = <1>; 1076 #size-cells = <0>; 1077 status = "disabled"; 1078 }; 1079 1080 i2c4: i2c@ff3d0000 { 1081 compatible = "rockchip,rk3399-i2c"; 1082 reg = <0x0 0xff3d0000 0x0 0x1000>; 1083 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1084 assigned-clock-rates = <200000000>; 1085 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1086 clock-names = "i2c", "pclk"; 1087 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1088 pinctrl-names = "default"; 1089 pinctrl-0 = <&i2c4_xfer>; 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 status = "disabled"; 1093 }; 1094 1095 i2c8: i2c@ff3e0000 { 1096 compatible = "rockchip,rk3399-i2c"; 1097 reg = <0x0 0xff3e0000 0x0 0x1000>; 1098 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1099 assigned-clock-rates = <200000000>; 1100 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1101 clock-names = "i2c", "pclk"; 1102 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1103 pinctrl-names = "default"; 1104 pinctrl-0 = <&i2c8_xfer>; 1105 #address-cells = <1>; 1106 #size-cells = <0>; 1107 status = "disabled"; 1108 }; 1109 1110 pwm0: pwm@ff420000 { 1111 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1112 reg = <0x0 0xff420000 0x0 0x10>; 1113 #pwm-cells = <3>; 1114 pinctrl-names = "default"; 1115 pinctrl-0 = <&pwm0_pin>; 1116 clocks = <&pmucru PCLK_RKPWM_PMU>; 1117 clock-names = "pwm"; 1118 status = "disabled"; 1119 }; 1120 1121 pwm1: pwm@ff420010 { 1122 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1123 reg = <0x0 0xff420010 0x0 0x10>; 1124 #pwm-cells = <3>; 1125 pinctrl-names = "default"; 1126 pinctrl-0 = <&pwm1_pin>; 1127 clocks = <&pmucru PCLK_RKPWM_PMU>; 1128 clock-names = "pwm"; 1129 status = "disabled"; 1130 }; 1131 1132 pwm2: pwm@ff420020 { 1133 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1134 reg = <0x0 0xff420020 0x0 0x10>; 1135 #pwm-cells = <3>; 1136 pinctrl-names = "default"; 1137 pinctrl-0 = <&pwm2_pin>; 1138 clocks = <&pmucru PCLK_RKPWM_PMU>; 1139 clock-names = "pwm"; 1140 status = "disabled"; 1141 }; 1142 1143 pwm3: pwm@ff420030 { 1144 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1145 reg = <0x0 0xff420030 0x0 0x10>; 1146 #pwm-cells = <3>; 1147 pinctrl-names = "default"; 1148 pinctrl-0 = <&pwm3a_pin>; 1149 clocks = <&pmucru PCLK_RKPWM_PMU>; 1150 clock-names = "pwm"; 1151 status = "disabled"; 1152 }; 1153 1154 efuse0: efuse@ff690000 { 1155 compatible = "rockchip,rk3399-efuse"; 1156 reg = <0x0 0xff690000 0x0 0x80>; 1157 #address-cells = <1>; 1158 #size-cells = <1>; 1159 clocks = <&cru PCLK_EFUSE1024NS>; 1160 clock-names = "pclk_efuse"; 1161 1162 /* Data cells */ 1163 cpu_id: cpu-id@7 { 1164 reg = <0x07 0x10>; 1165 }; 1166 cpub_leakage: cpu-leakage@17 { 1167 reg = <0x17 0x1>; 1168 }; 1169 gpu_leakage: gpu-leakage@18 { 1170 reg = <0x18 0x1>; 1171 }; 1172 center_leakage: center-leakage@19 { 1173 reg = <0x19 0x1>; 1174 }; 1175 cpul_leakage: cpu-leakage@1a { 1176 reg = <0x1a 0x1>; 1177 }; 1178 logic_leakage: logic-leakage@1b { 1179 reg = <0x1b 0x1>; 1180 }; 1181 wafer_info: wafer-info@1c { 1182 reg = <0x1c 0x1>; 1183 }; 1184 }; 1185 1186 pmucru: pmu-clock-controller@ff750000 { 1187 compatible = "rockchip,rk3399-pmucru"; 1188 reg = <0x0 0xff750000 0x0 0x1000>; 1189 rockchip,grf = <&pmugrf>; 1190 #clock-cells = <1>; 1191 #reset-cells = <1>; 1192 assigned-clocks = <&pmucru PLL_PPLL>; 1193 assigned-clock-rates = <676000000>; 1194 }; 1195 1196 cru: clock-controller@ff760000 { 1197 compatible = "rockchip,rk3399-cru"; 1198 reg = <0x0 0xff760000 0x0 0x1000>; 1199 rockchip,grf = <&grf>; 1200 #clock-cells = <1>; 1201 #reset-cells = <1>; 1202 assigned-clocks = 1203 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1204 <&cru PLL_NPLL>, 1205 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1206 <&cru PCLK_PERIHP>, 1207 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1208 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1209 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; 1210 assigned-clock-rates = 1211 <594000000>, <800000000>, 1212 <1000000000>, 1213 <150000000>, <75000000>, 1214 <37500000>, 1215 <100000000>, <100000000>, 1216 <50000000>, <600000000>, 1217 <100000000>, <50000000>; 1218 }; 1219 1220 grf: syscon@ff770000 { 1221 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1222 reg = <0x0 0xff770000 0x0 0x10000>; 1223 #address-cells = <1>; 1224 #size-cells = <1>; 1225 1226 io_domains: io-domains { 1227 compatible = "rockchip,rk3399-io-voltage-domain"; 1228 status = "disabled"; 1229 }; 1230 1231 u2phy0: usb2-phy@e450 { 1232 compatible = "rockchip,rk3399-usb2phy"; 1233 reg = <0xe450 0x10>; 1234 clocks = <&cru SCLK_USB2PHY0_REF>; 1235 clock-names = "phyclk"; 1236 #clock-cells = <0>; 1237 clock-output-names = "clk_usbphy0_480m"; 1238 status = "disabled"; 1239 1240 u2phy0_host: host-port { 1241 #phy-cells = <0>; 1242 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1243 interrupt-names = "linestate"; 1244 status = "disabled"; 1245 }; 1246 1247 u2phy0_otg: otg-port { 1248 #phy-cells = <0>; 1249 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1250 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1251 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1252 interrupt-names = "otg-bvalid", "otg-id", 1253 "linestate"; 1254 status = "disabled"; 1255 }; 1256 }; 1257 1258 u2phy1: usb2-phy@e460 { 1259 compatible = "rockchip,rk3399-usb2phy"; 1260 reg = <0xe460 0x10>; 1261 clocks = <&cru SCLK_USB2PHY1_REF>; 1262 clock-names = "phyclk"; 1263 #clock-cells = <0>; 1264 clock-output-names = "clk_usbphy1_480m"; 1265 status = "disabled"; 1266 1267 u2phy1_host: host-port { 1268 #phy-cells = <0>; 1269 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1270 interrupt-names = "linestate"; 1271 status = "disabled"; 1272 }; 1273 1274 u2phy1_otg: otg-port { 1275 #phy-cells = <0>; 1276 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1277 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1278 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1279 interrupt-names = "otg-bvalid", "otg-id", 1280 "linestate"; 1281 status = "disabled"; 1282 }; 1283 }; 1284 1285 emmc_phy: phy@f780 { 1286 compatible = "rockchip,rk3399-emmc-phy"; 1287 reg = <0xf780 0x24>; 1288 clocks = <&sdhci>; 1289 clock-names = "emmcclk"; 1290 #phy-cells = <0>; 1291 status = "disabled"; 1292 }; 1293 1294 pcie_phy: pcie-phy { 1295 compatible = "rockchip,rk3399-pcie-phy"; 1296 clocks = <&cru SCLK_PCIEPHY_REF>; 1297 clock-names = "refclk"; 1298 #phy-cells = <0>; 1299 resets = <&cru SRST_PCIEPHY>; 1300 reset-names = "phy"; 1301 status = "disabled"; 1302 }; 1303 }; 1304 1305 tcphy0: phy@ff7c0000 { 1306 compatible = "rockchip,rk3399-typec-phy"; 1307 reg = <0x0 0xff7c0000 0x0 0x40000>; 1308 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1309 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1310 clock-names = "tcpdcore", "tcpdphy-ref"; 1311 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1312 assigned-clock-rates = <50000000>; 1313 power-domains = <&power RK3399_PD_TCPD0>; 1314 resets = <&cru SRST_UPHY0>, 1315 <&cru SRST_UPHY0_PIPE_L00>, 1316 <&cru SRST_P_UPHY0_TCPHY>; 1317 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1318 rockchip,grf = <&grf>; 1319 rockchip,typec-conn-dir = <0xe580 0 16>; 1320 rockchip,usb3tousb2-en = <0xe580 3 19>; 1321 rockchip,external-psm = <0xe588 14 30>; 1322 rockchip,pipe-status = <0xe5c0 0 0>; 1323 status = "disabled"; 1324 1325 tcphy0_dp: dp-port { 1326 #phy-cells = <0>; 1327 }; 1328 1329 tcphy0_usb3: usb3-port { 1330 #phy-cells = <0>; 1331 }; 1332 }; 1333 1334 tcphy1: phy@ff800000 { 1335 compatible = "rockchip,rk3399-typec-phy"; 1336 reg = <0x0 0xff800000 0x0 0x40000>; 1337 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1338 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1339 clock-names = "tcpdcore", "tcpdphy-ref"; 1340 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1341 assigned-clock-rates = <50000000>; 1342 power-domains = <&power RK3399_PD_TCPD1>; 1343 resets = <&cru SRST_UPHY1>, 1344 <&cru SRST_UPHY1_PIPE_L00>, 1345 <&cru SRST_P_UPHY1_TCPHY>; 1346 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1347 rockchip,grf = <&grf>; 1348 rockchip,typec-conn-dir = <0xe58c 0 16>; 1349 rockchip,usb3tousb2-en = <0xe58c 3 19>; 1350 rockchip,external-psm = <0xe594 14 30>; 1351 rockchip,pipe-status = <0xe5c0 16 16>; 1352 status = "disabled"; 1353 1354 tcphy1_dp: dp-port { 1355 #phy-cells = <0>; 1356 }; 1357 1358 tcphy1_usb3: usb3-port { 1359 #phy-cells = <0>; 1360 }; 1361 }; 1362 1363 watchdog@ff848000 { 1364 compatible = "snps,dw-wdt"; 1365 reg = <0x0 0xff848000 0x0 0x100>; 1366 clocks = <&cru PCLK_WDT>; 1367 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1368 }; 1369 1370 rktimer: rktimer@ff850000 { 1371 compatible = "rockchip,rk3399-timer"; 1372 reg = <0x0 0xff850000 0x0 0x1000>; 1373 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1374 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1375 clock-names = "pclk", "timer"; 1376 }; 1377 1378 spdif: spdif@ff870000 { 1379 compatible = "rockchip,rk3399-spdif"; 1380 reg = <0x0 0xff870000 0x0 0x1000>; 1381 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1382 dmas = <&dmac_bus 7>; 1383 dma-names = "tx"; 1384 clock-names = "mclk", "hclk"; 1385 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1386 pinctrl-names = "default"; 1387 pinctrl-0 = <&spdif_bus>; 1388 status = "disabled"; 1389 }; 1390 1391 i2s0: i2s@ff880000 { 1392 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1393 reg = <0x0 0xff880000 0x0 0x1000>; 1394 rockchip,grf = <&grf>; 1395 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1396 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1397 dma-names = "tx", "rx"; 1398 clock-names = "i2s_clk", "i2s_hclk"; 1399 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1400 pinctrl-names = "default"; 1401 pinctrl-0 = <&i2s0_8ch_bus>; 1402 status = "disabled"; 1403 }; 1404 1405 i2s1: i2s@ff890000 { 1406 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1407 reg = <0x0 0xff890000 0x0 0x1000>; 1408 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1409 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1410 dma-names = "tx", "rx"; 1411 clock-names = "i2s_clk", "i2s_hclk"; 1412 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1413 pinctrl-names = "default"; 1414 pinctrl-0 = <&i2s1_2ch_bus>; 1415 status = "disabled"; 1416 }; 1417 1418 i2s2: i2s@ff8a0000 { 1419 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1420 reg = <0x0 0xff8a0000 0x0 0x1000>; 1421 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1422 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1423 dma-names = "tx", "rx"; 1424 clock-names = "i2s_clk", "i2s_hclk"; 1425 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1426 status = "disabled"; 1427 }; 1428 1429 pinctrl: pinctrl { 1430 compatible = "rockchip,rk3399-pinctrl"; 1431 rockchip,grf = <&grf>; 1432 rockchip,pmu = <&pmugrf>; 1433 #address-cells = <2>; 1434 #size-cells = <2>; 1435 ranges; 1436 1437 gpio0: gpio0@ff720000 { 1438 compatible = "rockchip,gpio-bank"; 1439 reg = <0x0 0xff720000 0x0 0x100>; 1440 clocks = <&pmucru PCLK_GPIO0_PMU>; 1441 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 1442 1443 gpio-controller; 1444 #gpio-cells = <0x2>; 1445 1446 interrupt-controller; 1447 #interrupt-cells = <0x2>; 1448 }; 1449 1450 gpio1: gpio1@ff730000 { 1451 compatible = "rockchip,gpio-bank"; 1452 reg = <0x0 0xff730000 0x0 0x100>; 1453 clocks = <&pmucru PCLK_GPIO1_PMU>; 1454 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 1455 1456 gpio-controller; 1457 #gpio-cells = <0x2>; 1458 1459 interrupt-controller; 1460 #interrupt-cells = <0x2>; 1461 }; 1462 1463 gpio2: gpio2@ff780000 { 1464 compatible = "rockchip,gpio-bank"; 1465 reg = <0x0 0xff780000 0x0 0x100>; 1466 clocks = <&cru PCLK_GPIO2>; 1467 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 1468 1469 gpio-controller; 1470 #gpio-cells = <0x2>; 1471 1472 interrupt-controller; 1473 #interrupt-cells = <0x2>; 1474 }; 1475 1476 gpio3: gpio3@ff788000 { 1477 compatible = "rockchip,gpio-bank"; 1478 reg = <0x0 0xff788000 0x0 0x100>; 1479 clocks = <&cru PCLK_GPIO3>; 1480 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 1481 1482 gpio-controller; 1483 #gpio-cells = <0x2>; 1484 1485 interrupt-controller; 1486 #interrupt-cells = <0x2>; 1487 }; 1488 1489 gpio4: gpio4@ff790000 { 1490 compatible = "rockchip,gpio-bank"; 1491 reg = <0x0 0xff790000 0x0 0x100>; 1492 clocks = <&cru PCLK_GPIO4>; 1493 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 1494 1495 gpio-controller; 1496 #gpio-cells = <0x2>; 1497 1498 interrupt-controller; 1499 #interrupt-cells = <0x2>; 1500 }; 1501 1502 pcfg_pull_up: pcfg-pull-up { 1503 bias-pull-up; 1504 }; 1505 1506 pcfg_pull_down: pcfg-pull-down { 1507 bias-pull-down; 1508 }; 1509 1510 pcfg_pull_none: pcfg-pull-none { 1511 bias-disable; 1512 }; 1513 1514 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1515 bias-disable; 1516 drive-strength = <12>; 1517 }; 1518 1519 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1520 bias-pull-up; 1521 drive-strength = <8>; 1522 }; 1523 1524 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1525 bias-pull-down; 1526 drive-strength = <4>; 1527 }; 1528 1529 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1530 bias-pull-up; 1531 drive-strength = <2>; 1532 }; 1533 1534 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 1535 bias-pull-down; 1536 drive-strength = <12>; 1537 }; 1538 1539 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 1540 bias-disable; 1541 drive-strength = <13>; 1542 }; 1543 1544 clock { 1545 clk_32k: clk-32k { 1546 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; 1547 }; 1548 }; 1549 1550 edp { 1551 edp_hpd: edp-hpd { 1552 rockchip,pins = 1553 <4 23 RK_FUNC_2 &pcfg_pull_none>; 1554 }; 1555 }; 1556 1557 gmac { 1558 rgmii_pins: rgmii-pins { 1559 rockchip,pins = 1560 /* mac_txclk */ 1561 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>, 1562 /* mac_rxclk */ 1563 <3 14 RK_FUNC_1 &pcfg_pull_none>, 1564 /* mac_mdio */ 1565 <3 13 RK_FUNC_1 &pcfg_pull_none>, 1566 /* mac_txen */ 1567 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>, 1568 /* mac_clk */ 1569 <3 11 RK_FUNC_1 &pcfg_pull_none>, 1570 /* mac_rxdv */ 1571 <3 9 RK_FUNC_1 &pcfg_pull_none>, 1572 /* mac_mdc */ 1573 <3 8 RK_FUNC_1 &pcfg_pull_none>, 1574 /* mac_rxd1 */ 1575 <3 7 RK_FUNC_1 &pcfg_pull_none>, 1576 /* mac_rxd0 */ 1577 <3 6 RK_FUNC_1 &pcfg_pull_none>, 1578 /* mac_txd1 */ 1579 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>, 1580 /* mac_txd0 */ 1581 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>, 1582 /* mac_rxd3 */ 1583 <3 3 RK_FUNC_1 &pcfg_pull_none>, 1584 /* mac_rxd2 */ 1585 <3 2 RK_FUNC_1 &pcfg_pull_none>, 1586 /* mac_txd3 */ 1587 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>, 1588 /* mac_txd2 */ 1589 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>; 1590 }; 1591 1592 rmii_pins: rmii-pins { 1593 rockchip,pins = 1594 /* mac_mdio */ 1595 <3 13 RK_FUNC_1 &pcfg_pull_none>, 1596 /* mac_txen */ 1597 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>, 1598 /* mac_clk */ 1599 <3 11 RK_FUNC_1 &pcfg_pull_none>, 1600 /* mac_rxer */ 1601 <3 10 RK_FUNC_1 &pcfg_pull_none>, 1602 /* mac_rxdv */ 1603 <3 9 RK_FUNC_1 &pcfg_pull_none>, 1604 /* mac_mdc */ 1605 <3 8 RK_FUNC_1 &pcfg_pull_none>, 1606 /* mac_rxd1 */ 1607 <3 7 RK_FUNC_1 &pcfg_pull_none>, 1608 /* mac_rxd0 */ 1609 <3 6 RK_FUNC_1 &pcfg_pull_none>, 1610 /* mac_txd1 */ 1611 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>, 1612 /* mac_txd0 */ 1613 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>; 1614 }; 1615 }; 1616 1617 i2c0 { 1618 i2c0_xfer: i2c0-xfer { 1619 rockchip,pins = 1620 <1 15 RK_FUNC_2 &pcfg_pull_none>, 1621 <1 16 RK_FUNC_2 &pcfg_pull_none>; 1622 }; 1623 }; 1624 1625 i2c1 { 1626 i2c1_xfer: i2c1-xfer { 1627 rockchip,pins = 1628 <4 2 RK_FUNC_1 &pcfg_pull_none>, 1629 <4 1 RK_FUNC_1 &pcfg_pull_none>; 1630 }; 1631 }; 1632 1633 i2c2 { 1634 i2c2_xfer: i2c2-xfer { 1635 rockchip,pins = 1636 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>, 1637 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>; 1638 }; 1639 }; 1640 1641 i2c3 { 1642 i2c3_xfer: i2c3-xfer { 1643 rockchip,pins = 1644 <4 17 RK_FUNC_1 &pcfg_pull_none>, 1645 <4 16 RK_FUNC_1 &pcfg_pull_none>; 1646 }; 1647 }; 1648 1649 i2c4 { 1650 i2c4_xfer: i2c4-xfer { 1651 rockchip,pins = 1652 <1 12 RK_FUNC_1 &pcfg_pull_none>, 1653 <1 11 RK_FUNC_1 &pcfg_pull_none>; 1654 }; 1655 }; 1656 1657 i2c5 { 1658 i2c5_xfer: i2c5-xfer { 1659 rockchip,pins = 1660 <3 11 RK_FUNC_2 &pcfg_pull_none>, 1661 <3 10 RK_FUNC_2 &pcfg_pull_none>; 1662 }; 1663 }; 1664 1665 i2c6 { 1666 i2c6_xfer: i2c6-xfer { 1667 rockchip,pins = 1668 <2 10 RK_FUNC_2 &pcfg_pull_none>, 1669 <2 9 RK_FUNC_2 &pcfg_pull_none>; 1670 }; 1671 }; 1672 1673 i2c7 { 1674 i2c7_xfer: i2c7-xfer { 1675 rockchip,pins = 1676 <2 8 RK_FUNC_2 &pcfg_pull_none>, 1677 <2 7 RK_FUNC_2 &pcfg_pull_none>; 1678 }; 1679 }; 1680 1681 i2c8 { 1682 i2c8_xfer: i2c8-xfer { 1683 rockchip,pins = 1684 <1 21 RK_FUNC_1 &pcfg_pull_none>, 1685 <1 20 RK_FUNC_1 &pcfg_pull_none>; 1686 }; 1687 }; 1688 1689 i2s0 { 1690 i2s0_8ch_bus: i2s0-8ch-bus { 1691 rockchip,pins = 1692 <3 24 RK_FUNC_1 &pcfg_pull_none>, 1693 <3 25 RK_FUNC_1 &pcfg_pull_none>, 1694 <3 26 RK_FUNC_1 &pcfg_pull_none>, 1695 <3 27 RK_FUNC_1 &pcfg_pull_none>, 1696 <3 28 RK_FUNC_1 &pcfg_pull_none>, 1697 <3 29 RK_FUNC_1 &pcfg_pull_none>, 1698 <3 30 RK_FUNC_1 &pcfg_pull_none>, 1699 <3 31 RK_FUNC_1 &pcfg_pull_none>, 1700 <4 0 RK_FUNC_1 &pcfg_pull_none>; 1701 }; 1702 }; 1703 1704 i2s1 { 1705 i2s1_2ch_bus: i2s1-2ch-bus { 1706 rockchip,pins = 1707 <4 3 RK_FUNC_1 &pcfg_pull_none>, 1708 <4 4 RK_FUNC_1 &pcfg_pull_none>, 1709 <4 5 RK_FUNC_1 &pcfg_pull_none>, 1710 <4 6 RK_FUNC_1 &pcfg_pull_none>, 1711 <4 7 RK_FUNC_1 &pcfg_pull_none>; 1712 }; 1713 }; 1714 1715 sdio0 { 1716 sdio0_bus1: sdio0-bus1 { 1717 rockchip,pins = 1718 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>; 1719 }; 1720 1721 sdio0_bus4: sdio0-bus4 { 1722 rockchip,pins = 1723 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>, 1724 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>, 1725 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>, 1726 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>; 1727 }; 1728 1729 sdio0_cmd: sdio0-cmd { 1730 rockchip,pins = 1731 <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>; 1732 }; 1733 1734 sdio0_clk: sdio0-clk { 1735 rockchip,pins = 1736 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 1737 }; 1738 1739 sdio0_cd: sdio0-cd { 1740 rockchip,pins = 1741 <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>; 1742 }; 1743 1744 sdio0_pwr: sdio0-pwr { 1745 rockchip,pins = 1746 <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>; 1747 }; 1748 1749 sdio0_bkpwr: sdio0-bkpwr { 1750 rockchip,pins = 1751 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; 1752 }; 1753 1754 sdio0_wp: sdio0-wp { 1755 rockchip,pins = 1756 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>; 1757 }; 1758 1759 sdio0_int: sdio0-int { 1760 rockchip,pins = 1761 <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>; 1762 }; 1763 }; 1764 1765 sdmmc { 1766 sdmmc_bus1: sdmmc-bus1 { 1767 rockchip,pins = 1768 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; 1769 }; 1770 1771 sdmmc_bus4: sdmmc-bus4 { 1772 rockchip,pins = 1773 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>, 1774 <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>, 1775 <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>, 1776 <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>; 1777 }; 1778 1779 sdmmc_clk: sdmmc-clk { 1780 rockchip,pins = 1781 <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 1782 }; 1783 1784 sdmmc_cmd: sdmmc-cmd { 1785 rockchip,pins = 1786 <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>; 1787 }; 1788 1789 sdmmc_cd: sdmcc-cd { 1790 rockchip,pins = 1791 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>; 1792 }; 1793 1794 sdmmc_wp: sdmmc-wp { 1795 rockchip,pins = 1796 <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; 1797 }; 1798 }; 1799 1800 sleep { 1801 ap_pwroff: ap-pwroff { 1802 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>; 1803 }; 1804 1805 ddrio_pwroff: ddrio-pwroff { 1806 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; 1807 }; 1808 }; 1809 1810 spdif { 1811 spdif_bus: spdif-bus { 1812 rockchip,pins = 1813 <4 21 RK_FUNC_1 &pcfg_pull_none>; 1814 }; 1815 1816 spdif_bus_1: spdif-bus-1 { 1817 rockchip,pins = 1818 <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; 1819 }; 1820 }; 1821 1822 spi0 { 1823 spi0_clk: spi0-clk { 1824 rockchip,pins = 1825 <3 6 RK_FUNC_2 &pcfg_pull_up>; 1826 }; 1827 spi0_cs0: spi0-cs0 { 1828 rockchip,pins = 1829 <3 7 RK_FUNC_2 &pcfg_pull_up>; 1830 }; 1831 spi0_cs1: spi0-cs1 { 1832 rockchip,pins = 1833 <3 8 RK_FUNC_2 &pcfg_pull_up>; 1834 }; 1835 spi0_tx: spi0-tx { 1836 rockchip,pins = 1837 <3 5 RK_FUNC_2 &pcfg_pull_up>; 1838 }; 1839 spi0_rx: spi0-rx { 1840 rockchip,pins = 1841 <3 4 RK_FUNC_2 &pcfg_pull_up>; 1842 }; 1843 }; 1844 1845 spi1 { 1846 spi1_clk: spi1-clk { 1847 rockchip,pins = 1848 <1 9 RK_FUNC_2 &pcfg_pull_up>; 1849 }; 1850 spi1_cs0: spi1-cs0 { 1851 rockchip,pins = 1852 <1 10 RK_FUNC_2 &pcfg_pull_up>; 1853 }; 1854 spi1_rx: spi1-rx { 1855 rockchip,pins = 1856 <1 7 RK_FUNC_2 &pcfg_pull_up>; 1857 }; 1858 spi1_tx: spi1-tx { 1859 rockchip,pins = 1860 <1 8 RK_FUNC_2 &pcfg_pull_up>; 1861 }; 1862 }; 1863 1864 spi2 { 1865 spi2_clk: spi2-clk { 1866 rockchip,pins = 1867 <2 11 RK_FUNC_1 &pcfg_pull_up>; 1868 }; 1869 spi2_cs0: spi2-cs0 { 1870 rockchip,pins = 1871 <2 12 RK_FUNC_1 &pcfg_pull_up>; 1872 }; 1873 spi2_rx: spi2-rx { 1874 rockchip,pins = 1875 <2 9 RK_FUNC_1 &pcfg_pull_up>; 1876 }; 1877 spi2_tx: spi2-tx { 1878 rockchip,pins = 1879 <2 10 RK_FUNC_1 &pcfg_pull_up>; 1880 }; 1881 }; 1882 1883 spi3 { 1884 spi3_clk: spi3-clk { 1885 rockchip,pins = 1886 <1 17 RK_FUNC_1 &pcfg_pull_up>; 1887 }; 1888 spi3_cs0: spi3-cs0 { 1889 rockchip,pins = 1890 <1 18 RK_FUNC_1 &pcfg_pull_up>; 1891 }; 1892 spi3_rx: spi3-rx { 1893 rockchip,pins = 1894 <1 15 RK_FUNC_1 &pcfg_pull_up>; 1895 }; 1896 spi3_tx: spi3-tx { 1897 rockchip,pins = 1898 <1 16 RK_FUNC_1 &pcfg_pull_up>; 1899 }; 1900 }; 1901 1902 spi4 { 1903 spi4_clk: spi4-clk { 1904 rockchip,pins = 1905 <3 2 RK_FUNC_2 &pcfg_pull_up>; 1906 }; 1907 spi4_cs0: spi4-cs0 { 1908 rockchip,pins = 1909 <3 3 RK_FUNC_2 &pcfg_pull_up>; 1910 }; 1911 spi4_rx: spi4-rx { 1912 rockchip,pins = 1913 <3 0 RK_FUNC_2 &pcfg_pull_up>; 1914 }; 1915 spi4_tx: spi4-tx { 1916 rockchip,pins = 1917 <3 1 RK_FUNC_2 &pcfg_pull_up>; 1918 }; 1919 }; 1920 1921 spi5 { 1922 spi5_clk: spi5-clk { 1923 rockchip,pins = 1924 <2 22 RK_FUNC_2 &pcfg_pull_up>; 1925 }; 1926 spi5_cs0: spi5-cs0 { 1927 rockchip,pins = 1928 <2 23 RK_FUNC_2 &pcfg_pull_up>; 1929 }; 1930 spi5_rx: spi5-rx { 1931 rockchip,pins = 1932 <2 20 RK_FUNC_2 &pcfg_pull_up>; 1933 }; 1934 spi5_tx: spi5-tx { 1935 rockchip,pins = 1936 <2 21 RK_FUNC_2 &pcfg_pull_up>; 1937 }; 1938 }; 1939 1940 tsadc { 1941 otp_gpio: otp-gpio { 1942 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>; 1943 }; 1944 1945 otp_out: otp-out { 1946 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>; 1947 }; 1948 }; 1949 1950 uart0 { 1951 uart0_xfer: uart0-xfer { 1952 rockchip,pins = 1953 <2 16 RK_FUNC_1 &pcfg_pull_up>, 1954 <2 17 RK_FUNC_1 &pcfg_pull_none>; 1955 }; 1956 1957 uart0_cts: uart0-cts { 1958 rockchip,pins = 1959 <2 18 RK_FUNC_1 &pcfg_pull_none>; 1960 }; 1961 1962 uart0_rts: uart0-rts { 1963 rockchip,pins = 1964 <2 19 RK_FUNC_1 &pcfg_pull_none>; 1965 }; 1966 }; 1967 1968 uart1 { 1969 uart1_xfer: uart1-xfer { 1970 rockchip,pins = 1971 <3 12 RK_FUNC_2 &pcfg_pull_up>, 1972 <3 13 RK_FUNC_2 &pcfg_pull_none>; 1973 }; 1974 }; 1975 1976 uart2a { 1977 uart2a_xfer: uart2a-xfer { 1978 rockchip,pins = 1979 <4 8 RK_FUNC_2 &pcfg_pull_up>, 1980 <4 9 RK_FUNC_2 &pcfg_pull_none>; 1981 }; 1982 }; 1983 1984 uart2b { 1985 uart2b_xfer: uart2b-xfer { 1986 rockchip,pins = 1987 <4 16 RK_FUNC_2 &pcfg_pull_up>, 1988 <4 17 RK_FUNC_2 &pcfg_pull_none>; 1989 }; 1990 }; 1991 1992 uart2c { 1993 uart2c_xfer: uart2c-xfer { 1994 rockchip,pins = 1995 <4 19 RK_FUNC_1 &pcfg_pull_up>, 1996 <4 20 RK_FUNC_1 &pcfg_pull_none>; 1997 }; 1998 }; 1999 2000 uart3 { 2001 uart3_xfer: uart3-xfer { 2002 rockchip,pins = 2003 <3 14 RK_FUNC_2 &pcfg_pull_up>, 2004 <3 15 RK_FUNC_2 &pcfg_pull_none>; 2005 }; 2006 2007 uart3_cts: uart3-cts { 2008 rockchip,pins = 2009 <3 18 RK_FUNC_2 &pcfg_pull_none>; 2010 }; 2011 2012 uart3_rts: uart3-rts { 2013 rockchip,pins = 2014 <3 19 RK_FUNC_2 &pcfg_pull_none>; 2015 }; 2016 }; 2017 2018 uart4 { 2019 uart4_xfer: uart4-xfer { 2020 rockchip,pins = 2021 <1 7 RK_FUNC_1 &pcfg_pull_up>, 2022 <1 8 RK_FUNC_1 &pcfg_pull_none>; 2023 }; 2024 }; 2025 2026 uarthdcp { 2027 uarthdcp_xfer: uarthdcp-xfer { 2028 rockchip,pins = 2029 <4 21 RK_FUNC_2 &pcfg_pull_up>, 2030 <4 22 RK_FUNC_2 &pcfg_pull_none>; 2031 }; 2032 }; 2033 2034 pwm0 { 2035 pwm0_pin: pwm0-pin { 2036 rockchip,pins = 2037 <4 18 RK_FUNC_1 &pcfg_pull_none>; 2038 }; 2039 2040 vop0_pwm_pin: vop0-pwm-pin { 2041 rockchip,pins = 2042 <4 18 RK_FUNC_2 &pcfg_pull_none>; 2043 }; 2044 }; 2045 2046 pwm1 { 2047 pwm1_pin: pwm1-pin { 2048 rockchip,pins = 2049 <4 22 RK_FUNC_1 &pcfg_pull_none>; 2050 }; 2051 2052 vop1_pwm_pin: vop1-pwm-pin { 2053 rockchip,pins = 2054 <4 18 RK_FUNC_3 &pcfg_pull_none>; 2055 }; 2056 }; 2057 2058 pwm2 { 2059 pwm2_pin: pwm2-pin { 2060 rockchip,pins = 2061 <1 19 RK_FUNC_1 &pcfg_pull_none>; 2062 }; 2063 }; 2064 2065 pwm3a { 2066 pwm3a_pin: pwm3a-pin { 2067 rockchip,pins = 2068 <0 6 RK_FUNC_1 &pcfg_pull_none>; 2069 }; 2070 }; 2071 2072 pwm3b { 2073 pwm3b_pin: pwm3b-pin { 2074 rockchip,pins = 2075 <1 14 RK_FUNC_1 &pcfg_pull_none>; 2076 }; 2077 }; 2078 2079 hdmi { 2080 hdmi_i2c_xfer: hdmi-i2c-xfer { 2081 rockchip,pins = 2082 <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>, 2083 <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; 2084 }; 2085 2086 hdmi_cec: hdmi-cec { 2087 rockchip,pins = 2088 <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>; 2089 }; 2090 }; 2091 2092 pcie { 2093 pcie_clkreqn: pci-clkreqn { 2094 rockchip,pins = 2095 <2 26 RK_FUNC_2 &pcfg_pull_none>; 2096 }; 2097 2098 pcie_clkreqnb: pci-clkreqnb { 2099 rockchip,pins = 2100 <4 24 RK_FUNC_1 &pcfg_pull_none>; 2101 }; 2102 2103 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2104 rockchip,pins = 2105 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2106 }; 2107 2108 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2109 rockchip,pins = 2110 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2111 }; 2112 }; 2113 2114 }; 2115}; 2116