1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
4 * Copyright (c) 2019 Markus Reichl <m.reichl@fivetechno.de>
5 */
6
7/dts-v1/;
8#include "rk3399-roc-pc.dtsi"
9
10/ {
11	model = "Firefly ROC-RK3399-PC Mezzanine Board";
12	compatible = "firefly,roc-rk3399-pc-mezzanine", "rockchip,rk3399";
13
14	vcc3v3_ngff: vcc3v3-ngff {
15		compatible = "regulator-fixed";
16		regulator-name = "vcc3v3_ngff";
17		enable-active-high;
18		gpio = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
19		pinctrl-names = "default";
20		pinctrl-0 = <&vcc3v3_ngff_en>;
21		regulator-always-on;
22		regulator-boot-on;
23		regulator-min-microvolt = <3300000>;
24		regulator-max-microvolt = <3300000>;
25		vin-supply = <&dc_12v>;
26	};
27
28	vcc3v3_pcie: vcc3v3-pcie {
29		compatible = "regulator-fixed";
30		regulator-name = "vcc3v3_pcie";
31		enable-active-high;
32		gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
33		pinctrl-names = "default";
34		pinctrl-0 = <&vcc3v3_pcie_en>;
35		regulator-always-on;
36		regulator-boot-on;
37		regulator-min-microvolt = <3300000>;
38		regulator-max-microvolt = <3300000>;
39		vin-supply = <&dc_12v>;
40	};
41};
42
43&pcie_phy {
44	status = "okay";
45};
46
47&pcie0 {
48	ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
49	num-lanes = <4>;
50	pinctrl-names = "default";
51	pinctrl-0 = <&pcie_perst>;
52	vpcie3v3-supply = <&vcc3v3_pcie>;
53	status = "okay";
54};
55
56&pinctrl {
57	ngff {
58		vcc3v3_ngff_en: vcc3v3-ngff-en {
59			rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
60		};
61	};
62
63	pcie {
64		vcc3v3_pcie_en: vcc3v3-pcie-en {
65			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
66		};
67
68		pcie_perst: pcie-perst {
69			rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
70		};
71	};
72};
73