1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Google Gru (and derivatives) board device tree source 4 * 5 * Copyright 2016-2017 Google, Inc 6 */ 7 8#include <dt-bindings/input/input.h> 9#include "rk3399.dtsi" 10#include "rk3399-op1-opp.dtsi" 11 12/ { 13 chosen { 14 stdout-path = "serial2:115200n8"; 15 }; 16 17 /* 18 * Power Tree 19 * 20 * In general an attempt is made to include all rails called out by 21 * the schematic as long as those rails interact in some way with 22 * the AP. AKA: 23 * - Rails that only connect to the EC (or devices that the EC talks to) 24 * are not included. 25 * - Rails _are_ included if the rails go to the AP even if the AP 26 * doesn't currently care about them / they are always on. The idea 27 * here is that it makes it easier to map to the schematic or extend 28 * later. 29 * 30 * If two rails are substantially the same from the AP's point of 31 * view, though, we won't create a full fixed regulator. We'll just 32 * put the child rail as an alias of the parent rail. Sometimes rails 33 * look the same to the AP because one of these is true: 34 * - The EC controls the enable and the EC always enables a rail as 35 * long as the AP is running. 36 * - The rails are actually connected to each other by a jumper and 37 * the distinction is just there to add clarity/flexibility to the 38 * schematic. 39 */ 40 41 ppvar_sys: ppvar-sys { 42 compatible = "regulator-fixed"; 43 regulator-name = "ppvar_sys"; 44 regulator-always-on; 45 regulator-boot-on; 46 }; 47 48 pp1200_lpddr: pp1200-lpddr { 49 compatible = "regulator-fixed"; 50 regulator-name = "pp1200_lpddr"; 51 52 /* EC turns on w/ lpddr_pwr_en; always on for AP */ 53 regulator-always-on; 54 regulator-boot-on; 55 regulator-min-microvolt = <1200000>; 56 regulator-max-microvolt = <1200000>; 57 58 vin-supply = <&ppvar_sys>; 59 }; 60 61 pp1800: pp1800 { 62 compatible = "regulator-fixed"; 63 regulator-name = "pp1800"; 64 65 /* Always on when ppvar_sys shows power good */ 66 regulator-always-on; 67 regulator-boot-on; 68 regulator-min-microvolt = <1800000>; 69 regulator-max-microvolt = <1800000>; 70 71 vin-supply = <&ppvar_sys>; 72 }; 73 74 pp3300: pp3300 { 75 compatible = "regulator-fixed"; 76 regulator-name = "pp3300"; 77 78 /* Always on; plain and simple */ 79 regulator-always-on; 80 regulator-boot-on; 81 regulator-min-microvolt = <3300000>; 82 regulator-max-microvolt = <3300000>; 83 84 vin-supply = <&ppvar_sys>; 85 }; 86 87 pp5000: pp5000 { 88 compatible = "regulator-fixed"; 89 regulator-name = "pp5000"; 90 91 /* EC turns on w/ pp5000_en; always on for AP */ 92 regulator-always-on; 93 regulator-boot-on; 94 regulator-min-microvolt = <5000000>; 95 regulator-max-microvolt = <5000000>; 96 97 vin-supply = <&ppvar_sys>; 98 }; 99 100 ppvar_bigcpu_pwm: ppvar-bigcpu-pwm { 101 compatible = "pwm-regulator"; 102 regulator-name = "ppvar_bigcpu_pwm"; 103 104 pwms = <&pwm1 0 3337 0>; 105 pwm-supply = <&ppvar_sys>; 106 pwm-dutycycle-range = <100 0>; 107 pwm-dutycycle-unit = <100>; 108 109 /* EC turns on w/ ap_core_en; always on for AP */ 110 regulator-always-on; 111 regulator-boot-on; 112 regulator-min-microvolt = <800107>; 113 regulator-max-microvolt = <1302232>; 114 }; 115 116 ppvar_bigcpu: ppvar-bigcpu { 117 compatible = "vctrl-regulator"; 118 regulator-name = "ppvar_bigcpu"; 119 120 regulator-min-microvolt = <800107>; 121 regulator-max-microvolt = <1302232>; 122 123 ctrl-supply = <&ppvar_bigcpu_pwm>; 124 ctrl-voltage-range = <800107 1302232>; 125 126 regulator-settling-time-up-us = <322>; 127 }; 128 129 ppvar_litcpu_pwm: ppvar-litcpu-pwm { 130 compatible = "pwm-regulator"; 131 regulator-name = "ppvar_litcpu_pwm"; 132 133 pwms = <&pwm2 0 3337 0>; 134 pwm-supply = <&ppvar_sys>; 135 pwm-dutycycle-range = <100 0>; 136 pwm-dutycycle-unit = <100>; 137 138 /* EC turns on w/ ap_core_en; always on for AP */ 139 regulator-always-on; 140 regulator-boot-on; 141 regulator-min-microvolt = <797743>; 142 regulator-max-microvolt = <1307837>; 143 }; 144 145 ppvar_litcpu: ppvar-litcpu { 146 compatible = "vctrl-regulator"; 147 regulator-name = "ppvar_litcpu"; 148 149 regulator-min-microvolt = <797743>; 150 regulator-max-microvolt = <1307837>; 151 152 ctrl-supply = <&ppvar_litcpu_pwm>; 153 ctrl-voltage-range = <797743 1307837>; 154 155 regulator-settling-time-up-us = <384>; 156 }; 157 158 ppvar_gpu_pwm: ppvar-gpu-pwm { 159 compatible = "pwm-regulator"; 160 regulator-name = "ppvar_gpu_pwm"; 161 162 pwms = <&pwm0 0 3337 0>; 163 pwm-supply = <&ppvar_sys>; 164 pwm-dutycycle-range = <100 0>; 165 pwm-dutycycle-unit = <100>; 166 167 /* EC turns on w/ ap_core_en; always on for AP */ 168 regulator-always-on; 169 regulator-boot-on; 170 regulator-min-microvolt = <786384>; 171 regulator-max-microvolt = <1217747>; 172 }; 173 174 ppvar_gpu: ppvar-gpu { 175 compatible = "vctrl-regulator"; 176 regulator-name = "ppvar_gpu"; 177 178 regulator-min-microvolt = <786384>; 179 regulator-max-microvolt = <1217747>; 180 181 ctrl-supply = <&ppvar_gpu_pwm>; 182 ctrl-voltage-range = <786384 1217747>; 183 184 regulator-settling-time-up-us = <390>; 185 }; 186 187 /* EC turns on w/ pp900_ddrpll_en */ 188 pp900_ddrpll: pp900-ap { 189 }; 190 191 /* EC turns on w/ pp900_pll_en */ 192 pp900_pll: pp900-ap { 193 }; 194 195 /* EC turns on w/ pp900_pmu_en */ 196 pp900_pmu: pp900-ap { 197 }; 198 199 /* EC turns on w/ pp1800_s0_en_l */ 200 pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 { 201 }; 202 203 /* EC turns on w/ pp1800_avdd_en_l */ 204 pp1800_avdd: pp1800 { 205 }; 206 207 /* EC turns on w/ pp1800_lid_en_l */ 208 pp1800_lid: pp1800_mic: pp1800 { 209 }; 210 211 /* EC turns on w/ lpddr_pwr_en */ 212 pp1800_lpddr: pp1800 { 213 }; 214 215 /* EC turns on w/ pp1800_pmu_en_l */ 216 pp1800_pmu: pp1800 { 217 }; 218 219 /* EC turns on w/ pp1800_usb_en_l */ 220 pp1800_usb: pp1800 { 221 }; 222 223 pp3000_sd_slot: pp3000-sd-slot { 224 compatible = "regulator-fixed"; 225 regulator-name = "pp3000_sd_slot"; 226 pinctrl-names = "default"; 227 pinctrl-0 = <&sd_slot_pwr_en>; 228 229 enable-active-high; 230 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; 231 232 vin-supply = <&pp3000>; 233 }; 234 235 /* 236 * Technically, this is a small abuse of 'regulator-gpio'; this 237 * regulator is a mux between pp1800 and pp3300. pp1800 and pp3300 are 238 * always on though, so it is sufficient to simply control the mux 239 * here. 240 */ 241 ppvar_sd_card_io: ppvar-sd-card-io { 242 compatible = "regulator-gpio"; 243 regulator-name = "ppvar_sd_card_io"; 244 pinctrl-names = "default"; 245 pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>; 246 247 enable-active-high; 248 enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; 249 gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; 250 states = <1800000 0x1 251 3000000 0x0>; 252 253 regulator-min-microvolt = <1800000>; 254 regulator-max-microvolt = <3000000>; 255 }; 256 257 /* EC turns on w/ pp3300_trackpad_en_l */ 258 pp3300_trackpad: pp3300-trackpad { 259 }; 260 261 /* EC turns on w/ usb_a_en */ 262 pp5000_usb_a_vbus: pp5000 { 263 }; 264 265 gpio_keys: gpio-keys { 266 compatible = "gpio-keys"; 267 pinctrl-names = "default"; 268 pinctrl-0 = <&bt_host_wake_l>; 269 270 wake_on_bt: wake-on-bt { 271 label = "Wake-on-Bluetooth"; 272 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; 273 linux,code = <KEY_WAKEUP>; 274 wakeup-source; 275 }; 276 }; 277 278 max98357a: max98357a { 279 compatible = "maxim,max98357a"; 280 pinctrl-names = "default"; 281 pinctrl-0 = <&sdmode_en>; 282 sdmode-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 283 sdmode-delay = <2>; 284 #sound-dai-cells = <0>; 285 status = "okay"; 286 }; 287 288 sound: sound { 289 compatible = "rockchip,rk3399-gru-sound"; 290 rockchip,cpu = <&i2s0 &i2s2>; 291 }; 292}; 293 294&cdn_dp { 295 status = "okay"; 296}; 297 298/* 299 * Set some suspend operating points to avoid OVP in suspend 300 * 301 * When we go into S3 ARM Trusted Firmware will transition our PWM regulators 302 * from wherever they're at back to the "default" operating point (whatever 303 * voltage we get when we set the PWM pins to "input"). 304 * 305 * This quick transition under light load has the possibility to trigger the 306 * regulator "over voltage protection" (OVP). 307 * 308 * To make extra certain that we don't hit this OVP at suspend time, we'll 309 * transition to a voltage that's much closer to the default (~1.0 V) so that 310 * there will not be a big jump. Technically we only need to get within 200 mV 311 * of the default voltage, but the speed here should be fast enough and we need 312 * suspend/resume to be rock solid. 313 */ 314 315&cluster0_opp { 316 opp05 { 317 opp-suspend; 318 }; 319}; 320 321&cluster1_opp { 322 opp06 { 323 opp-suspend; 324 }; 325}; 326 327&cpu_l0 { 328 cpu-supply = <&ppvar_litcpu>; 329}; 330 331&cpu_l1 { 332 cpu-supply = <&ppvar_litcpu>; 333}; 334 335&cpu_l2 { 336 cpu-supply = <&ppvar_litcpu>; 337}; 338 339&cpu_l3 { 340 cpu-supply = <&ppvar_litcpu>; 341}; 342 343&cpu_b0 { 344 cpu-supply = <&ppvar_bigcpu>; 345}; 346 347&cpu_b1 { 348 cpu-supply = <&ppvar_bigcpu>; 349}; 350 351 352&cru { 353 assigned-clocks = 354 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 355 <&cru PLL_NPLL>, 356 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 357 <&cru PCLK_PERIHP>, 358 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 359 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 360 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 361 <&cru ACLK_VIO>, <&cru ACLK_HDCP>, 362 <&cru ACLK_GIC_PRE>, 363 <&cru PCLK_DDR>; 364 assigned-clock-rates = 365 <600000000>, <800000000>, 366 <1000000000>, 367 <150000000>, <75000000>, 368 <37500000>, 369 <100000000>, <100000000>, 370 <50000000>, <800000000>, 371 <100000000>, <50000000>, 372 <400000000>, <400000000>, 373 <200000000>, 374 <200000000>; 375}; 376 377&emmc_phy { 378 status = "okay"; 379}; 380 381&gpu { 382 mali-supply = <&ppvar_gpu>; 383 status = "okay"; 384}; 385 386ap_i2c_ts: &i2c3 { 387 status = "okay"; 388 389 clock-frequency = <400000>; 390 391 /* These are relatively safe rise/fall times */ 392 i2c-scl-falling-time-ns = <50>; 393 i2c-scl-rising-time-ns = <300>; 394}; 395 396ap_i2c_audio: &i2c8 { 397 status = "okay"; 398 399 clock-frequency = <400000>; 400 401 /* These are relatively safe rise/fall times */ 402 i2c-scl-falling-time-ns = <50>; 403 i2c-scl-rising-time-ns = <300>; 404 405 codec: da7219@1a { 406 compatible = "dlg,da7219"; 407 reg = <0x1a>; 408 interrupt-parent = <&gpio1>; 409 interrupts = <23 IRQ_TYPE_LEVEL_LOW>; 410 clocks = <&cru SCLK_I2S_8CH_OUT>; 411 clock-names = "mclk"; 412 dlg,micbias-lvl = <2600>; 413 dlg,mic-amp-in-sel = "diff"; 414 pinctrl-names = "default"; 415 pinctrl-0 = <&headset_int_l>; 416 VDD-supply = <&pp1800>; 417 VDDMIC-supply = <&pp3300>; 418 VDDIO-supply = <&pp1800>; 419 420 da7219_aad { 421 dlg,adc-1bit-rpt = <1>; 422 dlg,btn-avg = <4>; 423 dlg,btn-cfg = <50>; 424 dlg,mic-det-thr = <500>; 425 dlg,jack-ins-deb = <20>; 426 dlg,jack-det-rate = "32ms_64ms"; 427 dlg,jack-rem-deb = <1>; 428 429 dlg,a-d-btn-thr = <0xa>; 430 dlg,d-b-btn-thr = <0x16>; 431 dlg,b-c-btn-thr = <0x21>; 432 dlg,c-mic-btn-thr = <0x3E>; 433 }; 434 }; 435}; 436 437&i2s0 { 438 status = "okay"; 439}; 440 441&i2s2 { 442 status = "okay"; 443}; 444 445&io_domains { 446 status = "okay"; 447 448 audio-supply = <&pp1800_audio>; /* APIO5_VDD; 3d 4a */ 449 bt656-supply = <&pp1800_ap_io>; /* APIO2_VDD; 2a 2b */ 450 gpio1830-supply = <&pp3000_ap>; /* APIO4_VDD; 4c 4d */ 451 sdmmc-supply = <&ppvar_sd_card_io>; /* SDMMC0_VDD; 4b */ 452}; 453 454&pcie0 { 455 status = "okay"; 456 457 ep-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; 458 pinctrl-names = "default"; 459 pinctrl-0 = <&pcie_clkreqn_cpm>, <&wifi_perst_l>; 460 vpcie3v3-supply = <&pp3300_wifi_bt>; 461 vpcie1v8-supply = <&wlan_pd_n>; /* HACK: see &wlan_pd_n */ 462 vpcie0v9-supply = <&pp900_pcie>; 463 464 pci_rootport: pcie@0,0 { 465 reg = <0x83000000 0x0 0x00000000 0x0 0x00000000>; 466 #address-cells = <3>; 467 #size-cells = <2>; 468 ranges; 469 }; 470}; 471 472&pcie_phy { 473 status = "okay"; 474}; 475 476&pmu_io_domains { 477 status = "okay"; 478 479 pmu1830-supply = <&pp1800_pmu>; /* PMUIO2_VDD */ 480}; 481 482&pwm0 { 483 status = "okay"; 484}; 485 486&pwm1 { 487 status = "okay"; 488}; 489 490&pwm2 { 491 status = "okay"; 492}; 493 494&pwm3 { 495 status = "okay"; 496}; 497 498&sdhci { 499 /* 500 * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the 501 * same (or nearly the same) performance for all eMMC that are intended 502 * to be used. 503 */ 504 assigned-clock-rates = <150000000>; 505 506 bus-width = <8>; 507 mmc-hs400-1_8v; 508 mmc-hs400-enhanced-strobe; 509 non-removable; 510 status = "okay"; 511}; 512 513&sdmmc { 514 status = "okay"; 515 516 /* 517 * Note: configure "sdmmc_cd" as card detect even though it's actually 518 * hooked to ground. Because we specified "cd-gpios" below dw_mmc 519 * should be ignoring card detect anyway. Specifying the pin as 520 * sdmmc_cd means that even if you've got GRF_SOC_CON7[12] (force_jtag) 521 * turned on that the system will still make sure the port is 522 * configured as SDMMC and not JTAG. 523 */ 524 pinctrl-names = "default"; 525 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_gpio 526 &sdmmc_bus4>; 527 528 bus-width = <4>; 529 cap-mmc-highspeed; 530 cap-sd-highspeed; 531 cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 532 disable-wp; 533 sd-uhs-sdr12; 534 sd-uhs-sdr25; 535 sd-uhs-sdr50; 536 sd-uhs-sdr104; 537 vmmc-supply = <&pp3000_sd_slot>; 538 vqmmc-supply = <&ppvar_sd_card_io>; 539}; 540 541&spi1 { 542 status = "okay"; 543 544 pinctrl-names = "default", "sleep"; 545 pinctrl-1 = <&spi1_sleep>; 546 547 spiflash@0 { 548 compatible = "jedec,spi-nor"; 549 reg = <0>; 550 551 /* May run faster once verified. */ 552 spi-max-frequency = <10000000>; 553 }; 554}; 555 556&spi2 { 557 status = "okay"; 558}; 559 560&spi5 { 561 status = "okay"; 562 563 cros_ec: ec@0 { 564 compatible = "google,cros-ec-spi"; 565 reg = <0>; 566 interrupt-parent = <&gpio0>; 567 interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 568 pinctrl-names = "default"; 569 pinctrl-0 = <&ec_ap_int_l>; 570 spi-max-frequency = <3000000>; 571 572 i2c_tunnel: i2c-tunnel { 573 compatible = "google,cros-ec-i2c-tunnel"; 574 google,remote-bus = <4>; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 }; 578 579 usbc_extcon0: extcon@0 { 580 compatible = "google,extcon-usbc-cros-ec"; 581 google,usb-port-id = <0>; 582 583 #extcon-cells = <0>; 584 }; 585 }; 586}; 587 588&tsadc { 589 status = "okay"; 590 591 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ 592 rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ 593}; 594 595&tcphy0 { 596 status = "okay"; 597 extcon = <&usbc_extcon0>; 598}; 599 600&u2phy0 { 601 status = "okay"; 602}; 603 604&u2phy0_host { 605 status = "okay"; 606}; 607 608&u2phy1_host { 609 status = "okay"; 610}; 611 612&u2phy0_otg { 613 status = "okay"; 614}; 615 616&u2phy1_otg { 617 status = "okay"; 618}; 619 620&uart2 { 621 status = "okay"; 622}; 623 624&usb_host0_ohci { 625 status = "okay"; 626}; 627 628&usbdrd3_0 { 629 status = "okay"; 630 extcon = <&usbc_extcon0>; 631}; 632 633&usbdrd_dwc3_0 { 634 status = "okay"; 635 dr_mode = "host"; 636}; 637 638&vopb { 639 status = "okay"; 640}; 641 642&vopb_mmu { 643 status = "okay"; 644}; 645 646&vopl { 647 status = "okay"; 648}; 649 650&vopl_mmu { 651 status = "okay"; 652}; 653 654#include <arm/cros-ec-keyboard.dtsi> 655#include <arm/cros-ec-sbs.dtsi> 656 657&pinctrl { 658 /* 659 * pinctrl settings for pins that have no real owners. 660 * 661 * At the moment settings are identical for S0 and S3, but if we later 662 * need to configure things differently for S3 we'll adjust here. 663 */ 664 pinctrl-names = "default"; 665 pinctrl-0 = < 666 &ap_pwroff /* AP will auto-assert this when in S3 */ 667 &clk_32k /* This pin is always 32k on gru boards */ 668 >; 669 670 pcfg_output_low: pcfg-output-low { 671 output-low; 672 }; 673 674 pcfg_output_high: pcfg-output-high { 675 output-high; 676 }; 677 678 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 679 bias-disable; 680 drive-strength = <8>; 681 }; 682 683 backlight-enable { 684 bl_en: bl-en { 685 rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_none>; 686 }; 687 }; 688 689 cros-ec { 690 ec_ap_int_l: ec-ap-int-l { 691 rockchip,pins = <RK_GPIO0 1 RK_FUNC_GPIO &pcfg_pull_up>; 692 }; 693 }; 694 695 discrete-regulators { 696 sd_io_pwr_en: sd-io-pwr-en { 697 rockchip,pins = <RK_GPIO2 2 RK_FUNC_GPIO 698 &pcfg_pull_none>; 699 }; 700 701 sd_pwr_1800_sel: sd-pwr-1800-sel { 702 rockchip,pins = <RK_GPIO2 28 RK_FUNC_GPIO 703 &pcfg_pull_none>; 704 }; 705 706 sd_slot_pwr_en: sd-slot-pwr-en { 707 rockchip,pins = <RK_GPIO4 29 RK_FUNC_GPIO 708 &pcfg_pull_none>; 709 }; 710 }; 711 712 codec { 713 /* Has external pullup */ 714 headset_int_l: headset-int-l { 715 rockchip,pins = <1 23 RK_FUNC_GPIO &pcfg_pull_none>; 716 }; 717 718 mic_int: mic-int { 719 rockchip,pins = <1 13 RK_FUNC_GPIO &pcfg_pull_down>; 720 }; 721 }; 722 723 max98357a { 724 sdmode_en: sdmode-en { 725 rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_down>; 726 }; 727 }; 728 729 pcie { 730 pcie_clkreqn_cpm: pci-clkreqn-cpm { 731 /* 732 * Since our pcie doesn't support ClockPM(CPM), we want 733 * to hack this as gpio, so the EP could be able to 734 * de-assert it along and make ClockPM(CPM) work. 735 */ 736 rockchip,pins = <2 26 RK_FUNC_GPIO &pcfg_pull_none>; 737 }; 738 }; 739 740 sdmmc { 741 /* 742 * We run sdmmc at max speed; bump up drive strength. 743 * We also have external pulls, so disable the internal ones. 744 */ 745 sdmmc_bus4: sdmmc-bus4 { 746 rockchip,pins = 747 <4 8 RK_FUNC_1 &pcfg_pull_none_8ma>, 748 <4 9 RK_FUNC_1 &pcfg_pull_none_8ma>, 749 <4 10 RK_FUNC_1 &pcfg_pull_none_8ma>, 750 <4 11 RK_FUNC_1 &pcfg_pull_none_8ma>; 751 }; 752 753 sdmmc_clk: sdmmc-clk { 754 rockchip,pins = 755 <4 12 RK_FUNC_1 &pcfg_pull_none_8ma>; 756 }; 757 758 sdmmc_cmd: sdmmc-cmd { 759 rockchip,pins = 760 <4 13 RK_FUNC_1 &pcfg_pull_none_8ma>; 761 }; 762 763 /* 764 * In our case the official card detect is hooked to ground 765 * to avoid getting access to JTAG just by sticking something 766 * in the SD card slot (see the force_jtag bit in the TRM). 767 * 768 * We still configure it as card detect because it doesn't 769 * hurt and dw_mmc will ignore it. We make sure to disable 770 * the pull though so we don't burn needless power. 771 */ 772 sdmmc_cd: sdmmc-cd { 773 rockchip,pins = 774 <0 7 RK_FUNC_1 &pcfg_pull_none>; 775 }; 776 777 /* This is where we actually hook up CD; has external pull */ 778 sdmmc_cd_gpio: sdmmc-cd-gpio { 779 rockchip,pins = <4 24 RK_FUNC_GPIO &pcfg_pull_none>; 780 }; 781 }; 782 783 spi1 { 784 spi1_sleep: spi1-sleep { 785 /* 786 * Pull down SPI1 CLK/CS/RX/TX during suspend, to 787 * prevent leakage. 788 */ 789 rockchip,pins = <1 9 RK_FUNC_GPIO &pcfg_pull_down>, 790 <1 10 RK_FUNC_GPIO &pcfg_pull_down>, 791 <1 7 RK_FUNC_GPIO &pcfg_pull_down>, 792 <1 8 RK_FUNC_GPIO &pcfg_pull_down>; 793 }; 794 }; 795 796 touchscreen { 797 touch_int_l: touch-int-l { 798 rockchip,pins = <3 13 RK_FUNC_GPIO &pcfg_pull_up>; 799 }; 800 801 touch_reset_l: touch-reset-l { 802 rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_pull_none>; 803 }; 804 }; 805 806 trackpad { 807 ap_i2c_tp_pu_en: ap-i2c-tp-pu-en { 808 rockchip,pins = <3 12 RK_FUNC_GPIO &pcfg_output_high>; 809 }; 810 811 trackpad_int_l: trackpad-int-l { 812 rockchip,pins = <1 4 RK_FUNC_GPIO &pcfg_pull_up>; 813 }; 814 }; 815 816 wifi: wifi { 817 wlan_module_reset_l: wlan-module-reset-l { 818 rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_pull_none>; 819 }; 820 821 bt_host_wake_l: bt-host-wake-l { 822 /* Kevin has an external pull up, but Gru does not */ 823 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>; 824 }; 825 }; 826 827 write-protect { 828 ap_fw_wp: ap-fw-wp { 829 rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_up>; 830 }; 831 }; 832}; 833