1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Google Gru (and derivatives) board device tree source 4 * 5 * Copyright 2016-2017 Google, Inc 6 */ 7 8#include <dt-bindings/input/input.h> 9#include "rk3399.dtsi" 10#include "rk3399-op1-opp.dtsi" 11 12/ { 13 aliases { 14 mmc0 = &sdmmc; 15 mmc1 = &sdhci; 16 }; 17 18 chosen { 19 stdout-path = "serial2:115200n8"; 20 }; 21 22 /* 23 * Power Tree 24 * 25 * In general an attempt is made to include all rails called out by 26 * the schematic as long as those rails interact in some way with 27 * the AP. AKA: 28 * - Rails that only connect to the EC (or devices that the EC talks to) 29 * are not included. 30 * - Rails _are_ included if the rails go to the AP even if the AP 31 * doesn't currently care about them / they are always on. The idea 32 * here is that it makes it easier to map to the schematic or extend 33 * later. 34 * 35 * If two rails are substantially the same from the AP's point of 36 * view, though, we won't create a full fixed regulator. We'll just 37 * put the child rail as an alias of the parent rail. Sometimes rails 38 * look the same to the AP because one of these is true: 39 * - The EC controls the enable and the EC always enables a rail as 40 * long as the AP is running. 41 * - The rails are actually connected to each other by a jumper and 42 * the distinction is just there to add clarity/flexibility to the 43 * schematic. 44 */ 45 46 ppvar_sys: ppvar-sys { 47 compatible = "regulator-fixed"; 48 regulator-name = "ppvar_sys"; 49 regulator-always-on; 50 regulator-boot-on; 51 }; 52 53 pp1200_lpddr: pp1200-lpddr { 54 compatible = "regulator-fixed"; 55 regulator-name = "pp1200_lpddr"; 56 57 /* EC turns on w/ lpddr_pwr_en; always on for AP */ 58 regulator-always-on; 59 regulator-boot-on; 60 regulator-min-microvolt = <1200000>; 61 regulator-max-microvolt = <1200000>; 62 63 vin-supply = <&ppvar_sys>; 64 }; 65 66 pp1800: pp1800 { 67 compatible = "regulator-fixed"; 68 regulator-name = "pp1800"; 69 70 /* Always on when ppvar_sys shows power good */ 71 regulator-always-on; 72 regulator-boot-on; 73 regulator-min-microvolt = <1800000>; 74 regulator-max-microvolt = <1800000>; 75 76 vin-supply = <&ppvar_sys>; 77 }; 78 79 pp3300: pp3300 { 80 compatible = "regulator-fixed"; 81 regulator-name = "pp3300"; 82 83 /* Always on; plain and simple */ 84 regulator-always-on; 85 regulator-boot-on; 86 regulator-min-microvolt = <3300000>; 87 regulator-max-microvolt = <3300000>; 88 89 vin-supply = <&ppvar_sys>; 90 }; 91 92 pp5000: pp5000 { 93 compatible = "regulator-fixed"; 94 regulator-name = "pp5000"; 95 96 /* EC turns on w/ pp5000_en; always on for AP */ 97 regulator-always-on; 98 regulator-boot-on; 99 regulator-min-microvolt = <5000000>; 100 regulator-max-microvolt = <5000000>; 101 102 vin-supply = <&ppvar_sys>; 103 }; 104 105 ppvar_bigcpu_pwm: ppvar-bigcpu-pwm { 106 compatible = "pwm-regulator"; 107 regulator-name = "ppvar_bigcpu_pwm"; 108 109 pwms = <&pwm1 0 3337 0>; 110 pwm-supply = <&ppvar_sys>; 111 pwm-dutycycle-range = <100 0>; 112 pwm-dutycycle-unit = <100>; 113 114 /* EC turns on w/ ap_core_en; always on for AP */ 115 regulator-always-on; 116 regulator-boot-on; 117 regulator-min-microvolt = <800107>; 118 regulator-max-microvolt = <1302232>; 119 }; 120 121 ppvar_bigcpu: ppvar-bigcpu { 122 compatible = "vctrl-regulator"; 123 regulator-name = "ppvar_bigcpu"; 124 125 regulator-min-microvolt = <800107>; 126 regulator-max-microvolt = <1302232>; 127 128 ctrl-supply = <&ppvar_bigcpu_pwm>; 129 ctrl-voltage-range = <800107 1302232>; 130 131 regulator-settling-time-up-us = <322>; 132 }; 133 134 ppvar_litcpu_pwm: ppvar-litcpu-pwm { 135 compatible = "pwm-regulator"; 136 regulator-name = "ppvar_litcpu_pwm"; 137 138 pwms = <&pwm2 0 3337 0>; 139 pwm-supply = <&ppvar_sys>; 140 pwm-dutycycle-range = <100 0>; 141 pwm-dutycycle-unit = <100>; 142 143 /* EC turns on w/ ap_core_en; always on for AP */ 144 regulator-always-on; 145 regulator-boot-on; 146 regulator-min-microvolt = <797743>; 147 regulator-max-microvolt = <1307837>; 148 }; 149 150 ppvar_litcpu: ppvar-litcpu { 151 compatible = "vctrl-regulator"; 152 regulator-name = "ppvar_litcpu"; 153 154 regulator-min-microvolt = <797743>; 155 regulator-max-microvolt = <1307837>; 156 157 ctrl-supply = <&ppvar_litcpu_pwm>; 158 ctrl-voltage-range = <797743 1307837>; 159 160 regulator-settling-time-up-us = <384>; 161 }; 162 163 ppvar_gpu_pwm: ppvar-gpu-pwm { 164 compatible = "pwm-regulator"; 165 regulator-name = "ppvar_gpu_pwm"; 166 167 pwms = <&pwm0 0 3337 0>; 168 pwm-supply = <&ppvar_sys>; 169 pwm-dutycycle-range = <100 0>; 170 pwm-dutycycle-unit = <100>; 171 172 /* EC turns on w/ ap_core_en; always on for AP */ 173 regulator-always-on; 174 regulator-boot-on; 175 regulator-min-microvolt = <786384>; 176 regulator-max-microvolt = <1217747>; 177 }; 178 179 ppvar_gpu: ppvar-gpu { 180 compatible = "vctrl-regulator"; 181 regulator-name = "ppvar_gpu"; 182 183 regulator-min-microvolt = <786384>; 184 regulator-max-microvolt = <1217747>; 185 186 ctrl-supply = <&ppvar_gpu_pwm>; 187 ctrl-voltage-range = <786384 1217747>; 188 189 regulator-settling-time-up-us = <390>; 190 }; 191 192 /* EC turns on w/ pp900_ddrpll_en */ 193 pp900_ddrpll: pp900-ap { 194 }; 195 196 /* EC turns on w/ pp900_pll_en */ 197 pp900_pll: pp900-ap { 198 }; 199 200 /* EC turns on w/ pp900_pmu_en */ 201 pp900_pmu: pp900-ap { 202 }; 203 204 /* EC turns on w/ pp1800_s0_en_l */ 205 pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 { 206 }; 207 208 /* EC turns on w/ pp1800_avdd_en_l */ 209 pp1800_avdd: pp1800 { 210 }; 211 212 /* EC turns on w/ pp1800_lid_en_l */ 213 pp1800_lid: pp1800_mic: pp1800 { 214 }; 215 216 /* EC turns on w/ lpddr_pwr_en */ 217 pp1800_lpddr: pp1800 { 218 }; 219 220 /* EC turns on w/ pp1800_pmu_en_l */ 221 pp1800_pmu: pp1800 { 222 }; 223 224 /* EC turns on w/ pp1800_usb_en_l */ 225 pp1800_usb: pp1800 { 226 }; 227 228 pp3000_sd_slot: pp3000-sd-slot { 229 compatible = "regulator-fixed"; 230 regulator-name = "pp3000_sd_slot"; 231 pinctrl-names = "default"; 232 pinctrl-0 = <&sd_slot_pwr_en>; 233 234 enable-active-high; 235 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; 236 237 vin-supply = <&pp3000>; 238 }; 239 240 /* 241 * Technically, this is a small abuse of 'regulator-gpio'; this 242 * regulator is a mux between pp1800 and pp3300. pp1800 and pp3300 are 243 * always on though, so it is sufficient to simply control the mux 244 * here. 245 */ 246 ppvar_sd_card_io: ppvar-sd-card-io { 247 compatible = "regulator-gpio"; 248 regulator-name = "ppvar_sd_card_io"; 249 pinctrl-names = "default"; 250 pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>; 251 252 enable-active-high; 253 enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; 254 gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; 255 states = <1800000 0x1>, 256 <3000000 0x0>; 257 258 regulator-min-microvolt = <1800000>; 259 regulator-max-microvolt = <3000000>; 260 }; 261 262 /* EC turns on w/ pp3300_trackpad_en_l */ 263 pp3300_trackpad: pp3300-trackpad { 264 }; 265 266 /* EC turns on w/ usb_a_en */ 267 pp5000_usb_a_vbus: pp5000 { 268 }; 269 270 ap_rtc_clk: ap-rtc-clk { 271 compatible = "fixed-clock"; 272 clock-frequency = <32768>; 273 clock-output-names = "xin32k"; 274 #clock-cells = <0>; 275 }; 276 277 max98357a: max98357a { 278 compatible = "maxim,max98357a"; 279 pinctrl-names = "default"; 280 pinctrl-0 = <&sdmode_en>; 281 sdmode-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 282 sdmode-delay = <2>; 283 #sound-dai-cells = <0>; 284 status = "okay"; 285 }; 286 287 sound: sound { 288 compatible = "rockchip,rk3399-gru-sound"; 289 rockchip,cpu = <&i2s0 &i2s2>; 290 }; 291}; 292 293&cdn_dp { 294 status = "okay"; 295}; 296 297/* 298 * Set some suspend operating points to avoid OVP in suspend 299 * 300 * When we go into S3 ARM Trusted Firmware will transition our PWM regulators 301 * from wherever they're at back to the "default" operating point (whatever 302 * voltage we get when we set the PWM pins to "input"). 303 * 304 * This quick transition under light load has the possibility to trigger the 305 * regulator "over voltage protection" (OVP). 306 * 307 * To make extra certain that we don't hit this OVP at suspend time, we'll 308 * transition to a voltage that's much closer to the default (~1.0 V) so that 309 * there will not be a big jump. Technically we only need to get within 200 mV 310 * of the default voltage, but the speed here should be fast enough and we need 311 * suspend/resume to be rock solid. 312 */ 313 314&cluster0_opp { 315 opp05 { 316 opp-suspend; 317 }; 318}; 319 320&cluster1_opp { 321 opp06 { 322 opp-suspend; 323 }; 324}; 325 326&cpu_l0 { 327 cpu-supply = <&ppvar_litcpu>; 328}; 329 330&cpu_l1 { 331 cpu-supply = <&ppvar_litcpu>; 332}; 333 334&cpu_l2 { 335 cpu-supply = <&ppvar_litcpu>; 336}; 337 338&cpu_l3 { 339 cpu-supply = <&ppvar_litcpu>; 340}; 341 342&cpu_b0 { 343 cpu-supply = <&ppvar_bigcpu>; 344}; 345 346&cpu_b1 { 347 cpu-supply = <&ppvar_bigcpu>; 348}; 349 350 351&cru { 352 assigned-clocks = 353 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 354 <&cru PLL_NPLL>, 355 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 356 <&cru PCLK_PERIHP>, 357 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 358 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 359 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 360 <&cru ACLK_VIO>, <&cru ACLK_HDCP>, 361 <&cru ACLK_GIC_PRE>, 362 <&cru PCLK_DDR>; 363 assigned-clock-rates = 364 <600000000>, <800000000>, 365 <1000000000>, 366 <150000000>, <75000000>, 367 <37500000>, 368 <100000000>, <100000000>, 369 <50000000>, <800000000>, 370 <100000000>, <50000000>, 371 <400000000>, <400000000>, 372 <200000000>, 373 <200000000>; 374}; 375 376&emmc_phy { 377 status = "okay"; 378}; 379 380&gpu { 381 mali-supply = <&ppvar_gpu>; 382 status = "okay"; 383}; 384 385ap_i2c_ts: &i2c3 { 386 status = "okay"; 387 388 clock-frequency = <400000>; 389 390 /* These are relatively safe rise/fall times */ 391 i2c-scl-falling-time-ns = <50>; 392 i2c-scl-rising-time-ns = <300>; 393}; 394 395ap_i2c_audio: &i2c8 { 396 status = "okay"; 397 398 clock-frequency = <400000>; 399 400 /* These are relatively safe rise/fall times */ 401 i2c-scl-falling-time-ns = <50>; 402 i2c-scl-rising-time-ns = <300>; 403 404 codec: da7219@1a { 405 compatible = "dlg,da7219"; 406 reg = <0x1a>; 407 interrupt-parent = <&gpio1>; 408 interrupts = <23 IRQ_TYPE_LEVEL_LOW>; 409 clocks = <&cru SCLK_I2S_8CH_OUT>; 410 clock-names = "mclk"; 411 dlg,micbias-lvl = <2600>; 412 dlg,mic-amp-in-sel = "diff"; 413 pinctrl-names = "default"; 414 pinctrl-0 = <&headset_int_l>; 415 VDD-supply = <&pp1800>; 416 VDDMIC-supply = <&pp3300>; 417 VDDIO-supply = <&pp1800>; 418 419 da7219_aad { 420 dlg,adc-1bit-rpt = <1>; 421 dlg,btn-avg = <4>; 422 dlg,btn-cfg = <50>; 423 dlg,mic-det-thr = <500>; 424 dlg,jack-ins-deb = <20>; 425 dlg,jack-det-rate = "32ms_64ms"; 426 dlg,jack-rem-deb = <1>; 427 428 dlg,a-d-btn-thr = <0xa>; 429 dlg,d-b-btn-thr = <0x16>; 430 dlg,b-c-btn-thr = <0x21>; 431 dlg,c-mic-btn-thr = <0x3E>; 432 }; 433 }; 434}; 435 436&i2s0 { 437 status = "okay"; 438}; 439 440&i2s2 { 441 status = "okay"; 442}; 443 444&io_domains { 445 status = "okay"; 446 447 audio-supply = <&pp1800_audio>; /* APIO5_VDD; 3d 4a */ 448 bt656-supply = <&pp1800_ap_io>; /* APIO2_VDD; 2a 2b */ 449 gpio1830-supply = <&pp3000_ap>; /* APIO4_VDD; 4c 4d */ 450 sdmmc-supply = <&ppvar_sd_card_io>; /* SDMMC0_VDD; 4b */ 451}; 452 453&pcie0 { 454 status = "okay"; 455 456 ep-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; 457 pinctrl-names = "default"; 458 pinctrl-0 = <&pcie_clkreqn_cpm>, <&wifi_perst_l>; 459 vpcie3v3-supply = <&pp3300_wifi_bt>; 460 vpcie1v8-supply = <&wlan_pd_n>; /* HACK: see &wlan_pd_n */ 461 vpcie0v9-supply = <&pp900_pcie>; 462 463 pci_rootport: pcie@0,0 { 464 reg = <0x83000000 0x0 0x00000000 0x0 0x00000000>; 465 #address-cells = <3>; 466 #size-cells = <2>; 467 ranges; 468 }; 469}; 470 471&pcie_phy { 472 status = "okay"; 473}; 474 475&pmu_io_domains { 476 status = "okay"; 477 478 pmu1830-supply = <&pp1800_pmu>; /* PMUIO2_VDD */ 479}; 480 481&pwm0 { 482 status = "okay"; 483}; 484 485&pwm1 { 486 status = "okay"; 487}; 488 489&pwm2 { 490 status = "okay"; 491}; 492 493&pwm3 { 494 status = "okay"; 495}; 496 497&sdhci { 498 /* 499 * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the 500 * same (or nearly the same) performance for all eMMC that are intended 501 * to be used. 502 */ 503 assigned-clock-rates = <150000000>; 504 505 bus-width = <8>; 506 mmc-hs400-1_8v; 507 mmc-hs400-enhanced-strobe; 508 non-removable; 509 status = "okay"; 510}; 511 512&sdmmc { 513 status = "okay"; 514 515 /* 516 * Note: configure "sdmmc_cd" as card detect even though it's actually 517 * hooked to ground. Because we specified "cd-gpios" below dw_mmc 518 * should be ignoring card detect anyway. Specifying the pin as 519 * sdmmc_cd means that even if you've got GRF_SOC_CON7[12] (force_jtag) 520 * turned on that the system will still make sure the port is 521 * configured as SDMMC and not JTAG. 522 */ 523 pinctrl-names = "default"; 524 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_pin 525 &sdmmc_bus4>; 526 527 bus-width = <4>; 528 cap-mmc-highspeed; 529 cap-sd-highspeed; 530 cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 531 disable-wp; 532 sd-uhs-sdr12; 533 sd-uhs-sdr25; 534 sd-uhs-sdr50; 535 sd-uhs-sdr104; 536 vmmc-supply = <&pp3000_sd_slot>; 537 vqmmc-supply = <&ppvar_sd_card_io>; 538}; 539 540&spi1 { 541 status = "okay"; 542 543 pinctrl-names = "default", "sleep"; 544 pinctrl-1 = <&spi1_sleep>; 545 546 spiflash@0 { 547 compatible = "jedec,spi-nor"; 548 reg = <0>; 549 550 /* May run faster once verified. */ 551 spi-max-frequency = <10000000>; 552 }; 553}; 554 555&spi2 { 556 status = "okay"; 557}; 558 559&spi5 { 560 status = "okay"; 561 562 cros_ec: ec@0 { 563 compatible = "google,cros-ec-spi"; 564 reg = <0>; 565 interrupt-parent = <&gpio0>; 566 interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 567 pinctrl-names = "default"; 568 pinctrl-0 = <&ec_ap_int_l>; 569 spi-max-frequency = <3000000>; 570 571 i2c_tunnel: i2c-tunnel { 572 compatible = "google,cros-ec-i2c-tunnel"; 573 google,remote-bus = <4>; 574 #address-cells = <1>; 575 #size-cells = <0>; 576 }; 577 578 usbc_extcon0: extcon0 { 579 compatible = "google,extcon-usbc-cros-ec"; 580 google,usb-port-id = <0>; 581 }; 582 }; 583}; 584 585&tsadc { 586 status = "okay"; 587 588 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ 589 rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ 590}; 591 592&tcphy0 { 593 status = "okay"; 594 extcon = <&usbc_extcon0>; 595}; 596 597&u2phy0 { 598 status = "okay"; 599}; 600 601&u2phy0_host { 602 status = "okay"; 603}; 604 605&u2phy1_host { 606 status = "okay"; 607}; 608 609&u2phy0_otg { 610 status = "okay"; 611}; 612 613&u2phy1_otg { 614 status = "okay"; 615}; 616 617&uart2 { 618 status = "okay"; 619}; 620 621&usb_host0_ohci { 622 status = "okay"; 623}; 624 625&usbdrd3_0 { 626 status = "okay"; 627 extcon = <&usbc_extcon0>; 628}; 629 630&usbdrd_dwc3_0 { 631 status = "okay"; 632 dr_mode = "host"; 633}; 634 635&vopb { 636 status = "okay"; 637}; 638 639&vopb_mmu { 640 status = "okay"; 641}; 642 643&vopl { 644 status = "okay"; 645}; 646 647&vopl_mmu { 648 status = "okay"; 649}; 650 651#include <arm/cros-ec-keyboard.dtsi> 652#include <arm/cros-ec-sbs.dtsi> 653 654&pinctrl { 655 /* 656 * pinctrl settings for pins that have no real owners. 657 * 658 * At the moment settings are identical for S0 and S3, but if we later 659 * need to configure things differently for S3 we'll adjust here. 660 */ 661 pinctrl-names = "default"; 662 pinctrl-0 = < 663 &ap_pwroff /* AP will auto-assert this when in S3 */ 664 &clk_32k /* This pin is always 32k on gru boards */ 665 >; 666 667 pcfg_output_low: pcfg-output-low { 668 output-low; 669 }; 670 671 pcfg_output_high: pcfg-output-high { 672 output-high; 673 }; 674 675 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 676 bias-disable; 677 drive-strength = <8>; 678 }; 679 680 backlight-enable { 681 bl_en: bl-en { 682 rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; 683 }; 684 }; 685 686 cros-ec { 687 ec_ap_int_l: ec-ap-int-l { 688 rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; 689 }; 690 }; 691 692 discrete-regulators { 693 sd_io_pwr_en: sd-io-pwr-en { 694 rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO 695 &pcfg_pull_none>; 696 }; 697 698 sd_pwr_1800_sel: sd-pwr-1800-sel { 699 rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO 700 &pcfg_pull_none>; 701 }; 702 703 sd_slot_pwr_en: sd-slot-pwr-en { 704 rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO 705 &pcfg_pull_none>; 706 }; 707 }; 708 709 codec { 710 /* Has external pullup */ 711 headset_int_l: headset-int-l { 712 rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; 713 }; 714 715 mic_int: mic-int { 716 rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; 717 }; 718 }; 719 720 max98357a { 721 sdmode_en: sdmode-en { 722 rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>; 723 }; 724 }; 725 726 pcie { 727 pcie_clkreqn_cpm: pci-clkreqn-cpm { 728 /* 729 * Since our pcie doesn't support ClockPM(CPM), we want 730 * to hack this as gpio, so the EP could be able to 731 * de-assert it along and make ClockPM(CPM) work. 732 */ 733 rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 734 }; 735 }; 736 737 sdmmc { 738 /* 739 * We run sdmmc at max speed; bump up drive strength. 740 * We also have external pulls, so disable the internal ones. 741 */ 742 sdmmc_bus4: sdmmc-bus4 { 743 rockchip,pins = 744 <4 RK_PB0 1 &pcfg_pull_none_8ma>, 745 <4 RK_PB1 1 &pcfg_pull_none_8ma>, 746 <4 RK_PB2 1 &pcfg_pull_none_8ma>, 747 <4 RK_PB3 1 &pcfg_pull_none_8ma>; 748 }; 749 750 sdmmc_clk: sdmmc-clk { 751 rockchip,pins = 752 <4 RK_PB4 1 &pcfg_pull_none_8ma>; 753 }; 754 755 sdmmc_cmd: sdmmc-cmd { 756 rockchip,pins = 757 <4 RK_PB5 1 &pcfg_pull_none_8ma>; 758 }; 759 760 /* 761 * In our case the official card detect is hooked to ground 762 * to avoid getting access to JTAG just by sticking something 763 * in the SD card slot (see the force_jtag bit in the TRM). 764 * 765 * We still configure it as card detect because it doesn't 766 * hurt and dw_mmc will ignore it. We make sure to disable 767 * the pull though so we don't burn needless power. 768 */ 769 sdmmc_cd: sdmmc-cd { 770 rockchip,pins = 771 <0 RK_PA7 1 &pcfg_pull_none>; 772 }; 773 774 /* This is where we actually hook up CD; has external pull */ 775 sdmmc_cd_pin: sdmmc-cd-pin { 776 rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 777 }; 778 }; 779 780 spi1 { 781 spi1_sleep: spi1-sleep { 782 /* 783 * Pull down SPI1 CLK/CS/RX/TX during suspend, to 784 * prevent leakage. 785 */ 786 rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>, 787 <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>, 788 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>, 789 <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; 790 }; 791 }; 792 793 touchscreen { 794 touch_int_l: touch-int-l { 795 rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; 796 }; 797 798 touch_reset_l: touch-reset-l { 799 rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 800 }; 801 }; 802 803 trackpad { 804 ap_i2c_tp_pu_en: ap-i2c-tp-pu-en { 805 rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>; 806 }; 807 808 trackpad_int_l: trackpad-int-l { 809 rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; 810 }; 811 }; 812 813 wifi: wifi { 814 wlan_module_reset_l: wlan-module-reset-l { 815 rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; 816 }; 817 818 bt_host_wake_l: bt-host-wake-l { 819 /* Kevin has an external pull up, but Gru does not */ 820 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; 821 }; 822 }; 823 824 write-protect { 825 ap_fw_wp: ap-fw-wp { 826 rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; 827 }; 828 }; 829}; 830