1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Google Gru (and derivatives) board device tree source
4 *
5 * Copyright 2016-2017 Google, Inc
6 */
7
8#include <dt-bindings/input/input.h>
9#include "rk3399.dtsi"
10#include "rk3399-op1-opp.dtsi"
11
12/ {
13	chosen {
14		stdout-path = "serial2:115200n8";
15	};
16
17	/*
18	 * Power Tree
19	 *
20	 * In general an attempt is made to include all rails called out by
21	 * the schematic as long as those rails interact in some way with
22	 * the AP.  AKA:
23	 * - Rails that only connect to the EC (or devices that the EC talks to)
24	 *   are not included.
25	 * - Rails _are_ included if the rails go to the AP even if the AP
26	 *   doesn't currently care about them / they are always on.  The idea
27	 *   here is that it makes it easier to map to the schematic or extend
28	 *   later.
29	 *
30	 * If two rails are substantially the same from the AP's point of
31	 * view, though, we won't create a full fixed regulator.  We'll just
32	 * put the child rail as an alias of the parent rail.  Sometimes rails
33	 * look the same to the AP because one of these is true:
34	 * - The EC controls the enable and the EC always enables a rail as
35	 *   long as the AP is running.
36	 * - The rails are actually connected to each other by a jumper and
37	 *   the distinction is just there to add clarity/flexibility to the
38	 *   schematic.
39	 */
40
41	ppvar_sys: ppvar-sys {
42		compatible = "regulator-fixed";
43		regulator-name = "ppvar_sys";
44		regulator-always-on;
45		regulator-boot-on;
46	};
47
48	pp1200_lpddr: pp1200-lpddr {
49		compatible = "regulator-fixed";
50		regulator-name = "pp1200_lpddr";
51
52		/* EC turns on w/ lpddr_pwr_en; always on for AP */
53		regulator-always-on;
54		regulator-boot-on;
55		regulator-min-microvolt = <1200000>;
56		regulator-max-microvolt = <1200000>;
57
58		vin-supply = <&ppvar_sys>;
59	};
60
61	pp1800: pp1800 {
62		compatible = "regulator-fixed";
63		regulator-name = "pp1800";
64
65		/* Always on when ppvar_sys shows power good */
66		regulator-always-on;
67		regulator-boot-on;
68		regulator-min-microvolt = <1800000>;
69		regulator-max-microvolt = <1800000>;
70
71		vin-supply = <&ppvar_sys>;
72	};
73
74	pp3300: pp3300 {
75		compatible = "regulator-fixed";
76		regulator-name = "pp3300";
77
78		/* Always on; plain and simple */
79		regulator-always-on;
80		regulator-boot-on;
81		regulator-min-microvolt = <3300000>;
82		regulator-max-microvolt = <3300000>;
83
84		vin-supply = <&ppvar_sys>;
85	};
86
87	pp5000: pp5000 {
88		compatible = "regulator-fixed";
89		regulator-name = "pp5000";
90
91		/* EC turns on w/ pp5000_en; always on for AP */
92		regulator-always-on;
93		regulator-boot-on;
94		regulator-min-microvolt = <5000000>;
95		regulator-max-microvolt = <5000000>;
96
97		vin-supply = <&ppvar_sys>;
98	};
99
100	ppvar_bigcpu_pwm: ppvar-bigcpu-pwm {
101		compatible = "pwm-regulator";
102		regulator-name = "ppvar_bigcpu_pwm";
103
104		pwms = <&pwm1 0 3337 0>;
105		pwm-supply = <&ppvar_sys>;
106		pwm-dutycycle-range = <100 0>;
107		pwm-dutycycle-unit = <100>;
108
109		/* EC turns on w/ ap_core_en; always on for AP */
110		regulator-always-on;
111		regulator-boot-on;
112		regulator-min-microvolt = <800107>;
113		regulator-max-microvolt = <1302232>;
114	};
115
116	ppvar_bigcpu: ppvar-bigcpu {
117		compatible = "vctrl-regulator";
118		regulator-name = "ppvar_bigcpu";
119
120		regulator-min-microvolt = <800107>;
121		regulator-max-microvolt = <1302232>;
122
123		ctrl-supply = <&ppvar_bigcpu_pwm>;
124		ctrl-voltage-range = <800107 1302232>;
125
126		regulator-settling-time-up-us = <322>;
127	};
128
129	ppvar_litcpu_pwm: ppvar-litcpu-pwm {
130		compatible = "pwm-regulator";
131		regulator-name = "ppvar_litcpu_pwm";
132
133		pwms = <&pwm2 0 3337 0>;
134		pwm-supply = <&ppvar_sys>;
135		pwm-dutycycle-range = <100 0>;
136		pwm-dutycycle-unit = <100>;
137
138		/* EC turns on w/ ap_core_en; always on for AP */
139		regulator-always-on;
140		regulator-boot-on;
141		regulator-min-microvolt = <797743>;
142		regulator-max-microvolt = <1307837>;
143	};
144
145	ppvar_litcpu: ppvar-litcpu {
146		compatible = "vctrl-regulator";
147		regulator-name = "ppvar_litcpu";
148
149		regulator-min-microvolt = <797743>;
150		regulator-max-microvolt = <1307837>;
151
152		ctrl-supply = <&ppvar_litcpu_pwm>;
153		ctrl-voltage-range = <797743 1307837>;
154
155		regulator-settling-time-up-us = <384>;
156	};
157
158	ppvar_gpu_pwm: ppvar-gpu-pwm {
159		compatible = "pwm-regulator";
160		regulator-name = "ppvar_gpu_pwm";
161
162		pwms = <&pwm0 0 3337 0>;
163		pwm-supply = <&ppvar_sys>;
164		pwm-dutycycle-range = <100 0>;
165		pwm-dutycycle-unit = <100>;
166
167		/* EC turns on w/ ap_core_en; always on for AP */
168		regulator-always-on;
169		regulator-boot-on;
170		regulator-min-microvolt = <786384>;
171		regulator-max-microvolt = <1217747>;
172	};
173
174	ppvar_gpu: ppvar-gpu {
175		compatible = "vctrl-regulator";
176		regulator-name = "ppvar_gpu";
177
178		regulator-min-microvolt = <786384>;
179		regulator-max-microvolt = <1217747>;
180
181		ctrl-supply = <&ppvar_gpu_pwm>;
182		ctrl-voltage-range = <786384 1217747>;
183
184		regulator-settling-time-up-us = <390>;
185	};
186
187	/* EC turns on w/ pp900_ddrpll_en */
188	pp900_ddrpll: pp900-ap {
189	};
190
191	/* EC turns on w/ pp900_pll_en */
192	pp900_pll: pp900-ap {
193	};
194
195	/* EC turns on w/ pp900_pmu_en */
196	pp900_pmu: pp900-ap {
197	};
198
199	/* EC turns on w/ pp1800_s0_en_l */
200	pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 {
201	};
202
203	/* EC turns on w/ pp1800_avdd_en_l */
204	pp1800_avdd: pp1800 {
205	};
206
207	/* EC turns on w/ pp1800_lid_en_l */
208	pp1800_lid: pp1800_mic: pp1800 {
209	};
210
211	/* EC turns on w/ lpddr_pwr_en */
212	pp1800_lpddr: pp1800 {
213	};
214
215	/* EC turns on w/ pp1800_pmu_en_l */
216	pp1800_pmu: pp1800 {
217	};
218
219	/* EC turns on w/ pp1800_usb_en_l */
220	pp1800_usb: pp1800 {
221	};
222
223	pp3000_sd_slot: pp3000-sd-slot {
224		compatible = "regulator-fixed";
225		regulator-name = "pp3000_sd_slot";
226		pinctrl-names = "default";
227		pinctrl-0 = <&sd_slot_pwr_en>;
228
229		enable-active-high;
230		gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
231
232		vin-supply = <&pp3000>;
233	};
234
235	/*
236	 * Technically, this is a small abuse of 'regulator-gpio'; this
237	 * regulator is a mux between pp1800 and pp3300. pp1800 and pp3300 are
238	 * always on though, so it is sufficient to simply control the mux
239	 * here.
240	 */
241	ppvar_sd_card_io: ppvar-sd-card-io {
242		compatible = "regulator-gpio";
243		regulator-name = "ppvar_sd_card_io";
244		pinctrl-names = "default";
245		pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>;
246
247		enable-active-high;
248		enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>;
249		gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
250		states = <1800000 0x1
251			  3000000 0x0>;
252
253		regulator-min-microvolt = <1800000>;
254		regulator-max-microvolt = <3000000>;
255	};
256
257	/* EC turns on w/ pp3300_trackpad_en_l */
258	pp3300_trackpad: pp3300-trackpad {
259	};
260
261	/* EC turns on w/ usb_a_en */
262	pp5000_usb_a_vbus: pp5000 {
263	};
264
265	ap_rtc_clk: ap-rtc-clk {
266		compatible = "fixed-clock";
267		clock-frequency = <32768>;
268		clock-output-names = "xin32k";
269		#clock-cells = <0>;
270	};
271
272	gpio_keys: gpio-keys {
273		compatible = "gpio-keys";
274		pinctrl-names = "default";
275		pinctrl-0 = <&bt_host_wake_l>;
276
277		wake_on_bt: wake-on-bt {
278			label = "Wake-on-Bluetooth";
279			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
280			linux,code = <KEY_WAKEUP>;
281			wakeup-source;
282		};
283	};
284
285	max98357a: max98357a {
286		compatible = "maxim,max98357a";
287		pinctrl-names = "default";
288		pinctrl-0 = <&sdmode_en>;
289		sdmode-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
290		sdmode-delay = <2>;
291		#sound-dai-cells = <0>;
292		status = "okay";
293	};
294
295	sound: sound {
296		compatible = "rockchip,rk3399-gru-sound";
297		rockchip,cpu = <&i2s0 &i2s2>;
298	};
299};
300
301&cdn_dp {
302	status = "okay";
303};
304
305/*
306 * Set some suspend operating points to avoid OVP in suspend
307 *
308 * When we go into S3 ARM Trusted Firmware will transition our PWM regulators
309 * from wherever they're at back to the "default" operating point (whatever
310 * voltage we get when we set the PWM pins to "input").
311 *
312 * This quick transition under light load has the possibility to trigger the
313 * regulator "over voltage protection" (OVP).
314 *
315 * To make extra certain that we don't hit this OVP at suspend time, we'll
316 * transition to a voltage that's much closer to the default (~1.0 V) so that
317 * there will not be a big jump.  Technically we only need to get within 200 mV
318 * of the default voltage, but the speed here should be fast enough and we need
319 * suspend/resume to be rock solid.
320 */
321
322&cluster0_opp {
323	opp05 {
324		opp-suspend;
325	};
326};
327
328&cluster1_opp {
329	opp06 {
330		opp-suspend;
331	};
332};
333
334&cpu_l0 {
335	cpu-supply = <&ppvar_litcpu>;
336};
337
338&cpu_l1 {
339	cpu-supply = <&ppvar_litcpu>;
340};
341
342&cpu_l2 {
343	cpu-supply = <&ppvar_litcpu>;
344};
345
346&cpu_l3 {
347	cpu-supply = <&ppvar_litcpu>;
348};
349
350&cpu_b0 {
351	cpu-supply = <&ppvar_bigcpu>;
352};
353
354&cpu_b1 {
355	cpu-supply = <&ppvar_bigcpu>;
356};
357
358
359&cru {
360	assigned-clocks =
361		<&cru PLL_GPLL>, <&cru PLL_CPLL>,
362		<&cru PLL_NPLL>,
363		<&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
364		<&cru PCLK_PERIHP>,
365		<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
366		<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
367		<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
368		<&cru ACLK_VIO>, <&cru ACLK_HDCP>,
369		<&cru ACLK_GIC_PRE>,
370		<&cru PCLK_DDR>;
371	assigned-clock-rates =
372		<600000000>, <800000000>,
373		<1000000000>,
374		<150000000>, <75000000>,
375		<37500000>,
376		<100000000>, <100000000>,
377		<50000000>, <800000000>,
378		<100000000>, <50000000>,
379		<400000000>, <400000000>,
380		<200000000>,
381		<200000000>;
382};
383
384&emmc_phy {
385	status = "okay";
386};
387
388&gpu {
389	mali-supply = <&ppvar_gpu>;
390	status = "okay";
391};
392
393ap_i2c_ts: &i2c3 {
394	status = "okay";
395
396	clock-frequency = <400000>;
397
398	/* These are relatively safe rise/fall times */
399	i2c-scl-falling-time-ns = <50>;
400	i2c-scl-rising-time-ns = <300>;
401};
402
403ap_i2c_audio: &i2c8 {
404	status = "okay";
405
406	clock-frequency = <400000>;
407
408	/* These are relatively safe rise/fall times */
409	i2c-scl-falling-time-ns = <50>;
410	i2c-scl-rising-time-ns = <300>;
411
412	codec: da7219@1a {
413		compatible = "dlg,da7219";
414		reg = <0x1a>;
415		interrupt-parent = <&gpio1>;
416		interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
417		clocks = <&cru SCLK_I2S_8CH_OUT>;
418		clock-names = "mclk";
419		dlg,micbias-lvl = <2600>;
420		dlg,mic-amp-in-sel = "diff";
421		pinctrl-names = "default";
422		pinctrl-0 = <&headset_int_l>;
423		VDD-supply = <&pp1800>;
424		VDDMIC-supply = <&pp3300>;
425		VDDIO-supply = <&pp1800>;
426
427		da7219_aad {
428			dlg,adc-1bit-rpt = <1>;
429			dlg,btn-avg = <4>;
430			dlg,btn-cfg = <50>;
431			dlg,mic-det-thr = <500>;
432			dlg,jack-ins-deb = <20>;
433			dlg,jack-det-rate = "32ms_64ms";
434			dlg,jack-rem-deb = <1>;
435
436			dlg,a-d-btn-thr = <0xa>;
437			dlg,d-b-btn-thr = <0x16>;
438			dlg,b-c-btn-thr = <0x21>;
439			dlg,c-mic-btn-thr = <0x3E>;
440		};
441	};
442};
443
444&i2s0 {
445	status = "okay";
446};
447
448&i2s2 {
449	status = "okay";
450};
451
452&io_domains {
453	status = "okay";
454
455	audio-supply = <&pp1800_audio>;		/* APIO5_VDD;  3d 4a */
456	bt656-supply = <&pp1800_ap_io>;		/* APIO2_VDD;  2a 2b */
457	gpio1830-supply = <&pp3000_ap>;		/* APIO4_VDD;  4c 4d */
458	sdmmc-supply = <&ppvar_sd_card_io>;	/* SDMMC0_VDD; 4b    */
459};
460
461&pcie0 {
462	status = "okay";
463
464	ep-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
465	pinctrl-names = "default";
466	pinctrl-0 = <&pcie_clkreqn_cpm>, <&wifi_perst_l>;
467	vpcie3v3-supply = <&pp3300_wifi_bt>;
468	vpcie1v8-supply = <&wlan_pd_n>; /* HACK: see &wlan_pd_n */
469	vpcie0v9-supply = <&pp900_pcie>;
470
471	pci_rootport: pcie@0,0 {
472		reg = <0x83000000 0x0 0x00000000 0x0 0x00000000>;
473		#address-cells = <3>;
474		#size-cells = <2>;
475		ranges;
476	};
477};
478
479&pcie_phy {
480	status = "okay";
481};
482
483&pmu_io_domains {
484	status = "okay";
485
486	pmu1830-supply = <&pp1800_pmu>;		/* PMUIO2_VDD */
487};
488
489&pwm0 {
490	status = "okay";
491};
492
493&pwm1 {
494	status = "okay";
495};
496
497&pwm2 {
498	status = "okay";
499};
500
501&pwm3 {
502	status = "okay";
503};
504
505&sdhci {
506	/*
507	 * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the
508	 * same (or nearly the same) performance for all eMMC that are intended
509	 * to be used.
510	 */
511	assigned-clock-rates = <150000000>;
512
513	bus-width = <8>;
514	mmc-hs400-1_8v;
515	mmc-hs400-enhanced-strobe;
516	non-removable;
517	status = "okay";
518};
519
520&sdmmc {
521	status = "okay";
522
523	/*
524	 * Note: configure "sdmmc_cd" as card detect even though it's actually
525	 * hooked to ground.  Because we specified "cd-gpios" below dw_mmc
526	 * should be ignoring card detect anyway.  Specifying the pin as
527	 * sdmmc_cd means that even if you've got GRF_SOC_CON7[12] (force_jtag)
528	 * turned on that the system will still make sure the port is
529	 * configured as SDMMC and not JTAG.
530	 */
531	pinctrl-names = "default";
532	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_gpio
533		     &sdmmc_bus4>;
534
535	bus-width = <4>;
536	cap-mmc-highspeed;
537	cap-sd-highspeed;
538	cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
539	disable-wp;
540	sd-uhs-sdr12;
541	sd-uhs-sdr25;
542	sd-uhs-sdr50;
543	sd-uhs-sdr104;
544	vmmc-supply = <&pp3000_sd_slot>;
545	vqmmc-supply = <&ppvar_sd_card_io>;
546};
547
548&spi1 {
549	status = "okay";
550
551	pinctrl-names = "default", "sleep";
552	pinctrl-1 = <&spi1_sleep>;
553
554	spiflash@0 {
555		compatible = "jedec,spi-nor";
556		reg = <0>;
557
558		/* May run faster once verified. */
559		spi-max-frequency = <10000000>;
560	};
561};
562
563&spi2 {
564	status = "okay";
565};
566
567&spi5 {
568	status = "okay";
569
570	cros_ec: ec@0 {
571		compatible = "google,cros-ec-spi";
572		reg = <0>;
573		interrupt-parent = <&gpio0>;
574		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
575		pinctrl-names = "default";
576		pinctrl-0 = <&ec_ap_int_l>;
577		spi-max-frequency = <3000000>;
578
579		i2c_tunnel: i2c-tunnel {
580			compatible = "google,cros-ec-i2c-tunnel";
581			google,remote-bus = <4>;
582			#address-cells = <1>;
583			#size-cells = <0>;
584		};
585
586		usbc_extcon0: extcon@0 {
587			compatible = "google,extcon-usbc-cros-ec";
588			google,usb-port-id = <0>;
589
590			#extcon-cells = <0>;
591		};
592	};
593};
594
595&tsadc {
596	status = "okay";
597
598	rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
599	rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
600};
601
602&tcphy0 {
603	status = "okay";
604	extcon = <&usbc_extcon0>;
605};
606
607&u2phy0 {
608	status = "okay";
609};
610
611&u2phy0_host {
612	status = "okay";
613};
614
615&u2phy1_host {
616	status = "okay";
617};
618
619&u2phy0_otg {
620	status = "okay";
621};
622
623&u2phy1_otg {
624	status = "okay";
625};
626
627&uart2 {
628	status = "okay";
629};
630
631&usb_host0_ohci {
632	status = "okay";
633};
634
635&usbdrd3_0 {
636	status = "okay";
637	extcon = <&usbc_extcon0>;
638};
639
640&usbdrd_dwc3_0 {
641	status = "okay";
642	dr_mode = "host";
643};
644
645&vopb {
646	status = "okay";
647};
648
649&vopb_mmu {
650	status = "okay";
651};
652
653&vopl {
654	status = "okay";
655};
656
657&vopl_mmu {
658	status = "okay";
659};
660
661#include <arm/cros-ec-keyboard.dtsi>
662#include <arm/cros-ec-sbs.dtsi>
663
664&pinctrl {
665	/*
666	 * pinctrl settings for pins that have no real owners.
667	 *
668	 * At the moment settings are identical for S0 and S3, but if we later
669	 * need to configure things differently for S3 we'll adjust here.
670	 */
671	pinctrl-names = "default";
672	pinctrl-0 = <
673		&ap_pwroff	/* AP will auto-assert this when in S3 */
674		&clk_32k	/* This pin is always 32k on gru boards */
675	>;
676
677	pcfg_output_low: pcfg-output-low {
678		output-low;
679	};
680
681	pcfg_output_high: pcfg-output-high {
682		output-high;
683	};
684
685	pcfg_pull_none_8ma: pcfg-pull-none-8ma {
686		bias-disable;
687		drive-strength = <8>;
688	};
689
690	backlight-enable {
691		bl_en: bl-en {
692			rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_none>;
693		};
694	};
695
696	cros-ec {
697		ec_ap_int_l: ec-ap-int-l {
698			rockchip,pins = <RK_GPIO0 1 RK_FUNC_GPIO &pcfg_pull_up>;
699		};
700	};
701
702	discrete-regulators {
703		sd_io_pwr_en: sd-io-pwr-en {
704			rockchip,pins = <RK_GPIO2 2 RK_FUNC_GPIO
705					 &pcfg_pull_none>;
706		};
707
708		sd_pwr_1800_sel: sd-pwr-1800-sel {
709			rockchip,pins = <RK_GPIO2 28 RK_FUNC_GPIO
710					 &pcfg_pull_none>;
711		};
712
713		sd_slot_pwr_en: sd-slot-pwr-en {
714			rockchip,pins = <RK_GPIO4 29 RK_FUNC_GPIO
715					 &pcfg_pull_none>;
716		};
717	};
718
719	codec {
720		/* Has external pullup */
721		headset_int_l: headset-int-l {
722			rockchip,pins = <1 23 RK_FUNC_GPIO &pcfg_pull_none>;
723		};
724
725		mic_int: mic-int {
726			rockchip,pins = <1 13 RK_FUNC_GPIO &pcfg_pull_down>;
727		};
728	};
729
730	max98357a {
731		sdmode_en: sdmode-en {
732			rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_down>;
733		};
734	};
735
736	pcie {
737		pcie_clkreqn_cpm: pci-clkreqn-cpm {
738			/*
739			 * Since our pcie doesn't support ClockPM(CPM), we want
740			 * to hack this as gpio, so the EP could be able to
741			 * de-assert it along and make ClockPM(CPM) work.
742			 */
743			rockchip,pins = <2 26 RK_FUNC_GPIO &pcfg_pull_none>;
744		};
745	};
746
747	sdmmc {
748		/*
749		 * We run sdmmc at max speed; bump up drive strength.
750		 * We also have external pulls, so disable the internal ones.
751		 */
752		sdmmc_bus4: sdmmc-bus4 {
753			rockchip,pins =
754				<4 8 RK_FUNC_1 &pcfg_pull_none_8ma>,
755				<4 9 RK_FUNC_1 &pcfg_pull_none_8ma>,
756				<4 10 RK_FUNC_1 &pcfg_pull_none_8ma>,
757				<4 11 RK_FUNC_1 &pcfg_pull_none_8ma>;
758		};
759
760		sdmmc_clk: sdmmc-clk {
761			rockchip,pins =
762				<4 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
763		};
764
765		sdmmc_cmd: sdmmc-cmd {
766			rockchip,pins =
767				<4 13 RK_FUNC_1 &pcfg_pull_none_8ma>;
768		};
769
770		/*
771		 * In our case the official card detect is hooked to ground
772		 * to avoid getting access to JTAG just by sticking something
773		 * in the SD card slot (see the force_jtag bit in the TRM).
774		 *
775		 * We still configure it as card detect because it doesn't
776		 * hurt and dw_mmc will ignore it.  We make sure to disable
777		 * the pull though so we don't burn needless power.
778		 */
779		sdmmc_cd: sdmmc-cd {
780			rockchip,pins =
781				<0 7 RK_FUNC_1 &pcfg_pull_none>;
782		};
783
784		/* This is where we actually hook up CD; has external pull */
785		sdmmc_cd_gpio: sdmmc-cd-gpio {
786			rockchip,pins = <4 24 RK_FUNC_GPIO &pcfg_pull_none>;
787		};
788	};
789
790	spi1 {
791		spi1_sleep: spi1-sleep {
792			/*
793			 * Pull down SPI1 CLK/CS/RX/TX during suspend, to
794			 * prevent leakage.
795			 */
796			rockchip,pins = <1 9 RK_FUNC_GPIO &pcfg_pull_down>,
797					<1 10 RK_FUNC_GPIO &pcfg_pull_down>,
798					<1 7 RK_FUNC_GPIO &pcfg_pull_down>,
799					<1 8 RK_FUNC_GPIO &pcfg_pull_down>;
800		};
801	};
802
803	touchscreen {
804		touch_int_l: touch-int-l {
805			rockchip,pins = <3 13 RK_FUNC_GPIO &pcfg_pull_up>;
806		};
807
808		touch_reset_l: touch-reset-l {
809			rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_pull_none>;
810		};
811	};
812
813	trackpad {
814		ap_i2c_tp_pu_en: ap-i2c-tp-pu-en {
815			rockchip,pins = <3 12 RK_FUNC_GPIO &pcfg_output_high>;
816		};
817
818		trackpad_int_l: trackpad-int-l {
819			rockchip,pins = <1 4 RK_FUNC_GPIO &pcfg_pull_up>;
820		};
821	};
822
823	wifi: wifi {
824		wlan_module_reset_l: wlan-module-reset-l {
825			rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_pull_none>;
826		};
827
828		bt_host_wake_l: bt-host-wake-l {
829			/* Kevin has an external pull up, but Gru does not */
830			rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>;
831		};
832	};
833
834	write-protect {
835		ap_fw_wp: ap-fw-wp {
836			rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_up>;
837		};
838	};
839};
840