1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Google Gru (and derivatives) board device tree source 4 * 5 * Copyright 2016-2017 Google, Inc 6 */ 7 8#include <dt-bindings/input/input.h> 9#include "rk3399.dtsi" 10#include "rk3399-op1-opp.dtsi" 11 12/ { 13 aliases { 14 mmc0 = &sdmmc; 15 mmc1 = &sdhci; 16 }; 17 18 chosen { 19 stdout-path = "serial2:115200n8"; 20 }; 21 22 /* 23 * Power Tree 24 * 25 * In general an attempt is made to include all rails called out by 26 * the schematic as long as those rails interact in some way with 27 * the AP. AKA: 28 * - Rails that only connect to the EC (or devices that the EC talks to) 29 * are not included. 30 * - Rails _are_ included if the rails go to the AP even if the AP 31 * doesn't currently care about them / they are always on. The idea 32 * here is that it makes it easier to map to the schematic or extend 33 * later. 34 * 35 * If two rails are substantially the same from the AP's point of 36 * view, though, we won't create a full fixed regulator. We'll just 37 * put the child rail as an alias of the parent rail. Sometimes rails 38 * look the same to the AP because one of these is true: 39 * - The EC controls the enable and the EC always enables a rail as 40 * long as the AP is running. 41 * - The rails are actually connected to each other by a jumper and 42 * the distinction is just there to add clarity/flexibility to the 43 * schematic. 44 */ 45 46 ppvar_sys: ppvar-sys { 47 compatible = "regulator-fixed"; 48 regulator-name = "ppvar_sys"; 49 regulator-always-on; 50 regulator-boot-on; 51 }; 52 53 pp1200_lpddr: pp1200-lpddr { 54 compatible = "regulator-fixed"; 55 regulator-name = "pp1200_lpddr"; 56 57 /* EC turns on w/ lpddr_pwr_en; always on for AP */ 58 regulator-always-on; 59 regulator-boot-on; 60 regulator-min-microvolt = <1200000>; 61 regulator-max-microvolt = <1200000>; 62 63 vin-supply = <&ppvar_sys>; 64 }; 65 66 pp1800: pp1800 { 67 compatible = "regulator-fixed"; 68 regulator-name = "pp1800"; 69 70 /* Always on when ppvar_sys shows power good */ 71 regulator-always-on; 72 regulator-boot-on; 73 regulator-min-microvolt = <1800000>; 74 regulator-max-microvolt = <1800000>; 75 76 vin-supply = <&ppvar_sys>; 77 }; 78 79 pp3300: pp3300 { 80 compatible = "regulator-fixed"; 81 regulator-name = "pp3300"; 82 83 /* Always on; plain and simple */ 84 regulator-always-on; 85 regulator-boot-on; 86 regulator-min-microvolt = <3300000>; 87 regulator-max-microvolt = <3300000>; 88 89 vin-supply = <&ppvar_sys>; 90 }; 91 92 pp5000: pp5000 { 93 compatible = "regulator-fixed"; 94 regulator-name = "pp5000"; 95 96 /* EC turns on w/ pp5000_en; always on for AP */ 97 regulator-always-on; 98 regulator-boot-on; 99 regulator-min-microvolt = <5000000>; 100 regulator-max-microvolt = <5000000>; 101 102 vin-supply = <&ppvar_sys>; 103 }; 104 105 ppvar_bigcpu_pwm: ppvar-bigcpu-pwm { 106 compatible = "pwm-regulator"; 107 regulator-name = "ppvar_bigcpu_pwm"; 108 109 pwms = <&pwm1 0 3337 0>; 110 pwm-supply = <&ppvar_sys>; 111 pwm-dutycycle-range = <100 0>; 112 pwm-dutycycle-unit = <100>; 113 114 /* EC turns on w/ ap_core_en; always on for AP */ 115 regulator-always-on; 116 regulator-boot-on; 117 regulator-min-microvolt = <800107>; 118 regulator-max-microvolt = <1302232>; 119 }; 120 121 ppvar_bigcpu: ppvar-bigcpu { 122 compatible = "vctrl-regulator"; 123 regulator-name = "ppvar_bigcpu"; 124 125 regulator-min-microvolt = <800107>; 126 regulator-max-microvolt = <1302232>; 127 128 ctrl-supply = <&ppvar_bigcpu_pwm>; 129 ctrl-voltage-range = <800107 1302232>; 130 131 regulator-settling-time-up-us = <322>; 132 }; 133 134 ppvar_litcpu_pwm: ppvar-litcpu-pwm { 135 compatible = "pwm-regulator"; 136 regulator-name = "ppvar_litcpu_pwm"; 137 138 pwms = <&pwm2 0 3337 0>; 139 pwm-supply = <&ppvar_sys>; 140 pwm-dutycycle-range = <100 0>; 141 pwm-dutycycle-unit = <100>; 142 143 /* EC turns on w/ ap_core_en; always on for AP */ 144 regulator-always-on; 145 regulator-boot-on; 146 regulator-min-microvolt = <797743>; 147 regulator-max-microvolt = <1307837>; 148 }; 149 150 ppvar_litcpu: ppvar-litcpu { 151 compatible = "vctrl-regulator"; 152 regulator-name = "ppvar_litcpu"; 153 154 regulator-min-microvolt = <797743>; 155 regulator-max-microvolt = <1307837>; 156 157 ctrl-supply = <&ppvar_litcpu_pwm>; 158 ctrl-voltage-range = <797743 1307837>; 159 160 regulator-settling-time-up-us = <384>; 161 }; 162 163 ppvar_gpu_pwm: ppvar-gpu-pwm { 164 compatible = "pwm-regulator"; 165 regulator-name = "ppvar_gpu_pwm"; 166 167 pwms = <&pwm0 0 3337 0>; 168 pwm-supply = <&ppvar_sys>; 169 pwm-dutycycle-range = <100 0>; 170 pwm-dutycycle-unit = <100>; 171 172 /* EC turns on w/ ap_core_en; always on for AP */ 173 regulator-always-on; 174 regulator-boot-on; 175 regulator-min-microvolt = <786384>; 176 regulator-max-microvolt = <1217747>; 177 }; 178 179 ppvar_gpu: ppvar-gpu { 180 compatible = "vctrl-regulator"; 181 regulator-name = "ppvar_gpu"; 182 183 regulator-min-microvolt = <786384>; 184 regulator-max-microvolt = <1217747>; 185 186 ctrl-supply = <&ppvar_gpu_pwm>; 187 ctrl-voltage-range = <786384 1217747>; 188 189 regulator-settling-time-up-us = <390>; 190 }; 191 192 /* EC turns on w/ pp900_ddrpll_en */ 193 pp900_ddrpll: pp900-ap { 194 }; 195 196 /* EC turns on w/ pp900_pll_en */ 197 pp900_pll: pp900-ap { 198 }; 199 200 /* EC turns on w/ pp900_pmu_en */ 201 pp900_pmu: pp900-ap { 202 }; 203 204 /* EC turns on w/ pp1800_s0_en_l */ 205 pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 { 206 }; 207 208 /* EC turns on w/ pp1800_avdd_en_l */ 209 pp1800_avdd: pp1800 { 210 }; 211 212 /* EC turns on w/ pp1800_lid_en_l */ 213 pp1800_lid: pp1800_mic: pp1800 { 214 }; 215 216 /* EC turns on w/ lpddr_pwr_en */ 217 pp1800_lpddr: pp1800 { 218 }; 219 220 /* EC turns on w/ pp1800_pmu_en_l */ 221 pp1800_pmu: pp1800 { 222 }; 223 224 /* EC turns on w/ pp1800_usb_en_l */ 225 pp1800_usb: pp1800 { 226 }; 227 228 pp3000_sd_slot: pp3000-sd-slot { 229 compatible = "regulator-fixed"; 230 regulator-name = "pp3000_sd_slot"; 231 pinctrl-names = "default"; 232 pinctrl-0 = <&sd_slot_pwr_en>; 233 234 enable-active-high; 235 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; 236 237 vin-supply = <&pp3000>; 238 }; 239 240 /* 241 * Technically, this is a small abuse of 'regulator-gpio'; this 242 * regulator is a mux between pp1800 and pp3300. pp1800 and pp3300 are 243 * always on though, so it is sufficient to simply control the mux 244 * here. 245 */ 246 ppvar_sd_card_io: ppvar-sd-card-io { 247 compatible = "regulator-gpio"; 248 regulator-name = "ppvar_sd_card_io"; 249 pinctrl-names = "default"; 250 pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>; 251 252 enable-active-high; 253 enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; 254 gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; 255 states = <1800000 0x1>, 256 <3000000 0x0>; 257 258 regulator-min-microvolt = <1800000>; 259 regulator-max-microvolt = <3000000>; 260 }; 261 262 /* EC turns on w/ pp3300_trackpad_en_l */ 263 pp3300_trackpad: pp3300-trackpad { 264 }; 265 266 /* EC turns on w/ usb_a_en */ 267 pp5000_usb_a_vbus: pp5000 { 268 }; 269 270 ap_rtc_clk: ap-rtc-clk { 271 compatible = "fixed-clock"; 272 clock-frequency = <32768>; 273 clock-output-names = "xin32k"; 274 #clock-cells = <0>; 275 }; 276 277 max98357a: max98357a { 278 compatible = "maxim,max98357a"; 279 pinctrl-names = "default"; 280 pinctrl-0 = <&sdmode_en>; 281 sdmode-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 282 sdmode-delay = <2>; 283 #sound-dai-cells = <0>; 284 status = "okay"; 285 }; 286 287 sound: sound { 288 compatible = "rockchip,rk3399-gru-sound"; 289 rockchip,cpu = <&i2s0 &spdif>; 290 }; 291}; 292 293&cdn_dp { 294 status = "okay"; 295}; 296 297/* 298 * Set some suspend operating points to avoid OVP in suspend 299 * 300 * When we go into S3 ARM Trusted Firmware will transition our PWM regulators 301 * from wherever they're at back to the "default" operating point (whatever 302 * voltage we get when we set the PWM pins to "input"). 303 * 304 * This quick transition under light load has the possibility to trigger the 305 * regulator "over voltage protection" (OVP). 306 * 307 * To make extra certain that we don't hit this OVP at suspend time, we'll 308 * transition to a voltage that's much closer to the default (~1.0 V) so that 309 * there will not be a big jump. Technically we only need to get within 200 mV 310 * of the default voltage, but the speed here should be fast enough and we need 311 * suspend/resume to be rock solid. 312 */ 313 314&cluster0_opp { 315 opp05 { 316 opp-suspend; 317 }; 318}; 319 320&cluster1_opp { 321 opp06 { 322 opp-suspend; 323 }; 324}; 325 326&cpu_l0 { 327 cpu-supply = <&ppvar_litcpu>; 328}; 329 330&cpu_l1 { 331 cpu-supply = <&ppvar_litcpu>; 332}; 333 334&cpu_l2 { 335 cpu-supply = <&ppvar_litcpu>; 336}; 337 338&cpu_l3 { 339 cpu-supply = <&ppvar_litcpu>; 340}; 341 342&cpu_b0 { 343 cpu-supply = <&ppvar_bigcpu>; 344}; 345 346&cpu_b1 { 347 cpu-supply = <&ppvar_bigcpu>; 348}; 349 350 351&cru { 352 assigned-clocks = 353 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 354 <&cru PLL_NPLL>, 355 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 356 <&cru PCLK_PERIHP>, 357 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 358 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 359 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 360 <&cru ACLK_VIO>, <&cru ACLK_HDCP>, 361 <&cru ACLK_GIC_PRE>, 362 <&cru PCLK_DDR>; 363 assigned-clock-rates = 364 <600000000>, <800000000>, 365 <1000000000>, 366 <150000000>, <75000000>, 367 <37500000>, 368 <100000000>, <100000000>, 369 <50000000>, <800000000>, 370 <100000000>, <50000000>, 371 <400000000>, <400000000>, 372 <200000000>, 373 <200000000>; 374}; 375 376&dfi { 377 status = "okay"; 378}; 379 380&dmc { 381 status = "okay"; 382 383 rockchip,pd-idle-ns = <160>; 384 rockchip,sr-idle-ns = <10240>; 385 rockchip,sr-mc-gate-idle-ns = <40960>; 386 rockchip,srpd-lite-idle-ns = <61440>; 387 rockchip,standby-idle-ns = <81920>; 388 389 rockchip,ddr3_odt_dis_freq = <666000000>; 390 rockchip,lpddr3_odt_dis_freq = <666000000>; 391 rockchip,lpddr4_odt_dis_freq = <666000000>; 392 393 rockchip,sr-mc-gate-idle-dis-freq-hz = <1000000000>; 394 rockchip,srpd-lite-idle-dis-freq-hz = <0>; 395 rockchip,standby-idle-dis-freq-hz = <928000000>; 396}; 397 398&dmc_opp_table { 399 opp03 { 400 opp-suspend; 401 }; 402}; 403 404&emmc_phy { 405 status = "okay"; 406}; 407 408&gpu { 409 mali-supply = <&ppvar_gpu>; 410 status = "okay"; 411}; 412 413ap_i2c_ts: &i2c3 { 414 status = "okay"; 415 416 clock-frequency = <400000>; 417 418 /* These are relatively safe rise/fall times */ 419 i2c-scl-falling-time-ns = <50>; 420 i2c-scl-rising-time-ns = <300>; 421}; 422 423ap_i2c_audio: &i2c8 { 424 status = "okay"; 425 426 clock-frequency = <400000>; 427 428 /* These are relatively safe rise/fall times */ 429 i2c-scl-falling-time-ns = <50>; 430 i2c-scl-rising-time-ns = <300>; 431 432 codec: da7219@1a { 433 compatible = "dlg,da7219"; 434 reg = <0x1a>; 435 interrupt-parent = <&gpio1>; 436 interrupts = <23 IRQ_TYPE_LEVEL_LOW>; 437 clocks = <&cru SCLK_I2S_8CH_OUT>; 438 clock-names = "mclk"; 439 dlg,micbias-lvl = <2600>; 440 dlg,mic-amp-in-sel = "diff"; 441 pinctrl-names = "default"; 442 pinctrl-0 = <&headset_int_l>; 443 VDD-supply = <&pp1800>; 444 VDDMIC-supply = <&pp3300>; 445 VDDIO-supply = <&pp1800>; 446 447 da7219_aad { 448 dlg,adc-1bit-rpt = <1>; 449 dlg,btn-avg = <4>; 450 dlg,btn-cfg = <50>; 451 dlg,mic-det-thr = <500>; 452 dlg,jack-ins-deb = <20>; 453 dlg,jack-det-rate = "32ms_64ms"; 454 dlg,jack-rem-deb = <1>; 455 456 dlg,a-d-btn-thr = <0xa>; 457 dlg,d-b-btn-thr = <0x16>; 458 dlg,b-c-btn-thr = <0x21>; 459 dlg,c-mic-btn-thr = <0x3E>; 460 }; 461 }; 462}; 463 464&i2s0 { 465 status = "okay"; 466}; 467 468&io_domains { 469 status = "okay"; 470 471 audio-supply = <&pp1800_audio>; /* APIO5_VDD; 3d 4a */ 472 bt656-supply = <&pp1800_ap_io>; /* APIO2_VDD; 2a 2b */ 473 gpio1830-supply = <&pp3000_ap>; /* APIO4_VDD; 4c 4d */ 474 sdmmc-supply = <&ppvar_sd_card_io>; /* SDMMC0_VDD; 4b */ 475}; 476 477&pcie0 { 478 status = "okay"; 479 480 ep-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; 481 pinctrl-names = "default"; 482 pinctrl-0 = <&pcie_clkreqn_cpm>, <&wifi_perst_l>; 483 vpcie3v3-supply = <&pp3300_wifi_bt>; 484 vpcie1v8-supply = <&wlan_pd_n>; /* HACK: see &wlan_pd_n */ 485 vpcie0v9-supply = <&pp900_pcie>; 486 487 pci_rootport: pcie@0,0 { 488 reg = <0x0000 0 0 0 0>; 489 #address-cells = <3>; 490 #size-cells = <2>; 491 ranges; 492 }; 493}; 494 495&pcie_phy { 496 status = "okay"; 497}; 498 499&pmu_io_domains { 500 status = "okay"; 501 502 pmu1830-supply = <&pp1800_pmu>; /* PMUIO2_VDD */ 503}; 504 505&pwm0 { 506 status = "okay"; 507}; 508 509&pwm1 { 510 status = "okay"; 511}; 512 513&pwm2 { 514 status = "okay"; 515}; 516 517&pwm3 { 518 status = "okay"; 519}; 520 521&sdhci { 522 /* 523 * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the 524 * same (or nearly the same) performance for all eMMC that are intended 525 * to be used. 526 */ 527 assigned-clock-rates = <150000000>; 528 529 bus-width = <8>; 530 mmc-hs400-1_8v; 531 mmc-hs400-enhanced-strobe; 532 non-removable; 533 status = "okay"; 534}; 535 536&sdmmc { 537 status = "okay"; 538 539 /* 540 * Note: configure "sdmmc_cd" as card detect even though it's actually 541 * hooked to ground. Because we specified "cd-gpios" below dw_mmc 542 * should be ignoring card detect anyway. Specifying the pin as 543 * sdmmc_cd means that even if you've got GRF_SOC_CON7[12] (force_jtag) 544 * turned on that the system will still make sure the port is 545 * configured as SDMMC and not JTAG. 546 */ 547 pinctrl-names = "default"; 548 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_pin 549 &sdmmc_bus4>; 550 551 bus-width = <4>; 552 cap-mmc-highspeed; 553 cap-sd-highspeed; 554 cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 555 disable-wp; 556 sd-uhs-sdr12; 557 sd-uhs-sdr25; 558 sd-uhs-sdr50; 559 sd-uhs-sdr104; 560 vmmc-supply = <&pp3000_sd_slot>; 561 vqmmc-supply = <&ppvar_sd_card_io>; 562}; 563 564&spdif { 565 status = "okay"; 566 567 /* 568 * SPDIF is routed internally to DP; we either don't use these pins, or 569 * mux them to something else. 570 */ 571 /delete-property/ pinctrl-0; 572 /delete-property/ pinctrl-names; 573}; 574 575&spi1 { 576 status = "okay"; 577 578 pinctrl-names = "default", "sleep"; 579 pinctrl-1 = <&spi1_sleep>; 580 581 flash@0 { 582 compatible = "jedec,spi-nor"; 583 reg = <0>; 584 585 /* May run faster once verified. */ 586 spi-max-frequency = <10000000>; 587 }; 588}; 589 590&spi2 { 591 status = "okay"; 592}; 593 594&spi5 { 595 status = "okay"; 596 597 cros_ec: ec@0 { 598 compatible = "google,cros-ec-spi"; 599 reg = <0>; 600 interrupt-parent = <&gpio0>; 601 interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 602 pinctrl-names = "default"; 603 pinctrl-0 = <&ec_ap_int_l>; 604 spi-max-frequency = <3000000>; 605 606 i2c_tunnel: i2c-tunnel { 607 compatible = "google,cros-ec-i2c-tunnel"; 608 google,remote-bus = <4>; 609 #address-cells = <1>; 610 #size-cells = <0>; 611 }; 612 613 usbc_extcon0: extcon0 { 614 compatible = "google,extcon-usbc-cros-ec"; 615 google,usb-port-id = <0>; 616 }; 617 }; 618}; 619 620&tsadc { 621 status = "okay"; 622 623 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ 624 rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ 625}; 626 627&tcphy0 { 628 status = "okay"; 629 extcon = <&usbc_extcon0>; 630}; 631 632&u2phy0 { 633 status = "okay"; 634}; 635 636&u2phy0_host { 637 status = "okay"; 638}; 639 640&u2phy1_host { 641 status = "okay"; 642}; 643 644&u2phy0_otg { 645 status = "okay"; 646}; 647 648&u2phy1_otg { 649 status = "okay"; 650}; 651 652&uart2 { 653 status = "okay"; 654}; 655 656&usb_host0_ohci { 657 status = "okay"; 658}; 659 660&usbdrd3_0 { 661 status = "okay"; 662 extcon = <&usbc_extcon0>; 663}; 664 665&usbdrd_dwc3_0 { 666 status = "okay"; 667 dr_mode = "host"; 668}; 669 670&vopb { 671 status = "okay"; 672}; 673 674&vopb_mmu { 675 status = "okay"; 676}; 677 678&vopl { 679 status = "okay"; 680}; 681 682&vopl_mmu { 683 status = "okay"; 684}; 685 686#include <arm/cros-ec-keyboard.dtsi> 687#include <arm/cros-ec-sbs.dtsi> 688 689&pinctrl { 690 /* 691 * pinctrl settings for pins that have no real owners. 692 * 693 * At the moment settings are identical for S0 and S3, but if we later 694 * need to configure things differently for S3 we'll adjust here. 695 */ 696 pinctrl-names = "default"; 697 pinctrl-0 = < 698 &ap_pwroff /* AP will auto-assert this when in S3 */ 699 &clk_32k /* This pin is always 32k on gru boards */ 700 >; 701 702 pcfg_output_low: pcfg-output-low { 703 output-low; 704 }; 705 706 pcfg_output_high: pcfg-output-high { 707 output-high; 708 }; 709 710 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 711 bias-disable; 712 drive-strength = <8>; 713 }; 714 715 backlight-enable { 716 bl_en: bl-en { 717 rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; 718 }; 719 }; 720 721 cros-ec { 722 ec_ap_int_l: ec-ap-int-l { 723 rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; 724 }; 725 }; 726 727 discrete-regulators { 728 sd_io_pwr_en: sd-io-pwr-en { 729 rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO 730 &pcfg_pull_none>; 731 }; 732 733 sd_pwr_1800_sel: sd-pwr-1800-sel { 734 rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO 735 &pcfg_pull_none>; 736 }; 737 738 sd_slot_pwr_en: sd-slot-pwr-en { 739 rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO 740 &pcfg_pull_none>; 741 }; 742 }; 743 744 codec { 745 /* Has external pullup */ 746 headset_int_l: headset-int-l { 747 rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; 748 }; 749 750 mic_int: mic-int { 751 rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; 752 }; 753 }; 754 755 max98357a { 756 sdmode_en: sdmode-en { 757 rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>; 758 }; 759 }; 760 761 pcie { 762 pcie_clkreqn_cpm: pci-clkreqn-cpm { 763 /* 764 * Since our pcie doesn't support ClockPM(CPM), we want 765 * to hack this as gpio, so the EP could be able to 766 * de-assert it along and make ClockPM(CPM) work. 767 */ 768 rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 769 }; 770 }; 771 772 sdmmc { 773 /* 774 * We run sdmmc at max speed; bump up drive strength. 775 * We also have external pulls, so disable the internal ones. 776 */ 777 sdmmc_bus4: sdmmc-bus4 { 778 rockchip,pins = 779 <4 RK_PB0 1 &pcfg_pull_none_8ma>, 780 <4 RK_PB1 1 &pcfg_pull_none_8ma>, 781 <4 RK_PB2 1 &pcfg_pull_none_8ma>, 782 <4 RK_PB3 1 &pcfg_pull_none_8ma>; 783 }; 784 785 sdmmc_clk: sdmmc-clk { 786 rockchip,pins = 787 <4 RK_PB4 1 &pcfg_pull_none_8ma>; 788 }; 789 790 sdmmc_cmd: sdmmc-cmd { 791 rockchip,pins = 792 <4 RK_PB5 1 &pcfg_pull_none_8ma>; 793 }; 794 795 /* 796 * In our case the official card detect is hooked to ground 797 * to avoid getting access to JTAG just by sticking something 798 * in the SD card slot (see the force_jtag bit in the TRM). 799 * 800 * We still configure it as card detect because it doesn't 801 * hurt and dw_mmc will ignore it. We make sure to disable 802 * the pull though so we don't burn needless power. 803 */ 804 sdmmc_cd: sdmmc-cd { 805 rockchip,pins = 806 <0 RK_PA7 1 &pcfg_pull_none>; 807 }; 808 809 /* This is where we actually hook up CD; has external pull */ 810 sdmmc_cd_pin: sdmmc-cd-pin { 811 rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 812 }; 813 }; 814 815 spi1 { 816 spi1_sleep: spi1-sleep { 817 /* 818 * Pull down SPI1 CLK/CS/RX/TX during suspend, to 819 * prevent leakage. 820 */ 821 rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>, 822 <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>, 823 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>, 824 <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; 825 }; 826 }; 827 828 touchscreen { 829 touch_int_l: touch-int-l { 830 rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; 831 }; 832 833 touch_reset_l: touch-reset-l { 834 rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 835 }; 836 }; 837 838 trackpad { 839 ap_i2c_tp_pu_en: ap-i2c-tp-pu-en { 840 rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>; 841 }; 842 843 trackpad_int_l: trackpad-int-l { 844 rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; 845 }; 846 }; 847 848 wifi: wifi { 849 wlan_module_reset_l: wlan-module-reset-l { 850 rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; 851 }; 852 853 bt_host_wake_l: bt-host-wake-l { 854 /* Kevin has an external pull up, but Gru does not */ 855 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; 856 }; 857 }; 858 859 write-protect { 860 ap_fw_wp: ap-fw-wp { 861 rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; 862 }; 863 }; 864}; 865